From c20388a31d68bcbaf70bb3a2208a92eb2c242995 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Tue, 27 Jan 2015 16:43:17 +0800 Subject: MLK-10161-2: ARM: imx6sl: Add SPDIF_GCLK clock in clock tree As spdif driver will register SPDIF clock to regmap, regmap will do clk_prepare in init function, so SPDIF clock is prepared in probe, then its root clock (pll clock) is prepared also, which cause the arm can't enter low power mode. Add SPDIF_GCLK in clock tree which share same gate bits with SPDIF clock. Its root clock is ipg clock, and register it to regmap, then the issue can be fixed. Signed-off-by: Shengjiu Wang (cherry picked from commit c3cd6268d80b4ea6a5ab88642e92f51f6ac56e51) --- arch/arm/boot/dts/imx6sl.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm/boot/dts/imx6sl.dtsi') diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index f15e733b7651..41ee662ca491 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -155,6 +155,20 @@ spdif: spdif@02004000 { reg = <0x02004000 0x4000>; interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 14 18 0>, + <&sdma 15 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>, + <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "dma"; + status = "disabled"; }; ecspi1: ecspi@02008000 { -- cgit v1.2.3