From 008d4f3881466cadbd1df2b7ca7d89f93ab2dab7 Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Wed, 10 May 2017 15:09:09 +0800 Subject: MLK-14866-2: dts: imx7ulp-evk: remove duplicated mux setting in config According to RM, Bit[11-8] is MUX_MODE which is configured by the PIN_FUNC_ID automatically, specify it in config part is wrong and violates the binding doc. So remove them all. It can also avoid the future confusing when customer wants to configure a pad by following the exist code. Signed-off-by: Dong Aisheng --- arch/arm/boot/dts/imx7ulp-evk.dts | 112 +++++++++++++++++++------------------- 1 file changed, 56 insertions(+), 56 deletions(-) (limited to 'arch/arm/boot/dts/imx7ulp-evk.dts') diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts index 4e7cf92430fc..3bb9df635986 100644 --- a/arch/arm/boot/dts/imx7ulp-evk.dts +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -198,147 +198,147 @@ imx7ulp-evk { pinctrl_hog_1: hoggrp-1 { fsl,pins = < - IMX7ULP_PAD_PTC1__PTC1 0x20100 + IMX7ULP_PAD_PTC1__PTC1 0x20000 >; }; pinctrl_pwm0: pwm0_grp { fsl,pins = < - IMX7ULP_PAD_PTF2__TPM4_CH1 0x403 + IMX7ULP_PAD_PTF2__TPM4_CH1 0x3 >; }; pinctrl_lpi2c5: lpi2c5grp { fsl,pins = < - IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x527 - IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x527 + IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x27 + IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x27 >; }; pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp { fsl,pins = < - IMX7ULP_PAD_PTC19__PTC19 0x20103 + IMX7ULP_PAD_PTC19__PTC19 0x20003 >; }; pinctrl_lpuart4: lpuart4grp { fsl,pins = < - IMX7ULP_PAD_PTC3__LPUART4_RX 0x403 - IMX7ULP_PAD_PTC2__LPUART4_TX 0x403 + IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 + IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 >; }; pinctrl_lpuart6: lpuart6grp { fsl,pins = < - IMX7ULP_PAD_PTE10__LPUART6_TX 0x403 - IMX7ULP_PAD_PTE11__LPUART6_RX 0x403 - IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x403 - IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x403 - IMX7ULP_PAD_PTE7__PTE7 0x20000 /* BT_REG_ON */ + IMX7ULP_PAD_PTE10__LPUART6_TX 0x3 + IMX7ULP_PAD_PTE11__LPUART6_RX 0x3 + IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x3 + IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x3 + IMX7ULP_PAD_PTE7__PTE7 0x20000 /* BT_REG_ON */ >; }; pinctrl_lpuart7: lpuart7grp { fsl,pins = < - IMX7ULP_PAD_PTF14__LPUART7_TX 0x403 - IMX7ULP_PAD_PTF15__LPUART7_RX 0x403 - IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x403 - IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x403 + IMX7ULP_PAD_PTF14__LPUART7_TX 0x3 + IMX7ULP_PAD_PTF15__LPUART7_RX 0x3 + IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x3 + IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x3 >; }; pinctrl_usdhc0: usdhc0grp { fsl,pins = < - IMX7ULP_PAD_PTD1__SDHC0_CMD 0x843 - IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10843 - IMX7ULP_PAD_PTD7__SDHC0_D3 0x843 - IMX7ULP_PAD_PTD8__SDHC0_D2 0x843 - IMX7ULP_PAD_PTD9__SDHC0_D1 0x843 - IMX7ULP_PAD_PTD10__SDHC0_D0 0x843 - IMX7ULP_PAD_PTC10__PTC10 0x10100 /* USDHC0 CD */ - IMX7ULP_PAD_PTD0__PTD0 0x20100 /* USDHC0 RST */ + IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 + IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10043 + IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 + IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 + IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 + IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 + IMX7ULP_PAD_PTC10__PTC10 0x10000 /* USDHC0 CD */ + IMX7ULP_PAD_PTD0__PTD0 0x20000 /* USDHC0 RST */ >; }; pinctrl_usdhc0_8bit: usdhc0grp_8bit { fsl,pins = < - IMX7ULP_PAD_PTD1__SDHC0_CMD 0x843 - IMX7ULP_PAD_PTD2__SDHC0_CLK 0x843 - IMX7ULP_PAD_PTD3__SDHC0_D7 0x843 - IMX7ULP_PAD_PTD4__SDHC0_D6 0x843 - IMX7ULP_PAD_PTD5__SDHC0_D5 0x843 - IMX7ULP_PAD_PTD6__SDHC0_D4 0x843 - IMX7ULP_PAD_PTD7__SDHC0_D3 0x843 - IMX7ULP_PAD_PTD8__SDHC0_D2 0x843 - IMX7ULP_PAD_PTD9__SDHC0_D1 0x843 - IMX7ULP_PAD_PTD10__SDHC0_D0 0x843 + IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 + IMX7ULP_PAD_PTD2__SDHC0_CLK 0x43 + IMX7ULP_PAD_PTD3__SDHC0_D7 0x43 + IMX7ULP_PAD_PTD4__SDHC0_D6 0x43 + IMX7ULP_PAD_PTD5__SDHC0_D5 0x43 + IMX7ULP_PAD_PTD6__SDHC0_D4 0x43 + IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 + IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 + IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 + IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 >; }; pinctrl_lpi2c7: lpi2c7grp { fsl,pins = < - IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x527 - IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x527 + IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x27 + IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x27 >; }; pinctrl_lpspi3: lpspi3grp { fsl,pins = < - IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x300 - IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x300 - IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x300 - IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x300 + IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x0 + IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x0 + IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x0 + IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x0 >; }; pinctrl_usb_otg1: usbotg1grp { fsl,pins = < - IMX7ULP_PAD_PTC0__PTC0 0x20100 + IMX7ULP_PAD_PTC0__PTC0 0x20000 >; }; pinctrl_extcon_usb1: extcon1grp { fsl,pins = < - IMX7ULP_PAD_PTC8__PTC8 0x10103 + IMX7ULP_PAD_PTC8__PTC8 0x10003 >; }; pinctrl_focaltech: focaltechgrp { fsl,pins = < - IMX7ULP_PAD_PTF0__PTF0 0x10143 - IMX7ULP_PAD_PTF1__PTF1 0x20143 + IMX7ULP_PAD_PTF0__PTF0 0x10043 + IMX7ULP_PAD_PTF1__PTF1 0x20043 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < - IMX7ULP_PAD_PTE3__SDHC1_CMD 0x843 - IMX7ULP_PAD_PTE2__SDHC1_CLK 0x843 - IMX7ULP_PAD_PTE1__SDHC1_D0 0x843 - IMX7ULP_PAD_PTE0__SDHC1_D1 0x843 - IMX7ULP_PAD_PTE5__SDHC1_D2 0x843 - IMX7ULP_PAD_PTE4__SDHC1_D3 0x843 + IMX7ULP_PAD_PTE3__SDHC1_CMD 0x43 + IMX7ULP_PAD_PTE2__SDHC1_CLK 0x43 + IMX7ULP_PAD_PTE1__SDHC1_D0 0x43 + IMX7ULP_PAD_PTE0__SDHC1_D1 0x43 + IMX7ULP_PAD_PTE5__SDHC1_D2 0x43 + IMX7ULP_PAD_PTE4__SDHC1_D3 0x43 >; }; pinctrl_usdhc1_rst: usdhc1grp_rst { fsl,pins = < - IMX7ULP_PAD_PTE11__PTE11 0x20100 /* USDHC1 RST */ - IMX7ULP_PAD_PTE13__PTE13 0x10103 /* USDHC1 CD */ - IMX7ULP_PAD_PTE12__PTE12 0x10103 /* USDHC1 WP */ - IMX7ULP_PAD_PTE14__SDHC1_VS 0x843 /* USDHC1 VSEL */ + IMX7ULP_PAD_PTE11__PTE11 0x20000 /* USDHC1 RST */ + IMX7ULP_PAD_PTE13__PTE13 0x10003 /* USDHC1 CD */ + IMX7ULP_PAD_PTE12__PTE12 0x10003 /* USDHC1 WP */ + IMX7ULP_PAD_PTE14__SDHC1_VS 0x43 /* USDHC1 VSEL */ >; }; pinctrl_wifi: wifigrp { fsl,pins = < - IMX7ULP_PAD_PTE6__PTE6 0x20043 /* WL_REG_ON */ + IMX7ULP_PAD_PTE6__PTE6 0x20043 /* WL_REG_ON */ >; }; pinctrl_dsi_hdmi: dsi_hdmi_grp { fsl,pins = < - IMX7ULP_PAD_PTC18__PTC18 0x10103 /* DSI_HDMI_INT */ + IMX7ULP_PAD_PTC18__PTC18 0x10003 /* DSI_HDMI_INT */ >; }; }; -- cgit v1.2.3