From ded79bebcace01c803c8b71871fd13c90ca5cffd Mon Sep 17 00:00:00 2001 From: Ivan Khoronzhuk Date: Fri, 23 May 2014 16:34:55 -0400 Subject: ARM: dts: keystone: update reset node to work with reset driver The pll controller register set and device state control registers include sets of registers with different purposes, so it's logically to add syscon entry to be able to access them from appropriate places. So added pll controller and device state control syscon entries. The keystone driver requires the next additional properties: "ti,syscon-pll" - phandle/offset pair. The phandle to syscon used to access pll controller registers and the offset to use reset control registers. "ti,syscon-dev" - phandle/offset pair. The phandle to syscon used to access device state control registers and the offset in order to use mux block registers for all watchdogs. "ti,wdt-list" - option to declare what watchdogs are used to reboot the SoC, so set "0" WDT as default. Reviewed-by: Arnd Bergmann Signed-off-by: Ivan Khoronzhuk Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/keystone.dtsi') diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 90823eb90c1b..a8052fd657e5 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -67,9 +67,21 @@ interrupt-parent = <&gic>; ranges = <0x0 0x0 0x0 0xc0000000>; + pllctrl: pll-controller@02310000 { + compatible = "ti,keystone-pllctrl", "syscon"; + reg = <0x02310000 0x200>; + }; + + devctrl: device-state-control@02620000 { + compatible = "ti,keystone-devctrl", "syscon"; + reg = <0x02620000 0x1000>; + }; + rstctrl: reset-controller { compatible = "ti,keystone-reset"; - reg = <0x023100e8 4>; /* pll reset control reg */ + ti,syscon-pll = <&pllctrl 0xe4>; + ti,syscon-dev = <&devctrl 0x328>; + ti,wdt-list = <0>; }; /include/ "keystone-clocks.dtsi" -- cgit v1.2.3