From 4018fba454602cc1d01a216352935d88582353f1 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 13 Jun 2016 00:15:55 +0300 Subject: ARM: dts: blanche: initial device tree Add the initial device tree for the R8A7792 SoC based Blanche board. The board has 2 debug serial ports: SCIF0 and SCIF3; include support for them, so that the serial console can work. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-blanche.dts | 45 +++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7792-blanche.dts (limited to 'arch/arm/boot/dts/r8a7792-blanche.dts') diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts new file mode 100644 index 000000000000..e277d924441b --- /dev/null +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -0,0 +1,45 @@ +/* + * Device Tree Source for the Blanche board + * + * Copyright (C) 2014 Renesas Electronics Corporation + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7792.dtsi" + +/ { + model = "Blanche"; + compatible = "renesas,blanche", "renesas,r8a7792"; + + aliases { + serial0 = &scif0; + serial1 = &scif3; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&scif0 { + status = "okay"; +}; + +&scif3 { + status = "okay"; +}; -- cgit v1.2.3