From 288fb7ff8eed8a611af0fa35648a035976ed5108 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 29 Jul 2015 14:10:06 +0200 Subject: ARM: at91/dt: sama5d3: use slow clock where necessary The watchdog, the reset controller, the RTC, the shutdown controller, the timer counters and the LCD PWM need the slow clock, add it where necessary. [boris.brezillon@free-electrons.com: add tcb clocks] Signed-off-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/sama5d3.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts/sama5d3.dtsi') diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 81ced62cedaf..7fa276515f11 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -145,8 +145,8 @@ compatible = "atmel,at91sam9x5-tcb"; reg = <0xf0010000 0x100>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>; - clock-names = "t0_clk"; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; i2c0: i2c@f0014000 { @@ -1261,11 +1261,13 @@ rstc@fffffe00 { compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; + clocks = <&clk32k>; }; shutdown-controller@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; + clocks = <&clk32k>; }; pit: timer@fffffe30 { @@ -1279,6 +1281,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffe40 0x10>; interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; atmel,watchdog-type = "hardware"; atmel,reset-type = "all"; atmel,dbg-halt; @@ -1315,6 +1318,7 @@ compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffeb0 0x30>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; }; }; -- cgit v1.2.3