From d31e2e846b35370a2317a211a50d8248d46fc83b Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Wed, 10 Feb 2016 13:26:22 -0600 Subject: ARM: dts: Add Altera L2 Cache and OCRAM EDAC entries Add the device tree entries and bindings needed to support the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon an earlier patch to declare and setup On-chip RAM properly: 8b907c8b62ac ("arm: dts: socfpga: Add OCRAM node") Signed-off-by: Thor Thayer Acked-by: Rob Herring Cc: devicetree@vger.kernel.org Cc: Dinh Nguyen Cc: galak@codeaurora.org Cc: grant.likely@linaro.org Cc: Ian Campbell Cc: ijc+devicetree@hellion.org.uk Cc: Kumar Gala Cc: linux-arm-kernel@lists.infradead.org Cc: linux@arm.linux.org.uk Cc: linux-doc@vger.kernel.org Cc: linux-edac Cc: Mark Rutland Cc: m.chehab@samsung.com Cc: Pawel Moll Cc: Rob Herring Cc: Russell King Link: http://lkml.kernel.org/r/1455132384-17108-2-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov --- arch/arm/boot/dts/socfpga.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/boot/dts/socfpga.dtsi') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 3ed4abdaaa9c..15cbc747c242 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -656,6 +656,26 @@ status = "disabled"; }; + eccmgr: eccmgr@ffd08140 { + compatible = "altr,socfpga-ecc-manager"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + l2-ecc@ffd08140 { + compatible = "altr,socfpga-l2-ecc"; + reg = <0xffd08140 0x4>; + interrupts = <0 36 1>, <0 37 1>; + }; + + ocram-ecc@ffd08144 { + compatible = "altr,socfpga-ocram-ecc"; + reg = <0xffd08144 0x4>; + iram = <&ocram>; + interrupts = <0 178 1>, <0 179 1>; + }; + }; + L2: l2-cache@fffef000 { compatible = "arm,pl310-cache"; reg = <0xfffef000 0x1000>; -- cgit v1.2.3