From e8f0ff58330b76342359986a0321520106e80ad3 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 18 Oct 2016 22:51:42 -0500 Subject: ARM: dts: socfpga: enable qspi on the Cyclone5 devkit Enable the qspi controller on the devkit and add the flash chip. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 33 ++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch/arm/boot/dts/socfpga_cyclone5_socdk.dts') diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 7a5f42dba12e..6306d008f01b 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -87,6 +87,39 @@ status = "okay"; }; +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; /* chip select */ + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@qspi-boot { + /* 8MB for raw data. */ + label = "Flash 0 Raw Data"; + reg = <0x0 0x800000>; + }; + + partition@qspi-rootfs { + /* 120MB for jffs2 data. */ + label = "Flash 0 jffs2 Filesystem"; + reg = <0x800000 0x7800000>; + }; + }; +}; + &usb1 { status = "okay"; }; -- cgit v1.2.3