From dbbcd881ee97100077295f48fcc7a53a8ce95c52 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 23 Nov 2014 14:38:14 +0100 Subject: ARM: dts: sun6i: Add pinmux settings for the ir pins Add pinmux settings for the ir receive pin of the A31. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts/sun6i-a31.dtsi') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index f47156b6572b..02d990a1e382 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -901,6 +901,13 @@ #interrupt-cells = <2>; #size-cells = <0>; #gpio-cells = <3>; + + ir_pins_a: ir@0 { + allwinner,pins = "PL4"; + allwinner,function = "s_ir"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; }; }; -- cgit v1.2.3 From 9b5c6e06937a7bbbc3af60b3041ff6523cb4a23e Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 17 Dec 2014 18:18:19 +0100 Subject: ARM: dts: sun6i: Add ir_clk node Add an ir_clk sub-node to the prcm node. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts/sun6i-a31.dtsi') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 02d990a1e382..766822ddb739 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -878,6 +878,13 @@ "apb0_i2c"; }; + ir_clk: ir_clk { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + clocks = <&osc32k>, <&osc24M>; + clock-output-names = "ir"; + }; + apb0_rst: apb0_rst { compatible = "allwinner,sun6i-a31-clock-reset"; #reset-cells = <1>; -- cgit v1.2.3 From 4ac367b4ec7257a300bd39e5757aa988f1435194 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 29 Dec 2014 12:09:24 +0100 Subject: ARM: dts: sun6i: Add ir node Add a node for the ir receiver found on the A31. Signed-off-by: Hans de Goede [Maxime: Added a node label] Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot/dts/sun6i-a31.dtsi') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 766822ddb739..c50d4e8c1150 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -896,6 +896,16 @@ reg = <0x01f01c00 0x300>; }; + ir: ir@01f02000 { + compatible = "allwinner,sun5i-a13-ir"; + clocks = <&apb0_gates 1>, <&ir_clk>; + clock-names = "apb", "ir"; + resets = <&apb0_rst 1>; + interrupts = <0 37 4>; + reg = <0x01f02000 0x40>; + status = "disabled"; + }; + r_pio: pinctrl@01f02c00 { compatible = "allwinner,sun6i-a31-r-pinctrl"; reg = <0x01f02c00 0x400>; -- cgit v1.2.3 From 7145570159fb20654b507026a8e388f739fffa5c Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Dec 2014 22:59:54 +0100 Subject: ARM: sunxi: DT: Convert to device tree includes Prepare the device trees to use the C preprocessor. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/sun6i-a31.dtsi') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index c50d4e8c1150..b47d42ab1c1f 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -47,7 +47,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { interrupt-parent = <&gic>; -- cgit v1.2.3 From 092a0c3b18ce8f2207591846dad5c9071ed2f832 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Dec 2014 22:59:57 +0100 Subject: ARM: sunxi: DT: Convert the DTs to use a header for the pinctrl nodes The pinctrl nodes require some extra opaque arguments for the pull up and drive strength values. Introduce a new header file and convert the device trees to replace these opaque numbers by defines. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) (limited to 'arch/arm/boot/dts/sun6i-a31.dtsi') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index b47d42ab1c1f..6d53d38ebde1 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -49,6 +49,8 @@ #include "skeleton.dtsi" +#include + / { interrupt-parent = <&gic>; @@ -509,36 +511,36 @@ uart0_pins_a: uart0@0 { allwinner,pins = "PH20", "PH21"; allwinner,function = "uart0"; - allwinner,drive = <0>; - allwinner,pull = <0>; + allwinner,drive = ; + allwinner,pull = ; }; i2c0_pins_a: i2c0@0 { allwinner,pins = "PH14", "PH15"; allwinner,function = "i2c0"; - allwinner,drive = <0>; - allwinner,pull = <0>; + allwinner,drive = ; + allwinner,pull = ; }; i2c1_pins_a: i2c1@0 { allwinner,pins = "PH16", "PH17"; allwinner,function = "i2c1"; - allwinner,drive = <0>; - allwinner,pull = <0>; + allwinner,drive = ; + allwinner,pull = ; }; i2c2_pins_a: i2c2@0 { allwinner,pins = "PH18", "PH19"; allwinner,function = "i2c2"; - allwinner,drive = <0>; - allwinner,pull = <0>; + allwinner,drive = ; + allwinner,pull = ; }; mmc0_pins_a: mmc0@0 { allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; allwinner,function = "mmc0"; - allwinner,drive = <2>; - allwinner,pull = <0>; + allwinner,drive = ; + allwinner,pull = ; }; gmac_pins_mii_a: gmac_mii@0 { @@ -548,8 +550,8 @@ "PA20", "PA21", "PA22", "PA23", "PA24", "PA26", "PA27"; allwinner,function = "gmac"; - allwinner,drive = <0>; - allwinner,pull = <0>; + allwinner,drive = ; + allwinner,pull = ; }; gmac_pins_gmii_a: gmac_gmii@0 { @@ -565,8 +567,8 @@ * data lines in GMII mode run at 125MHz and * might need a higher signal drive strength */ - allwinner,drive = <2>; - allwinner,pull = <0>; + allwinner,drive = ; + allwinner,pull = ; }; gmac_pins_rgmii_a: gmac_rgmii@0 { @@ -579,8 +581,8 @@ * data lines in RGMII mode use DDR mode * and need a higher signal drive strength */ - allwinner,drive = <3>; - allwinner,pull = <0>; + allwinner,drive = ; + allwinner,pull = ; }; }; @@ -922,8 +924,8 @@ ir_pins_a: ir@0 { allwinner,pins = "PL4"; allwinner,function = "s_ir"; - allwinner,drive = <0>; - allwinner,pull = <0>; + allwinner,drive = ; + allwinner,pull = ; }; }; }; -- cgit v1.2.3 From 19882b84d7d9b1888b03f35b2430de550b61e49d Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Dec 2014 22:59:58 +0100 Subject: ARM: sunxi: DT: Convert the DTs to use the GIC headers The GIC requires some extra opaque arguments to set the IRQ type and flags. Convert the DTs to using the common defines. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 99 +++++++++++++++++++++------------------- 1 file changed, 51 insertions(+), 48 deletions(-) (limited to 'arch/arm/boot/dts/sun6i-a31.dtsi') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 6d53d38ebde1..97b6c3393099 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -49,6 +49,8 @@ #include "skeleton.dtsi" +#include + #include / { @@ -113,10 +115,10 @@ pmu { compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; - interrupts = <0 120 4>, - <0 121 4>, - <0 122 4>, - <0 123 4>; + interrupts = , + , + , + ; }; clocks { @@ -363,7 +365,7 @@ dma: dma-controller@01c02000 { compatible = "allwinner,sun6i-a31-dma"; reg = <0x01c02000 0x1000>; - interrupts = <0 50 4>; + interrupts = ; clocks = <&ahb1_gates 6>; resets = <&ahb1_rst 6>; #dma-cells = <1>; @@ -380,7 +382,7 @@ clock-names = "ahb", "mmc"; resets = <&ahb1_rst 8>; reset-names = "ahb"; - interrupts = <0 60 4>; + interrupts = ; status = "disabled"; }; @@ -391,7 +393,7 @@ clock-names = "ahb", "mmc"; resets = <&ahb1_rst 9>; reset-names = "ahb"; - interrupts = <0 61 4>; + interrupts = ; status = "disabled"; }; @@ -402,7 +404,7 @@ clock-names = "ahb", "mmc"; resets = <&ahb1_rst 10>; reset-names = "ahb"; - interrupts = <0 62 4>; + interrupts = ; status = "disabled"; }; @@ -413,7 +415,7 @@ clock-names = "ahb", "mmc"; resets = <&ahb1_rst 11>; reset-names = "ahb"; - interrupts = <0 63 4>; + interrupts = ; status = "disabled"; }; @@ -444,7 +446,7 @@ ehci0: usb@01c1a000 { compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; - interrupts = <0 72 4>; + interrupts = ; clocks = <&ahb1_gates 26>; resets = <&ahb1_rst 26>; phys = <&usbphy 1>; @@ -455,7 +457,7 @@ ohci0: usb@01c1a400 { compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; - interrupts = <0 73 4>; + interrupts = ; clocks = <&ahb1_gates 29>, <&usb_clk 16>; resets = <&ahb1_rst 29>; phys = <&usbphy 1>; @@ -466,7 +468,7 @@ ehci1: usb@01c1b000 { compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; reg = <0x01c1b000 0x100>; - interrupts = <0 74 4>; + interrupts = ; clocks = <&ahb1_gates 27>; resets = <&ahb1_rst 27>; phys = <&usbphy 2>; @@ -477,7 +479,7 @@ ohci1: usb@01c1b400 { compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1b400 0x100>; - interrupts = <0 75 4>; + interrupts = ; clocks = <&ahb1_gates 30>, <&usb_clk 17>; resets = <&ahb1_rst 30>; phys = <&usbphy 2>; @@ -488,7 +490,7 @@ ohci2: usb@01c1c400 { compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; - interrupts = <0 77 4>; + interrupts = ; clocks = <&ahb1_gates 31>, <&usb_clk 18>; resets = <&ahb1_rst 31>; status = "disabled"; @@ -497,10 +499,10 @@ pio: pinctrl@01c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>; - interrupts = <0 11 4>, - <0 15 4>, - <0 16 4>, - <0 17 4>; + interrupts = , + , + , + ; clocks = <&apb1_gates 5>; gpio-controller; interrupt-controller; @@ -607,11 +609,11 @@ timer@01c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; - interrupts = <0 18 4>, - <0 19 4>, - <0 20 4>, - <0 21 4>, - <0 22 4>; + interrupts = , + , + , + , + ; clocks = <&osc24M>; }; @@ -623,7 +625,7 @@ uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; - interrupts = <0 0 4>; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 16>; @@ -636,7 +638,7 @@ uart1: serial@01c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; - interrupts = <0 1 4>; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 17>; @@ -649,7 +651,7 @@ uart2: serial@01c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; - interrupts = <0 2 4>; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 18>; @@ -662,7 +664,7 @@ uart3: serial@01c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; - interrupts = <0 3 4>; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 19>; @@ -675,7 +677,7 @@ uart4: serial@01c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; - interrupts = <0 4 4>; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 20>; @@ -688,7 +690,7 @@ uart5: serial@01c29400 { compatible = "snps,dw-apb-uart"; reg = <0x01c29400 0x400>; - interrupts = <0 5 4>; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 21>; @@ -701,7 +703,7 @@ i2c0: i2c@01c2ac00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; - interrupts = <0 6 4>; + interrupts = ; clocks = <&apb2_gates 0>; resets = <&apb2_rst 0>; status = "disabled"; @@ -712,7 +714,7 @@ i2c1: i2c@01c2b000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; - interrupts = <0 7 4>; + interrupts = ; clocks = <&apb2_gates 1>; resets = <&apb2_rst 1>; status = "disabled"; @@ -723,7 +725,7 @@ i2c2: i2c@01c2b400 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b400 0x400>; - interrupts = <0 8 4>; + interrupts = ; clocks = <&apb2_gates 2>; resets = <&apb2_rst 2>; status = "disabled"; @@ -734,7 +736,7 @@ i2c3: i2c@01c2b800 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b800 0x400>; - interrupts = <0 9 4>; + interrupts = ; clocks = <&apb2_gates 3>; resets = <&apb2_rst 3>; status = "disabled"; @@ -745,7 +747,7 @@ gmac: ethernet@01c30000 { compatible = "allwinner,sun7i-a20-gmac"; reg = <0x01c30000 0x1054>; - interrupts = <0 82 4>; + interrupts = ; interrupt-names = "macirq"; clocks = <&ahb1_gates 17>, <&gmac_tx_clk>; clock-names = "stmmaceth", "allwinner_gmac_tx"; @@ -762,10 +764,10 @@ timer@01c60000 { compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; reg = <0x01c60000 0x1000>; - interrupts = <0 51 4>, - <0 52 4>, - <0 53 4>, - <0 54 4>; + interrupts = , + , + , + ; clocks = <&ahb1_gates 19>; resets = <&ahb1_rst 19>; }; @@ -773,7 +775,7 @@ spi0: spi@01c68000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c68000 0x1000>; - interrupts = <0 65 4>; + interrupts = ; clocks = <&ahb1_gates 20>, <&spi0_clk>; clock-names = "ahb", "mod"; dmas = <&dma 23>, <&dma 23>; @@ -785,7 +787,7 @@ spi1: spi@01c69000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c69000 0x1000>; - interrupts = <0 66 4>; + interrupts = ; clocks = <&ahb1_gates 21>, <&spi1_clk>; clock-names = "ahb", "mod"; dmas = <&dma 24>, <&dma 24>; @@ -797,7 +799,7 @@ spi2: spi@01c6a000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c6a000 0x1000>; - interrupts = <0 67 4>; + interrupts = ; clocks = <&ahb1_gates 22>, <&spi2_clk>; clock-names = "ahb", "mod"; dmas = <&dma 25>, <&dma 25>; @@ -809,7 +811,7 @@ spi3: spi@01c6b000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c6b000 0x1000>; - interrupts = <0 68 4>; + interrupts = ; clocks = <&ahb1_gates 23>, <&spi3_clk>; clock-names = "ahb", "mod"; dmas = <&dma 26>, <&dma 26>; @@ -826,13 +828,14 @@ <0x01c86000 0x2000>; interrupt-controller; #interrupt-cells = <3>; - interrupts = <1 9 0xf04>; + interrupts = ; }; rtc: rtc@01f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; - interrupts = <0 40 4>, <0 41 4>; + interrupts = , + ; }; nmi_intc: interrupt-controller@01f00c0c { @@ -840,7 +843,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x01f00c0c 0x38>; - interrupts = <0 32 4>; + interrupts = ; }; prcm@01f01400 { @@ -903,7 +906,7 @@ clocks = <&apb0_gates 1>, <&ir_clk>; clock-names = "apb", "ir"; resets = <&apb0_rst 1>; - interrupts = <0 37 4>; + interrupts = ; reg = <0x01f02000 0x40>; status = "disabled"; }; @@ -911,8 +914,8 @@ r_pio: pinctrl@01f02c00 { compatible = "allwinner,sun6i-a31-r-pinctrl"; reg = <0x01f02c00 0x400>; - interrupts = <0 45 4>, - <0 46 4>; + interrupts = , + ; clocks = <&apb0_gates 0>; resets = <&apb0_rst 0>; gpio-controller; -- cgit v1.2.3 From fd18c7eac03540654abdbfedd52e6dfb3718b489 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 19 Jan 2015 14:05:12 +0100 Subject: ARM: dts: sunxi: Add simplefb nodes for de_be0-lcd0, de_be0-lcd0-tve0 pipelines Add simplefb nodes for "[de_fe0-]de_be0-lcd0" and "[de_fe0-]de_be0-lcd0-tve0" display pipelines for when u-boot has set up a pipeline to drive a LCD panel / VGA output rather then the HDMI output. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts/sun6i-a31.dtsi') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 97b6c3393099..4ae3e2eef679 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -77,6 +77,14 @@ clocks = <&pll6 0>; status = "disabled"; }; + + framebuffer@1 { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0"; + clocks = <&pll6 0>; + status = "disabled"; + }; }; cpus { -- cgit v1.2.3 From 121b96cd9d7e6ec090331c4e7ef1298198bd8522 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sun, 11 Jan 2015 20:33:44 +0100 Subject: ARM: sun6i: Enable ARM arch timers The A31 has non-initialized architected timers, without CNTFRQ or CNTVOFF set by the Allwinner's bootloader. Use the new DT property for such case, and enable the arch timers. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot/dts/sun6i-a31.dtsi') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 4ae3e2eef679..0c17079b4636 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -87,6 +87,16 @@ }; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + arm,cpu-registers-not-fw-configured; + }; + cpus { enable-method = "allwinner,sun6i-a31"; #address-cells = <1>; -- cgit v1.2.3 From 4ec45cd3fc239fc93649ac34bd9463d8cdc26d84 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 24 Jan 2015 22:33:48 +0800 Subject: ARM: dts: sun6i: Add resistive touchscreen controller node to dtsi Now that we support the sun6i variant of the touchscreen controller, add the device node to the dtsi so we can use it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts/sun6i-a31.dtsi') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 0c17079b4636..805f67a2e02f 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -640,6 +640,13 @@ reg = <0x01c20ca0 0x20>; }; + rtp: rtp@01c25000 { + compatible = "allwinner,sun6i-a31-ts"; + reg = <0x01c25000 0x100>; + interrupts = ; + #thermal-sensor-cells = <0>; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; -- cgit v1.2.3