From a7311a3229d6a46a74dcc6812686636e47d37fa6 Mon Sep 17 00:00:00 2001 From: Juan Gutierrez Date: Tue, 24 Jan 2017 10:30:34 -0600 Subject: MXSCM-240-2 arm: dts: imx: make mmdc clk accessible from the busfreq driver The mmdc clk rate needs to be explicitly updated when moving to high audio rate by the busfreq module for the i.mx6q lpddr2 systems. In order to make the mmdc_ch0_axi clk visible by this driver, it needs to be included on the clocks/clock-names list. For the imx6dqscm-1gb-evb systems the clocks list for the busfreq module is originally inherited from imx6q.dtsi. To include the mmdc clk, the full clocks list plus the mmdc clk needs to be overwriten on the individual dts files. Signed-off-by: Juan Gutierrez --- arch/arm/boot/dts/imx6dqscm-1gb-evb-fix-ldo.dts | 4 ++++ arch/arm/boot/dts/imx6dqscm-1gb-evb-interleave-android-ldo.dts | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-evb-fix-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-evb-fix-ldo.dts index 04eacee73d52..48504ab7b01b 100644 --- a/arch/arm/boot/dts/imx6dqscm-1gb-evb-fix-ldo.dts +++ b/arch/arm/boot/dts/imx6dqscm-1gb-evb-fix-ldo.dts @@ -19,6 +19,10 @@ busfreq { fsl,max_ddr_freq = <400000000>; status = "okay"; + clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>, + <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>, <&clks 140>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", + "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "mmdc"; }; }; }; diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-evb-interleave-android-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-evb-interleave-android-ldo.dts index 6b0542195d2a..e0ca32841ced 100644 --- a/arch/arm/boot/dts/imx6dqscm-1gb-evb-interleave-android-ldo.dts +++ b/arch/arm/boot/dts/imx6dqscm-1gb-evb-interleave-android-ldo.dts @@ -15,6 +15,10 @@ busfreq { fsl,max_ddr_freq = <400000000>; status = "okay"; + clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>, + <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>, <&clks 140>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", + "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "mmdc"; }; }; }; -- cgit v1.2.3