From 52effd517ca3520d10311be1885f860414928e6f Mon Sep 17 00:00:00 2001 From: Chris Johnson Date: Tue, 14 Feb 2012 17:27:08 -0800 Subject: ARM: tegra: define/enable ARCH_HAS_SUSPEND_PAGETABLE For Tegra, the CPU suspend code path installs its own 1:1 pagetable setup once at init time. This pagetable is used by all CPUs doing suspend/resume. We want to use the common ARM code for CPU suspend/resume, but don't want the MMU reenable code to patch the current pagetable as it's shared (and could cause problems if the pagetable loads/stores were were interleaved). The installed pagetable already covers the cpu_resume_turn_mmu_on VA, so we're able to just use the existing pagetable. This sets up the CONFIG option to skip this part of the MMU reenable. Bug 929856 Change-Id: Ibbac258122df6def7f7a2d511778a6f11d474938 Signed-off-by: Chris Johnson Reviewed-on: http://git-master/r/92350 Reviewed-by: Sang-Hun Lee Tested-by: Sang-Hun Lee Reviewed-by: Thomas Cherry Reviewed-by: Krishna Reddy Reviewed-by: Ahung Cheng Tested-by: Ahung Cheng Reviewed-on: http://git-master/r/103205 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/kernel/sleep.S | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/kernel') diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S index e87f5f243012..714664b2b2ee 100644 --- a/arch/arm/kernel/sleep.S +++ b/arch/arm/kernel/sleep.S @@ -72,12 +72,14 @@ ENDPROC(cpu_suspend_abort) * r3 = L1 section flags */ ENTRY(cpu_resume_mmu) +#ifndef CONFIG_ARCH_HAS_SUSPEND_PAGETABLE adr r4, cpu_resume_turn_mmu_on mov r4, r4, lsr #20 orr r3, r3, r4, lsl #20 ldr r5, [r2, r4, lsl #2] @ save old mapping str r3, [r2, r4, lsl #2] @ setup 1:1 mapping for mmu code sub r2, r2, r1 +#endif ldr r3, =cpu_resume_after_mmu bic r1, r0, #CR_C @ ensure D-cache is disabled b cpu_resume_turn_mmu_on @@ -92,7 +94,9 @@ cpu_resume_turn_mmu_on: mov pc, r3 @ jump to virtual address ENDPROC(cpu_resume_turn_mmu_on) cpu_resume_after_mmu: +#ifndef CONFIG_ARCH_HAS_SUSPEND_PAGETABLE str r5, [r2, r4, lsl #2] @ restore old mapping +#endif mcr p15, 0, r0, c1, c0, 0 @ turn on D-cache mov r0, #0 @ return zero on success ldmfd sp!, {r4 - r11, pc} -- cgit v1.2.3