From 6861a197e2ed6dd05c0316ee2006730fbb6e7f9a Mon Sep 17 00:00:00 2001 From: Jonghwan Choi Date: Tue, 23 Aug 2011 16:27:17 +0900 Subject: ARM: EXYNOS4: Fix wrong pll type for vpll The PLL4650C is used for VPLL on EXYNOS4 so should be fixed. Signed-off-by: Jonghwan Choi [kgene.kim@samsung.com: added message] Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos4/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-exynos4') diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index 1561b036a9bf..79d6cd0c8e7b 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c @@ -1160,7 +1160,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void) vpllsrc = clk_get_rate(&clk_vpllsrc.clk); vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), - __raw_readl(S5P_VPLL_CON1), pll_4650); + __raw_readl(S5P_VPLL_CON1), pll_4650c); clk_fout_apll.ops = &exynos4_fout_apll_ops; clk_fout_mpll.rate = mpll; -- cgit v1.2.3