From c94e4ad2d5e0e5f4036cccaa0e6e773841e8f859 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 19 Aug 2016 16:24:36 +0100 Subject: ARM: document and update UNCACHEABLE_ADDR definitions Document the UNCACHEABLE_ADDR definitions for footbridge and SA1100 so that we know where they're located and/or what they're accessing. Change RiscPC to calculate the UNCACHEABLE_ADDR value from FLUSH_BASE as that's where we locate that. UNCACHEABLE_ADDR is used to perform an uncached access (ARMv4 terminology) necessary to force a CPU clock-switch to the memory- speed clock, as required for entering WFI. Signed-off-by: Russell King --- arch/arm/mach-footbridge/include/mach/hardware.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-footbridge') diff --git a/arch/arm/mach-footbridge/include/mach/hardware.h b/arch/arm/mach-footbridge/include/mach/hardware.h index 02f6d7a706b1..20d5ad781fe2 100644 --- a/arch/arm/mach-footbridge/include/mach/hardware.h +++ b/arch/arm/mach-footbridge/include/mach/hardware.h @@ -59,7 +59,7 @@ #define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5)) #define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6)) -#define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108) +#define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108) /* CSR_ROMBASEMASK */ /* PIC irq control */ -- cgit v1.2.3