From ee977c2c4f09c36e47c3113ecfe856fcce3ca7b9 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 10 Apr 2010 21:32:39 +0100 Subject: ixp4xx/vulcan: add PCI support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add PCI support for the Vulcan board, supporting USB and CF ports. The PC/104 bus (actually a hack on the second CarBus slot) is not currently supported. Signed-off-by: Marc Zyngier Cc: Imre Kaloz Cc: Krzysztof Halasa Signed-off-by: Krzysztof Hałasa --- arch/arm/mach-ixp4xx/vulcan-pci.c | 73 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 arch/arm/mach-ixp4xx/vulcan-pci.c (limited to 'arch/arm/mach-ixp4xx/vulcan-pci.c') diff --git a/arch/arm/mach-ixp4xx/vulcan-pci.c b/arch/arm/mach-ixp4xx/vulcan-pci.c new file mode 100644 index 000000000000..f3111c6840ef --- /dev/null +++ b/arch/arm/mach-ixp4xx/vulcan-pci.c @@ -0,0 +1,73 @@ +/* + * arch/arch/mach-ixp4xx/vulcan-pci.c + * + * Vulcan board-level PCI initialization + * + * Copyright (C) 2010 Marc Zyngier + * + * based on ixdp425-pci.c: + * Copyright (C) 2002 Intel Corporation. + * Copyright (C) 2003-2004 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include + +/* PCI controller GPIO to IRQ pin mappings */ +#define INTA 2 +#define INTB 3 + +void __init vulcan_pci_preinit(void) +{ +#ifndef CONFIG_IXP4XX_INDIRECT_PCI + /* + * Cardbus bridge wants way more than the SoC can actually offer, + * and leaves the whole PCI bus in a mess. Artificially limit it + * to 8MB per region. Of course indirect mode doesn't have this + * limitation... + */ + pci_cardbus_mem_size = SZ_8M; + pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n", + (int)(pci_cardbus_mem_size >> 20)); +#endif + set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + ixp4xx_pci_preinit(); +} + +static int __init vulcan_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + if (slot == 1) + return IXP4XX_GPIO_IRQ(INTA); + + if (slot == 2) + return IXP4XX_GPIO_IRQ(INTB); + + return -1; +} + +struct hw_pci vulcan_pci __initdata = { + .nr_controllers = 1, + .preinit = vulcan_pci_preinit, + .swizzle = pci_std_swizzle, + .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, + .map_irq = vulcan_map_irq, +}; + +int __init vulcan_pci_init(void) +{ + if (machine_is_arcom_vulcan()) + pci_common_init(&vulcan_pci); + return 0; +} + +subsys_initcall(vulcan_pci_init); -- cgit v1.2.3