From c17afc0aa69615b4c2250b6476431c4d601890a0 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 1 Jun 2011 10:44:51 +0100 Subject: ARM: S3C64XX: Ensure VIC based IRQs can be resumed from Any interrupts based off either of the onboard VICs cannot be resumed from any more as it seems set_irq_wake() is now checking the error code returned from the low level handlers and not setting the wake-state on the interrupt if this fails. Ensure that we make the interrupts we can resume from available on the VIC and then do a pre-sleep mask of all the VIC interrupts as the wakeup is handled by a seperate block. Signed-off-by: Ben Dooks Signed-off-by: Mark Brown Signed-off-by: Kukjin Kim --- arch/arm/mach-s3c64xx/include/mach/pm-core.h | 2 +- arch/arm/mach-s3c64xx/irq.c | 12 ++++++++++-- 2 files changed, 11 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-s3c64xx') diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h index 1e9f20f0bb7b..4ed0f582d222 100644 --- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h +++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h @@ -53,7 +53,7 @@ static inline void s3c_pm_arch_show_resume_irqs(void) * the IRQ wake controls depending on the CPU we are running on */ #define s3c_irqwake_eintallow ((1 << 28) - 1) -#define s3c_irqwake_intallow (0) +#define s3c_irqwake_intallow (~0) static inline void s3c_pm_arch_update_uart(void __iomem *regs, struct pm_uart_save *save) diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c index 97660c8141ae..75d9a0e49193 100644 --- a/arch/arm/mach-s3c64xx/irq.c +++ b/arch/arm/mach-s3c64xx/irq.c @@ -48,14 +48,22 @@ static struct s3c_uart_irq uart_irqs[] = { }, }; +/* setup the sources the vic should advertise resume for, even though it + * is not doing the wake (set_irq_wake needs to be valid) */ +#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE)) +#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \ + 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \ + 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \ + 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \ + 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE)) void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) { printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); /* initialise the pair of VICs */ - vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0); - vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0); + vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME); + vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME); /* add the timer sub-irqs */ s3c_init_vic_timer_irq(5, IRQ_TIMER0); -- cgit v1.2.3 From 1bac282af43d81d826ef25945a35536fa9bd041d Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 1 Jun 2011 10:44:50 +0100 Subject: ARM: SAMSUNG: Add support for pre-sleep/post-restore gpio control Add a callback so that per-arch can do pre-sleep and post-resume gpio configuration so that for the S3C64XX, the GPIO configuration is restored before the sleep mode is cleared. For the S3C64XX case, it means that the GPIOs get set back to normal operation after the restore code puts the original configurations back in after the Signed-off-by: Ben Dooks Signed-off-by: Mark Brown Signed-off-by: Kukjin Kim --- arch/arm/mach-s3c64xx/include/mach/pm-core.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm/mach-s3c64xx') diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h index 4ed0f582d222..38659bebe4b1 100644 --- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h +++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h @@ -96,3 +96,20 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, save->ucon = new_ucon; } } + +static inline void s3c_pm_restored_gpios(void) +{ + /* ensure sleep mode has been cleared from the system */ + + __raw_writel(0, S3C64XX_SLPEN); +} + +static inline void s3c_pm_saved_gpios(void) +{ + /* turn on the sleep mode and keep it there, as it seems that during + * suspend the xCON registers get re-set and thus you can end up with + * problems between going to sleep and resuming. + */ + + __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN); +} -- cgit v1.2.3 From 2d21237e38120c2dfbc047b39aa2a56df67bdeec Mon Sep 17 00:00:00 2001 From: Sangbeom Kim Date: Thu, 21 Jul 2011 14:15:11 +0900 Subject: ARM: SAMSUNG: Add IRQ_I2S0 definition To handle i2s0 interrupt and To fix compilation error adds IRQ_I2S0 for exynos4, s3c64xx, s5p64x0 Signed-off-by: Sangbeom Kim [kgene.kim@samsung.com: Fixed build failure due to inclusion] Signed-off-by: Kukjin Kim --- arch/arm/mach-s3c64xx/include/mach/irqs.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-s3c64xx') diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h index 8e2df26cf14a..bf7cc82ea6d0 100644 --- a/arch/arm/mach-s3c64xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h @@ -215,6 +215,7 @@ /* Compatibility */ #define IRQ_ONENAND IRQ_ONENAND0 +#define IRQ_I2S0 IRQ_S3C6410_IIS #endif /* __ASM_MACH_S3C64XX_IRQS_H */ -- cgit v1.2.3