From bf55e0a48f8ee086c71d1a9de1f0eeee7501b1c4 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 25 Mar 2015 11:27:47 +0000 Subject: ARM: socfpga: enable big endian for secondary core(s) Update the secondary code to allow the secondary boot to work when the system is running big endian. Signed-off-by: Ben Dooks Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/headsmp.S | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-socfpga') diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S index f65ea0af4af3..a580dcdec526 100644 --- a/arch/arm/mach-socfpga/headsmp.S +++ b/arch/arm/mach-socfpga/headsmp.S @@ -10,6 +10,7 @@ #include #include #include +#include .arch armv7-a @@ -18,12 +19,14 @@ ENTRY(secondary_trampoline) * Thus, we can just subtract the PAGE_OFFSET to get the physical * address of &cpu1start_addr. This would not work for platforms * where the physical memory does not start at 0x0. - */ + */ +ARM_BE8(setend be) adr r0, 1f ldmia r0, {r1, r2} sub r2, r2, #PAGE_OFFSET ldr r3, [r2] ldr r4, [r3] +ARM_BE8(rev r4, r4) bx r4 .align -- cgit v1.2.3 From 3c5ac3f3921b0f905a94185065a7a149c46c5681 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 25 Mar 2015 11:27:48 +0000 Subject: ARM: socfpga: support big endian for socfpga Now the debug and platsmp.S are fixed for big endian, the architecture can now advertise big endian support. Signed-off-by: Ben Dooks Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-socfpga') diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index b5f8d75d51a0..f420a1b200c2 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -1,5 +1,6 @@ config ARCH_SOCFPGA bool "Altera SOCFPGA family" if ARCH_MULTI_V7 + select ARCH_SUPPORTS_BIG_ENDIAN select ARM_AMBA select ARM_GIC select CACHE_L2X0 -- cgit v1.2.3 From 65ce7a37ec23c9e7878bd77e2f75b1eb9d8926e3 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 9 Mar 2015 22:10:02 -0500 Subject: ARM: socfpga: remove the need to map uart_io_desc All the necessary debug uart mapping is already being done in debug_ll_io_init, there's no need for it here. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/socfpga.c | 9 --------- 1 file changed, 9 deletions(-) (limited to 'arch/arm/mach-socfpga') diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index f5e597c207b9..358f2c712979 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -39,13 +39,6 @@ static struct map_desc scu_io_desc __initdata = { .type = MT_DEVICE, }; -static struct map_desc uart_io_desc __initdata = { - .virtual = 0xfec02000, - .pfn = __phys_to_pfn(0xffc02000), - .length = SZ_8K, - .type = MT_DEVICE, -}; - static void __init socfpga_scu_map_io(void) { unsigned long base; @@ -60,8 +53,6 @@ static void __init socfpga_scu_map_io(void) static void __init socfpga_map_io(void) { socfpga_scu_map_io(); - iotable_init(&uart_io_desc, 1); - early_printk("Early printk initialized\n"); } void __init socfpga_sysmgr_init(void) -- cgit v1.2.3 From 122694a0c71281cf2b349af41309c3caf5f31d61 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 12 May 2015 16:49:21 -0500 Subject: ARM: socfpga: use of_iomap to map the SCU Use of_iomap to map the "arm,cortex-a9-scu". By doing this, we can remove map_io in socfpga.c. Also, we can remove socfpga_smp_init_cpus, as arm_dt_init_cpu_maps is already doing the CPU mapping. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/core.h | 1 - arch/arm/mach-socfpga/platsmp.c | 33 ++++++++++----------------------- arch/arm/mach-socfpga/socfpga.c | 25 ------------------------- 3 files changed, 10 insertions(+), 49 deletions(-) (limited to 'arch/arm/mach-socfpga') diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index a0f3b1cd497c..5913bbb50036 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h @@ -32,7 +32,6 @@ #define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */ extern void socfpga_secondary_startup(void); -extern void __iomem *socfpga_scu_base_addr; extern void socfpga_init_clocks(void); extern void socfpga_sysmgr_init(void); diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c index c64d89b7c0ca..7886eaeb6723 100644 --- a/arch/arm/mach-socfpga/platsmp.c +++ b/arch/arm/mach-socfpga/platsmp.c @@ -54,32 +54,20 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) return 0; } -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ -static void __init socfpga_smp_init_cpus(void) +static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus) { - unsigned int i, ncores; - - ncores = scu_get_core_count(socfpga_scu_base_addr); - - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); + struct device_node *np; + void __iomem *socfpga_scu_base_addr; - /* sanity check */ - if (ncores > num_possible_cpus()) { - pr_warn("socfpga: no. of cores (%d) greater than configured" - "maximum of %d - clipping\n", ncores, num_possible_cpus()); - ncores = num_possible_cpus(); + np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); + if (!np) { + pr_err("%s: missing scu\n", __func__); + return; } - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); -} - -static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus) -{ + socfpga_scu_base_addr = of_iomap(np, 0); + if (!socfpga_scu_base_addr) + return; scu_enable(socfpga_scu_base_addr); } @@ -96,7 +84,6 @@ static void socfpga_cpu_die(unsigned int cpu) } struct smp_operations socfpga_smp_ops __initdata = { - .smp_init_cpus = socfpga_smp_init_cpus, .smp_prepare_cpus = socfpga_smp_prepare_cpus, .smp_boot_secondary = socfpga_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 358f2c712979..b63dec6e740c 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -27,34 +27,10 @@ #include "core.h" -void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE)); void __iomem *sys_manager_base_addr; void __iomem *rst_manager_base_addr; unsigned long socfpga_cpu1start_addr; -static struct map_desc scu_io_desc __initdata = { - .virtual = SOCFPGA_SCU_VIRT_BASE, - .pfn = 0, /* run-time */ - .length = SZ_8K, - .type = MT_DEVICE, -}; - -static void __init socfpga_scu_map_io(void) -{ - unsigned long base; - - /* Get SCU base */ - asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); - - scu_io_desc.pfn = __phys_to_pfn(base); - iotable_init(&scu_io_desc, 1); -} - -static void __init socfpga_map_io(void) -{ - socfpga_scu_map_io(); -} - void __init socfpga_sysmgr_init(void) { struct device_node *np; @@ -103,7 +79,6 @@ DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA") .l2c_aux_val = 0, .l2c_aux_mask = ~0, .smp = smp_ops(socfpga_smp_ops), - .map_io = socfpga_map_io, .init_irq = socfpga_init_irq, .restart = socfpga_cyclone5_restart, .dt_compat = altera_dt_match, -- cgit v1.2.3 From 5f763ef80d4dff7f2aa519a31472b03499e2c2e1 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 2 Jun 2015 21:14:01 -0500 Subject: ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5 Convert cyclone5/arria5 to use CPU_METHOD_OF_DECLARE for smp operations. Signed-off-by: Dinh Nguyen Signed-off-by: Kevin Hilman --- arch/arm/mach-socfpga/core.h | 1 - arch/arm/mach-socfpga/platsmp.c | 4 +++- arch/arm/mach-socfpga/socfpga.c | 1 - 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-socfpga') diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index 5913bbb50036..38e5cbf37f45 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h @@ -39,7 +39,6 @@ extern void socfpga_sysmgr_init(void); extern void __iomem *sys_manager_base_addr; extern void __iomem *rst_manager_base_addr; -extern struct smp_operations socfpga_smp_ops; extern char secondary_trampoline, secondary_trampoline_end; extern unsigned long socfpga_cpu1start_addr; diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c index 7886eaeb6723..b84c1a12d3ae 100644 --- a/arch/arm/mach-socfpga/platsmp.c +++ b/arch/arm/mach-socfpga/platsmp.c @@ -83,10 +83,12 @@ static void socfpga_cpu_die(unsigned int cpu) cpu_do_idle(); } -struct smp_operations socfpga_smp_ops __initdata = { +static struct smp_operations socfpga_smp_ops __initdata = { .smp_prepare_cpus = socfpga_smp_prepare_cpus, .smp_boot_secondary = socfpga_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = socfpga_cpu_die, #endif }; + +CPU_METHOD_OF_DECLARE(socfpga_smp, "altr,socfpga-smp", &socfpga_smp_ops); diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index b63dec6e740c..a154920b06ab 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -78,7 +78,6 @@ static const char *altera_dt_match[] = { DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA") .l2c_aux_val = 0, .l2c_aux_mask = ~0, - .smp = smp_ops(socfpga_smp_ops), .init_irq = socfpga_init_irq, .restart = socfpga_cyclone5_restart, .dt_compat = altera_dt_match, -- cgit v1.2.3 From 45be0cdb5323d6f2b4005a4d9263a72eac2040cd Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 2 Jun 2015 21:14:02 -0500 Subject: ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10 Add boot_secondary implementation for the Arria10 platform. Bringing up the secondary core on the Arria 10 platform is pretty similar to the Cyclone/Arria 5 platform, with the exception of the following differences: - Register offset to bringup CPU1 out of reset is different. - The cpu1-start-addr for Arria10 contains an additional nibble. Signed-off-by: Dinh Nguyen Signed-off-by: Kevin Hilman --- arch/arm/mach-socfpga/core.h | 2 ++ arch/arm/mach-socfpga/platsmp.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) (limited to 'arch/arm/mach-socfpga') diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index 38e5cbf37f45..27e7c65093c0 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h @@ -25,6 +25,8 @@ #define SOCFPGA_RSTMGR_MODPERRST 0x14 #define SOCFPGA_RSTMGR_BRGMODRST 0x1c +#define SOCFPGA_A10_RSTMGR_MODMPURST 0x20 + /* System Manager bits */ #define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c index b84c1a12d3ae..5454e9ce31ea 100644 --- a/arch/arm/mach-socfpga/platsmp.c +++ b/arch/arm/mach-socfpga/platsmp.c @@ -54,6 +54,29 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) return 0; } +static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; + + if (socfpga_cpu1start_addr) { + writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr + + SOCFPGA_A10_RSTMGR_MODMPURST); + memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); + + writel(virt_to_phys(socfpga_secondary_startup), + sys_manager_base_addr + (socfpga_cpu1start_addr & 0x00000fff)); + + flush_cache_all(); + smp_wmb(); + outer_clean_range(0, trampoline_size); + + /* This will release CPU #1 out of reset. */ + writel(0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_MODMPURST); + } + + return 0; +} + static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus) { struct device_node *np; @@ -91,4 +114,13 @@ static struct smp_operations socfpga_smp_ops __initdata = { #endif }; +static struct smp_operations socfpga_a10_smp_ops __initdata = { + .smp_prepare_cpus = socfpga_smp_prepare_cpus, + .smp_boot_secondary = socfpga_a10_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = socfpga_cpu_die, +#endif +}; + CPU_METHOD_OF_DECLARE(socfpga_smp, "altr,socfpga-smp", &socfpga_smp_ops); +CPU_METHOD_OF_DECLARE(socfpga_a10_smp, "altr,socfpga-a10-smp", &socfpga_a10_smp_ops); -- cgit v1.2.3 From 44fd8c7d4005f660f48679439f0a54225ba234a4 Mon Sep 17 00:00:00 2001 From: Alan Tull Date: Fri, 5 Jun 2015 08:24:52 -0500 Subject: ARM: socfpga: support suspend to ram Add code that requests that the sdr controller go into self-refresh mode. This code is run from ocram. Suspend-to-RAM and EDAC support are mutually exclusive on SOCFPGA. If the EDAC is enabled, it will prevent the platform from going into suspend. Example of how to request to suspend to ram: $ echo enabled > \ /sys/devices/soc/ffc02000.serial0/tty/ttyS0/power/wakeup $ echo -n mem > /sys/power/state Signed-off-by: Alan Tull Signed-off-by: Dinh Nguyen Signed-off-by: Kevin Hilman --- arch/arm/mach-socfpga/Kconfig | 10 ++- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/core.h | 6 +- arch/arm/mach-socfpga/pm.c | 149 +++++++++++++++++++++++++++++++++++ arch/arm/mach-socfpga/self-refresh.S | 136 ++++++++++++++++++++++++++++++++ arch/arm/mach-socfpga/socfpga.c | 6 +- 6 files changed, 305 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-socfpga/pm.c create mode 100644 arch/arm/mach-socfpga/self-refresh.S (limited to 'arch/arm/mach-socfpga') diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index f420a1b200c2..90efdeb56be5 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -1,4 +1,4 @@ -config ARCH_SOCFPGA +menuconfig ARCH_SOCFPGA bool "Altera SOCFPGA family" if ARCH_MULTI_V7 select ARCH_SUPPORTS_BIG_ENDIAN select ARM_AMBA @@ -9,3 +9,11 @@ config ARCH_SOCFPGA select HAVE_ARM_SCU select HAVE_ARM_TWD if SMP select MFD_SYSCON + +if ARCH_SOCFPGA +config SOCFPGA_SUSPEND + bool "Suspend to RAM on SOCFPGA" + help + Select this if you want to enable Suspend-to-RAM on SOCFPGA + platforms. +endif diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 6dd7a93a90fe..b8f9e238e4ab 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -4,3 +4,4 @@ obj-y := socfpga.o obj-$(CONFIG_SMP) += headsmp.o platsmp.o +obj-$(CONFIG_SOCFPGA_SUSPEND) += pm.o self-refresh.o diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index 27e7c65093c0..2484179c2b47 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h @@ -1,6 +1,6 @@ /* * Copyright 2012 Pavel Machek - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012-2015 Altera Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -40,6 +40,10 @@ extern void socfpga_sysmgr_init(void); extern void __iomem *sys_manager_base_addr; extern void __iomem *rst_manager_base_addr; +extern void __iomem *sdr_ctl_base_addr; + +u32 socfpga_sdram_self_refresh(u32 sdr_base); +extern unsigned int socfpga_sdram_self_refresh_sz; extern char secondary_trampoline, secondary_trampoline_end; diff --git a/arch/arm/mach-socfpga/pm.c b/arch/arm/mach-socfpga/pm.c new file mode 100644 index 000000000000..1ed89fc2b7a8 --- /dev/null +++ b/arch/arm/mach-socfpga/pm.c @@ -0,0 +1,149 @@ +/* + * arch/arm/mach-socfpga/pm.c + * + * Copyright (C) 2014-2015 Altera Corporation. All rights reserved. + * + * with code from pm-imx6.c + * Copyright 2011-2014 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "core.h" + +/* Pointer to function copied to ocram */ +static u32 (*socfpga_sdram_self_refresh_in_ocram)(u32 sdr_base); + +static int socfpga_setup_ocram_self_refresh(void) +{ + struct platform_device *pdev; + phys_addr_t ocram_pbase; + struct device_node *np; + struct gen_pool *ocram_pool; + unsigned long ocram_base; + void __iomem *suspend_ocram_base; + int ret = 0; + + np = of_find_compatible_node(NULL, NULL, "mmio-sram"); + if (!np) { + pr_err("%s: Unable to find mmio-sram in dtb\n", __func__); + return -ENODEV; + } + + pdev = of_find_device_by_node(np); + if (!pdev) { + pr_warn("%s: failed to find ocram device!\n", __func__); + ret = -ENODEV; + goto put_node; + } + + ocram_pool = dev_get_gen_pool(&pdev->dev); + if (!ocram_pool) { + pr_warn("%s: ocram pool unavailable!\n", __func__); + ret = -ENODEV; + goto put_node; + } + + ocram_base = gen_pool_alloc(ocram_pool, socfpga_sdram_self_refresh_sz); + if (!ocram_base) { + pr_warn("%s: unable to alloc ocram!\n", __func__); + ret = -ENOMEM; + goto put_node; + } + + ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base); + + suspend_ocram_base = __arm_ioremap_exec(ocram_pbase, + socfpga_sdram_self_refresh_sz, + false); + if (!suspend_ocram_base) { + pr_warn("%s: __arm_ioremap_exec failed!\n", __func__); + ret = -ENOMEM; + goto put_node; + } + + /* Copy the code that puts DDR in self refresh to ocram */ + socfpga_sdram_self_refresh_in_ocram = + (void *)fncpy(suspend_ocram_base, + &socfpga_sdram_self_refresh, + socfpga_sdram_self_refresh_sz); + + WARN(!socfpga_sdram_self_refresh_in_ocram, + "could not copy function to ocram"); + if (!socfpga_sdram_self_refresh_in_ocram) + ret = -EFAULT; + +put_node: + of_node_put(np); + + return ret; +} + +static int socfpga_pm_suspend(unsigned long arg) +{ + u32 ret; + + if (!sdr_ctl_base_addr) + return -EFAULT; + + ret = socfpga_sdram_self_refresh_in_ocram((u32)sdr_ctl_base_addr); + + pr_debug("%s self-refresh loops request=%d exit=%d\n", __func__, + ret & 0xffff, (ret >> 16) & 0xffff); + + return 0; +} + +static int socfpga_pm_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + case PM_SUSPEND_MEM: + outer_disable(); + cpu_suspend(0, socfpga_pm_suspend); + outer_resume(); + break; + default: + return -EINVAL; + } + return 0; +} + +static const struct platform_suspend_ops socfpga_pm_ops = { + .valid = suspend_valid_only_mem, + .enter = socfpga_pm_enter, +}; + +static int __init socfpga_pm_init(void) +{ + int ret; + + ret = socfpga_setup_ocram_self_refresh(); + if (ret) + return ret; + + suspend_set_ops(&socfpga_pm_ops); + pr_info("SoCFPGA initialized for DDR self-refresh during suspend.\n"); + + return 0; +} +arch_initcall(socfpga_pm_init); diff --git a/arch/arm/mach-socfpga/self-refresh.S b/arch/arm/mach-socfpga/self-refresh.S new file mode 100644 index 000000000000..f2d7f883e33d --- /dev/null +++ b/arch/arm/mach-socfpga/self-refresh.S @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2014-2015 Altera Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ +#include +#include + +#define MAX_LOOP_COUNT 1000 + +/* Register offset */ +#define SDR_CTRLGRP_LOWPWREQ_ADDR 0x54 +#define SDR_CTRLGRP_LOWPWRACK_ADDR 0x58 + +/* Bitfield positions */ +#define SELFRSHREQ_POS 3 +#define SELFRSHREQ_MASK 0x8 + +#define SELFRFSHACK_POS 1 +#define SELFRFSHACK_MASK 0x2 + + /* + * This code assumes that when the bootloader configured + * the sdram controller for the DDR on the board it + * configured the following fields depending on the DDR + * vendor/configuration: + * + * sdr.ctrlcfg.lowpwreq.selfrfshmask + * sdr.ctrlcfg.lowpwrtiming.clkdisablecycles + * sdr.ctrlcfg.dramtiming4.selfrfshexit + */ + + .arch armv7-a + .text + .align 3 + + /* + * socfpga_sdram_self_refresh + * + * r0 : sdr_ctl_base_addr + * r1 : temp storage of return value + * r2 : temp storage of register values + * r3 : loop counter + * + * return value: lower 16 bits: loop count going into self refresh + * upper 16 bits: loop count exiting self refresh + */ +ENTRY(socfpga_sdram_self_refresh) + /* Enable dynamic clock gating in the Power Control Register. */ + mrc p15, 0, r2, c15, c0, 0 + orr r2, r2, #1 + mcr p15, 0, r2, c15, c0, 0 + + /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */ + ldr r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR] + orr r2, r2, #SELFRSHREQ_MASK + str r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR] + + /* Poll until sdr.ctrlgrp.lowpwrack.selfrfshack == 1 or hit max loops */ + mov r3, #0 +while_ack_0: + ldr r2, [r0, #SDR_CTRLGRP_LOWPWRACK_ADDR] + and r2, r2, #SELFRFSHACK_MASK + cmp r2, #SELFRFSHACK_MASK + beq ack_1 + + add r3, #1 + cmp r3, #MAX_LOOP_COUNT + bne while_ack_0 + +ack_1: + mov r1, r3 + + /* + * Execute an ISB instruction to ensure that all of the + * CP15 register changes have been committed. + */ + isb + + /* + * Execute a barrier instruction to ensure that all cache, + * TLB and branch predictor maintenance operations issued + * by any CPU in the cluster have completed. + */ + dsb + dmb + + wfi + + /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */ + ldr r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR] + bic r2, r2, #SELFRSHREQ_MASK + str r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR] + + /* Poll until sdr.ctrlgrp.lowpwrack.selfrfshack == 0 or hit max loops */ + mov r3, #0 +while_ack_1: + ldr r2, [r0, #SDR_CTRLGRP_LOWPWRACK_ADDR] + and r2, r2, #SELFRFSHACK_MASK + cmp r2, #SELFRFSHACK_MASK + bne ack_0 + + add r3, #1 + cmp r3, #MAX_LOOP_COUNT + bne while_ack_1 + +ack_0: + /* + * Prepare return value: + * Shift loop count for exiting self refresh into upper 16 bits. + * Leave loop count for requesting self refresh in lower 16 bits. + */ + mov r3, r3, lsl #16 + add r1, r1, r3 + + /* Disable dynamic clock gating in the Power Control Register. */ + mrc p15, 0, r2, c15, c0, 0 + bic r2, r2, #1 + mcr p15, 0, r2, c15, c0, 0 + + mov r0, r1 @ return value + bx lr @ return + +ENDPROC(socfpga_sdram_self_refresh) +ENTRY(socfpga_sdram_self_refresh_sz) + .word . - socfpga_sdram_self_refresh diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index a154920b06ab..19643a756c48 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012-2015 Altera Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,6 +29,7 @@ void __iomem *sys_manager_base_addr; void __iomem *rst_manager_base_addr; +void __iomem *sdr_ctl_base_addr; unsigned long socfpga_cpu1start_addr; void __init socfpga_sysmgr_init(void) @@ -49,6 +50,9 @@ void __init socfpga_sysmgr_init(void) np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr"); rst_manager_base_addr = of_iomap(np, 0); + + np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl"); + sdr_ctl_base_addr = of_iomap(np, 0); } static void __init socfpga_init_irq(void) -- cgit v1.2.3 From 89b8da06ba302dd130df60df7964ccd3ab151cd6 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Thu, 11 Jun 2015 15:41:58 -0700 Subject: ARM: socfpga: fix build error due to secondary_startup After commit 02b4e2756e01 (ARM: v7 setup function should invalidate L1 cache) the soc specific secondary_startup is removed, causing build failures: ../arch/arm/mach-socfpga/platsmp.c: In function 'socfpga_a10_boot_secondary': ../arch/arm/mach-socfpga/platsmp.c:66:140: error: 'socfpga_secondary_startup' undeclared (first use in this function) ../arch/arm/mach-socfpga/platsmp.c:66:140: note: each undeclared identifier is reported only once for each function it appears in To fix, use the generic secondary_startup. Cc: Dinh Nguyen Signed-off-by: Kevin Hilman --- arch/arm/mach-socfpga/platsmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-socfpga') diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c index 5454e9ce31ea..7ed612793323 100644 --- a/arch/arm/mach-socfpga/platsmp.c +++ b/arch/arm/mach-socfpga/platsmp.c @@ -63,7 +63,7 @@ static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct *idle SOCFPGA_A10_RSTMGR_MODMPURST); memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); - writel(virt_to_phys(socfpga_secondary_startup), + writel(virt_to_phys(secondary_startup), sys_manager_base_addr + (socfpga_cpu1start_addr & 0x00000fff)); flush_cache_all(); -- cgit v1.2.3