From 0ace7d3bd1f232d074d032bdbe7aa855a4ce4085 Mon Sep 17 00:00:00 2001 From: Pavan Kunapuli Date: Wed, 9 May 2012 18:59:19 +0530 Subject: arm: tegra: sdhci: Limit eMMC,SDIO,SD DDR clock Limit eMMC, SD and SDIO DDR mode clock to 41MHz. Bug 967719 Change-Id: Iaccc5b771b81b15226f87684b547ad1fb7dd38d3 Signed-off-by: Pavan Kunapuli Reviewed-on: http://git-master/r/101173 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan --- arch/arm/mach-tegra/board-cardhu-sdhci.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-tegra/board-cardhu-sdhci.c') diff --git a/arch/arm/mach-tegra/board-cardhu-sdhci.c b/arch/arm/mach-tegra/board-cardhu-sdhci.c index e203e6cf34a5..c4e631ddc108 100644 --- a/arch/arm/mach-tegra/board-cardhu-sdhci.c +++ b/arch/arm/mach-tegra/board-cardhu-sdhci.c @@ -153,6 +153,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = { .wp_gpio = -1, .power_gpio = -1, .tap_delay = 0x0F, + .ddr_clk_limit = 41000000, /* .is_voltage_switch_supported = false, .vdd_rail_name = NULL, .slot_rail_name = NULL, @@ -167,6 +168,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = { .wp_gpio = CARDHU_SD_WP, .power_gpio = -1, .tap_delay = 0x0F, + .ddr_clk_limit = 41000000, /* .is_voltage_switch_supported = true, .vdd_rail_name = "vddio_sdmmc1", .slot_rail_name = "vddio_sd_slot", @@ -182,11 +184,11 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = { .power_gpio = -1, .is_8bit = 1, .tap_delay = 0x0F, + .ddr_clk_limit = 41000000, .mmc_data = { .built_in = 1, } -/* .tap_delay = 6, - .is_voltage_switch_supported = false, +/* .is_voltage_switch_supported = false, .vdd_rail_name = NULL, .slot_rail_name = NULL, .vdd_max_uv = -1, -- cgit v1.2.3