From e43a17627f3e7151170082660040d9679c5fa9b1 Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Thu, 12 Jan 2012 17:39:04 -0800 Subject: ARM: tegra: clock: Auto-detect PLLP rate in uart init Tegra3 platform may boot with one of the predefined fixed PLLP (peripheral PLL) output rates: 216MHz, 408MHz, or 204MHz. This commit implements auto-detection of PLLP rate, and debug uart configuration during kernel uart initialization. Bug 928260 Change-Id: I3fac4c462f28ac3dc1c72c0cc0f8f87fa0a809c4 Reviewed-on: http://git-master/r/75849 Reviewed-by: Krishna Reddy Signed-off-by: Alex Frid Signed-off-by: Varun Wadekar Reviewed-on: http://git-master/r/77294 Reviewed-by: Automatic_Commit_Validation_User --- arch/arm/mach-tegra/board-cardhu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-tegra/board-cardhu.c') diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c index bea6a6f19882..8bf2501c29c6 100644 --- a/arch/arm/mach-tegra/board-cardhu.c +++ b/arch/arm/mach-tegra/board-cardhu.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/board-cardhu.c * - * Copyright (c) 2011, NVIDIA Corporation. + * Copyright (c) 2011-2012, NVIDIA Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -346,6 +346,8 @@ static void __init uart_debug_init(void) (board_info.board_id == BOARD_E1257)) debug_port_id = 1; } + + tegra_init_debug_uart_rate(); switch (debug_port_id) { case 0: /* UARTA is the debug port. */ -- cgit v1.2.3