From fe9861c7723e9624cf71fe7af320785c7b833196 Mon Sep 17 00:00:00 2001
From: Scott Williams <scwilliams@nvidia.com>
Date: Fri, 14 Jan 2011 16:19:23 -0800
Subject: arm: tegra: Enable Tegra3 APB DMA channels 16-31

Original-Change-Id: Ia098e22789f4817e14ac34de01f8d990b4b4d29b
Reviewed-on: http://git-master/r/15975
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: If9677ac2190d8d2266ee40d011f5841e97838522

Rebase-Id: R2a64c748b9d73d8c833ef09aa3c7d19b7eee532b
---
 arch/arm/mach-tegra/dma.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'arch/arm/mach-tegra/dma.c')

diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
index 0ddb2c7b24df..c5b5247c2372 100644
--- a/arch/arm/mach-tegra/dma.c
+++ b/arch/arm/mach-tegra/dma.c
@@ -96,7 +96,11 @@
 #define APB_SEQ_WRAP_SHIFT			16
 #define APB_SEQ_WRAP_MASK			(0x7<<APB_SEQ_WRAP_SHIFT)
 
-#define TEGRA_SYSTEM_DMA_CH_NR			16	/* !!!FIXME!!! T30 has 32 channels .............. */
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+#define TEGRA_SYSTEM_DMA_CH_NR			16
+#else
+#define TEGRA_SYSTEM_DMA_CH_NR			32
+#endif
 #define TEGRA_SYSTEM_DMA_AVP_CH_NUM		4
 #define TEGRA_SYSTEM_DMA_CH_MIN			0
 #define TEGRA_SYSTEM_DMA_CH_MAX	\
-- 
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