From b29689a4794086b37fc34461cbedcedbf952634f Mon Sep 17 00:00:00 2001 From: Puneet Saxena Date: Thu, 3 Nov 2011 15:31:23 +0530 Subject: ARM: tegra: power: Correct PL310 virt addr calculation PL310 virtual address was calculated using PPSB virtual/phy address. It should be done using CPU virtual/phy address. This causes TEGRA_PL310_VIRT value to get overlapped with virtual kerenl memory map's Vmalloc region on whistler. Bug 881831 Bug 867094 Change-Id: Ifaeeb9291553af59453f0041ad7cb1fe9d27979b Signed-off-by: Puneet Saxena Signed-off-by: Prashant Gaikwad Reviewed-on: http://git-master/r/62097 Tested-by: Bharat Nihalani Reviewed-by: Scott Williams Reviewed-by: Bharat Nihalani Reviewed-by: Mayuresh Kulkarni Rebase-Id: Ra5a6165c8a02f0ac130bbaac4a477b901ceea62f --- arch/arm/mach-tegra/sleep-t2.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-tegra/sleep-t2.S') diff --git a/arch/arm/mach-tegra/sleep-t2.S b/arch/arm/mach-tegra/sleep-t2.S index f3bd0ca9450a..298f0a13e9fb 100644 --- a/arch/arm/mach-tegra/sleep-t2.S +++ b/arch/arm/mach-tegra/sleep-t2.S @@ -70,7 +70,6 @@ #define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT) #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS + IO_CPU_VIRT) #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS + IO_PPSB_VIRT) -#define TEGRA_PL310_VIRT (TEGRA_ARM_PL310_BASE - IO_PPSB_PHYS + IO_PPSB_VIRT) #ifdef CONFIG_HOTPLUG_CPU /* @@ -262,7 +261,8 @@ ENTRY(tegra2_sleep_wfi) #ifdef CONFIG_CACHE_L2X0 /* Issue a PL310 cache sync operation */ dsb - mov32 r2, TEGRA_PL310_VIRT + 0x730 @ cache sync + mov32 r2, TEGRA_PL310_VIRT + movw r1, 0x730 @ cache sync add r2, r2, r1 mov r1, #0 str r1, [r2] -- cgit v1.2.3