From d177f4e51d81f29699f6041909c26ae43a27bd76 Mon Sep 17 00:00:00 2001 From: Scott Williams Date: Mon, 25 Jul 2011 14:55:25 -0700 Subject: ARM: tegra: power: Split CPU context save and coherency exit Separate the CPU context save and CPU coherency exit into separate functions. Change-Id: I7c5376677e293342b02b5bebdef6be2610522936 Signed-off-by: Scott Williams Signed-off-by: Dan Willemsen Rebase-Id: R17eb40d551e797448410cf6220dfba122faa702d --- arch/arm/mach-tegra/sleep-t2.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-tegra/sleep-t2.S') diff --git a/arch/arm/mach-tegra/sleep-t2.S b/arch/arm/mach-tegra/sleep-t2.S index 9daf61a76ea4..071932713871 100644 --- a/arch/arm/mach-tegra/sleep-t2.S +++ b/arch/arm/mach-tegra/sleep-t2.S @@ -183,7 +183,7 @@ ENDPROC(tegra2_cpu_is_resettable_soon) ENTRY(tegra2_sleep_core) mov r3, lr @ set resume address to lr bl tegra_cpu_save - + bl tegra_cpu_exit_coherency mov32 r1, tegra2_tear_down_core mov32 r2, tegra2_iram_start sub r1, r1, r2 @@ -199,7 +199,7 @@ ENTRY(tegra2_sleep_wfi) mov r3, lr @ set resume address to lr mrc p15, 0, r2, c1, c0, 1 @ save actlr before exiting coherency bl tegra_cpu_save - + bl tegra_cpu_exit_coherency mov r11, r2 mov32 r3, TEGRA_PMC_VIRT -- cgit v1.2.3