From 743c03fbeb5908faf4aef6bee7702a2ad4caac22 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Tue, 27 Mar 2012 16:17:20 +0530 Subject: ARM: tegra30: pm: flush L1 data before exit coherency on secondary CPU Change-Id: Ib16ee5efdf8686d750a5263baa8fff4d258e68cd Signed-off-by: Varun Wadekar Reviewed-on: http://git-master/r/92542 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/sleep-t3.S | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-tegra/sleep-t3.S') diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S index 6d58585a4903..caabeb751390 100644 --- a/arch/arm/mach-tegra/sleep-t3.S +++ b/arch/arm/mach-tegra/sleep-t3.S @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/include/mach/sleep-t3.S * - * Copyright (c) 2010-2011, NVIDIA Corporation. + * Copyright (c) 2010-2012, NVIDIA Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -235,6 +235,16 @@ ENDPROC(tegra3_sleep_core_finish) */ ENTRY(tegra3_sleep_cpu_secondary_finish) mov r6, lr + + dsb +#ifdef MULTI_CACHE + mov32 r10, cpu_cache + mov lr, pc + ldr pc, [r10, #CACHE_FLUSH_KERN_ALL] +#else + bl __cpuc_flush_kern_all +#endif + bl tegra_cpu_exit_coherency /* Powergate this CPU. */ -- cgit v1.2.3