From 16cf91484364b27fe463c81e8eaeb7668c6de954 Mon Sep 17 00:00:00 2001 From: Heechul Yun Date: Thu, 30 Jun 2011 15:40:43 -0700 Subject: arm: mm: Remove unnecessary cache flush on page table modification Since MMU of Cortex-A9 read from L1-D not from memory, there's no need to flush the cache line of the modified page table entry. Original-Change-Id: Ie5e6a027f633ed6060b8d2a9fdcd6a5399736d55 Reviewed-on: http://git-master/r/39697 Reviewed-by: Heechul Yun Tested-by: Heechul Yun Reviewed-by: Krishna Reddy Reviewed-by: Yu-Huan Hsu Rebase-Id: Rb8fd18147f8eb30b7969a6eac490efe03b646f16 --- arch/arm/mm/proc-v7.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm/mm') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 26ee164fc803..8c165d905461 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -176,7 +176,9 @@ ENTRY(cpu_v7_set_pte_ext) ARM( str r3, [r0, #2048]! ) THUMB( add r0, r0, #2048 ) THUMB( str r3, [r0] ) - mcr p15, 0, r0, c7, c10, 1 @ flush_pte + mrc p15, 0, r3, c0, c1, 7 @ read ID_MMFR3 + tst r3, #0xf << 20 @ check the coherent walk bits + mcreq p15, 0, r0, c7, c10, 1 @ flush_pte #endif mov pc, lr ENDPROC(cpu_v7_set_pte_ext) -- cgit v1.2.3