From 9705ceab5813d5e8e544a7195d8991cdcd96817a Mon Sep 17 00:00:00 2001 From: Prashant Gaikwad Date: Thu, 1 Mar 2012 11:05:50 +0530 Subject: arm: cache: fix v7 boot with lockdep enabled Bootup with lockdep enabled has been broken on v7 since b46c0f74657d ("ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR"). This is because v7_setup (which is called very early during boot) calls v7_flush_dcache_all, and the save_and_disable_irqs added by that patch ends up attempting to call into lockdep C code (trace_hardirqs_off()) when we are in no position to execute it (no stack, MMU off). Fix this by using a notrace variant of save_and_disable_irqs. The code already uses the notrace variant of restore_irqs. Change-Id: I1110a7e07fa3f96022b2e198488fa698c91e2642 Reviewed-by: Nicolas Pitre <(address hidden)> Acked-by: Stephen Boyd <(address hidden)> Cc: Catalin Marinas <(address hidden)> Cc: stable@vger.kernel.org Signed-off-by: Rabin Vincent <(address hidden)> Reviewed-on: http://git-master/r/86779 Reviewed-by: Prashant Gaikwad Tested-by: Prashant Gaikwad Reviewed-by: Varun Wadekar Reviewed-by: Scott Williams --- arch/arm/mm/cache-v7.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mm') diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 66bf91bd75a3..ac0925bc4fa7 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -56,7 +56,7 @@ ENDPROC(v7_flush_icache_all) cmp r1, #2 @ see what cache we have at this level blt 1004f @ skip if no cache, or just i-cache #ifdef CONFIG_PREEMPT - save_and_disable_irqs r9 @ make cssr&csidr read atomic + save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic #endif mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr isb @ isb to sych the new cssr&csidr -- cgit v1.2.3