From 8a83780a187ba1961380814eaf9c503043345d12 Mon Sep 17 00:00:00 2001 From: Ian Wisbon Date: Mon, 14 Feb 2011 16:41:03 -0500 Subject: Digi Release Code from del-5.6/main --- arch/arm/plat-mxc/include/mach/mxc_dvfs.h | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) (limited to 'arch/arm/plat-mxc/include/mach/mxc_dvfs.h') diff --git a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h index 05c6ea4bda77..43bcd2f7043a 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h +++ b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h @@ -35,7 +35,6 @@ #include extern void __iomem *gpc_base; -extern void __iomem *ccm_base; #define MXC_GPCCNTR_GPCIRQ2M (1 << 25) #define MXC_GPCCNTR_GPCIRQ2 (1 << 24) @@ -144,16 +143,16 @@ struct mxc_dvfs_platform_data { void __iomem *membase; /* The interrupt number used by the DVFS core */ int irq; - /* GPC control reg offset */ - int gpc_cntr_offset; - /* GPC voltage counter reg offset */ - int gpc_vcr_offset; - /* CCM DVFS control reg offset */ - int ccm_cdcr_offset; - /* CCM ARM clock root reg offset */ - int ccm_cacrr_offset; - /* CCM divider handshake in-progress reg offset */ - int ccm_cdhipr_offset; + /* GPC control reg address */ + void __iomem *gpc_cntr_reg_addr; + /* GPC voltage counter reg address */ + void __iomem *gpc_vcr_reg_addr; + /* CCM DVFS control reg address */ + void __iomem *ccm_cdcr_reg_addr; + /* CCM ARM clock root reg address */ + void __iomem *ccm_cacrr_reg_addr; + /* CCM divider handshake in-progree reg address */ + void __iomem *ccm_cdhipr_reg_addr; /* PREDIV mask */ u32 prediv_mask; /* PREDIV offset */ -- cgit v1.2.3