From 086025cc8d385a122089b78f0a146d58392af733 Mon Sep 17 00:00:00 2001 From: Fugang Duan Date: Sat, 29 Feb 2020 22:04:43 +0800 Subject: MLK-23424 arm64: dts: imx8dxl: enable legacy enet0 port Enable legacy enet0 port to support daughter RGMII AR8031 PHY board. imx8dxl evk board rework: - Remove U30, R181, R182 - Connect U30.2 -U30.7 - Connect U30.3 ->U30.6 - Change R178/R179 to 1.5K Reviewed-by: Richard Zhu Signed-off-by: Fugang Duan --- arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi') diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 4eb51cad186d..53bc4f2587af 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -131,9 +131,8 @@ conn_subsys: bus@5b000000 { <&enet0_lpcg 0>, <&enet0_lpcg 1>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; - assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, - <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; - assigned-clock-rates = <250000000>, <125000000>; + assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; + assigned-clock-rates = <125000000>; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; power-domains = <&pd IMX_SC_R_ENET_0>; -- cgit v1.2.3