From a1b1d7b416c32fb3d06da8e17b06a7d35a7a0d95 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Tue, 29 Dec 2020 09:24:27 +0800 Subject: LF-3050-2 arm64: dts: imx8mp: use the correct hsio axi clock Since the CG bit of the AXI clock would be handled by the composite clock "IMX8MP_CLK_HSIO_AXI" instead, correct the i.MX8MP PCIe AXI clock to IMX8MP_CLK_HSIO_AXI. Otherwise, it would break USB functions. Signed-off-by: Richard Zhu Reviewed-by: Jun Li Reviewed-by: Ye Li --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index f19a117b2ac6..402a3f7962ea 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -640,7 +640,7 @@ ext_osc = <1>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_PCIE_AUX>, - <&clk IMX8MP_CLK_HSIO_AXI_CG>, + <&clk IMX8MP_CLK_HSIO_AXI>, <&clk IMX8MP_CLK_PCIE_ROOT>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, @@ -656,7 +656,7 @@ ext_osc = <1>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_PCIE_AUX>, - <&clk IMX8MP_CLK_HSIO_AXI_CG>, + <&clk IMX8MP_CLK_HSIO_AXI>, <&clk IMX8MP_CLK_PCIE_ROOT>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, -- cgit v1.2.3