From 898814df9b4f63524d7c09ccc218f1dcdb22a106 Mon Sep 17 00:00:00 2001 From: Nitin Garg Date: Wed, 11 Dec 2019 10:47:16 -0600 Subject: MLK-23112 arm64: Update the SW workaround for i.MX8QM B0 ERR050104 The upper bits, above bit-35, of ARADDR and ACADDR buses within in Arm A53 sub-system have been incorrectly connected. Therefore ARADDR and ACADDR address bits above bit-35 should not be used. Hence downgrade instructions using higher address bits. Signed-off-by: Nitin Garg Reviewed-by: Anson Huang (cherry picked from commit 1894c0ed972d04d790a742c67b330d8a5d57e54c) --- arch/arm64/kvm/hyp/tlb.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'arch/arm64/kvm') diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index 73464a96c365..2e93b4d86826 100644 --- a/arch/arm64/kvm/hyp/tlb.c +++ b/arch/arm64/kvm/hyp/tlb.c @@ -18,6 +18,8 @@ #include #include +extern bool TKT340553_SW_WORKAROUND; + static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm) { u64 val; @@ -80,8 +82,12 @@ void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) * Instead, we invalidate Stage-2 for this IPA, and the * whole of Stage-1. Weep... */ - ipa >>= 12; - __tlbi(ipas2e1is, ipa); + if (TKT340553_SW_WORKAROUND) { + __tlbi(vmalls12e1is); + } else { + ipa >>= 12; + __tlbi(ipas2e1is, ipa); + } /* * We have to ensure completion of the invalidation at Stage-2, -- cgit v1.2.3