From 7f9749a0050aa4bbe770f1a061f5ae8c8545dfa8 Mon Sep 17 00:00:00 2001 From: Bitan Biswas Date: Mon, 6 Aug 2012 11:17:25 +0530 Subject: ARM: tegra: lp0 WAKE2 status clear Tegra pmc WAKE2 status registers also need to be cleared before re-entering lp0 mode. Change-Id: I1bd5c48baf86ba23d0352594e97c360d363ce991 Signed-off-by: Bitan Biswas Reviewed-on: http://git-master/r/121185 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan --- arch/arm/mach-tegra/pm-irq.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-tegra/pm-irq.c b/arch/arm/mach-tegra/pm-irq.c index 4a3f3c31830c..4e3c06835b2f 100644 --- a/arch/arm/mach-tegra/pm-irq.c +++ b/arch/arm/mach-tegra/pm-irq.c @@ -284,10 +284,15 @@ static int tegra_pm_irq_syscore_suspend(void) wake_enb = 0xffffffff; } - /* Clear PMC Wake Status register while going to suspend */ + /* Clear PMC Wake Status registers while going to suspend */ temp = readl(pmc + PMC_WAKE_STATUS); if (temp) pmc_32kwritel(temp, PMC_WAKE_STATUS); +#ifndef CONFIG_ARCH_TEGRA_2x_SOC + temp = readl(pmc + PMC_WAKE2_STATUS); + if (temp) + pmc_32kwritel(temp, PMC_WAKE2_STATUS); +#endif write_pmc_wake_level(wake_level); -- cgit v1.2.3