From 0ba06992e8919128d0547066247de9e54a8bb992 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 14 May 2014 16:51:19 +0200 Subject: ARM: shmobile: armadillo800eva reference dts: Add matching LED labels And make the node name numbering match the label numbering. Signed-off-by: Geert Uytterhoeven Cc: devicetree@vger.kernel.org Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index 486007d7ffe4..f6ef73ff49e8 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -104,17 +104,21 @@ leds { compatible = "gpio-leds"; - led1 { + led3 { gpios = <&pfc 102 GPIO_ACTIVE_HIGH>; + label = "LED3"; }; - led2 { + led4 { gpios = <&pfc 111 GPIO_ACTIVE_HIGH>; + label = "LED4"; }; - led3 { + led5 { gpios = <&pfc 110 GPIO_ACTIVE_HIGH>; + label = "LED5"; }; - led4 { + led6 { gpios = <&pfc 177 GPIO_ACTIVE_HIGH>; + label = "LED6"; }; }; -- cgit v1.2.3 From 7432695daeebffa39bae94d8f15ffe96ede3e581 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 15 May 2014 20:39:31 +0900 Subject: ARM: shmobile: marzen: Remove early_printk from command line As early printk support is not enabled in the kernel in the shmobile defconfig it does not make much sense to provide for it in the default command line. Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779-marzen.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index a7af2c2371f2..ee2338838b3f 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -17,7 +17,7 @@ compatible = "renesas,marzen", "renesas,r8a7779"; chosen { - bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on"; + bootargs = "console=ttySC2,115200 ignore_loglevel root=/dev/nfs ip=on"; }; memory { -- cgit v1.2.3 From 44991eb4bfd63b043b50e880d347a7946d6a9736 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Thu, 12 Jun 2014 17:38:40 +0800 Subject: ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles For all BG2Q SoCs, 2 cycles is the best/correct value. Signed-off-by: Jisheng Zhang Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2q.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 635a16a64cb4..3f95dc568b23 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -90,6 +90,8 @@ compatible = "arm,pl310-cache"; reg = <0xac0000 0x1000>; cache-level = <2>; + arm,data-latency = <2 2 2>; + arm,tag-latency = <2 2 2>; }; scu: snoop-control-unit@ad0000 { -- cgit v1.2.3 From 99f3deb8c95c999cd90f324c81d839b154acd244 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Antoine=20T=C3=A9nart?= Date: Tue, 3 Jun 2014 09:33:09 +0200 Subject: ARM: dts: berlin: add I2C nodes for BG2Q MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Marvell Berlin BG2Q has 4 TWSI compatible with the Synopsys DesignWare I2C driver. Add the corresponding nodes. The pin-muxing setup is also done here, since there cannot be another muxing setup if I2C{0,1,2,3} are enabled. Signed-off-by: Antoine Ténart Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2q.dtsi | 72 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 3f95dc568b23..bf163f48bd7c 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -193,6 +193,32 @@ }; }; + i2c0: i2c@1400 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1400 0x100>; + interrupt-parent = <&aic>; + interrupts = <4>; + clocks = <&chip CLKID_CFG>; + pinctrl-0 = <&twsi0_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c1: i2c@1800 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1800 0x100>; + interrupt-parent = <&aic>; + interrupts = <5>; + clocks = <&chip CLKID_CFG>; + pinctrl-0 = <&twsi1_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + timer0: timer@2c00 { compatible = "snps,dw-apb-timer"; reg = <0x2c00 0x14>; @@ -303,6 +329,16 @@ reg = <0xea0000 0x400>, <0xdd0170 0x10>; clocks = <&refclk>; clock-names = "refclk"; + + twsi0_pmux: twsi0-pmux { + groups = "G6"; + function = "twsi0"; + }; + + twsi1_pmux: twsi1-pmux { + groups = "G7"; + function = "twsi1"; + }; }; apb@fc0000 { @@ -313,6 +349,32 @@ ranges = <0 0xfc0000 0x10000>; interrupt-parent = <&sic>; + i2c2: i2c@7000 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7000 0x100>; + interrupt-parent = <&sic>; + interrupts = <6>; + clocks = <&refclk>; + pinctrl-0 = <&twsi2_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c3: i2c@8000 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8000 0x100>; + interrupt-parent = <&sic>; + interrupts = <7>; + clocks = <&refclk>; + pinctrl-0 = <&twsi3_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + uart0: uart@9000 { compatible = "snps,dw-apb-uart"; reg = <0x9000 0x100>; @@ -350,6 +412,16 @@ groups = "GSM14"; function = "uart1"; }; + + twsi2_pmux: twsi2-pmux { + groups = "GSM13"; + function = "twsi2"; + }; + + twsi3_pmux: twsi3-pmux { + groups = "GSM14"; + function = "twsi3"; + }; }; sic: interrupt-controller@e000 { -- cgit v1.2.3 From fbcdc07971cd274e444593a862783e94fbf4f1ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Antoine=20T=C3=A9nart?= Date: Tue, 3 Jun 2014 09:33:10 +0200 Subject: ARM: dts: berlin: enable i2c0 and i2c2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the I2C0 and I2C2 for the Marvell Berlin BG2G DMP. I2C1 and I2C3 are also working on this board, but no devices seemed to be there. Signed-off-by: Antoine Ténart Reviewed-by: Andrew Lunn Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts index 995150f93795..a357ce02a64e 100644 --- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts +++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts @@ -34,6 +34,14 @@ status = "okay"; }; +&i2c0 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + &uart0 { status = "okay"; }; -- cgit v1.2.3 From 460d02ac9599e91d64522a9380f03d2e2e3086e7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Antoine=20T=C3=A9nart?= Date: Wed, 4 Jun 2014 18:03:45 +0200 Subject: ARM: dts: berlin: add SMP related nodes and properties for BG2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add required nodes and properties into the Berlin BG2 device tree to take advantage of the newly introduced SMP support. Add the scu and cpu-ctrl nodes along with the CPUs enable-method property. Signed-off-by: Antoine Ténart Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index 2477dac4d643..9d7c810ebd0b 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -22,6 +22,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,berlin-smp"; cpu@0 { compatible = "marvell,pj4b"; @@ -78,6 +79,11 @@ clocks = <&chip CLKID_TWD>; }; + cpu-ctrl@dd0000 { + compatible = "marvell,berlin-cpu-ctrl"; + reg = <0xdd0000 0x10000>; + }; + apb@e80000 { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.3 From d19c93670a3dc6d8b37a3256f20eeafff5417f93 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Antoine=20T=C3=A9nart?= Date: Wed, 4 Jun 2014 18:03:46 +0200 Subject: ARM: dts: berlin: add SMP related nodes and properties for BG2Q MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add required nodes and properties into the Berlin BG2Q device tree to take advantage of the newly introduced SMP support. Add the scu and cpu-ctrl nodes along with the CPUs enable-method property. Signed-off-by: Antoine Ténart Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2q.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index bf163f48bd7c..400c40fceccc 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -18,6 +18,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,berlin-smp"; cpu@0 { compatible = "arm,cortex-a9"; @@ -113,6 +114,11 @@ #interrupt-cells = <3>; }; + cpu-ctrl@dd0000 { + compatible = "marvell,berlin-cpu-ctrl"; + reg = <0xdd0000 0x10000>; + }; + apb@e80000 { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.3 From 0fc2b7af8cd5918c0101dfb178b5a3a4b021a50b Mon Sep 17 00:00:00 2001 From: Alexander Bersenev Date: Mon, 9 Jun 2014 00:08:11 +0600 Subject: ARM: sunxi: Add pins for IR controller on A20 to dtsi This patch adds pins for two IR controllers on A20 Signed-off-by: Alexander Bersenev Signed-off-by: Alexsey Shestacov Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 01e94664232a..656d7d36a162 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -738,6 +738,20 @@ allwinner,drive = <2>; allwinner,pull = <0>; }; + + ir0_pins_a: ir0@0 { + allwinner,pins = "PB3","PB4"; + allwinner,function = "ir0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + ir1_pins_a: ir1@0 { + allwinner,pins = "PB22","PB23"; + allwinner,function = "ir1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { -- cgit v1.2.3 From 0256452ecf89139d2a33b03c8470c8b47d322da2 Mon Sep 17 00:00:00 2001 From: Alexander Bersenev Date: Mon, 9 Jun 2014 00:08:13 +0600 Subject: ARM: sunxi: Enable IR controller on cubieboard 2 and cubietruck in dts This patch enables two IR devices in dts: - One IR device physically found on Cubieboard 2 - One IR device physically found on Cubietruck Signed-off-by: Alexander Bersenev Signed-off-by: Alexsey Shestacov Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 6 ++++++ arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 6 ++++++ 2 files changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index a5ad945197e8..a70f0b4aa4ed 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -66,6 +66,12 @@ }; }; + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index b87fea901489..96639d59e22c 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -100,6 +100,12 @@ status = "okay"; }; + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; -- cgit v1.2.3 From eba9295328f069a6bce0dbc0223a79665b4a7c0f Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Wed, 4 Jun 2014 15:20:18 -0700 Subject: ARM: dts: Create a cros-ec-keyboard fragment All ChromeOS ARM devices that have the standard "CrOS EC" have the same keyboard mapping. It's silly to include this same definition everywhere. Let's create a "dtsi" fragment that we can include from many different boards. This fragment is based on what's currently in tegra124-venice2.dts Signed-off-by: Doug Anderson Signed-off-by: Stephen Warren --- arch/arm/boot/dts/cros-ec-keyboard.dtsi | 105 ++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 arch/arm/boot/dts/cros-ec-keyboard.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/cros-ec-keyboard.dtsi b/arch/arm/boot/dts/cros-ec-keyboard.dtsi new file mode 100644 index 000000000000..9c7fb0acae79 --- /dev/null +++ b/arch/arm/boot/dts/cros-ec-keyboard.dtsi @@ -0,0 +1,105 @@ +/* + * Keyboard dts fragment for devices that use cros-ec-keyboard + * + * Copyright (c) 2014 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include + +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb"; + keypad,num-rows = <8>; + keypad,num-columns = <13>; + google,needs-ghost-filter; + + linux,keymap = < + MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) + MATRIX_KEY(0x00, 0x02, KEY_F1) + MATRIX_KEY(0x00, 0x03, KEY_B) + MATRIX_KEY(0x00, 0x04, KEY_F10) + MATRIX_KEY(0x00, 0x06, KEY_N) + MATRIX_KEY(0x00, 0x08, KEY_EQUAL) + MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) + + MATRIX_KEY(0x01, 0x01, KEY_ESC) + MATRIX_KEY(0x01, 0x02, KEY_F4) + MATRIX_KEY(0x01, 0x03, KEY_G) + MATRIX_KEY(0x01, 0x04, KEY_F7) + MATRIX_KEY(0x01, 0x06, KEY_H) + MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) + MATRIX_KEY(0x01, 0x09, KEY_F9) + MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) + + MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) + MATRIX_KEY(0x02, 0x01, KEY_TAB) + MATRIX_KEY(0x02, 0x02, KEY_F3) + MATRIX_KEY(0x02, 0x03, KEY_T) + MATRIX_KEY(0x02, 0x04, KEY_F6) + MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) + MATRIX_KEY(0x02, 0x06, KEY_Y) + MATRIX_KEY(0x02, 0x07, KEY_102ND) + MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) + MATRIX_KEY(0x02, 0x09, KEY_F8) + + MATRIX_KEY(0x03, 0x01, KEY_GRAVE) + MATRIX_KEY(0x03, 0x02, KEY_F2) + MATRIX_KEY(0x03, 0x03, KEY_5) + MATRIX_KEY(0x03, 0x04, KEY_F5) + MATRIX_KEY(0x03, 0x06, KEY_6) + MATRIX_KEY(0x03, 0x08, KEY_MINUS) + MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) + + MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) + MATRIX_KEY(0x04, 0x01, KEY_A) + MATRIX_KEY(0x04, 0x02, KEY_D) + MATRIX_KEY(0x04, 0x03, KEY_F) + MATRIX_KEY(0x04, 0x04, KEY_S) + MATRIX_KEY(0x04, 0x05, KEY_K) + MATRIX_KEY(0x04, 0x06, KEY_J) + MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) + MATRIX_KEY(0x04, 0x09, KEY_L) + MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) + MATRIX_KEY(0x04, 0x0b, KEY_ENTER) + + MATRIX_KEY(0x05, 0x01, KEY_Z) + MATRIX_KEY(0x05, 0x02, KEY_C) + MATRIX_KEY(0x05, 0x03, KEY_V) + MATRIX_KEY(0x05, 0x04, KEY_X) + MATRIX_KEY(0x05, 0x05, KEY_COMMA) + MATRIX_KEY(0x05, 0x06, KEY_M) + MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) + MATRIX_KEY(0x05, 0x08, KEY_SLASH) + MATRIX_KEY(0x05, 0x09, KEY_DOT) + MATRIX_KEY(0x05, 0x0b, KEY_SPACE) + + MATRIX_KEY(0x06, 0x01, KEY_1) + MATRIX_KEY(0x06, 0x02, KEY_3) + MATRIX_KEY(0x06, 0x03, KEY_4) + MATRIX_KEY(0x06, 0x04, KEY_2) + MATRIX_KEY(0x06, 0x05, KEY_8) + MATRIX_KEY(0x06, 0x06, KEY_7) + MATRIX_KEY(0x06, 0x08, KEY_0) + MATRIX_KEY(0x06, 0x09, KEY_9) + MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) + MATRIX_KEY(0x06, 0x0b, KEY_DOWN) + MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) + + MATRIX_KEY(0x07, 0x01, KEY_Q) + MATRIX_KEY(0x07, 0x02, KEY_E) + MATRIX_KEY(0x07, 0x03, KEY_R) + MATRIX_KEY(0x07, 0x04, KEY_W) + MATRIX_KEY(0x07, 0x05, KEY_I) + MATRIX_KEY(0x07, 0x06, KEY_U) + MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) + MATRIX_KEY(0x07, 0x08, KEY_P) + MATRIX_KEY(0x07, 0x09, KEY_O) + MATRIX_KEY(0x07, 0x0b, KEY_UP) + MATRIX_KEY(0x07, 0x0c, KEY_LEFT) + >; + }; +}; -- cgit v1.2.3 From f01dd55aa5d302fb2212f8edbadaf97d1d6089f7 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Wed, 4 Jun 2014 15:20:19 -0700 Subject: ARM: tegra: Use the cros-ec-keyboard fragment in venice2 Signed-off-by: Doug Anderson Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 96 ++-------------------------------- 1 file changed, 3 insertions(+), 93 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index f0bb84244025..72585c82a307 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -816,7 +816,7 @@ spi@0,7000d400 { status = "okay"; - cros-ec@0 { + cros_ec: cros-ec@0 { compatible = "google,cros-ec-spi"; spi-max-frequency = <4000000>; interrupt-parent = <&gpio>; @@ -824,98 +824,6 @@ reg = <0>; google,cros-ec-spi-msg-delay = <2000>; - - cros-ec-keyb { - compatible = "google,cros-ec-keyb"; - keypad,num-rows = <8>; - keypad,num-columns = <13>; - google,needs-ghost-filter; - - linux,keymap = < - MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) - MATRIX_KEY(0x00, 0x02, KEY_F1) - MATRIX_KEY(0x00, 0x03, KEY_B) - MATRIX_KEY(0x00, 0x04, KEY_F10) - MATRIX_KEY(0x00, 0x06, KEY_N) - MATRIX_KEY(0x00, 0x08, KEY_EQUAL) - MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) - - MATRIX_KEY(0x01, 0x01, KEY_ESC) - MATRIX_KEY(0x01, 0x02, KEY_F4) - MATRIX_KEY(0x01, 0x03, KEY_G) - MATRIX_KEY(0x01, 0x04, KEY_F7) - MATRIX_KEY(0x01, 0x06, KEY_H) - MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) - MATRIX_KEY(0x01, 0x09, KEY_F9) - MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) - - MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) - MATRIX_KEY(0x02, 0x01, KEY_TAB) - MATRIX_KEY(0x02, 0x02, KEY_F3) - MATRIX_KEY(0x02, 0x03, KEY_T) - MATRIX_KEY(0x02, 0x04, KEY_F6) - MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) - MATRIX_KEY(0x02, 0x06, KEY_Y) - MATRIX_KEY(0x02, 0x07, KEY_102ND) - MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) - MATRIX_KEY(0x02, 0x09, KEY_F8) - - MATRIX_KEY(0x03, 0x01, KEY_GRAVE) - MATRIX_KEY(0x03, 0x02, KEY_F2) - MATRIX_KEY(0x03, 0x03, KEY_5) - MATRIX_KEY(0x03, 0x04, KEY_F5) - MATRIX_KEY(0x03, 0x06, KEY_6) - MATRIX_KEY(0x03, 0x08, KEY_MINUS) - MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) - - MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) - MATRIX_KEY(0x04, 0x01, KEY_A) - MATRIX_KEY(0x04, 0x02, KEY_D) - MATRIX_KEY(0x04, 0x03, KEY_F) - MATRIX_KEY(0x04, 0x04, KEY_S) - MATRIX_KEY(0x04, 0x05, KEY_K) - MATRIX_KEY(0x04, 0x06, KEY_J) - MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) - MATRIX_KEY(0x04, 0x09, KEY_L) - MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) - MATRIX_KEY(0x04, 0x0b, KEY_ENTER) - - MATRIX_KEY(0x05, 0x01, KEY_Z) - MATRIX_KEY(0x05, 0x02, KEY_C) - MATRIX_KEY(0x05, 0x03, KEY_V) - MATRIX_KEY(0x05, 0x04, KEY_X) - MATRIX_KEY(0x05, 0x05, KEY_COMMA) - MATRIX_KEY(0x05, 0x06, KEY_M) - MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) - MATRIX_KEY(0x05, 0x08, KEY_SLASH) - MATRIX_KEY(0x05, 0x09, KEY_DOT) - MATRIX_KEY(0x05, 0x0b, KEY_SPACE) - - MATRIX_KEY(0x06, 0x01, KEY_1) - MATRIX_KEY(0x06, 0x02, KEY_3) - MATRIX_KEY(0x06, 0x03, KEY_4) - MATRIX_KEY(0x06, 0x04, KEY_2) - MATRIX_KEY(0x06, 0x05, KEY_8) - MATRIX_KEY(0x06, 0x06, KEY_7) - MATRIX_KEY(0x06, 0x08, KEY_0) - MATRIX_KEY(0x06, 0x09, KEY_9) - MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) - MATRIX_KEY(0x06, 0x0b, KEY_DOWN) - MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) - - MATRIX_KEY(0x07, 0x01, KEY_Q) - MATRIX_KEY(0x07, 0x02, KEY_E) - MATRIX_KEY(0x07, 0x03, KEY_R) - MATRIX_KEY(0x07, 0x04, KEY_W) - MATRIX_KEY(0x07, 0x05, KEY_I) - MATRIX_KEY(0x07, 0x06, KEY_U) - MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) - MATRIX_KEY(0x07, 0x08, KEY_P) - MATRIX_KEY(0x07, 0x09, KEY_O) - MATRIX_KEY(0x07, 0x0b, KEY_UP) - MATRIX_KEY(0x07, 0x0c, KEY_LEFT) - >; - }; }; }; @@ -1205,3 +1113,5 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; + +#include "cros-ec-keyboard.dtsi" -- cgit v1.2.3 From 1a395e3b4f2e9038964c9eec392ed5300a4b5b83 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Wed, 4 Jun 2014 15:20:20 -0700 Subject: ARM: dts: Use the cros-ec-keyboard fragment in exynos5250-snow Signed-off-by: Doug Anderson Signed-off-by: Stephen Warren --- arch/arm/boot/dts/exynos5250-snow.dts | 93 ++--------------------------------- 1 file changed, 3 insertions(+), 90 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 079fdf9e3f18..7bd2df1364c2 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -137,7 +137,7 @@ sbs,poll-retry-count = <1>; }; - ec: embedded-controller { + cros_ec: embedded-controller { compatible = "google,cros-ec-i2c"; reg = <0x1e>; interrupts = <6 0>; @@ -145,95 +145,6 @@ pinctrl-names = "default"; pinctrl-0 = <&ec_irq>; wakeup-source; - - keyboard-controller { - compatible = "google,cros-ec-keyb"; - keypad,num-rows = <8>; - keypad,num-columns = <13>; - google,needs-ghost-filter; - linux,keymap = <0x0001007d /* L_META */ - 0x0002003b /* F1 */ - 0x00030030 /* B */ - 0x00040044 /* F10 */ - 0x00060031 /* N */ - 0x0008000d /* = */ - 0x000a0064 /* R_ALT */ - - 0x01010001 /* ESC */ - 0x0102003e /* F4 */ - 0x01030022 /* G */ - 0x01040041 /* F7 */ - 0x01060023 /* H */ - 0x01080028 /* ' */ - 0x01090043 /* F9 */ - 0x010b000e /* BKSPACE */ - - 0x0200001d /* L_CTRL */ - 0x0201000f /* TAB */ - 0x0202003d /* F3 */ - 0x02030014 /* T */ - 0x02040040 /* F6 */ - 0x0205001b /* ] */ - 0x02060015 /* Y */ - 0x02070056 /* 102ND */ - 0x0208001a /* [ */ - 0x02090042 /* F8 */ - - 0x03010029 /* GRAVE */ - 0x0302003c /* F2 */ - 0x03030006 /* 5 */ - 0x0304003f /* F5 */ - 0x03060007 /* 6 */ - 0x0308000c /* - */ - 0x030b002b /* \ */ - - 0x04000061 /* R_CTRL */ - 0x0401001e /* A */ - 0x04020020 /* D */ - 0x04030021 /* F */ - 0x0404001f /* S */ - 0x04050025 /* K */ - 0x04060024 /* J */ - 0x04080027 /* ; */ - 0x04090026 /* L */ - 0x040a002b /* \ */ - 0x040b001c /* ENTER */ - - 0x0501002c /* Z */ - 0x0502002e /* C */ - 0x0503002f /* V */ - 0x0504002d /* X */ - 0x05050033 /* , */ - 0x05060032 /* M */ - 0x0507002a /* L_SHIFT */ - 0x05080035 /* / */ - 0x05090034 /* . */ - 0x050B0039 /* SPACE */ - - 0x06010002 /* 1 */ - 0x06020004 /* 3 */ - 0x06030005 /* 4 */ - 0x06040003 /* 2 */ - 0x06050009 /* 8 */ - 0x06060008 /* 7 */ - 0x0608000b /* 0 */ - 0x0609000a /* 9 */ - 0x060a0038 /* L_ALT */ - 0x060b006c /* DOWN */ - 0x060c006a /* RIGHT */ - - 0x07010010 /* Q */ - 0x07020012 /* E */ - 0x07030013 /* R */ - 0x07040011 /* W */ - 0x07050017 /* I */ - 0x07060016 /* U */ - 0x07070036 /* R_SHIFT */ - 0x07080019 /* P */ - 0x07090018 /* O */ - 0x070b0067 /* UP */ - 0x070c0069>; /* LEFT */ - }; }; power-regulator { @@ -431,3 +342,5 @@ }; }; }; + +#include "cros-ec-keyboard.dtsi" -- cgit v1.2.3 From 35b5da7b0abfda695924bef011995031f4f3dcfe Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 3 Jun 2014 15:54:19 +0900 Subject: ARM: shmobile: r8a7790: add USB3.0 clocks to device tree Signed-off-by: Yoshihiro Shimoda Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 7ff29601f962..e2c7d6df5be4 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -754,17 +754,17 @@ reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, - <&hp_clk>, <&hp_clk>, <&rclk_clk>; + <&hp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 - R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_CMT1 + R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 >; clock-output-names = "iic2", "tpu0", "mmcif1", "sdhi3", "sdhi2", "sdhi1", "sdhi0", "mmcif0", - "iic0", "iic1", "cmt1"; + "iic0", "iic1", "ssusb", "cmt1"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; -- cgit v1.2.3 From 308f306283894a0d3eeee7d1030289e4e668d49d Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 3 Jun 2014 15:57:05 +0900 Subject: ARM: shmobile: r8a7791: add USB3.0 clocks to device tree Signed-off-by: Yoshihiro Shimoda Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 8d7ffaeff6e0..2c27e36cb954 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -758,15 +758,15 @@ compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, - <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>; + <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 - R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_CMT1 + R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 >; clock-output-names = "tpu0", "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "i2c7", "i2c8", "cmt1"; + "mmcif0", "i2c7", "i2c8", "ssusb", "cmt1"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; -- cgit v1.2.3 From 4e074bc8114f0ba8a2e0a69fb459564814c9e966 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 2 Jun 2014 15:42:07 +0200 Subject: ARM: shmobile: r8a7791 dtsi: add SYS-DMAC clocks Add clocks for the SYS-DMAC0 and SYS-DMAC1 hardware blocks. Cfr. the r8a7790 version by Ben Dooks. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 2c27e36cb954..d683982a299d 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -743,16 +743,19 @@ compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&mp_clk>; + <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&zs_clk>, <&zs_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 + R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0 >; clock-output-names = "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", - "scifb1", "msiof1", "scifb2"; + "scifb1", "msiof1", "scifb2", + "sys-dmac1", "sys-dmac0"; }; mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; -- cgit v1.2.3 From 05f72e03b7553958609d1475c79491f90e6b50d3 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Tue, 3 Jun 2014 21:02:12 +0900 Subject: ARM: shmobile: lager: Add VDD MPU regulator for DVFS The CA15 cluster is capable of voltage scaling. Add the regulator in the i2c3 node, to allow the generic CPUFreq driver to use it. Enable the i2c3 pin mux and the device node as well since the da9210 is connected to that bus. Note: In R-CAR Gen2, each frequency is using the same voltage, and DVS control is not used. Therefore, this patch set the voltage(Vmin/Vmax) to 1000mv. Signed-off-by: Benoit Cousson [gaku.inami.xw@bp.renesas.com: Changes Vmin for disabling DVS] Signed-off-by: Gaku Inami Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index dd2fe46073f2..6472cf0914e2 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -204,6 +204,11 @@ "msiof1_tx"; renesas,function = "msiof1"; }; + + i2c3_pins: i2c3 { + renesas,groups = "i2c3"; + renesas,function = "i2c3"; + }; }; ðer { @@ -317,3 +322,19 @@ cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; status = "okay"; }; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + status = "okay"; + + vdd_dvfs: regulator@68 { + compatible = "diasemi,da9210"; + reg = <0x68>; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; +}; -- cgit v1.2.3 From b989e1386385466761f703b8a91e00468bb5ca2a Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Tue, 3 Jun 2014 21:02:24 +0900 Subject: ARM: shmobile: r8a7790/lager dts: Add DVFS parameters into cpu0 node for r8a7790 Add needed information inside CPU0 for the generic cpufreq-cpu0 driver. - voltage-tolerance = 1% It reflects the tolerance for the CPU voltage defined inside the OPP table. Due to the lack of proper OPP definition, use an arbitrary safe value. - clock-latency = 300 us Approximate worst-case latency to do a full DVFS transition for every OPPs. Due to the lack of HW information, use an arbitrary safe value. Note: The term transition-latency will be more accurate to define this value since the clock transition latency is not the only parameter that will define the overall DVFS transition. - operating-points = < kHz - uV > List of 6 operating points. All of them are using the same voltage since the valid Vmin voltage is not documented in the HW spec. - clocks phandle to the CPU clock source. This clock source is used for all the 4 CortexA15 located inside the same cluster. Signed-off-by: Benoit Cousson [gaku.inami.xw@bp.renesas.com: Change the setting of OPPs for ES2.0] Signed-off-by: Gaku Inami Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 4 ++++ arch/arm/boot/dts/r8a7790.dtsi | 11 +++++++++++ 2 files changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 6472cf0914e2..cc65e3f96f08 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -338,3 +338,7 @@ regulator-always-on; }; }; + +&cpu0 { + cpu0-supply = <&vdd_dvfs>; +}; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index e2c7d6df5be4..e990d3c4fe62 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -44,6 +44,17 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1300000000>; + voltage-tolerance = <1>; /* 1% */ + clocks = <&cpg_clocks R8A7790_CLK_Z>; + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; }; cpu1: cpu@1 { -- cgit v1.2.3 From 1d41f36a68c0f4e9b01d563ce33bab5201858b54 Mon Sep 17 00:00:00 2001 From: Gaku Inami Date: Tue, 3 Jun 2014 21:02:59 +0900 Subject: ARM: shmobile: koelsch dts: Add VDD MPU regulator for DVFS The CA15 cluster is capable of voltage scaling. Add the regulator in the i2c6 node, to allow the generic CPUFreq driver to use it. Enable the i2c6 pin mux and the device node as well since the da9210 is connected to that bus. Note: In R-CAR Gen2, each frequency is using the same voltage, and DVS control is not used. Therefore, this patch set the voltage(Vmin/Vmax) to 1000mv. Signed-off-by: Gaku Inami Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 05d44f9b202f..95331d73042d 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -293,6 +293,11 @@ "msiof0_tx"; renesas,function = "msiof0"; }; + + i2c6_pins: i2c6 { + renesas,groups = "i2c6"; + renesas,function = "i2c6"; + }; }; ðer { @@ -408,3 +413,19 @@ spi-cpha; }; }; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + status = "okay"; + + vdd_dvfs: regulator@68 { + compatible = "diasemi,da9210"; + reg = <0x68>; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; +}; -- cgit v1.2.3 From a57004eca542428a444025847098b2af4e52a81c Mon Sep 17 00:00:00 2001 From: Gaku Inami Date: Tue, 3 Jun 2014 21:03:10 +0900 Subject: ARM: shmobile: r8a7791/koelsch dts: Add DVFS parameters into cpu0 node for r8a7791 Add needed information inside CPU0 for the generic cpufreq-cpu0 driver. - voltage-tolerance = 1% It reflects the tolerance for the CPU voltage defined inside the OPP table. Due to the lack of proper OPP definition, use an arbitrary safe value. - clock-latency = 300 us Approximate worst-case latency to do a full DVFS transition for every OPPs. Due to the lack of HW information, use an arbitrary safe value. Note: The term transition-latency will be more accurate to define this value since the clock transition latency is not the only parameter that will define the overall DVFS transition. - operating-points = < kHz - uV > List of 6 operating points. All of them are using the same voltage since DVS is not supported in R-CAR Gen2. - clocks phandle to the CPU clock source. This clock source is used for all the 2 CortexA15 located inside the same cluster. Signed-off-by: Gaku Inami Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 4 ++++ arch/arm/boot/dts/r8a7791.dtsi | 11 +++++++++++ 2 files changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 95331d73042d..b2e661613dda 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -429,3 +429,7 @@ regulator-always-on; }; }; + +&cpu0 { + cpu0-supply = <&vdd_dvfs>; +}; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index d683982a299d..b639006da7e1 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -45,6 +45,17 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1500000000>; + voltage-tolerance = <1>; /* 1% */ + clocks = <&cpg_clocks R8A7791_CLK_Z>; + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; }; cpu1: cpu@1 { -- cgit v1.2.3 From e489c2a9bc82713167d9f721ca764f4b0d37e543 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 12 Feb 2014 17:04:33 +0000 Subject: ARM: shmobile: lager: enable i2c devices Add i2c0, i2c1, i2c2 and i2c3 nodes to the Lager reference device tree as these busses all have devices on them that can be probed even if they are no drivers yet. Signed-off-by: Ben Dooks [horms+renesas@verge.net.au: Added shmobile to title] Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index cc65e3f96f08..bd92dcf1ee9b 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -342,3 +342,19 @@ &cpu0 { cpu0-supply = <&vdd_dvfs>; }; + +&i2c0 { + status = "ok"; +}; + +&i2c1 { + status = "ok"; +}; + +&i2c2 { + status = "ok"; +}; + +&i2c3 { + status = "ok"; +}; -- cgit v1.2.3 From e1a2c4eb132018ce5b988c9ff5ba7a01e5494af5 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 12 Feb 2014 17:04:34 +0000 Subject: ARM: shmobile: lager: add i2c1, i2c2 pins Add pinctrl definitions for i2c1 and i2c2 busses on the Lager board to ensure these are setup correctly at initialisation time. The i2c0 and i2c3 busses are connected to single function pins. Signed-off-by: Ben Dooks [horms+renesas@verge.net.au: Added shmobile to patch title] Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index bd92dcf1ee9b..3297b86a52b7 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -144,6 +144,16 @@ states = <3300000 1 1800000 0>; }; + + i2c1_pins: i2c1 { + renesas,groups = "i2c1"; + renesas,function = "i2c1"; + }; + + i2c2_pins: i2c2 { + renesas,groups = "i2c2"; + renesas,function = "i2c2"; + }; }; &extal_clk { @@ -349,10 +359,14 @@ &i2c1 { status = "ok"; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; }; &i2c2 { status = "ok"; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; }; &i2c3 { -- cgit v1.2.3 From d90bf60ceaf453b59c8cd5dbfa59538e27255706 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 6 Jun 2014 16:11:00 +0900 Subject: ARM: shmobile: lager: Move i2c[12]_pins nodes to pfc node Due to an error when resolving conflicts df40f256b18300e1 ("ARM: shmobile: lager: add i2c1, i2c2 pins") added the i2c[12]_pins nodes to the wrong node. This patch moves them to their correct location in the pfc node. Cc: Ben Dooks Reported-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 3297b86a52b7..b68ff56be67e 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -144,16 +144,6 @@ states = <3300000 1 1800000 0>; }; - - i2c1_pins: i2c1 { - renesas,groups = "i2c1"; - renesas,function = "i2c1"; - }; - - i2c2_pins: i2c2 { - renesas,groups = "i2c2"; - renesas,function = "i2c2"; - }; }; &extal_clk { @@ -215,6 +205,16 @@ renesas,function = "msiof1"; }; + i2c1_pins: i2c1 { + renesas,groups = "i2c1"; + renesas,function = "i2c1"; + }; + + i2c2_pins: i2c2 { + renesas,groups = "i2c2"; + renesas,function = "i2c2"; + }; + i2c3_pins: i2c3 { renesas,groups = "i2c3"; renesas,function = "i2c3"; -- cgit v1.2.3 From 7b16c61a86ce41edd5c42a87f22a0a146968b62f Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 6 Jun 2014 15:40:26 +0900 Subject: ARM: shmobile: Lager memory map update Update the Lager DTS to make use of the new unified legacy memory map where the legacy window on Lager and Koelsch have the same size. With this change in place the code gets aligned with the documentation. After update the Lager board has the following map: Bank0: 1GiB RAM (Legacy 32-bit: 0x40000000->0x7fffffff) Bank1: 3GiB RAM (LPAE area: 0x140000000->0x1ffffffff) Before the update the old map looked like this: Bank0: 2GiB RAM (Legacy 32-bit: 0x40000000->0xbfffffff) Bank1: 2GiB RAM (LPAE area: 0x180000000->0x1ffffffff) Tested with and without LPAE on r8a7790 Lager. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index b68ff56be67e..b04d25762f1d 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -29,12 +29,12 @@ memory@40000000 { device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; + reg = <0 0x40000000 0 0x40000000>; }; memory@180000000 { device_type = "memory"; - reg = <1 0x80000000 0 0x80000000>; + reg = <1 0x40000000 0 0xc0000000>; }; lbsc { -- cgit v1.2.3 From aca4ec446c646d8794fdbf617d187423a227305d Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 9 Jun 2014 11:09:44 +0900 Subject: ARM: shmobile: lager: Remove duplicate i2c3 nodes Due to an error when merging df40f256b18300e1 ("ARM: shmobile: lager: add i2c1, i2c2 pins") a duplicate i2c3 node. This patch moves the duplicate and moves to old node to be closer to the other new i2c nodes. Cc: Ben Dooks Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index b04d25762f1d..0890d475c2c7 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -333,22 +333,6 @@ status = "okay"; }; -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - status = "okay"; - - vdd_dvfs: regulator@68 { - compatible = "diasemi,da9210"; - reg = <0x68>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - &cpu0 { cpu0-supply = <&vdd_dvfs>; }; @@ -369,6 +353,18 @@ pinctrl-names = "default"; }; -&i2c3 { - status = "ok"; +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + status = "okay"; + + vdd_dvfs: regulator@68 { + compatible = "diasemi,da9210"; + reg = <0x68>; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; }; -- cgit v1.2.3 From 897dfdbc14603d764637dea92696fef4fc66ea3e Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 9 Jun 2014 17:50:28 +0900 Subject: ARM: shmobile: koelsch: Remove duplicate i2c6 nodes A second i2c6 node was a added by 05e234a187058ee ("ARM: shmobile: koelsch dts: Add VDD MPU regulator for DVFS"). Merge this into the existing node. Also shuffle i2c nodes so they are all together. Cc: Gaku Inami Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 34 +++++++++++++++------------------- 1 file changed, 15 insertions(+), 19 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index b2e661613dda..b0cfbd48e299 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -215,25 +215,6 @@ clock-frequency = <20000000>; }; -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - eeprom@50 { - compatible = "renesas,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c6 { - status = "okay"; - clock-frequency = <100000>; -}; - &pfc { pinctrl-0 = <&du_pins>; pinctrl-names = "default"; @@ -414,10 +395,25 @@ }; }; +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "renesas,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + &i2c6 { pinctrl-names = "default"; pinctrl-0 = <&i2c6_pins>; status = "okay"; + clock-frequency = <100000>; vdd_dvfs: regulator@68 { compatible = "diasemi,da9210"; -- cgit v1.2.3 From 29a647c396a054b087b124372ffb261f40ee9856 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 11 Jun 2014 02:45:21 +0400 Subject: ARM: shmobile: henninger: add I2C2 DT support Define the Henninger board dependent part of the I2C2 device node. Based on the Koelsch I2C2 device tree patch by Wolfram Sang. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-henninger.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts index cc6d992e8db2..c0c58ce7746e 100644 --- a/arch/arm/boot/dts/r8a7791-henninger.dts +++ b/arch/arm/boot/dts/r8a7791-henninger.dts @@ -110,6 +110,11 @@ renesas,function = "sdhi2"; }; + i2c2_pins: i2c2 { + renesas,groups = "i2c2"; + renesas,function = "i2c2"; + }; + qspi_pins: spi0 { renesas,groups = "qspi_ctrl", "qspi_data4"; renesas,function = "qspi"; @@ -170,6 +175,14 @@ status = "okay"; }; +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; +}; + &qspi { pinctrl-0 = <&qspi_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From bcde37225438687231bb9510c07e60dcb8db1988 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 10 Jun 2014 23:53:27 -0700 Subject: ARM: shmobile: r8a7790: add MSTP10 support on DTSI Signed-off-by: Kuninori Morimoto Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index e990d3c4fe62..0f83bd778a3d 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -835,6 +835,39 @@ "rcan1", "rcan0", "qspi_mod", "iic3", "i2c3", "i2c2", "i2c1", "i2c0"; }; + mstp10_clks: mstp10_clks@e6150998 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; + clocks = <&p_clk>, + <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&p_clk>, + <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, + <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, + <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, + <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, + <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, + <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>; + + #clock-cells = <1>; + clock-indices = < + R8A7790_CLK_SSI_ALL + R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5 + R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0 + R8A7790_CLK_SCU_ALL + R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0 + R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5 + R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0 + >; + clock-output-names = + "ssi-all", + "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", + "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", + "scu-all", + "scu-dvc1", "scu-dvc0", + "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", + "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; + }; }; qspi: spi@e6b10000 { -- cgit v1.2.3 From 7df2fd572b9f159657a145f3fdd700d3e00760d9 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 10 Jun 2014 23:53:54 -0700 Subject: ARM: shmobile: r8a7790: add R-Car sound support on DTSI This patch support PIO transfer only at this point Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 56 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 0f83bd778a3d..29907c9d8e5b 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -920,4 +920,60 @@ #size-cells = <0>; status = "disabled"; }; + + rcar_sound: rcar_sound@0xec500000 { + #sound-dai-cells = <1>; + compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; + interrupt-parent = <&gic>; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x1280>; /* SSI */ + clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>, + <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>, + <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>, + <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>, + <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>, + <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>, + <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>, + <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>, + <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>, + <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>, + <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", "src.5", + "src.4", "src.3", "src.2", "src.1", "src.0", + "clk_a", "clk_b", "clk_c", "clk_i"; + + status = "disabled"; + + rcar_sound,src { + src0: src@0 { }; + src1: src@1 { }; + src2: src@2 { }; + src3: src@3 { }; + src4: src@4 { }; + src5: src@5 { }; + src6: src@6 { }; + src7: src@7 { }; + src8: src@8 { }; + src9: src@9 { }; + }; + + rcar_sound,ssi { + ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; }; + ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; }; + ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; }; + ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; }; + ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; }; + ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; }; + ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; }; + ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; }; + ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; }; + ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; }; + }; + }; }; -- cgit v1.2.3 From 0d3dbde84a45977cdd7d85115cd5ea1b4ede312e Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 11 Jun 2014 21:44:04 -0700 Subject: ARM: shmobile: r8a7791: add audio clock on DTSI audio_clk_a/b/c are required from sound driver Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index b639006da7e1..f3b6219cc09e 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -532,6 +532,29 @@ clock-output-names = "extal"; }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency clocks by + * default. Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "audio_clk_a"; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "audio_clk_b"; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "audio_clk_c"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7791-cpg-clocks", -- cgit v1.2.3 From ee9141522dcf13f861ed3cef6490c6cbfaafefb9 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 11 Jun 2014 21:44:16 -0700 Subject: ARM: shmobile: r8a7791: add MSTP10 support on DTSI Signed-off-by: Kuninori Morimoto Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index f3b6219cc09e..380d058e4210 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -865,6 +865,39 @@ "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; }; + mstp10_clks: mstp10_clks@e6150998 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; + clocks = <&p_clk>, + <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&p_clk>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; + + #clock-cells = <1>; + clock-indices = < + R8A7791_CLK_SSI_ALL + R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5 + R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 + R8A7791_CLK_SCU_ALL + R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 + R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 + R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 + >; + clock-output-names = + "ssi-all", + "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", + "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", + "scu-all", + "scu-dvc1", "scu-dvc0", + "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", + "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; + }; mstp11_clks: mstp11_clks@e615099c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; -- cgit v1.2.3 From ecafea8cd261833d7bb857aad76cf2e721821e88 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Fri, 13 Jun 2014 10:37:15 +0100 Subject: ARM: shmobile: r8a7790: Add PCIEC clock device tree node This patch adds the device tree clock node for the PCIe Controller Signed-off-by: Phil Edworthy Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 29907c9d8e5b..9df57122e9c0 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -765,17 +765,17 @@ reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, - <&hp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; + <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 - R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 + R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 >; clock-output-names = "iic2", "tpu0", "mmcif1", "sdhi3", "sdhi2", "sdhi1", "sdhi0", "mmcif0", - "iic0", "iic1", "ssusb", "cmt1"; + "iic0", "pciec", "iic1", "ssusb", "cmt1"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; -- cgit v1.2.3 From 51d17918077215cd93d78a2b13a3b57090eb1f3d Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Fri, 13 Jun 2014 10:37:16 +0100 Subject: ARM: shmobile: r8a7790: Add default PCIe bus clock This patch adds a default PCIe bus clock node. Signed-off-by: Phil Edworthy Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 9df57122e9c0..2c55c4b8295f 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -487,6 +487,15 @@ clock-output-names = "extal"; }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie_bus"; + status = "disabled"; + }; + /* * The external audio clocks are configured as 0 Hz fixed frequency clocks by * default. Boards that provide audio clocks should override them. -- cgit v1.2.3 From 745329d280c8c73f00724745693658f3d4113ea8 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Fri, 13 Jun 2014 10:37:17 +0100 Subject: ARM: shmobile: r8a7790: Add PCIe Controller device node Signed-off-by: Phil Edworthy [horms+renesas@verge.net.au: resolved conflict] Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 2c55c4b8295f..994330e81a52 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -930,6 +930,31 @@ status = "disabled"; }; + pciec: pcie@fe000000 { + compatible = "renesas,pcie-r8a7790"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 + 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; + interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>, + <0 117 IRQ_TYPE_LEVEL_HIGH>, + <0 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + status = "disabled"; + }; + rcar_sound: rcar_sound@0xec500000 { #sound-dai-cells = <1>; compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; -- cgit v1.2.3 From 4bfb37675b5343798f5260adad92a67444a9fd47 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Fri, 13 Jun 2014 10:37:18 +0100 Subject: ARM: shmobile: r8a7791: Add PCIEC clock device tree node This patch adds the device tree clock node for the PCIe Controller Signed-off-by: Phil Edworthy Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 380d058e4210..a15bf7af63e4 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -795,15 +795,16 @@ compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, - <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; + <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 - R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 + R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 + R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 >; clock-output-names = "tpu0", "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "i2c7", "i2c8", "ssusb", "cmt1"; + "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; -- cgit v1.2.3 From 66c405e72bf332e59ab29461e33a4e94cb8bdd7a Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Fri, 13 Jun 2014 10:37:19 +0100 Subject: ARM: shmobile: r8a7791: Add default PCIe bus clock This patch adds a default PCIe bus clock node. Signed-off-by: Phil Edworthy Acked-by: Laurent Pinchart [horms+renesas@verge.net.au: resolved conflict] Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index a15bf7af63e4..7f7eda7f2e23 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -555,6 +555,15 @@ clock-output-names = "audio_clk_c"; }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie_bus"; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7791-cpg-clocks", -- cgit v1.2.3 From 811cdfae502137a21b91326ed6912a94d3dc7723 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Fri, 13 Jun 2014 10:37:20 +0100 Subject: ARM: shmobile: r8a7791: Add PCIe Controller device node Signed-off-by: Phil Edworthy Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 7f7eda7f2e23..43d2130ddc29 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -960,4 +960,29 @@ #size-cells = <0>; status = "disabled"; }; + + pciec: pcie@fe000000 { + compatible = "renesas,pcie-r8a7791"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 + 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; + interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>, + <0 117 IRQ_TYPE_LEVEL_HIGH>, + <0 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + status = "disabled"; + }; }; -- cgit v1.2.3 From 998d7d64e1aeede4e03b6c67adb78fe55a278db7 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Fri, 13 Jun 2014 10:37:21 +0100 Subject: ARM: shmobile: koelsch: Enable PCIe Controller & PCIe bus clock Signed-off-by: Phil Edworthy Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index b0cfbd48e299..5dac67395525 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -426,6 +426,14 @@ }; }; +&pcie_bus_clk { + status = "okay"; +}; + +&pciec { + status = "okay"; +}; + &cpu0 { cpu0-supply = <&vdd_dvfs>; }; -- cgit v1.2.3 From 485f3ce67c11ce086c322b2622db01d7e7c59a84 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Fri, 13 Jun 2014 10:37:22 +0100 Subject: ARM: shmobile: henninger: Enable PCIe Controller & PCIe bus clock Signed-off-by: Phil Edworthy Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-henninger.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts index c0c58ce7746e..bc48bccfff54 100644 --- a/arch/arm/boot/dts/r8a7791-henninger.dts +++ b/arch/arm/boot/dts/r8a7791-henninger.dts @@ -230,3 +230,11 @@ spi-cpha; }; }; + +&pcie_bus_clk { + status = "okay"; +}; + +&pciec { + status = "okay"; +}; -- cgit v1.2.3 From 09abd1fd11f98d6abde9c23244234170e7e36c2f Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 11 Jun 2014 21:44:26 -0700 Subject: ARM: shmobile: r8a7791: add R-Car sound support on DTSI This patch support PIO transfer only at this point Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 56 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 43d2130ddc29..1997f168141a 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -985,4 +985,60 @@ clock-names = "pcie", "pcie_bus"; status = "disabled"; }; + + rcar_sound: rcar_sound@0xec500000 { + #sound-dai-cells = <1>; + compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; + interrupt-parent = <&gic>; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x1280>; /* SSI */ + clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>, + <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>, + <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>, + <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>, + <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>, + <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>, + <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>, + <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>, + <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>, + <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>, + <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", "src.5", + "src.4", "src.3", "src.2", "src.1", "src.0", + "clk_a", "clk_b", "clk_c", "clk_i"; + + status = "disabled"; + + rcar_sound,src { + src0: src@0 { }; + src1: src@1 { }; + src2: src@2 { }; + src3: src@3 { }; + src4: src@4 { }; + src5: src@5 { }; + src6: src@6 { }; + src7: src@7 { }; + src8: src@8 { }; + src9: src@9 { }; + }; + + rcar_sound,ssi { + ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; }; + ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; }; + ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; }; + ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; }; + ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; }; + ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; }; + ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; }; + ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; }; + ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; }; + ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; }; + }; + }; }; -- cgit v1.2.3 From 7e0a6b8988944e5992833e21fc65cdaf0619da45 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Mon, 26 May 2014 21:29:49 +0200 Subject: ARM: Kirkwood: Add DT descriptions for net2big and net5big. Describe LaCie 2Big and 5Big Network v2 using device tree. Signed-off-by: Andrew Lunn Link: https://lkml.kernel.org/r/1401132591-26305-3-git-send-email-andrew@lunn.ch Acked-by: Sebastian Hesselbarth Tested-by: Simon Guinot Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/kirkwood-net2big.dts | 30 ++++++ arch/arm/boot/dts/kirkwood-net5big.dts | 83 +++++++++++++++ arch/arm/boot/dts/kirkwood-netxbig.dtsi | 180 ++++++++++++++++++++++++++++++++ 4 files changed, 295 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-net2big.dts create mode 100644 arch/arm/boot/dts/kirkwood-net5big.dts create mode 100644 arch/arm/boot/dts/kirkwood-netxbig.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5986ff63b901..43e8cda5d635 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -123,6 +123,8 @@ kirkwood := \ kirkwood-lsxhl.dtb \ kirkwood-mplcec4.dtb \ kirkwood-mv88f6281gtw-ge.dtb \ + kirkwood-net2big.dtb \ + kirkwood-net5big.dtb \ kirkwood-netgear_readynas_duo_v2.dtb \ kirkwood-netgear_readynas_nv+_v2.dtb \ kirkwood-ns2.dtb \ diff --git a/arch/arm/boot/dts/kirkwood-net2big.dts b/arch/arm/boot/dts/kirkwood-net2big.dts new file mode 100644 index 000000000000..a98deccee59f --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-net2big.dts @@ -0,0 +1,30 @@ +/* + * Device Tree file for LaCie 2Big Network v2 + * + * Copyright (C) 2014 + * + * Andrew Lunn + * + * Based on netxbig_v2-setup.c, + * Copyright (C) 2010 Simon Guinot + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-netxbig.dtsi" + +/ { + model = "LaCie 2Big Network v2"; + compatible = "lacie,net2big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-net5big.dts b/arch/arm/boot/dts/kirkwood-net5big.dts new file mode 100644 index 000000000000..51c56a9490b3 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-net5big.dts @@ -0,0 +1,83 @@ +/* + * Device Tree file for LaCie 5Big Network v2 + * + * Copyright (C) 2014 + * + * Andrew Lunn + * + * Based on netxbig_v2-setup.c, + * Copyright (C) 2010 Simon Guinot + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-netxbig.dtsi" + +/ { + model = "LaCie 5Big Network v2"; + compatible = "lacie,net5big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + +}; + +®ulators { + regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "hdd2power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + + regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "hdd3power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; + }; + + regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "hdd4power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + }; +}; + +&mdio { + ethphy1: ethernet-phy@1 { + reg = <0>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; + diff --git a/arch/arm/boot/dts/kirkwood-netxbig.dtsi b/arch/arm/boot/dts/kirkwood-netxbig.dtsi new file mode 100644 index 000000000000..fd75720547e3 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-netxbig.dtsi @@ -0,0 +1,180 @@ +/* + * Device Tree common file for LaCie 2Big and 5Big Network v2 + * + * Copyright (C) 2014 + * + * Andrew Lunn + * + * Based on netxbig_v2-setup.c, + * Copyright (C) 2010 Simon Guinot + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + serial@12000 { + status = "okay"; + }; + + spi@10600 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mxicy,mx25l4005a"; + reg = <0>; + spi-max-frequency = <20000000>; + mode = <0>; + + partition@0 { + reg = <0x0 0x80000>; + label = "u-boot"; + }; + }; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + /* + * button@1 and button@2 represent a three position rocker + * switch. Thus the conventional KEY_POWER does not fit + */ + button@1 { + label = "Back power switch (on|auto)"; + linux,code = ; + linux,input-type = <5>; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + button@2 { + label = "Back power switch (auto|off)"; + linux,code = ; + linux,input-type = <5>; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + button@3 { + label = "Function button"; + linux,code = ; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + }; + + regulators: regulators { + status = "okay"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "hdd0power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; + }; + + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <8>; + }; + + ethphy1: ethernet-phy@1 { + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + + pmx_button_function: pmx-button-function { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + pmx_button_power_off: pmx-button-power-off { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + pmx_button_power_on: pmx-button-power-on { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; +}; + +&i2c0 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + pagesize = <16>; + reg = <0x50>; + }; + + g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; + }; +}; -- cgit v1.2.3 From 133cea6680349962b60e50475952b5a643a75eb4 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 28 May 2014 00:00:06 +0200 Subject: ARM: dts: mvebu: split SolidRun CuBox into variants As Mainlining effort for SolidRun CuBox has been carried out on the Engineering Sample, the board DTS was reflecting this. Actually, SolidRun CuBox comes in three different variants: Engineering Sample (ES), production with 1GB RAM (1G), and production with 2GB RAM (2G). Therefore, we base current dove-cubox.dts on to the 1G production variant and add a ES dts to add required quirk for misrouted SDHCI card detect on top of dove-cubox.dts. For the 2G variant we rely on the bootloader to setup correct RAM size. Signed-off-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1401228006-3212-1-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/dove-cubox-es.dts | 12 ++++++++++++ arch/arm/boot/dts/dove-cubox.dts | 3 --- 3 files changed, 13 insertions(+), 3 deletions(-) create mode 100644 arch/arm/boot/dts/dove-cubox-es.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 43e8cda5d635..8e75c1f7fa23 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -444,6 +444,7 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-openblocks-ax3-4.dtb dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \ dove-cubox.dtb \ + dove-cubox-es.dtb \ dove-d2plug.dtb \ dove-d3plug.dtb \ dove-dove-db.dtb diff --git a/arch/arm/boot/dts/dove-cubox-es.dts b/arch/arm/boot/dts/dove-cubox-es.dts new file mode 100644 index 000000000000..e28ef056dd17 --- /dev/null +++ b/arch/arm/boot/dts/dove-cubox-es.dts @@ -0,0 +1,12 @@ +#include "dove-cubox.dts" + +/ { + model = "SolidRun CuBox (Engineering Sample)"; + compatible = "solidrun,cubox-es", "solidrun,cubox", "marvell,dove"; +}; + +&sdio0 { + /* sdio0 card detect is connected to wrong pin on CuBox ES */ + cd-gpios = <&gpio0 12 1>; + pinctrl-0 = <&pmx_sdio0 &pmx_gpio_12>; +}; diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index 7a70f4ca502a..aae7efc09b0b 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -111,9 +111,6 @@ &sdio0 { status = "okay"; - /* sdio0 card detect is connected to wrong pin on CuBox */ - cd-gpios = <&gpio0 12 1>; - pinctrl-0 = <&pmx_sdio0 &pmx_gpio_12>; }; &spi0 { -- cgit v1.2.3 From db91fb2cf4aeec274fdacef9a7ad48294baf6e7e Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Sat, 21 Jun 2014 21:50:14 +0900 Subject: ARM: dts: Enable audio support for exynos5800-peach-pi Peach-pi board has MAX98091 audio codec connected on HSI2C-7 bus. Signed-off-by: Tushar Behera Reviewed-by: Doug Anderson Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5800-peach-pi.dts | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index f3af2079a063..ef94ab83b152 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -57,6 +57,13 @@ pinctrl-names = "default"; }; + sound { + compatible = "google,snow-audio-max98091"; + + samsung,i2s-controller = <&i2s0>; + samsung,audio-codec = <&max98091>; + }; + usb300_vbus_reg: regulator-usb300 { compatible = "regulator-fixed"; regulator-name = "P5.0V_USB3CON0"; @@ -81,6 +88,13 @@ }; &pinctrl_0 { + max98091_irq: max98091-irq { + samsung,pins = "gpx0-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + tpm_irq: tpm-irq { samsung,pins = "gpx1-0"; samsung,pin-function = <0>; @@ -207,6 +221,19 @@ samsung,invert-vclk; }; +&hsi2c_7 { + status = "okay"; + + max98091: codec@10 { + compatible = "maxim,max98091"; + reg = <0x10>; + interrupts = <2 0>; + interrupt-parent = <&gpx0>; + pinctrl-names = "default"; + pinctrl-0 = <&max98091_irq>; + }; +}; + &hsi2c_9 { status = "okay"; clock-frequency = <400000>; @@ -251,3 +278,7 @@ &watchdog { timeout-sec = <32>; }; + +&i2s0 { + status = "okay"; +}; -- cgit v1.2.3 From 522c8ff5c3204f566f10388b96d0c6e6c51e69fe Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Sat, 21 Jun 2014 21:50:17 +0900 Subject: ARM: dts: Sort nodes within Peach-pit/Peach-pi dts files Peach-pit and Peach-pi boards are almost similar, hence the DTS file is also very similar. Sorting nodes in both these files will allow us to figure out the difference easily. All the node aliases are sorted in alphabetically increasing order. There is no functional change with this patch. Signed-off-by: Tushar Behera Reviewed-by: Doug Anderson Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420-peach-pit.dts | 236 +++++++++++++++-------------- arch/arm/boot/dts/exynos5800-peach-pi.dts | 225 +++++++++++++-------------- 2 files changed, 233 insertions(+), 228 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 1c5b8f9f4a36..764998205354 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -25,8 +25,13 @@ "google,pit", "google,peach","samsung,exynos5420", "samsung,exynos5"; - memory { - reg = <0x20000000 0x80000000>; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 1000000 0>; + brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; + default-brightness-level = <7>; + pinctrl-0 = <&pwm0_out>; + pinctrl-names = "default"; }; fixed-rate-clocks { @@ -50,13 +55,8 @@ }; }; - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 1000000 0>; - brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; - default-brightness-level = <7>; - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; + memory { + reg = <0x20000000 0x80000000>; }; sound { @@ -89,64 +89,83 @@ }; }; -&pinctrl_0 { - max98090_irq: max98090-irq { - samsung,pins = "gpx0-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; +&dp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd_gpio>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x06>; + samsung,lane-count = <2>; + samsung,hpd-gpio = <&gpx2 6 0>; - tpm_irq: tpm-irq { - samsung,pins = "gpx1-0"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; + display-timings { + native-mode = <&timing1>; - power_key_irq: power-key-irq { - samsung,pins = "gpx1-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + timing1: timing@1 { + clock-frequency = <70589280>; + hactive = <1366>; + vactive = <768>; + hfront-porch = <40>; + hback-porch = <40>; + hsync-len = <32>; + vback-porch = <10>; + vfront-porch = <12>; + vsync-len = <6>; + }; }; +}; - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; - }; +&fimd { + status = "okay"; + samsung,invert-vclk; +}; - dp_hpd_gpio: dp_hpd_gpio { - samsung,pins = "gpx2-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; +&hdmi { + status = "okay"; + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + ddc = <&i2c_2>; }; -&pinctrl_3 { - usb300_vbus_en: usb300-vbus-en { - samsung,pins = "gph0-0"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; +&hsi2c_7 { + status = "okay"; + + max98090: codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupts = <2 0>; + interrupt-parent = <&gpx0>; + pinctrl-names = "default"; + pinctrl-0 = <&max98090_irq>; }; +}; - usb301_vbus_en: usb301-vbus-en { - samsung,pins = "gph0-1"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; +&hsi2c_9 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + + /* Unused irq; but still need to configure the pins */ + pinctrl-names = "default"; + pinctrl-0 = <&tpm_irq>; }; }; -&rtc { +&i2c_2 { status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + samsung,i2c-slave-addr = <0x50>; }; -&uart_3 { +&i2s0 { status = "okay"; }; @@ -189,46 +208,66 @@ }; }; -&hsi2c_7 { - status = "okay"; - max98090: codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupts = <2 0>; - interrupt-parent = <&gpx0>; - pinctrl-names = "default"; - pinctrl-0 = <&max98090_irq>; +&pinctrl_0 { + max98090_irq: max98090-irq { + samsung,pins = "gpx0-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; }; -}; -&hsi2c_9 { - status = "okay"; - clock-frequency = <400000>; + tpm_irq: tpm-irq { + samsung,pins = "gpx1-0"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; + power_key_irq: power-key-irq { + samsung,pins = "gpx1-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; - /* Unused irq; but still need to configure the pins */ - pinctrl-names = "default"; - pinctrl-0 = <&tpm_irq>; + dp_hpd_gpio: dp_hpd_gpio { + samsung,pins = "gpx2-6"; + samsung,pin-function = <0>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hdmi_hpd_irq: hdmi-hpd-irq { + samsung,pins = "gpx3-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; }; }; -&i2c_2 { +&pinctrl_3 { + usb300_vbus_en: usb300-vbus-en { + samsung,pins = "gph0-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + usb301_vbus_en: usb301-vbus-en { + samsung,pins = "gph0-1"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&rtc { status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x50>; }; -&hdmi { +&uart_3 { status = "okay"; - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - ddc = <&i2c_2>; }; &usbdrd_phy0 { @@ -248,40 +287,3 @@ timeout-sec = <32>; }; -&i2s0 { - status = "okay"; -}; - -&fimd { - status = "okay"; - samsung,invert-vclk; -}; - -&dp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd_gpio>; - samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x06>; - samsung,lane-count = <2>; - samsung,hpd-gpio = <&gpx2 6 0>; - - display-timings { - native-mode = <&timing1>; - - timing1: timing@1 { - clock-frequency = <70589280>; - hactive = <1366>; - vactive = <768>; - hfront-porch = <40>; - hback-porch = <40>; - hsync-len = <32>; - vback-porch = <10>; - vfront-porch = <12>; - vsync-len = <6>; - }; - }; -}; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index ef94ab83b152..2c2c1379519c 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -23,8 +23,13 @@ "google,pi", "google,peach", "samsung,exynos5800", "samsung,exynos5"; - memory { - reg = <0x20000000 0x80000000>; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 1000000 0>; + brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; + default-brightness-level = <7>; + pinctrl-0 = <&pwm0_out>; + pinctrl-names = "default"; }; fixed-rate-clocks { @@ -48,13 +53,8 @@ }; }; - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 1000000 0>; - brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; - default-brightness-level = <7>; - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; + memory { + reg = <0x20000000 0x80000000>; }; sound { @@ -87,64 +87,83 @@ }; }; -&pinctrl_0 { - max98091_irq: max98091-irq { - samsung,pins = "gpx0-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; +&dp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd_gpio>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <2>; + samsung,hpd-gpio = <&gpx2 6 0>; - tpm_irq: tpm-irq { - samsung,pins = "gpx1-0"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; + display-timings { + native-mode = <&timing1>; - power_key_irq: power-key-irq { - samsung,pins = "gpx1-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + timing1: timing@1 { + clock-frequency = <150660000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <60>; + hback-porch = <172>; + hsync-len = <80>; + vback-porch = <25>; + vfront-porch = <10>; + vsync-len = <10>; + }; }; +}; - dp_hpd_gpio: dp_hpd_gpio { - samsung,pins = "gpx2-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; +&fimd { + status = "okay"; + samsung,invert-vclk; +}; - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; - }; +&hdmi { + status = "okay"; + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + ddc = <&i2c_2>; }; -&pinctrl_3 { - usb300_vbus_en: usb300-vbus-en { - samsung,pins = "gph0-0"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; +&hsi2c_7 { + status = "okay"; + + max98091: codec@10 { + compatible = "maxim,max98091"; + reg = <0x10>; + interrupts = <2 0>; + interrupt-parent = <&gpx0>; + pinctrl-names = "default"; + pinctrl-0 = <&max98091_irq>; }; +}; - usb301_vbus_en: usb301-vbus-en { - samsung,pins = "gph0-1"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; +&hsi2c_9 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + + /* Unused irq; but still need to configure the pins */ + pinctrl-names = "default"; + pinctrl-0 = <&tpm_irq>; }; }; -&rtc { +&i2c_2 { status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + samsung,i2c-slave-addr = <0x50>; }; -&uart_3 { +&i2s0 { status = "okay"; }; @@ -187,79 +206,66 @@ }; }; -&dp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd_gpio>; - samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <2>; - samsung,hpd-gpio = <&gpx2 6 0>; - display-timings { - native-mode = <&timing1>; +&pinctrl_0 { + max98091_irq: max98091-irq { + samsung,pins = "gpx0-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; - timing1: timing@1 { - clock-frequency = <150660000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <60>; - hback-porch = <172>; - hsync-len = <80>; - vback-porch = <25>; - vfront-porch = <10>; - vsync-len = <10>; - }; + tpm_irq: tpm-irq { + samsung,pins = "gpx1-0"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; }; -}; -&fimd { - status = "okay"; - samsung,invert-vclk; -}; + power_key_irq: power-key-irq { + samsung,pins = "gpx1-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; -&hsi2c_7 { - status = "okay"; + dp_hpd_gpio: dp_hpd_gpio { + samsung,pins = "gpx2-6"; + samsung,pin-function = <0>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; - max98091: codec@10 { - compatible = "maxim,max98091"; - reg = <0x10>; - interrupts = <2 0>; - interrupt-parent = <&gpx0>; - pinctrl-names = "default"; - pinctrl-0 = <&max98091_irq>; + hdmi_hpd_irq: hdmi-hpd-irq { + samsung,pins = "gpx3-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; }; }; -&hsi2c_9 { - status = "okay"; - clock-frequency = <400000>; +&pinctrl_3 { + usb300_vbus_en: usb300-vbus-en { + samsung,pins = "gph0-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - /* Unused irq; but still need to configure the pins */ - pinctrl-names = "default"; - pinctrl-0 = <&tpm_irq>; + usb301_vbus_en: usb301-vbus-en { + samsung,pins = "gph0-1"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; }; }; -&i2c_2 { +&rtc { status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x50>; }; -&hdmi { +&uart_3 { status = "okay"; - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - ddc = <&i2c_2>; }; &usbdrd_phy0 { @@ -279,6 +285,3 @@ timeout-sec = <32>; }; -&i2s0 { - status = "okay"; -}; -- cgit v1.2.3 From d854fa8a1500bec982ed9cb26b82d96bd5ae8dab Mon Sep 17 00:00:00 2001 From: Jason Cooper Date: Sat, 21 Jun 2014 19:21:13 +0000 Subject: ARM: kirkwood: fix net5big regulator gpio assignments Late correction from Simon's testing. Reported-by: Simon Guinot Link: https://lkml.kernel.org/r/20140621095001.GW20207@kw.sim.vm.gnt Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-net5big.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/kirkwood-net5big.dts b/arch/arm/boot/dts/kirkwood-net5big.dts index 51c56a9490b3..d2887ed493f2 100644 --- a/arch/arm/boot/dts/kirkwood-net5big.dts +++ b/arch/arm/boot/dts/kirkwood-net5big.dts @@ -40,7 +40,7 @@ enable-active-high; regulator-always-on; regulator-boot-on; - gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; }; regulator@4 { @@ -52,7 +52,7 @@ enable-active-high; regulator-always-on; regulator-boot-on; - gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; regulator@5 { @@ -64,7 +64,7 @@ enable-active-high; regulator-always-on; regulator-boot-on; - gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; }; }; -- cgit v1.2.3 From c1a0ee3d5322d488c539e20d40db88b181628670 Mon Sep 17 00:00:00 2001 From: Alexander Bersenev Date: Sat, 21 Jun 2014 17:04:05 +0600 Subject: ARM: sunxi: Add IR controllers on A20 to dtsi This patch adds records for two IR controllers on A20 Signed-off-by: Alexander Bersenev Signed-off-by: Alexsey Shestacov Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 656d7d36a162..17823759bdc9 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -785,6 +785,24 @@ status = "disabled"; }; + ir0: ir@01c21800 { + compatible = "allwinner,sun7i-a20-ir"; + clocks = <&apb0_gates 6>, <&ir0_clk>; + clock-names = "apb", "ir"; + interrupts = <0 5 4>; + reg = <0x01c21800 0x40>; + status = "disabled"; + }; + + ir1: ir@01c21c00 { + compatible = "allwinner,sun7i-a20-ir"; + clocks = <&apb0_gates 7>, <&ir1_clk>; + clock-names = "apb", "ir"; + interrupts = <0 6 4>; + reg = <0x01c21c00 0x40>; + status = "disabled"; + }; + sid: eeprom@01c23800 { compatible = "allwinner,sun7i-a20-sid"; reg = <0x01c23800 0x200>; -- cgit v1.2.3 From ff4f3eb8b3386208944fe60b85e6cba4d338198e Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 24 Jun 2014 21:59:54 +0400 Subject: ARM: shmobile: r8a7790: add internal PCI bridge nodes Add device nodes for the R8A7790 internal PCI bridge devices. Signed-off-by: Ben Dooks Reviewed-by: Ian Molton [Sergei: added several properties to the PCI bridge nodes] Signed-off-by: Sergei Shtylyov Acked-by: Arnd Bergmann Tested-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 994330e81a52..373d9a21c912 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -930,6 +930,66 @@ status = "disabled"; }; + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7790"; + device_type = "pci"; + clocks = <&mstp7_clks R8A7790_CLK_EHCI>; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; + }; + + pci1: pci@ee0b0000 { + compatible = "renesas,pci-r8a7790"; + device_type = "pci"; + clocks = <&mstp7_clks R8A7790_CLK_EHCI>; + reg = <0 0xee0b0000 0 0xc00>, + <0 0xee0a0000 0 0x1100>; + interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>; + }; + + pci2: pci@ee0d0000 { + compatible = "renesas,pci-r8a7790"; + device_type = "pci"; + clocks = <&mstp7_clks R8A7790_CLK_EHCI>; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + bus-range = <2 2>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; + }; + pciec: pcie@fe000000 { compatible = "renesas,pcie-r8a7790"; reg = <0 0xfe000000 0 0x80000>; -- cgit v1.2.3 From d8584660676e00157735abcb34b09d690d96ee16 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 24 Jun 2014 22:02:21 +0400 Subject: ARM: shmobile: lager: enable internal PCI Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to them. Signed-off-by: Ben Dooks Reviewed-by: Ian Molton [Sergei: enabled PCI0] Signed-off-by: Sergei Shtylyov Tested-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 0890d475c2c7..544202bab9fa 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -219,6 +219,21 @@ renesas,groups = "i2c3"; renesas,function = "i2c3"; }; + + usb0_pins: usb0 { + renesas,groups = "usb0"; + renesas,function = "usb0"; + }; + + usb1_pins: usb1 { + renesas,groups = "usb1"; + renesas,function = "usb1"; + }; + + usb2_pins: usb2 { + renesas,groups = "usb2"; + renesas,function = "usb2"; + }; }; ðer { @@ -368,3 +383,21 @@ regulator-always-on; }; }; + +&pci0 { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; + +&pci2 { + status = "okay"; + pinctrl-0 = <&usb2_pins>; + pinctrl-names = "default"; +}; -- cgit v1.2.3 From 334d69a23b177a4ed38e654912444dc48ac46765 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 25 Jun 2014 17:52:17 -0700 Subject: ARM: shmobile: r8a7790: add DVC support for sound node on DTSI Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 373d9a21c912..bdcb7f08fcc5 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1034,16 +1034,23 @@ <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>, <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>, <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>, + <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", "src.9", "src.8", "src.7", "src.6", "src.5", "src.4", "src.3", "src.2", "src.1", "src.0", + "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; status = "disabled"; + rcar_sound,dvc { + dvc0: dvc@0 { }; + dvc1: dvc@1 { }; + }; + rcar_sound,src { src0: src@0 { }; src1: src@1 { }; -- cgit v1.2.3 From 150c8ad40808189423002ea9fc6a858a3a59e6dc Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 25 Jun 2014 17:52:33 -0700 Subject: ARM: shmobile: r8a7791: add DVC support for sound node on DTSI Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 1997f168141a..336a6c03b510 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1005,16 +1005,23 @@ <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>, <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>, <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>, + <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", "src.9", "src.8", "src.7", "src.6", "src.5", "src.4", "src.3", "src.2", "src.1", "src.0", + "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; status = "disabled"; + rcar_sound,dvc { + dvc0: dvc@0 { }; + dvc1: dvc@1 { }; + }; + rcar_sound,src { src0: src@0 { }; src1: src@1 { }; -- cgit v1.2.3 From 517ec80a3321e01fd07eeb6098c3d7b455fcca68 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 30 Jun 2014 11:49:53 +0200 Subject: ARM: shmobile: r8a7790: Fix whitespace errors in pci nodes Remove spaces in between tabs. Introduced by commit ff4f3eb8b3386208944fe60b85e6cba4d338198e ("ARM: shmobile: r8a7790: add internal PCI bridge nodes"). Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index bdcb7f08fcc5..d9ddecbb859c 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -946,8 +946,8 @@ ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; interrupt-map-mask = <0xff00 0 0 0x7>; interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; + 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; }; pci1: pci@ee0b0000 { @@ -966,8 +966,8 @@ ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; interrupt-map-mask = <0xff00 0 0 0x7>; interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>; + 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>; }; pci2: pci@ee0d0000 { @@ -986,8 +986,8 @@ ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; interrupt-map-mask = <0xff00 0 0 0x7>; interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; + 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; }; pciec: pcie@fe000000 { -- cgit v1.2.3 From fd6c10fb1012c773820c5a308a7ab01879628c69 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 20 Jun 2014 22:52:52 +0800 Subject: ARM: sunxi: Add Allwinner A23 dtsi The Allwinner A23 is a tablet oriented SoC with 2 Cortex-A7 cores and a Mali-400MP2 GPU. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23.dtsi | 160 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-a23.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi new file mode 100644 index 000000000000..ac5f69afb595 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -0,0 +1,160 @@ +/* + * Copyright 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &r_uart; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + }; + + memory { + reg = <0x40000000 0x40000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + soc@01c00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + timer@01c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = <0 18 4>, + <0 19 4>; + clocks = <&osc24M>; + }; + + wdt0: watchdog@01c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = <0 25 4>; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <0 0 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <0 1 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <0 2 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <0 3 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart4: serial@01c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = <0 4 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <1 9 0xf04>; + }; + + r_uart: serial@01f02800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01f02800 0x400>; + interrupts = <0 38 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + }; +}; -- cgit v1.2.3 From 4c3d4a361b7e6a24303e65f443285afd91371694 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 20 Jun 2014 22:52:53 +0800 Subject: ARM: sun8i: dt: Add Ippo-q8h v5 support The Ippo-q8h is a tablet circuit board commonly found in cheap Android tablets with A23 SoCs. There are at least 2 versions of the board, with different peripherals, such as WiFi chips. Common features among these tablets include 512 MB DRAM, NAND, MMC, LCD, capacitive touchscreen, accelerometer, 1 or 2 camera sensors, USB OTG, microphone and speaker. v5 of these board designs has a ESP8089 WiFi chip (not supported) connected to mmc1. This patch adds very basic support. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 2 ++ arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 30 +++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5986ff63b901..774a14b91151 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -380,6 +380,8 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-cubietruck.dtb \ sun7i-a20-i12-tvbox.dtb \ sun7i-a20-olinuxino-micro.dtb +dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-a23-ippo-q8h-v5.dtb dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra20-iris-512.dtb \ tegra20-medcom-wide.dtb \ diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts new file mode 100644 index 000000000000..34002e3eba9d --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts @@ -0,0 +1,30 @@ +/* + * Copyright 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun8i-a23.dtsi" + +/ { + model = "Ippo Q8H Dual Core Tablet (v5)"; + compatible = "ippo,q8h-v5", "allwinner,sun8i-a23"; + + chosen { + bootargs = "earlyprintk console=ttyS0,115200"; + }; + + soc@01c00000 { + r_uart: serial@01f02800 { + status = "okay"; + }; + }; +}; -- cgit v1.2.3 From 7d4ff96dd390cbcf6053398bd33b194f87ef60ba Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 30 Jun 2014 23:57:51 +0200 Subject: ARM: dts: sunxi: Add #interrupt-cells to pinctrl nodes The pinctrl device is also an interrupt controller for external interrupts. Add the missing #interrupt-cells property. Also remove the unused #address-cells property. Signed-off-by: Chen-Yu Tsai [hdegoede@redhat.com: make the same change for sun4i, sun5i and sun6i] Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 2 +- arch/arm/boot/dts/sun5i-a10s.dtsi | 2 +- arch/arm/boot/dts/sun5i-a13.dtsi | 2 +- arch/arm/boot/dts/sun6i-a31.dtsi | 4 ++-- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index d96e179490ce..37a6fb8013cc 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -509,7 +509,7 @@ clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #address-cells = <1>; + #interrupt-cells = <2>; #size-cells = <0>; #gpio-cells = <3>; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index b64f705d9008..24b0ad3a7c07 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -422,7 +422,7 @@ clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #address-cells = <1>; + #interrupt-cells = <2>; #size-cells = <0>; #gpio-cells = <3>; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 3b2a94c40f6e..bf86e65dd167 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -395,7 +395,7 @@ clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #address-cells = <1>; + #interrupt-cells = <2>; #size-cells = <0>; #gpio-cells = <3>; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index a9dfa12eb735..baf8eff57610 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -429,7 +429,7 @@ clocks = <&apb1_gates 5>; gpio-controller; interrupt-controller; - #address-cells = <1>; + #interrupt-cells = <2>; #size-cells = <0>; #gpio-cells = <3>; @@ -756,7 +756,7 @@ resets = <&apb0_rst 0>; gpio-controller; interrupt-controller; - #address-cells = <1>; + #interrupt-cells = <2>; #size-cells = <0>; #gpio-cells = <3>; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 17823759bdc9..edf16b512f43 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -586,7 +586,7 @@ clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #address-cells = <1>; + #interrupt-cells = <2>; #size-cells = <0>; #gpio-cells = <3>; -- cgit v1.2.3 From e288f1bac490791e7564474b89b7c48ee537b6a7 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Mon, 30 Jun 2014 23:57:52 +0200 Subject: ARM: dts: sun4i: Add AXP209 support to various boards At a node for the axp209, and where necessary the i2c controller to the dts for various boards. Note the axp209 regulators are omitted as we don't have any use for them yet, and on some boards were not sure how exactly they are wired up. Adding support for just the axp209 without the regulators is still useful, as it will give us power-button and poweroff support. Signed-off-by: Carlo Caione [hdegoede@redhat.com: Drop the regulator bits for now] Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-a1000.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-hackberry.dts | 15 +++++++++++++++ arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 21 +++++++++++++++------ arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 15 +++++++++++++++ arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 15 +++++++++++++++ arch/arm/boot/dts/sun4i-a10-pcduino.dts | 9 +++++++++ 7 files changed, 87 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index 0b97c071dd56..55d951070bff 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -98,6 +98,15 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index c200eacc66e8..539b693f69dd 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -90,6 +90,15 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; }; i2c1: i2c@01c2b000 { diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index 547fadcb984b..21df4e3f7ba3 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -92,6 +92,21 @@ pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; }; reg_emac_3v3: emac-3v3 { diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts index f13723e18b86..6b0c37812ade 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts @@ -40,12 +40,6 @@ status = "okay"; }; - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - }; - usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; @@ -67,6 +61,21 @@ ohci1: usb@01c1c400 { status = "okay"; }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; }; reg_usb1_vbus: usb1-vbus { diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index c01cea50cf0c..387770db995f 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -57,6 +57,21 @@ pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; }; reg_usb1_vbus: usb1-vbus { diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index d46a7dbecef5..d046d568f5a1 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts @@ -91,6 +91,21 @@ pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; }; leds { diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index fb03bccb78d2..6675bcd7860e 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -76,6 +76,15 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; -- cgit v1.2.3 From ec0c933d972ba69f06251f7d215723f61535fc16 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Mon, 30 Jun 2014 23:57:53 +0200 Subject: ARM: dts: sun7i: Add AXP209 support to various boards At a node for the axp209, and where necessary the i2c controller to the dts for various boards. Note the axp209 regulators are omitted as we don't have any use for them yet, and on some boards were not sure how exactly they are wired up. Adding support for just the axp209 without the regulators is still useful, as it will give us power-button and poweroff support. Signed-off-by: Carlo Caione [hdegoede@redhat.com: Drop the regulator bits for now] Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 10 ++++++++++ arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 10 ++++++++++ arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 16 ++++++++++++++++ arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 10 ++++++++++ 4 files changed, 46 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index a70f0b4aa4ed..53680983461a 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -82,6 +82,16 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + + interrupt-controller; + #interrupt-cells = <1>; + }; }; i2c1: i2c@01c2b000 { diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 96639d59e22c..a6c1a3c717bc 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -116,6 +116,16 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + + interrupt-controller; + #interrupt-cells = <1>; + }; }; i2c1: i2c@01c2b000 { diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts index b77308e90199..cba1567d5151 100644 --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts @@ -100,6 +100,22 @@ status = "okay"; }; + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + gmac: ethernet@01c50000 { pinctrl-names = "default"; pinctrl-0 = <&gmac_pins_mii_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index b759630bc9a9..9d669cdf031d 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -122,6 +122,16 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + + interrupt-controller; + #interrupt-cells = <1>; + }; }; i2c1: i2c@01c2b000 { -- cgit v1.2.3 From 1715a389949a4a3f03192268dfb3ac5710f2dd3c Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 30 Jun 2014 23:57:54 +0200 Subject: ARM: dts: sun7i: Rename sun7i-a20-ir to sun4i-a10-ir The sun7i block is the same as the one in the sun4i, rename the compatible to reflect this. Signed-off-by: Hans de Goede -- I've already included the matching change to sunxi-cir.c in my pull-req to Mauro. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index edf16b512f43..4011628c7381 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -786,7 +786,7 @@ }; ir0: ir@01c21800 { - compatible = "allwinner,sun7i-a20-ir"; + compatible = "allwinner,sun4i-a10-ir"; clocks = <&apb0_gates 6>, <&ir0_clk>; clock-names = "apb", "ir"; interrupts = <0 5 4>; @@ -795,7 +795,7 @@ }; ir1: ir@01c21c00 { - compatible = "allwinner,sun7i-a20-ir"; + compatible = "allwinner,sun4i-a10-ir"; clocks = <&apb0_gates 7>, <&ir1_clk>; clock-names = "apb", "ir"; interrupts = <0 6 4>; -- cgit v1.2.3 From abe36869a5dd5ac03a54eee3ad117bbe78efe792 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 30 Jun 2014 23:57:55 +0200 Subject: ARM: dts: sun7i: Add ir receiver support to a20-i12-tvbox Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts index cba1567d5151..6a67712d417a 100644 --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts @@ -94,6 +94,12 @@ }; }; + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; -- cgit v1.2.3 From 04089927981f295b42cd695485383b2d11283d59 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Mon, 30 Jun 2014 23:57:56 +0200 Subject: ARM: dts: sun7i: Add board support for LinkSprite pcDuino V3 The LinkSprite pcDuino V3 is an A20 based development board featuring arduino compatible io headers, 1G RAM, 4G nand, sata, rtl8188cus usb wifi and 100 Mbit ethernet using an ip101a phy: http://www.pcduino.com/pcduino-v3/ Signed-off-by: Zoltan HERPAI [hdegoede@redhat.com: Various cleanups, correct led pins] [hdegoede@redhat.com: Add axp209, ir and gpio-keys nodes] Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 173 +++++++++++++++++++++++++++++++ 2 files changed, 175 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun7i-a20-pcduino3.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 774a14b91151..796fea874183 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -379,7 +379,8 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-cubieboard2.dtb \ sun7i-a20-cubietruck.dtb \ sun7i-a20-i12-tvbox.dtb \ - sun7i-a20-olinuxino-micro.dtb + sun7i-a20-olinuxino-micro.dtb \ + sun7i-a20-pcduino3.dtb dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a23-ippo-q8h-v5.dtb dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts new file mode 100644 index 000000000000..046dfc0d45d8 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -0,0 +1,173 @@ +/* + * Copyright 2014 Zoltan HERPAI + * Zoltan HERPAI + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun7i-a20.dtsi" +/include/ "sunxi-common-regulators.dtsi" +#include +#include + +/ { + model = "LinkSprite pcDuino3"; + compatible = "linksprite,pcduino3", "allwinner,sun7i-a20"; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ahci: sata@01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + + pinctrl@01c20800 { + ahci_pwr_pin_a: ahci_pwr_pin@0 { + allwinner,pins = "PH2"; + }; + + led_pins_pcduino3: led_pins@0 { + allwinner,pins = "PH15", "PH16"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + key_pins_pcduino3: key_pins@0 { + allwinner,pins = "PH17", "PH18", "PH19"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + gmac: ethernet@01c50000 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_pcduino3>; + + tx { + label = "pcduino3:green:tx"; + gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; + }; + + rx { + label = "pcduino3:green:rx"; + gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_pins_pcduino3>; + #address-cells = <1>; + #size-cells = <0>; + button@0 { + label = "Key Back"; + linux,code = ; + gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; + }; + button@1 { + label = "Key Home"; + linux,code = ; + gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; + }; + button@2 { + label = "Key Menu"; + linux,code = ; + gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; + }; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; + + reg_ahci_5v: ahci-5v { + gpio = <&pio 7 2 0>; + status = "okay"; + }; +}; -- cgit v1.2.3 From 97cb8f1ed91fd1d4993cd18168b600a8294a7c6f Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 30 Jun 2014 23:57:57 +0200 Subject: ARM: dts: sun4i: Add new ba10-tvbox board The ba10 tvbox is an A10 based android tvbox, with 512M RAM, 8G nand flash, rtl8188ctv usb wifi 1 USB-A receptacle hooked up to an EHCI/OHCI controller, 1 USB-A receptacle hooked up to the OTG and 100Mbit ethernet using a rtl8201 phy. The PCB is labelled ba10 hence I've named the board ba10-tvbox. It is used in noname allwinner A10 tv-boxes. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts | 110 +++++++++++++++++++++++++++++ 2 files changed, 111 insertions(+) create mode 100644 arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 796fea874183..c3ee9fba892b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -360,6 +360,7 @@ dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \ stih416-b2020-revE.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ + sun4i-a10-ba10-tvbox.dtb \ sun4i-a10-cubieboard.dtb \ sun4i-a10-mini-xplus.dtb \ sun4i-a10-hackberry.dtb \ diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts new file mode 100644 index 000000000000..1763cc7ec023 --- /dev/null +++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts @@ -0,0 +1,110 @@ +/* + * Copyright 2014 Hans de Goede + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun4i-a10.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "BA10 tvbox"; + compatible = "allwinner,ba10-tvbox", "allwinner,sun4i-a10"; + + soc@01c00000 { + emac: ethernet@01c0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; + }; + + mdio@01c0b080 { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + + pinctrl@01c20800 { + usb2_vbus_pin_a: usb2_vbus_pin@0 { + allwinner,pins = "PH12"; + }; + }; + + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + gpio = <&pio 7 12 0>; + status = "okay"; + }; +}; -- cgit v1.2.3 From a4e1099a46a3ec76ae3a2a219a5931fe7fb2674d Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 30 Jun 2014 23:57:58 +0200 Subject: ARM: dts: sun4i: Add ir controller nodes and pinmux Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 37a6fb8013cc..459cb6377764 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -593,6 +593,20 @@ allwinner,drive = <0>; allwinner,pull = <1>; }; + + ir0_pins_a: ir0@0 { + allwinner,pins = "PB3","PB4"; + allwinner,function = "ir0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + ir1_pins_a: ir1@0 { + allwinner,pins = "PB22","PB23"; + allwinner,function = "ir1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { @@ -621,6 +635,24 @@ status = "disabled"; }; + ir0: ir@01c21800 { + compatible = "allwinner,sun4i-a10-ir"; + clocks = <&apb0_gates 6>, <&ir0_clk>; + clock-names = "apb", "ir"; + interrupts = <5>; + reg = <0x01c21800 0x40>; + status = "disabled"; + }; + + ir1: ir@01c21c00 { + compatible = "allwinner,sun4i-a10-ir"; + clocks = <&apb0_gates 7>, <&ir1_clk>; + clock-names = "apb", "ir"; + interrupts = <6>; + reg = <0x01c21c00 0x40>; + status = "disabled"; + }; + sid: eeprom@01c23800 { compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10>; -- cgit v1.2.3 From 4a5c586127253bdfa4d8b5bc72be1a9ad6ba5585 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 30 Jun 2014 23:57:59 +0200 Subject: ARM: dts: sun4i: Add ir node to various boards Tested on a cubieboard and the mini-x. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-a1000.dts | 6 ++++++ arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 6 ++++++ arch/arm/boot/dts/sun4i-a10-hackberry.dts | 6 ++++++ arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 13 +++++++++++++ 4 files changed, 31 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index 55d951070bff..9e99ade35e37 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -88,6 +88,12 @@ }; }; + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 539b693f69dd..3ce56bfbc0b5 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -80,6 +80,12 @@ }; }; + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index 21df4e3f7ba3..891ea446abae 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -87,6 +87,12 @@ }; }; + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index 387770db995f..b9ecce60f2e7 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -52,6 +52,19 @@ status = "okay"; }; + pinctrl@01c20800 { + ir0_pins_a: ir0@0 { + /* The ir receiver is not always populated */ + allwinner,pull = <1>; + }; + }; + + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; -- cgit v1.2.3 From 08ecb28a7047d4431b61b73ebf9b216de6b29444 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 23 Jun 2014 13:20:58 -0500 Subject: ARM: dts: am4372: let boards access all nodes through labels By providing labels for rtc, wdt, cpu and dispc nodes, boards can access them to add board-specific data. Signed-off-by: Felipe Balbi Tested-by: Franklin Cooper Jr. Tested-by: Tom Rini Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 49fa59622254..8d3c16304636 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -30,7 +30,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; @@ -270,7 +270,7 @@ ti,hwmods = "counter_32k"; }; - rtc@44e3e000 { + rtc: rtc@44e3e000 { compatible = "ti,am4372-rtc","ti,da830-rtc"; reg = <0x44e3e000 0x1000>; interrupts = ; interrupts = ; @@ -871,7 +871,7 @@ #size-cells = <1>; ranges; - dispc@4832a400 { + dispc: dispc@4832a400 { compatible = "ti,omap3-dispc"; reg = <0x4832a400 0x400>; interrupts = ; -- cgit v1.2.3 From 4a45787dec8a15b211110be807b4f4aad2828385 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 23 Jun 2014 13:20:59 -0500 Subject: ARM: dts: add support for AM437x StarterKit Add support for TI's AM437x StarterKit Evaluation Module. Cc: Josh Elliot Signed-off-by: Felipe Balbi Tested-by: Franklin Cooper Jr. Tested-by: Tom Rini Tested-by: Darren Etheridge Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/am437x-sk-evm.dts | 613 ++++++++++++++++++++++++++++++++++++ 2 files changed, 614 insertions(+) create mode 100644 arch/arm/boot/dts/am437x-sk-evm.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5986ff63b901..63d1e5399629 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -301,6 +301,7 @@ dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \ omap4-var-dvk-om44.dtb \ omap4-var-stk-om44.dtb dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \ + am437x-sk-evm.dtb \ am437x-gp-evm.dtb dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \ omap5-sbc-t54.dtb \ diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts new file mode 100644 index 000000000000..859ff3d620ee --- /dev/null +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -0,0 +1,613 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* AM437x SK EVM */ + +/dts-v1/; + +#include "am4372.dtsi" +#include +#include +#include +#include + +/ { + model = "TI AM437x SK EVM"; + compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43"; + + aliases { + display0 = &lcd0; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; + + sound { + compatible = "ti,da830-evm-audio"; + ti,model = "AM437x-SK-EVM"; + ti,audio-codec = <&tlv320aic3106>; + ti,mcasp-controller = <&mcasp1>; + ti,codec-clock-rate = <24000000>; + ti,audio-routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT"; + }; + + matrix_keypad: matrix_keypad@0 { + compatible = "gpio-matrix-keypad"; + + pinctrl-names = "default"; + pinctrl-0 = <&matrix_keypad_pins>; + + debounce-delay-ms = <5>; + col-scan-delay-us = <1500>; + + row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ + &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ + + col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */ + &gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */ + + linux,keymap = < + MATRIX_KEY(0, 0, KEY_DOWN) + MATRIX_KEY(0, 1, KEY_RIGHT) + MATRIX_KEY(1, 0, KEY_LEFT) + MATRIX_KEY(1, 1, KEY_UP) + >; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins>; + + led@0 { + label = "am437x-sk:red:heartbeat"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */ + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led@1 { + label = "am437x-sk:green:mmc1"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */ + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@2 { + label = "am437x-sk:blue:cpu0"; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */ + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led@3 { + label = "am437x-sk:blue:usr3"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */ + default-state = "off"; + }; + }; + + lcd0: display { + compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; + label = "lcd"; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + + panel-timing { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <43>; + hsync-len = <4>; + vback-porch = <12>; + vfront-porch = <4>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; +}; + +&am43xx_pinmux { + matrix_keypad_pins: matrix_keypad_pins { + pinctrl-single,pins = < + 0x24c (PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */ + 0x250 (PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */ + 0x254 (PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */ + 0x258 (PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */ + >; + }; + + leds_pins: leds_pins { + pinctrl-single,pins = < + 0x228 (PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */ + 0x22c (PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */ + 0x230 (PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */ + 0x234 (PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */ + >; + }; + + i2c0_pins: i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c1_pins: i2c1_pins { + pinctrl-single,pins = < + 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + ecap0_pins: backlight_pins { + pinctrl-single,pins = < + 0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ + >; + }; + + edt_ft5306_ts_pins: edt_ft5306_ts_pins { + pinctrl-single,pins = < + 0x74 (PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + 0x78 (PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ + + /* Slave 2 */ + 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + + /* Slave 2 reset value */ + 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + dss_pins: dss_pins { + pinctrl-single,pins = < + 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ + 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */ + 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ + 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ + 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ + 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ + 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ + 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ + + >; + }; + + qspi_pins: qspi_pins { + pinctrl-single,pins = < + 0x7c (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */ + 0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ + 0x90 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ + 0x94 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ + 0x98 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */ + 0x9c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ + >; + }; + + mcasp1_pins: mcasp1_pins { + pinctrl-single,pins = < + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ + 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ + >; + }; + + lcd_pins: lcd_pins { + pinctrl-single,pins = < + /* GPIO 5_8 to select LCD / HDMI */ + 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + + tps@24 { + compatible = "ti,tps65218"; + reg = <0x24>; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + compatible = "ti,tps65218-dcdc1"; + /* VDD_CORE limits min of OPP50 and max of OPP100 */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + compatible = "ti,tps65218-dcdc2"; + /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + compatible = "ti,tps65218-dcdc3"; + regulator-name = "vdds_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc4: regulator-dcdc4 { + compatible = "ti,tps65218-dcdc4"; + regulator-name = "v3_3d"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,tps65218-ldo1"; + regulator-name = "v1_8d"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + }; + + at24@50 { + compatible = "at24,24c256"; + pagesize = <64>; + reg = <0x50>; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + + edt-ft5306@38 { + status = "okay"; + compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; + pinctrl-names = "default"; + pinctrl-0 = <&edt_ft5306_ts_pins>; + + reg = <0x38>; + interrupt-parent = <&gpio0>; + interrupts = <31 0>; + + wake-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + + touchscreen-size-x = <480>; + touchscreen-size-y = <272>; + }; + + tlv320aic3106: tlv320aic3106@1b { + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + status = "okay"; + + /* Regulators */ + AVDD-supply = <&dcdc4>; + IOVDD-supply = <&dcdc4>; + DRVDD-supply = <&dcdc4>; + DVDD-supply = <&ldo1>; + }; + + lis331dlh@18 { + compatible = "st,lis331dlh"; + reg = <0x18>; + status = "okay"; + + Vdd-supply = <&dcdc4>; + Vdd_IO-supply = <&dcdc4>; + interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&ecap0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + + vmmc-supply = <&dcdc4>; + bus-width = <4>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; +}; + +&usb2_phy1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb2_phy2 { + status = "okay"; +}; + +&usb2 { + dr_mode = "host"; + status = "okay"; +}; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_pins>; + + spi-max-frequency = <48000000>; + m25p80@0 { + compatible = "mx66l51235l"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-cpol; + spi-cpha; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first 512KiB + * for a valid file to boot(XIP). + */ + partition@0 { + label = "QSPI.U_BOOT"; + reg = <0x00000000 0x000080000>; + }; + partition@1 { + label = "QSPI.U_BOOT.backup"; + reg = <0x00080000 0x00080000>; + }; + partition@2 { + label = "QSPI.U-BOOT-SPL_OS"; + reg = <0x00100000 0x00010000>; + }; + partition@3 { + label = "QSPI.U_BOOT_ENV"; + reg = <0x00110000 0x00010000>; + }; + partition@4 { + label = "QSPI.U-BOOT-ENV.backup"; + reg = <0x00120000 0x00010000>; + }; + partition@5 { + label = "QSPI.KERNEL"; + reg = <0x00130000 0x0800000>; + }; + partition@6 { + label = "QSPI.FILESYSTEM"; + reg = <0x00930000 0x36D0000>; + }; + }; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + dual_emac = <1>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <4>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <5>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <2>; +}; + +&elm { + status = "okay"; +}; + +&mcasp1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcasp1_pins>; + + status = "okay"; + + op-mode = <0>; + tdm-slots = <2>; + serial-dir = < + 0 0 1 2 + >; + + tx-num-evt = <1>; + rx-num-evt = <1>; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_pins>; + + port { + dpi_out: endpoint@0 { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; -- cgit v1.2.3 From 944ee5dc154b1618d4c794376af237f370c1e6b3 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 20 Feb 2014 19:09:18 +0200 Subject: ARM: OMAP2: convert sys_ck and osc_ck to standard clock types osc_ck can be simply defined as a multiplexer clock, and the sys_ck can be a simple divider. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Makefile | 3 +- arch/arm/mach-omap2/cclock2420_data.c | 52 ++++++++++++++------------ arch/arm/mach-omap2/cclock2430_data.c | 60 ++++++++++++++++-------------- arch/arm/mach-omap2/clkt2xxx_osc.c | 69 ----------------------------------- arch/arm/mach-omap2/clkt2xxx_sys.c | 47 ------------------------ arch/arm/mach-omap2/clock2xxx.h | 2 - arch/arm/mach-omap2/cm-regbits-24xx.h | 1 + arch/arm/mach-omap2/pm24xx.c | 4 ++ 8 files changed, 67 insertions(+), 171 deletions(-) delete mode 100644 arch/arm/mach-omap2/clkt2xxx_osc.c delete mode 100644 arch/arm/mach-omap2/clkt2xxx_sys.c (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 8421f38cf445..b5dc4b5aaac3 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -174,10 +174,9 @@ obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o +obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c index 3662f4d4c8ea..3e46ac188533 100644 --- a/arch/arm/mach-omap2/cclock2420_data.c +++ b/arch/arm/mach-omap2/cclock2420_data.c @@ -57,40 +57,39 @@ DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); -static struct clk osc_ck; +DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0); -static const struct clk_ops osc_ck_ops = { - .recalc_rate = &omap2_osc_clk_recalc, -}; +DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0); -static struct clk_hw_omap osc_ck_hw = { - .hw = { - .clk = &osc_ck, - }, -}; +DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_26m_ck, CLK_IS_ROOT, 26000000, 0x0); -static struct clk osc_ck = { - .name = "osc_ck", - .ops = &osc_ck_ops, - .hw = &osc_ck_hw.hw, - .flags = CLK_IS_ROOT, +/* 26M ck is a dummy, added to fill the hole in the aplls_clkin parent list */ +static const char *aplls_clkin_ck_parent_names[] = { + "virt_19200000_ck", "virt_26m_ck", "virt_13m_ck", "virt_12m_ck", }; +DEFINE_CLK_MUX(aplls_clkin_ck, aplls_clkin_ck_parent_names, NULL, 0x0, + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_APLLS_CLKIN_SHIFT, + OMAP24XX_APLLS_CLKIN_WIDTH, 0x0, NULL); + DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); -static struct clk sys_ck; +DEFINE_CLK_FIXED_FACTOR(aplls_clkin_x2_ck, "aplls_clkin_ck", &aplls_clkin_ck, + 0x0, 2, 1); -static const char *sys_ck_parent_names[] = { - "osc_ck", +static const char *osc_ck_parent_names[] = { + "aplls_clkin_ck", "aplls_clkin_x2_ck", }; -static const struct clk_ops sys_ck_ops = { - .init = &omap2_init_clk_clkdm, - .recalc_rate = &omap2xxx_sys_clk_recalc, -}; +DEFINE_CLK_MUX(osc_ck, osc_ck_parent_names, NULL, 0x0, + OMAP2420_PRCM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT, + OMAP_SYSCLKDIV_WIDTH, CLK_MUX_INDEX_ONE, NULL); -DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm"); -DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops); +DEFINE_CLK_DIVIDER(sys_ck, "osc_ck", &osc_ck, 0x0, OMAP2420_PRCM_CLKSRC_CTRL, + OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); static struct dpll_data dpll_dd = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), @@ -1741,6 +1740,12 @@ static struct omap_clk omap2420_clks[] = { /* external root sources */ CLK(NULL, "func_32k_ck", &func_32k_ck), CLK(NULL, "secure_32k_ck", &secure_32k_ck), + CLK(NULL, "virt_12m_ck", &virt_12m_ck), + CLK(NULL, "virt_13m_ck", &virt_13m_ck), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), + CLK(NULL, "virt_26m_ck", &virt_26m_ck), + CLK(NULL, "aplls_clkin_ck", &aplls_clkin_ck), + CLK(NULL, "aplls_clkin_x2_ck", &aplls_clkin_x2_ck), CLK(NULL, "osc_ck", &osc_ck), CLK(NULL, "sys_ck", &sys_ck), CLK(NULL, "alt_ck", &alt_ck), @@ -1904,7 +1909,6 @@ static const char *enable_init_clks[] = { int __init omap2420_clk_init(void) { - prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; cpu_mask = RATE_IN_242X; rate_table = omap2420_rate_table; diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c index 5e4b037bb24c..582abc221ece 100644 --- a/arch/arm/mach-omap2/cclock2430_data.c +++ b/arch/arm/mach-omap2/cclock2430_data.c @@ -55,42 +55,39 @@ DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); -static struct clk osc_ck; +DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0); -static const struct clk_ops osc_ck_ops = { - .enable = &omap2_enable_osc_ck, - .disable = omap2_disable_osc_ck, - .recalc_rate = &omap2_osc_clk_recalc, -}; +DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0); -static struct clk_hw_omap osc_ck_hw = { - .hw = { - .clk = &osc_ck, - }, -}; +DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); -static struct clk osc_ck = { - .name = "osc_ck", - .ops = &osc_ck_ops, - .hw = &osc_ck_hw.hw, - .flags = CLK_IS_ROOT, +DEFINE_CLK_FIXED_RATE(virt_26m_ck, CLK_IS_ROOT, 26000000, 0x0); + +/* 26M ck is a dummy, added to filla hole in the aplls_clkin parent list */ +static const char *aplls_clkin_ck_parent_names[] = { + "virt_19200000_ck", "virt_26m_ck", "virt_13m_ck", "virt_12m_ck", }; +DEFINE_CLK_MUX(aplls_clkin_ck, aplls_clkin_ck_parent_names, NULL, 0x0, + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_APLLS_CLKIN_SHIFT, + OMAP24XX_APLLS_CLKIN_WIDTH, 0x0, NULL); + DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); -static struct clk sys_ck; +DEFINE_CLK_FIXED_FACTOR(aplls_clkin_x2_ck, "aplls_clkin_ck", &aplls_clkin_ck, + 0x0, 2, 1); -static const char *sys_ck_parent_names[] = { - "osc_ck", +static const char *osc_ck_parent_names[] = { + "aplls_clkin_ck", "aplls_clkin_x2_ck", }; -static const struct clk_ops sys_ck_ops = { - .init = &omap2_init_clk_clkdm, - .recalc_rate = &omap2xxx_sys_clk_recalc, -}; +DEFINE_CLK_MUX(osc_ck, osc_ck_parent_names, NULL, 0x0, + OMAP2430_PRCM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT, + OMAP_SYSCLKDIV_WIDTH, CLK_MUX_INDEX_ONE, NULL); -DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm"); -DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops); +DEFINE_CLK_DIVIDER(sys_ck, "osc_ck", &osc_ck, 0x0, OMAP2430_PRCM_CLKSRC_CTRL, + OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); static struct dpll_data dpll_dd = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), @@ -1308,7 +1305,11 @@ static struct clk_hw_omap mdm_osc_ck_hw = { .clkdm_name = "mdm_clkdm", }; -DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops); +static const char *mdm_osc_ck_parent_names[] = { + "osc_ck", +}; + +DEFINE_STRUCT_CLK(mdm_osc_ck, mdm_osc_ck_parent_names, aes_ick_ops); static struct clk mmchs1_fck; @@ -1842,6 +1843,12 @@ static struct omap_clk omap2430_clks[] = { /* external root sources */ CLK(NULL, "func_32k_ck", &func_32k_ck), CLK(NULL, "secure_32k_ck", &secure_32k_ck), + CLK(NULL, "virt_12m_ck", &virt_12m_ck), + CLK(NULL, "virt_13m_ck", &virt_13m_ck), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), + CLK(NULL, "virt_26m_ck", &virt_26m_ck), + CLK(NULL, "aplls_clkin_ck", &aplls_clkin_ck), + CLK(NULL, "aplls_clkin_x2_ck", &aplls_clkin_x2_ck), CLK(NULL, "osc_ck", &osc_ck), CLK("twl", "fck", &osc_ck), CLK(NULL, "sys_ck", &sys_ck), @@ -2021,7 +2028,6 @@ static const char *enable_init_clks[] = { int __init omap2430_clk_init(void) { - prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; cpu_mask = RATE_IN_243X; rate_table = omap2430_rate_table; diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c deleted file mode 100644 index 0717dff1bc04..000000000000 --- a/arch/arm/mach-omap2/clkt2xxx_osc.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * OMAP2xxx osc_clk-specific clock code - * - * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2010 Nokia Corporation - * - * Contacts: - * Richard Woodruff - * Paul Walmsley - * - * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, - * Gordon McNutt and RidgeRun, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include -#include -#include -#include -#include - -#include "clock.h" -#include "clock2xxx.h" -#include "prm2xxx_3xxx.h" -#include "prm-regbits-24xx.h" - -/* - * XXX This does not actually enable the osc_ck, since the osc_ck must - * be running for this function to be called. Instead, this function - * is used to disable an autoidle mode on the osc_ck. The existing - * clk_enable/clk_disable()-based usecounting for osc_ck should be - * replaced with autoidle-based usecounting. - */ -int omap2_enable_osc_ck(struct clk_hw *clk) -{ - u32 pcc; - - pcc = readl_relaxed(prcm_clksrc_ctrl); - - writel_relaxed(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); - - return 0; -} - -/* - * XXX This does not actually disable the osc_ck, since doing so would - * immediately halt the system. Instead, this function is used to - * enable an autoidle mode on the osc_ck. The existing - * clk_enable/clk_disable()-based usecounting for osc_ck should be - * replaced with autoidle-based usecounting. - */ -void omap2_disable_osc_ck(struct clk_hw *clk) -{ - u32 pcc; - - pcc = readl_relaxed(prcm_clksrc_ctrl); - - writel_relaxed(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); -} - -unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, - unsigned long parent_rate) -{ - return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv(); -} diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c deleted file mode 100644 index 58dd3a9b726c..000000000000 --- a/arch/arm/mach-omap2/clkt2xxx_sys.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * OMAP2xxx sys_clk-specific clock code - * - * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2010 Nokia Corporation - * - * Contacts: - * Richard Woodruff - * Paul Walmsley - * - * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, - * Gordon McNutt and RidgeRun, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include -#include -#include -#include - -#include "clock.h" -#include "clock2xxx.h" -#include "prm2xxx_3xxx.h" -#include "prm-regbits-24xx.h" - -void __iomem *prcm_clksrc_ctrl; - -u32 omap2xxx_get_sysclkdiv(void) -{ - u32 div; - - div = readl_relaxed(prcm_clksrc_ctrl); - div &= OMAP_SYSCLKDIV_MASK; - div >>= OMAP_SYSCLKDIV_SHIFT; - - return div; -} - -unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk, - unsigned long parent_rate) -{ - return parent_rate / omap2xxx_get_sysclkdiv(); -} diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index 45f41a411603..a090225ceeba 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h @@ -45,8 +45,6 @@ int omap2430_clk_init(void); #define omap2430_clk_init() do { } while(0) #endif -extern void __iomem *prcm_clksrc_ctrl; - extern struct clk_hw *dclk_hw; int omap2_enable_osc_ck(struct clk_hw *hw); void omap2_disable_osc_ck(struct clk_hw *hw); diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 8538669cc2ad..d7a5d11cbcbf 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -107,6 +107,7 @@ #define OMAP24XX_AUTO_DPLL_SHIFT 0 #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) #define OMAP24XX_APLLS_CLKIN_SHIFT 23 +#define OMAP24XX_APLLS_CLKIN_WIDTH 3 #define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) #define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index a5ea988ff340..d7ac05c6e5e2 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -249,6 +249,10 @@ static void __init prcm_setup_regs(void) /* Enable wake-up events */ omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, WKUP_MOD, PM_WKEN); + + /* Enable SYS_CLKEN control when all domains idle */ + omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD, + OMAP2_PRCM_CLKSRC_CTRL_OFFSET); } int __init omap2_pm_init(void) -- cgit v1.2.3 From b675d1ecced015f180d5d43056bed94cda87d80f Mon Sep 17 00:00:00 2001 From: Darren Etheridge Date: Tue, 1 Jul 2014 16:00:20 -0500 Subject: ARM: dts: am335x-evmsk: enable display and lcd panel support Add the necessary nodes to enable the LCD controller and the LCD panel that is attached to the Texas Instruments AM335x EVMSK platform. Also setup the necessary pin mux within the DT file to drive the LCD connector and add the correct pinmux settings for the lcd pins to be configured to when the SoC goes into sleep state for the minimum power consumption. For the sleep mode LCD pin settings, MUX_MODE7 is chosen as this corresponds to switching the pins into input GPIO's with an internal pulldown. Which has been determined to offer the lowest power solution vs leaving the pins configured in LCD mode. Signed-off-by: Darren Etheridge Acked-by: Wolfram Sang Tested-by: Felipe Balbi Acked-by: Tomi Valkeinen Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-evmsk.dts | 105 +++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index ab9a34ce524c..59766e2c2980 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -149,12 +149,113 @@ "Headphone Jack", "HPLOUT", "Headphone Jack", "HPROUT"; }; + + panel { + compatible = "ti,tilcdc,panel"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcd_pins_default>; + pinctrl-1 = <&lcd_pins_sleep>; + status = "okay"; + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <32>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + display-timings { + 480x272 { + hactive = <480>; + vactive = <272>; + hback-porch = <43>; + hfront-porch = <8>; + hsync-len = <4>; + vback-porch = <12>; + vfront-porch = <4>; + vsync-len = <10>; + clock-frequency = <9000000>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; + }; }; &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; + lcd_pins_default: lcd_pins_default { + pinctrl-single,pins = < + 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ + 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ + 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ + 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ + 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ + 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ + 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ + 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ + 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + + lcd_pins_sleep: lcd_pins_sleep { + pinctrl-single,pins = < + 0x20 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */ + 0x24 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */ + 0x28 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */ + 0x2c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */ + 0x30 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */ + 0x34 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */ + 0x38 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */ + 0x3c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */ + 0xa0 (PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */ + 0xa4 (PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */ + 0xa8 (PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */ + 0xac (PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */ + 0xb0 (PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */ + 0xb4 (PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */ + 0xb8 (PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */ + 0xbc (PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */ + 0xc0 (PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */ + 0xc4 (PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */ + 0xc8 (PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */ + 0xcc (PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */ + 0xd0 (PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */ + 0xd4 (PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */ + 0xd8 (PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */ + 0xdc (PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */ + 0xe0 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */ + 0xe4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */ + 0xe8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */ + 0xec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + + user_leds_s0: user_leds_s0 { pinctrl-single,pins = < 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ @@ -573,3 +674,7 @@ ti,wire-config = <0x00 0x11 0x22 0x33>; }; }; + +&lcdc { + status = "okay"; +}; -- cgit v1.2.3 From a37f05ac094fb0474ddaea8bcfa2c18e0df8cb2e Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 21 Feb 2014 15:33:05 +0200 Subject: ARM: OMAP2420: clock: get rid of fixed-div property use Cleans up the code a bit and is useful for clock data DT conversion. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/cclock2420_data.c | 15 ++++----------- arch/arm/mach-omap2/clock.c | 21 --------------------- arch/arm/mach-omap2/clock.h | 3 --- 3 files changed, 4 insertions(+), 35 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c index 3e46ac188533..3b0beea8440d 100644 --- a/arch/arm/mach-omap2/cclock2420_data.c +++ b/arch/arm/mach-omap2/cclock2420_data.c @@ -1025,18 +1025,12 @@ DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel, OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait, dsp_fck_parent_names, dsp_fck_ops); +DEFINE_CLK_FIXED_FACTOR(iva1_ifck_div, "iva1_ifck", &iva1_ifck, 0x0, 1, 2); + static struct clk iva1_mpu_int_ifck; static const char *iva1_mpu_int_ifck_parent_names[] = { - "iva1_ifck", -}; - -static const struct clk_ops iva1_mpu_int_ifck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap_fixed_divisor_recalc, + "iva1_ifck_div", }; static struct clk_hw_omap iva1_mpu_int_ifck_hw = { @@ -1047,11 +1041,10 @@ static struct clk_hw_omap iva1_mpu_int_ifck_hw = { .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, .clkdm_name = "iva1_clkdm", - .fixed_div = 2, }; DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names, - iva1_mpu_int_ifck_ops); + aes_ick_ops); static struct clk mailboxes_ick; diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 591581a66532..4ac6e3d2df03 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -81,27 +81,6 @@ u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) return val; } -/* - * Used for clocks that have the same value as the parent clock, - * divided by some factor - */ -unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_hw_omap *oclk; - - if (!hw) { - pr_warn("%s: hw is NULL\n", __func__); - return -EINVAL; - } - - oclk = to_clk_hw_omap(hw); - - WARN_ON(!oclk->fixed_div); - - return parent_rate / oclk->fixed_div; -} - /* * OMAP2+ specific clock functions */ diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 12f54d428d7c..bb6723842c4a 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -178,9 +178,6 @@ struct clksel { const struct clksel_rate *rates; }; -unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, - unsigned long parent_rate); - /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0 #define CORE_CLK_SRC_DPLL 0x1 -- cgit v1.2.3 From ee200119c03c7d43ebaf7ae70985244aedb0586d Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 25 Feb 2014 09:21:39 +0200 Subject: ARM: OMAP2: PRM: add support for OMAP2 specific clock providers This patch adds support for initializing also omap2-prcm and omap2-scrm through DT. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/prm_common.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 25e8b8232115..76ca320f007c 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -472,6 +472,8 @@ static struct of_device_id omap_prcm_dt_match_table[] = { { .compatible = "ti,am3-scrm" }, { .compatible = "ti,am4-prcm" }, { .compatible = "ti,am4-scrm" }, + { .compatible = "ti,omap2-prcm" }, + { .compatible = "ti,omap2-scrm" }, { .compatible = "ti,omap3-prm" }, { .compatible = "ti,omap3-cm" }, { .compatible = "ti,omap3-scrm" }, -- cgit v1.2.3 From 69a1e7a1feb5bac44a5a76380768596a12a33050 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 24 Feb 2014 18:51:05 +0200 Subject: ARM: OMAP2: clock: use DT clock boot if available Otherwise legacy boot clock data is used. This patch also includes the clock data files to the base dtsi files. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap2420.dtsi | 3 +++ arch/arm/boot/dts/omap2430.dtsi | 3 +++ arch/arm/mach-omap2/io.c | 15 +++++++++++++-- 3 files changed, 19 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index e83b0468080c..2ad3e3b29411 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -182,3 +182,6 @@ &i2c2 { compatible = "ti,omap2420-i2c"; }; + +/include/ "omap24xx-clocks.dtsi" +/include/ "omap2420-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index c4e8013801ee..f9ab99d5c951 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -288,3 +288,6 @@ &i2c2 { compatible = "ti,omap2430-i2c"; }; + +/include/ "omap24xx-clocks.dtsi" +/include/ "omap2430-clocks.dtsi" diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 8f559450c876..80bf63359c24 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -53,6 +53,7 @@ #include "prm2xxx.h" #include "prm3xxx.h" #include "prm44xx.h" +#include "opp2xxx.h" /* * omap_clk_soc_init: points to a function that does the SoC-specific @@ -410,7 +411,12 @@ void __init omap2420_init_early(void) omap242x_clockdomains_init(); omap2420_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_soc_init = omap2420_clk_init; + if (of_have_populated_dt()) { + omap_clk_soc_init = omap2420_dt_clk_init; + rate_table = omap2420_rate_table; + } else { + omap_clk_soc_init = omap2420_clk_init; + } } void __init omap2420_init_late(void) @@ -439,7 +445,12 @@ void __init omap2430_init_early(void) omap243x_clockdomains_init(); omap2430_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_soc_init = omap2430_clk_init; + if (of_have_populated_dt()) { + omap_clk_soc_init = omap2430_dt_clk_init; + rate_table = omap2430_rate_table; + } else { + omap_clk_soc_init = omap2430_clk_init; + } } void __init omap2430_init_late(void) -- cgit v1.2.3 From 6a194a6e2a8fa55e133936a124ed500aea434116 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 4 Mar 2014 10:53:54 +0200 Subject: ARM: OMAP24xx: clock: remove legacy clock data This is no longer needed as clock data is provided through DT. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Makefile | 3 +- arch/arm/mach-omap2/cclock2420_data.c | 1928 ------------------------------- arch/arm/mach-omap2/cclock2430_data.c | 2054 --------------------------------- arch/arm/mach-omap2/io.c | 16 +- 4 files changed, 5 insertions(+), 3996 deletions(-) delete mode 100644 arch/arm/mach-omap2/cclock2420_data.c delete mode 100644 arch/arm/mach-omap2/cclock2430_data.c (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index b5dc4b5aaac3..7d387c008738 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -178,8 +178,7 @@ obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o -obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o -obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o +obj-$(CONFIG_SOC_OMAP2430) += clock2430.o obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c deleted file mode 100644 index 3b0beea8440d..000000000000 --- a/arch/arm/mach-omap2/cclock2420_data.c +++ /dev/null @@ -1,1928 +0,0 @@ -/* - * OMAP2420 clock data - * - * Copyright (C) 2005-2012 Texas Instruments, Inc. - * Copyright (C) 2004-2011 Nokia Corporation - * - * Contacts: - * Richard Woodruff - * Paul Walmsley - * Updated to COMMON clk format by Rajendra Nayak - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include "soc.h" -#include "iomap.h" -#include "clock.h" -#include "clock2xxx.h" -#include "opp2xxx.h" -#include "cm2xxx.h" -#include "prm2xxx.h" -#include "prm-regbits-24xx.h" -#include "cm-regbits-24xx.h" -#include "sdrc.h" -#include "control.h" - -#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR - -/* - * 2420 clock tree. - * - * NOTE:In many cases here we are assigning a 'default' parent. In - * many cases the parent is selectable. The set parent calls will - * also switch sources. - * - * Several sources are given initial rates which may be wrong, this will - * be fixed up in the init func. - * - * Things are broadly separated below by clock domains. It is - * noteworthy that most peripherals have dependencies on multiple clock - * domains. Many get their interface clocks from the L4 domain, but get - * functional clocks from fixed sources or other core domain derived - * clocks. - */ - -DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0); - -DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); - -DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_26m_ck, CLK_IS_ROOT, 26000000, 0x0); - -/* 26M ck is a dummy, added to fill the hole in the aplls_clkin parent list */ -static const char *aplls_clkin_ck_parent_names[] = { - "virt_19200000_ck", "virt_26m_ck", "virt_13m_ck", "virt_12m_ck", -}; - -DEFINE_CLK_MUX(aplls_clkin_ck, aplls_clkin_ck_parent_names, NULL, 0x0, - OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_APLLS_CLKIN_SHIFT, - OMAP24XX_APLLS_CLKIN_WIDTH, 0x0, NULL); - -DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); - -DEFINE_CLK_FIXED_FACTOR(aplls_clkin_x2_ck, "aplls_clkin_ck", &aplls_clkin_ck, - 0x0, 2, 1); - -static const char *osc_ck_parent_names[] = { - "aplls_clkin_ck", "aplls_clkin_x2_ck", -}; - -DEFINE_CLK_MUX(osc_ck, osc_ck_parent_names, NULL, 0x0, - OMAP2420_PRCM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT, - OMAP_SYSCLKDIV_WIDTH, CLK_MUX_INDEX_ONE, NULL); - -DEFINE_CLK_DIVIDER(sys_ck, "osc_ck", &osc_ck, 0x0, OMAP2420_PRCM_CLKSRC_CTRL, - OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -static struct dpll_data dpll_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .mult_mask = OMAP24XX_DPLL_MULT_MASK, - .div1_mask = OMAP24XX_DPLL_DIV_MASK, - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_mask = OMAP24XX_EN_DPLL_MASK, - .max_multiplier = 1023, - .min_divider = 1, - .max_divider = 16, -}; - -static struct clk dpll_ck; - -static const char *dpll_ck_parent_names[] = { - "sys_ck", -}; - -static const struct clk_ops dpll_ck_ops = { - .init = &omap2_init_clk_clkdm, - .get_parent = &omap2_init_dpll_parent, - .recalc_rate = &omap2_dpllcore_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap2_reprogram_dpllcore, -}; - -static struct clk_hw_omap dpll_ck_hw = { - .hw = { - .clk = &dpll_ck, - }, - .ops = &clkhwops_omap2xxx_dpll, - .dpll_data = &dpll_dd, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); - -static struct clk core_ck; - -static const char *core_ck_parent_names[] = { - "dpll_ck", -}; - -static const struct clk_ops core_ck_ops = { - .init = &omap2_init_clk_clkdm, -}; - -DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm"); -DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops); - -DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -static struct clk aes_ick; - -static const char *aes_ick_parent_names[] = { - "l4_ck", -}; - -static const struct clk_ops aes_ick_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, -}; - -static struct clk_hw_omap aes_ick_hw = { - .hw = { - .clk = &aes_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_AES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk apll54_ck; - -static const struct clk_ops apll54_ck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_clk_apll54_enable, - .disable = &omap2_clk_apll54_disable, - .recalc_rate = &omap2_clk_apll54_recalc, -}; - -static struct clk_hw_omap apll54_ck_hw = { - .hw = { - .clk = &apll54_ck, - }, - .ops = &clkhwops_apll54, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); - -static struct clk apll96_ck; - -static const struct clk_ops apll96_ck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_clk_apll96_enable, - .disable = &omap2_clk_apll96_disable, - .recalc_rate = &omap2_clk_apll96_recalc, -}; - -static struct clk_hw_omap apll96_ck_hw = { - .hw = { - .clk = &apll96_ck, - }, - .ops = &clkhwops_apll96, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops); - -static struct clk func_96m_ck; - -static const char *func_96m_ck_parent_names[] = { - "apll96_ck", -}; - -DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm"); -DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops); - -static struct clk cam_fck; - -static const char *cam_fck_parent_names[] = { - "func_96m_ck", -}; - -static struct clk_hw_omap cam_fck_hw = { - .hw = { - .clk = &cam_fck, - }, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_CAM_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk cam_ick; - -static struct clk_hw_omap cam_ick_hw = { - .hw = { - .clk = &cam_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_CAM_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk des_ick; - -static struct clk_hw_omap des_ick_hw = { - .hw = { - .clk = &des_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_DES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate dsp_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_242X }, - { .div = 8, .val = 8, .flags = RATE_IN_242X }, - { .div = 12, .val = 12, .flags = RATE_IN_242X }, - { .div = 0 } -}; - -static const struct clksel dsp_fck_clksel[] = { - { .parent = &core_ck, .rates = dsp_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *dsp_fck_parent_names[] = { - "core_ck", -}; - -static const struct clk_ops dsp_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, -}; - -DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_DSP_MASK, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, - dsp_fck_parent_names, dsp_fck_ops); - -static const struct clksel dsp_ick_clksel[] = { - { .parent = &dsp_fck, .rates = dsp_ick_rates }, - { .parent = NULL }, -}; - -static const char *dsp_ick_parent_names[] = { - "dsp_fck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_DSP_IF_MASK, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), - OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait, - dsp_ick_parent_names, dsp_fck_ops); - -static const struct clksel_rate dss1_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate dss1_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 5, .val = 5, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_24XX }, - { .div = 8, .val = 8, .flags = RATE_IN_24XX }, - { .div = 9, .val = 9, .flags = RATE_IN_24XX }, - { .div = 12, .val = 12, .flags = RATE_IN_24XX }, - { .div = 16, .val = 16, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel dss1_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, - { .parent = &core_ck, .rates = dss1_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *dss1_fck_parent_names[] = { - "sys_ck", "core_ck", -}; - -static struct clk dss1_fck; - -static const struct clk_ops dss1_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_DSS1_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_DSS1_SHIFT, NULL, - dss1_fck_parent_names, dss1_fck_ops); - -static const struct clksel_rate dss2_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate dss2_fck_48m_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate func_48m_apll96_rates[] = { - { .div = 2, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate func_48m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel func_48m_clksel[] = { - { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, - { .parent = &alt_ck, .rates = func_48m_alt_rates }, - { .parent = NULL }, -}; - -static const char *func_48m_ck_parent_names[] = { - "apll96_ck", "alt_ck", -}; - -static struct clk func_48m_ck; - -static const struct clk_ops func_48m_ck_ops = { - .init = &omap2_init_clk_clkdm, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -static struct clk_hw_omap func_48m_ck_hw = { - .hw = { - .clk = &func_48m_ck, - }, - .clksel = func_48m_clksel, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_48M_SOURCE_MASK, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops); - -static const struct clksel dss2_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, - { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, - { .parent = NULL }, -}; - -static const char *dss2_fck_parent_names[] = { - "sys_ck", "func_48m_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_DSS2_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_DSS2_SHIFT, NULL, - dss2_fck_parent_names, dss1_fck_ops); - -static const char *func_54m_ck_parent_names[] = { - "apll54_ck", "alt_ck", -}; - -DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, - OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, - 0x0, NULL); - -static struct clk dss_54m_fck; - -static const char *dss_54m_fck_parent_names[] = { - "func_54m_ck", -}; - -static struct clk_hw_omap dss_54m_fck_hw = { - .hw = { - .clk = &dss_54m_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_TV_SHIFT, - .clkdm_name = "dss_clkdm", -}; - -DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); - -static struct clk dss_ick; - -static struct clk_hw_omap dss_ick_hw = { - .hw = { - .clk = &dss_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_DSS1_SHIFT, - .clkdm_name = "dss_clkdm", -}; - -DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk eac_fck; - -static struct clk_hw_omap eac_fck_hw = { - .hw = { - .clk = &eac_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_EAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk eac_ick; - -static struct clk_hw_omap eac_ick_hw = { - .hw = { - .clk = &eac_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_EAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk emul_ck; - -static struct clk_hw_omap emul_ck_hw = { - .hw = { - .clk = &emul_ck, - }, - .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL, - .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); - -DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); - -static struct clk fac_fck; - -static const char *fac_fck_parent_names[] = { - "func_12m_ck", -}; - -static struct clk_hw_omap fac_fck_hw = { - .hw = { - .clk = &fac_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk fac_ick; - -static struct clk_hw_omap fac_ick_hw = { - .hw = { - .clk = &fac_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel gfx_fck_clksel[] = { - { .parent = &core_l3_ck, .rates = gfx_l3_rates }, - { .parent = NULL }, -}; - -static const char *gfx_2d_fck_parent_names[] = { - "core_l3_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel, - OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - OMAP_CLKSEL_GFX_MASK, - OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - OMAP24XX_EN_2D_SHIFT, &clkhwops_wait, - gfx_2d_fck_parent_names, dsp_fck_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, - OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - OMAP_CLKSEL_GFX_MASK, - OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, - gfx_2d_fck_parent_names, dsp_fck_ops); - -static struct clk gfx_ick; - -static const char *gfx_ick_parent_names[] = { - "core_l3_ck", -}; - -static struct clk_hw_omap gfx_ick_hw = { - .hw = { - .clk = &gfx_ick, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), - .enable_bit = OMAP_EN_GFX_SHIFT, - .clkdm_name = "gfx_clkdm", -}; - -DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); - -static struct clk gpios_fck; - -static const char *gpios_fck_parent_names[] = { - "func_32k_ck", -}; - -static struct clk_hw_omap gpios_fck_hw = { - .hw = { - .clk = &gpios_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops); - -static struct clk gpios_ick; - -static const char *gpios_ick_parent_names[] = { - "sys_ck", -}; - -static struct clk_hw_omap gpios_ick_hw = { - .hw = { - .clk = &gpios_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk gpmc_fck; - -static struct clk_hw_omap gpmc_fck_hw = { - .hw = { - .clk = &gpmc_fck, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops); - -static const struct clksel_rate gpt_alt_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel omap24xx_gpt_clksel[] = { - { .parent = &func_32k_ck, .rates = gpt_32k_rates }, - { .parent = &sys_ck, .rates = gpt_sys_rates }, - { .parent = &alt_ck, .rates = gpt_alt_rates }, - { .parent = NULL }, -}; - -static const char *gpt10_fck_parent_names[] = { - "func_32k_ck", "sys_ck", "alt_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT10_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt10_ick; - -static struct clk_hw_omap gpt10_ick_hw = { - .hw = { - .clk = &gpt10_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT10_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT11_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt11_ick; - -static struct clk_hw_omap gpt11_ick_hw = { - .hw = { - .clk = &gpt11_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT11_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT12_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt12_ick; - -static struct clk_hw_omap gpt12_ick_hw = { - .hw = { - .clk = &gpt12_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT12_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clk_ops gpt1_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_GPT1_MASK, - OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, gpt1_fck_ops); - -static struct clk gpt1_ick; - -static struct clk_hw_omap gpt1_ick_hw = { - .hw = { - .clk = &gpt1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_GPT1_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT2_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt2_ick; - -static struct clk_hw_omap gpt2_ick_hw = { - .hw = { - .clk = &gpt2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT3_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt3_ick; - -static struct clk_hw_omap gpt3_ick_hw = { - .hw = { - .clk = &gpt3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT4_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt4_ick; - -static struct clk_hw_omap gpt4_ick_hw = { - .hw = { - .clk = &gpt4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT5_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt5_ick; - -static struct clk_hw_omap gpt5_ick_hw = { - .hw = { - .clk = &gpt5_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT5_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT6_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt6_ick; - -static struct clk_hw_omap gpt6_ick_hw = { - .hw = { - .clk = &gpt6_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT6_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT7_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt7_ick; - -static struct clk_hw_omap gpt7_ick_hw = { - .hw = { - .clk = &gpt7_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT7_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT8_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt8_ick; - -static struct clk_hw_omap gpt8_ick_hw = { - .hw = { - .clk = &gpt8_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT8_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT9_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt9_ick; - -static struct clk_hw_omap gpt9_ick_hw = { - .hw = { - .clk = &gpt9_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT9_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk hdq_fck; - -static struct clk_hw_omap hdq_fck_hw = { - .hw = { - .clk = &hdq_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk hdq_ick; - -static struct clk_hw_omap hdq_ick_hw = { - .hw = { - .clk = &hdq_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk i2c1_fck; - -static struct clk_hw_omap i2c1_fck_hw = { - .hw = { - .clk = &i2c1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_I2C1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk i2c1_ick; - -static struct clk_hw_omap i2c1_ick_hw = { - .hw = { - .clk = &i2c1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_I2C1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk i2c2_fck; - -static struct clk_hw_omap i2c2_fck_hw = { - .hw = { - .clk = &i2c2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_I2C2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk i2c2_ick; - -static struct clk_hw_omap i2c2_ick_hw = { - .hw = { - .clk = &i2c2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_I2C2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - OMAP2420_CLKSEL_IVA_MASK, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait, - dsp_fck_parent_names, dsp_fck_ops); - -DEFINE_CLK_FIXED_FACTOR(iva1_ifck_div, "iva1_ifck", &iva1_ifck, 0x0, 1, 2); - -static struct clk iva1_mpu_int_ifck; - -static const char *iva1_mpu_int_ifck_parent_names[] = { - "iva1_ifck_div", -}; - -static struct clk_hw_omap iva1_mpu_int_ifck_hw = { - .hw = { - .clk = &iva1_mpu_int_ifck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, - .clkdm_name = "iva1_clkdm", -}; - -DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names, - aes_ick_ops); - -static struct clk mailboxes_ick; - -static struct clk_hw_omap mailboxes_ick_hw = { - .hw = { - .clk = &mailboxes_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate common_mcbsp_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel mcbsp_fck_clksel[] = { - { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, - { .parent = NULL }, -}; - -static const char *mcbsp1_fck_parent_names[] = { - "func_96m_ck", "mcbsp_clks", -}; - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - OMAP2_MCBSP1_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp1_ick; - -static struct clk_hw_omap mcbsp1_ick_hw = { - .hw = { - .clk = &mcbsp1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - OMAP2_MCBSP2_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp2_ick; - -static struct clk_hw_omap mcbsp2_ick_hw = { - .hw = { - .clk = &mcbsp2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mcspi1_fck; - -static const char *mcspi1_fck_parent_names[] = { - "func_48m_ck", -}; - -static struct clk_hw_omap mcspi1_fck_hw = { - .hw = { - .clk = &mcspi1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk mcspi1_ick; - -static struct clk_hw_omap mcspi1_ick_hw = { - .hw = { - .clk = &mcspi1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mcspi2_fck; - -static struct clk_hw_omap mcspi2_fck_hw = { - .hw = { - .clk = &mcspi2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk mcspi2_ick; - -static struct clk_hw_omap mcspi2_ick_hw = { - .hw = { - .clk = &mcspi2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mmc_fck; - -static struct clk_hw_omap mmc_fck_hw = { - .hw = { - .clk = &mmc_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_MMC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk mmc_ick; - -static struct clk_hw_omap mmc_ick_hw = { - .hw = { - .clk = &mmc_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_MMC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, - OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -static struct clk mpu_wdt_fck; - -static struct clk_hw_omap mpu_wdt_fck_hw = { - .hw = { - .clk = &mpu_wdt_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops); - -static struct clk mpu_wdt_ick; - -static struct clk_hw_omap mpu_wdt_ick_hw = { - .hw = { - .clk = &mpu_wdt_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk mspro_fck; - -static struct clk_hw_omap mspro_fck_hw = { - .hw = { - .clk = &mspro_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk mspro_ick; - -static struct clk_hw_omap mspro_ick_hw = { - .hw = { - .clk = &mspro_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk omapctrl_ick; - -static struct clk_hw_omap omapctrl_ick_hw = { - .hw = { - .clk = &omapctrl_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk pka_ick; - -static struct clk_hw_omap pka_ick_hw = { - .hw = { - .clk = &pka_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_PKA_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk rng_ick; - -static struct clk_hw_omap rng_ick_hw = { - .hw = { - .clk = &rng_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_RNG_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk sdma_fck; - -DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); -DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); - -static struct clk sdma_ick; - -static struct clk_hw_omap sdma_ick_hw = { - .hw = { - .clk = &sdma_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); - -static struct clk sdrc_ick; - -static struct clk_hw_omap sdrc_ick_hw = { - .hw = { - .clk = &sdrc_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); - -static struct clk sha_ick; - -static struct clk_hw_omap sha_ick_hw = { - .hw = { - .clk = &sha_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_SHA_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk ssi_l4_ick; - -static struct clk_hw_omap ssi_l4_ick_hw = { - .hw = { - .clk = &ssi_l4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_SSI_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_242X }, - { .div = 8, .val = 8, .flags = RATE_IN_242X }, - { .div = 0 } -}; - -static const struct clksel ssi_ssr_sst_fck_clksel[] = { - { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *ssi_ssr_sst_fck_parent_names[] = { - "core_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", - ssi_ssr_sst_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_SSI_MASK, - OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, - ssi_ssr_sst_fck_parent_names, dsp_fck_ops); - -static struct clk sync_32k_ick; - -static struct clk_hw_omap sync_32k_ick_hw = { - .hw = { - .clk = &sync_32k_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate common_clkout_src_core_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_96m_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_54m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel common_clkout_src_clksel[] = { - { .parent = &core_ck, .rates = common_clkout_src_core_rates }, - { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, - { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, - { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, - { .parent = NULL }, -}; - -static const char *sys_clkout_src_parent_names[] = { - "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel, - OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK, - OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT, - NULL, sys_clkout_src_parent_names, gpt1_fck_ops); - -DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0, - OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT, - OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); - -DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm", - common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL, - OMAP2420_CLKOUT2_SOURCE_MASK, - OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT, - NULL, sys_clkout_src_parent_names, gpt1_fck_ops); - -DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0, - OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT, - OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); - -static struct clk uart1_fck; - -static struct clk_hw_omap uart1_fck_hw = { - .hw = { - .clk = &uart1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_UART1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart1_ick; - -static struct clk_hw_omap uart1_ick_hw = { - .hw = { - .clk = &uart1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_UART1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk uart2_fck; - -static struct clk_hw_omap uart2_fck_hw = { - .hw = { - .clk = &uart2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_UART2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart2_ick; - -static struct clk_hw_omap uart2_ick_hw = { - .hw = { - .clk = &uart2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_UART2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk uart3_fck; - -static struct clk_hw_omap uart3_fck_hw = { - .hw = { - .clk = &uart3_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_UART3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart3_ick; - -static struct clk_hw_omap uart3_ick_hw = { - .hw = { - .clk = &uart3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_UART3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk usb_fck; - -static struct clk_hw_omap usb_fck_hw = { - .hw = { - .clk = &usb_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_USB_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel usb_l4_ick_clksel[] = { - { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, - { .parent = NULL }, -}; - -static const char *usb_l4_ick_parent_names[] = { - "core_l3_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_USB_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, - usb_l4_ick_parent_names, dsp_fck_ops); - -static struct clk virt_prcm_set; - -static const char *virt_prcm_set_parent_names[] = { - "mpu_ck", -}; - -static const struct clk_ops virt_prcm_set_ops = { - .recalc_rate = &omap2_table_mpu_recalc, - .set_rate = &omap2_select_table_rate, - .round_rate = &omap2_round_to_table_rate, -}; - -DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL); -DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops); - -static const struct clksel_rate vlynq_fck_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_242X }, - { .div = 0 } -}; - -static const struct clksel_rate vlynq_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_242X }, - { .div = 2, .val = 2, .flags = RATE_IN_242X }, - { .div = 3, .val = 3, .flags = RATE_IN_242X }, - { .div = 4, .val = 4, .flags = RATE_IN_242X }, - { .div = 6, .val = 6, .flags = RATE_IN_242X }, - { .div = 8, .val = 8, .flags = RATE_IN_242X }, - { .div = 9, .val = 9, .flags = RATE_IN_242X }, - { .div = 12, .val = 12, .flags = RATE_IN_242X }, - { .div = 16, .val = 16, .flags = RATE_IN_242X }, - { .div = 18, .val = 18, .flags = RATE_IN_242X }, - { .div = 0 } -}; - -static const struct clksel vlynq_fck_clksel[] = { - { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, - { .parent = &core_ck, .rates = vlynq_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *vlynq_fck_parent_names[] = { - "func_96m_ck", "core_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP2420_CLKSEL_VLYNQ_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait, - vlynq_fck_parent_names, dss1_fck_ops); - -static struct clk vlynq_ick; - -static struct clk_hw_omap vlynq_ick_hw = { - .hw = { - .clk = &vlynq_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops); - -static struct clk wdt1_ick; - -static struct clk_hw_omap wdt1_ick_hw = { - .hw = { - .clk = &wdt1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_WDT1_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk wdt3_fck; - -static struct clk_hw_omap wdt3_fck_hw = { - .hw = { - .clk = &wdt3_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_WDT3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops); - -static struct clk wdt3_ick; - -static struct clk_hw_omap wdt3_ick_hw = { - .hw = { - .clk = &wdt3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_WDT3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk wdt4_fck; - -static struct clk_hw_omap wdt4_fck_hw = { - .hw = { - .clk = &wdt4_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_WDT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops); - -static struct clk wdt4_ick; - -static struct clk_hw_omap wdt4_ick_hw = { - .hw = { - .clk = &wdt4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_WDT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); - -/* - * clkdev integration - */ - -static struct omap_clk omap2420_clks[] = { - /* external root sources */ - CLK(NULL, "func_32k_ck", &func_32k_ck), - CLK(NULL, "secure_32k_ck", &secure_32k_ck), - CLK(NULL, "virt_12m_ck", &virt_12m_ck), - CLK(NULL, "virt_13m_ck", &virt_13m_ck), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), - CLK(NULL, "virt_26m_ck", &virt_26m_ck), - CLK(NULL, "aplls_clkin_ck", &aplls_clkin_ck), - CLK(NULL, "aplls_clkin_x2_ck", &aplls_clkin_x2_ck), - CLK(NULL, "osc_ck", &osc_ck), - CLK(NULL, "sys_ck", &sys_ck), - CLK(NULL, "alt_ck", &alt_ck), - CLK(NULL, "mcbsp_clks", &mcbsp_clks), - /* internal analog sources */ - CLK(NULL, "dpll_ck", &dpll_ck), - CLK(NULL, "apll96_ck", &apll96_ck), - CLK(NULL, "apll54_ck", &apll54_ck), - /* internal prcm root sources */ - CLK(NULL, "func_54m_ck", &func_54m_ck), - CLK(NULL, "core_ck", &core_ck), - CLK(NULL, "func_96m_ck", &func_96m_ck), - CLK(NULL, "func_48m_ck", &func_48m_ck), - CLK(NULL, "func_12m_ck", &func_12m_ck), - CLK(NULL, "sys_clkout_src", &sys_clkout_src), - CLK(NULL, "sys_clkout", &sys_clkout), - CLK(NULL, "sys_clkout2_src", &sys_clkout2_src), - CLK(NULL, "sys_clkout2", &sys_clkout2), - CLK(NULL, "emul_ck", &emul_ck), - /* mpu domain clocks */ - CLK(NULL, "mpu_ck", &mpu_ck), - /* dsp domain clocks */ - CLK(NULL, "dsp_fck", &dsp_fck), - CLK(NULL, "dsp_ick", &dsp_ick), - CLK(NULL, "iva1_ifck", &iva1_ifck), - CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck), - /* GFX domain clocks */ - CLK(NULL, "gfx_3d_fck", &gfx_3d_fck), - CLK(NULL, "gfx_2d_fck", &gfx_2d_fck), - CLK(NULL, "gfx_ick", &gfx_ick), - /* DSS domain clocks */ - CLK("omapdss_dss", "ick", &dss_ick), - CLK(NULL, "dss_ick", &dss_ick), - CLK(NULL, "dss1_fck", &dss1_fck), - CLK(NULL, "dss2_fck", &dss2_fck), - CLK(NULL, "dss_54m_fck", &dss_54m_fck), - /* L3 domain clocks */ - CLK(NULL, "core_l3_ck", &core_l3_ck), - CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck), - CLK(NULL, "usb_l4_ick", &usb_l4_ick), - /* L4 domain clocks */ - CLK(NULL, "l4_ck", &l4_ck), - CLK(NULL, "ssi_l4_ick", &ssi_l4_ick), - /* virtual meta-group clock */ - CLK(NULL, "virt_prcm_set", &virt_prcm_set), - /* general l4 interface ck, multi-parent functional clk */ - CLK(NULL, "gpt1_ick", &gpt1_ick), - CLK(NULL, "gpt1_fck", &gpt1_fck), - CLK(NULL, "gpt2_ick", &gpt2_ick), - CLK(NULL, "gpt2_fck", &gpt2_fck), - CLK(NULL, "gpt3_ick", &gpt3_ick), - CLK(NULL, "gpt3_fck", &gpt3_fck), - CLK(NULL, "gpt4_ick", &gpt4_ick), - CLK(NULL, "gpt4_fck", &gpt4_fck), - CLK(NULL, "gpt5_ick", &gpt5_ick), - CLK(NULL, "gpt5_fck", &gpt5_fck), - CLK(NULL, "gpt6_ick", &gpt6_ick), - CLK(NULL, "gpt6_fck", &gpt6_fck), - CLK(NULL, "gpt7_ick", &gpt7_ick), - CLK(NULL, "gpt7_fck", &gpt7_fck), - CLK(NULL, "gpt8_ick", &gpt8_ick), - CLK(NULL, "gpt8_fck", &gpt8_fck), - CLK(NULL, "gpt9_ick", &gpt9_ick), - CLK(NULL, "gpt9_fck", &gpt9_fck), - CLK(NULL, "gpt10_ick", &gpt10_ick), - CLK(NULL, "gpt10_fck", &gpt10_fck), - CLK(NULL, "gpt11_ick", &gpt11_ick), - CLK(NULL, "gpt11_fck", &gpt11_fck), - CLK(NULL, "gpt12_ick", &gpt12_ick), - CLK(NULL, "gpt12_fck", &gpt12_fck), - CLK("omap-mcbsp.1", "ick", &mcbsp1_ick), - CLK(NULL, "mcbsp1_ick", &mcbsp1_ick), - CLK(NULL, "mcbsp1_fck", &mcbsp1_fck), - CLK("omap-mcbsp.2", "ick", &mcbsp2_ick), - CLK(NULL, "mcbsp2_ick", &mcbsp2_ick), - CLK(NULL, "mcbsp2_fck", &mcbsp2_fck), - CLK("omap2_mcspi.1", "ick", &mcspi1_ick), - CLK(NULL, "mcspi1_ick", &mcspi1_ick), - CLK(NULL, "mcspi1_fck", &mcspi1_fck), - CLK("omap2_mcspi.2", "ick", &mcspi2_ick), - CLK(NULL, "mcspi2_ick", &mcspi2_ick), - CLK(NULL, "mcspi2_fck", &mcspi2_fck), - CLK(NULL, "uart1_ick", &uart1_ick), - CLK(NULL, "uart1_fck", &uart1_fck), - CLK(NULL, "uart2_ick", &uart2_ick), - CLK(NULL, "uart2_fck", &uart2_fck), - CLK(NULL, "uart3_ick", &uart3_ick), - CLK(NULL, "uart3_fck", &uart3_fck), - CLK(NULL, "gpios_ick", &gpios_ick), - CLK(NULL, "gpios_fck", &gpios_fck), - CLK("omap_wdt", "ick", &mpu_wdt_ick), - CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick), - CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck), - CLK(NULL, "sync_32k_ick", &sync_32k_ick), - CLK(NULL, "wdt1_ick", &wdt1_ick), - CLK(NULL, "omapctrl_ick", &omapctrl_ick), - CLK("omap24xxcam", "fck", &cam_fck), - CLK(NULL, "cam_fck", &cam_fck), - CLK("omap24xxcam", "ick", &cam_ick), - CLK(NULL, "cam_ick", &cam_ick), - CLK(NULL, "mailboxes_ick", &mailboxes_ick), - CLK(NULL, "wdt4_ick", &wdt4_ick), - CLK(NULL, "wdt4_fck", &wdt4_fck), - CLK(NULL, "wdt3_ick", &wdt3_ick), - CLK(NULL, "wdt3_fck", &wdt3_fck), - CLK(NULL, "mspro_ick", &mspro_ick), - CLK(NULL, "mspro_fck", &mspro_fck), - CLK("mmci-omap.0", "ick", &mmc_ick), - CLK(NULL, "mmc_ick", &mmc_ick), - CLK("mmci-omap.0", "fck", &mmc_fck), - CLK(NULL, "mmc_fck", &mmc_fck), - CLK(NULL, "fac_ick", &fac_ick), - CLK(NULL, "fac_fck", &fac_fck), - CLK(NULL, "eac_ick", &eac_ick), - CLK(NULL, "eac_fck", &eac_fck), - CLK("omap_hdq.0", "ick", &hdq_ick), - CLK(NULL, "hdq_ick", &hdq_ick), - CLK("omap_hdq.0", "fck", &hdq_fck), - CLK(NULL, "hdq_fck", &hdq_fck), - CLK("omap_i2c.1", "ick", &i2c1_ick), - CLK(NULL, "i2c1_ick", &i2c1_ick), - CLK(NULL, "i2c1_fck", &i2c1_fck), - CLK("omap_i2c.2", "ick", &i2c2_ick), - CLK(NULL, "i2c2_ick", &i2c2_ick), - CLK(NULL, "i2c2_fck", &i2c2_fck), - CLK(NULL, "gpmc_fck", &gpmc_fck), - CLK(NULL, "sdma_fck", &sdma_fck), - CLK(NULL, "sdma_ick", &sdma_ick), - CLK(NULL, "sdrc_ick", &sdrc_ick), - CLK(NULL, "vlynq_ick", &vlynq_ick), - CLK(NULL, "vlynq_fck", &vlynq_fck), - CLK(NULL, "des_ick", &des_ick), - CLK("omap-sham", "ick", &sha_ick), - CLK(NULL, "sha_ick", &sha_ick), - CLK("omap_rng", "ick", &rng_ick), - CLK(NULL, "rng_ick", &rng_ick), - CLK("omap-aes", "ick", &aes_ick), - CLK(NULL, "aes_ick", &aes_ick), - CLK(NULL, "pka_ick", &pka_ick), - CLK(NULL, "usb_fck", &usb_fck), - CLK("musb-hdrc", "fck", &osc_ck), - CLK(NULL, "timer_32k_ck", &func_32k_ck), - CLK(NULL, "timer_sys_ck", &sys_ck), - CLK(NULL, "timer_ext_ck", &alt_ck), - CLK(NULL, "cpufreq_ck", &virt_prcm_set), -}; - - -static const char *enable_init_clks[] = { - "apll96_ck", - "apll54_ck", - "sync_32k_ick", - "omapctrl_ick", - "gpmc_fck", - "sdrc_ick", -}; - -/* - * init code - */ - -int __init omap2420_clk_init(void) -{ - cpu_mask = RATE_IN_242X; - rate_table = omap2420_rate_table; - - omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw); - - omap2xxx_clkt_vps_check_bootloader_rates(); - - omap_clocks_register(omap2420_clks, ARRAY_SIZE(omap2420_clks)); - - omap2xxx_clkt_vps_late_init(); - - omap2_clk_disable_autoidle_all(); - - omap2_clk_enable_init_clocks(enable_init_clks, - ARRAY_SIZE(enable_init_clks)); - - pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(&sys_ck) / 1000000), - (clk_get_rate(&sys_ck) / 100000) % 10, - (clk_get_rate(&dpll_ck) / 1000000), - (clk_get_rate(&mpu_ck) / 1000000)); - - return 0; -} diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c deleted file mode 100644 index 582abc221ece..000000000000 --- a/arch/arm/mach-omap2/cclock2430_data.c +++ /dev/null @@ -1,2054 +0,0 @@ -/* - * OMAP2430 clock data - * - * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc. - * Copyright (C) 2004-2011 Nokia Corporation - * - * Contacts: - * Richard Woodruff - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include "soc.h" -#include "iomap.h" -#include "clock.h" -#include "clock2xxx.h" -#include "opp2xxx.h" -#include "cm2xxx.h" -#include "prm2xxx.h" -#include "prm-regbits-24xx.h" -#include "cm-regbits-24xx.h" -#include "sdrc.h" -#include "control.h" - -#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR - -/* - * 2430 clock tree. - * - * NOTE:In many cases here we are assigning a 'default' parent. In - * many cases the parent is selectable. The set parent calls will - * also switch sources. - * - * Several sources are given initial rates which may be wrong, this will - * be fixed up in the init func. - * - * Things are broadly separated below by clock domains. It is - * noteworthy that most peripherals have dependencies on multiple clock - * domains. Many get their interface clocks from the L4 domain, but get - * functional clocks from fixed sources or other core domain derived - * clocks. - */ - -DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0); - -DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); - -DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_26m_ck, CLK_IS_ROOT, 26000000, 0x0); - -/* 26M ck is a dummy, added to filla hole in the aplls_clkin parent list */ -static const char *aplls_clkin_ck_parent_names[] = { - "virt_19200000_ck", "virt_26m_ck", "virt_13m_ck", "virt_12m_ck", -}; - -DEFINE_CLK_MUX(aplls_clkin_ck, aplls_clkin_ck_parent_names, NULL, 0x0, - OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_APLLS_CLKIN_SHIFT, - OMAP24XX_APLLS_CLKIN_WIDTH, 0x0, NULL); - -DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); - -DEFINE_CLK_FIXED_FACTOR(aplls_clkin_x2_ck, "aplls_clkin_ck", &aplls_clkin_ck, - 0x0, 2, 1); - -static const char *osc_ck_parent_names[] = { - "aplls_clkin_ck", "aplls_clkin_x2_ck", -}; - -DEFINE_CLK_MUX(osc_ck, osc_ck_parent_names, NULL, 0x0, - OMAP2430_PRCM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT, - OMAP_SYSCLKDIV_WIDTH, CLK_MUX_INDEX_ONE, NULL); - -DEFINE_CLK_DIVIDER(sys_ck, "osc_ck", &osc_ck, 0x0, OMAP2430_PRCM_CLKSRC_CTRL, - OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -static struct dpll_data dpll_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .mult_mask = OMAP24XX_DPLL_MULT_MASK, - .div1_mask = OMAP24XX_DPLL_DIV_MASK, - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_mask = OMAP24XX_EN_DPLL_MASK, - .max_multiplier = 1023, - .min_divider = 1, - .max_divider = 16, -}; - -static struct clk dpll_ck; - -static const char *dpll_ck_parent_names[] = { - "sys_ck", -}; - -static const struct clk_ops dpll_ck_ops = { - .init = &omap2_init_clk_clkdm, - .get_parent = &omap2_init_dpll_parent, - .recalc_rate = &omap2_dpllcore_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap2_reprogram_dpllcore, -}; - -static struct clk_hw_omap dpll_ck_hw = { - .hw = { - .clk = &dpll_ck, - }, - .ops = &clkhwops_omap2xxx_dpll, - .dpll_data = &dpll_dd, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); - -static struct clk core_ck; - -static const char *core_ck_parent_names[] = { - "dpll_ck", -}; - -static const struct clk_ops core_ck_ops = { - .init = &omap2_init_clk_clkdm, -}; - -DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm"); -DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops); - -DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -static struct clk aes_ick; - -static const char *aes_ick_parent_names[] = { - "l4_ck", -}; - -static const struct clk_ops aes_ick_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, -}; - -static struct clk_hw_omap aes_ick_hw = { - .hw = { - .clk = &aes_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_AES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk apll54_ck; - -static const struct clk_ops apll54_ck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_clk_apll54_enable, - .disable = &omap2_clk_apll54_disable, - .recalc_rate = &omap2_clk_apll54_recalc, -}; - -static struct clk_hw_omap apll54_ck_hw = { - .hw = { - .clk = &apll54_ck, - }, - .ops = &clkhwops_apll54, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); - -static struct clk apll96_ck; - -static const struct clk_ops apll96_ck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_clk_apll96_enable, - .disable = &omap2_clk_apll96_disable, - .recalc_rate = &omap2_clk_apll96_recalc, -}; - -static struct clk_hw_omap apll96_ck_hw = { - .hw = { - .clk = &apll96_ck, - }, - .ops = &clkhwops_apll96, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops); - -static const char *func_96m_ck_parent_names[] = { - "apll96_ck", "alt_ck", -}; - -DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0, - OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT, - OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL); - -static struct clk cam_fck; - -static const char *cam_fck_parent_names[] = { - "func_96m_ck", -}; - -static struct clk_hw_omap cam_fck_hw = { - .hw = { - .clk = &cam_fck, - }, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_CAM_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk cam_ick; - -static struct clk_hw_omap cam_ick_hw = { - .hw = { - .clk = &cam_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_CAM_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk des_ick; - -static struct clk_hw_omap des_ick_hw = { - .hw = { - .clk = &des_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_DES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate dsp_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel dsp_fck_clksel[] = { - { .parent = &core_ck, .rates = dsp_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *dsp_fck_parent_names[] = { - "core_ck", -}; - -static struct clk dsp_fck; - -static const struct clk_ops dsp_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, -}; - -DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_DSP_MASK, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, - dsp_fck_parent_names, dsp_fck_ops); - -static const struct clksel_rate dss1_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate dss1_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 5, .val = 5, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_24XX }, - { .div = 8, .val = 8, .flags = RATE_IN_24XX }, - { .div = 9, .val = 9, .flags = RATE_IN_24XX }, - { .div = 12, .val = 12, .flags = RATE_IN_24XX }, - { .div = 16, .val = 16, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel dss1_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, - { .parent = &core_ck, .rates = dss1_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *dss1_fck_parent_names[] = { - "sys_ck", "core_ck", -}; - -static const struct clk_ops dss1_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_DSS1_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_DSS1_SHIFT, NULL, - dss1_fck_parent_names, dss1_fck_ops); - -static const struct clksel_rate dss2_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate dss2_fck_48m_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate func_48m_apll96_rates[] = { - { .div = 2, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate func_48m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel func_48m_clksel[] = { - { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, - { .parent = &alt_ck, .rates = func_48m_alt_rates }, - { .parent = NULL }, -}; - -static const char *func_48m_ck_parent_names[] = { - "apll96_ck", "alt_ck", -}; - -static struct clk func_48m_ck; - -static const struct clk_ops func_48m_ck_ops = { - .init = &omap2_init_clk_clkdm, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -static struct clk_hw_omap func_48m_ck_hw = { - .hw = { - .clk = &func_48m_ck, - }, - .clksel = func_48m_clksel, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_48M_SOURCE_MASK, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops); - -static const struct clksel dss2_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, - { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, - { .parent = NULL }, -}; - -static const char *dss2_fck_parent_names[] = { - "sys_ck", "func_48m_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_DSS2_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_DSS2_SHIFT, NULL, - dss2_fck_parent_names, dss1_fck_ops); - -static const char *func_54m_ck_parent_names[] = { - "apll54_ck", "alt_ck", -}; - -DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, - OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL); - -static struct clk dss_54m_fck; - -static const char *dss_54m_fck_parent_names[] = { - "func_54m_ck", -}; - -static struct clk_hw_omap dss_54m_fck_hw = { - .hw = { - .clk = &dss_54m_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_TV_SHIFT, - .clkdm_name = "dss_clkdm", -}; - -DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); - -static struct clk dss_ick; - -static struct clk_hw_omap dss_ick_hw = { - .hw = { - .clk = &dss_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_DSS1_SHIFT, - .clkdm_name = "dss_clkdm", -}; - -DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk emul_ck; - -static struct clk_hw_omap emul_ck_hw = { - .hw = { - .clk = &emul_ck, - }, - .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL, - .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); - -DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); - -static struct clk fac_fck; - -static const char *fac_fck_parent_names[] = { - "func_12m_ck", -}; - -static struct clk_hw_omap fac_fck_hw = { - .hw = { - .clk = &fac_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk fac_ick; - -static struct clk_hw_omap fac_ick_hw = { - .hw = { - .clk = &fac_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel gfx_fck_clksel[] = { - { .parent = &core_l3_ck, .rates = gfx_l3_rates }, - { .parent = NULL }, -}; - -static const char *gfx_2d_fck_parent_names[] = { - "core_l3_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel, - OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - OMAP_CLKSEL_GFX_MASK, - OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - OMAP24XX_EN_2D_SHIFT, &clkhwops_wait, - gfx_2d_fck_parent_names, dsp_fck_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, - OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - OMAP_CLKSEL_GFX_MASK, - OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, - gfx_2d_fck_parent_names, dsp_fck_ops); - -static struct clk gfx_ick; - -static const char *gfx_ick_parent_names[] = { - "core_l3_ck", -}; - -static struct clk_hw_omap gfx_ick_hw = { - .hw = { - .clk = &gfx_ick, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), - .enable_bit = OMAP_EN_GFX_SHIFT, - .clkdm_name = "gfx_clkdm", -}; - -DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); - -static struct clk gpio5_fck; - -static const char *gpio5_fck_parent_names[] = { - "func_32k_ck", -}; - -static struct clk_hw_omap gpio5_fck_hw = { - .hw = { - .clk = &gpio5_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_GPIO5_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops); - -static struct clk gpio5_ick; - -static struct clk_hw_omap gpio5_ick_hw = { - .hw = { - .clk = &gpio5_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_GPIO5_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk gpios_fck; - -static struct clk_hw_omap gpios_fck_hw = { - .hw = { - .clk = &gpios_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops); - -static struct clk gpios_ick; - -static const char *gpios_ick_parent_names[] = { - "sys_ck", -}; - -static struct clk_hw_omap gpios_ick_hw = { - .hw = { - .clk = &gpios_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk gpmc_fck; - -static struct clk_hw_omap gpmc_fck_hw = { - .hw = { - .clk = &gpmc_fck, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops); - -static const struct clksel_rate gpt_alt_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel omap24xx_gpt_clksel[] = { - { .parent = &func_32k_ck, .rates = gpt_32k_rates }, - { .parent = &sys_ck, .rates = gpt_sys_rates }, - { .parent = &alt_ck, .rates = gpt_alt_rates }, - { .parent = NULL }, -}; - -static const char *gpt10_fck_parent_names[] = { - "func_32k_ck", "sys_ck", "alt_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT10_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt10_ick; - -static struct clk_hw_omap gpt10_ick_hw = { - .hw = { - .clk = &gpt10_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT10_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT11_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt11_ick; - -static struct clk_hw_omap gpt11_ick_hw = { - .hw = { - .clk = &gpt11_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT11_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT12_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt12_ick; - -static struct clk_hw_omap gpt12_ick_hw = { - .hw = { - .clk = &gpt12_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT12_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clk_ops gpt1_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_GPT1_MASK, - OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, gpt1_fck_ops); - -static struct clk gpt1_ick; - -static struct clk_hw_omap gpt1_ick_hw = { - .hw = { - .clk = &gpt1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_GPT1_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT2_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt2_ick; - -static struct clk_hw_omap gpt2_ick_hw = { - .hw = { - .clk = &gpt2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT3_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt3_ick; - -static struct clk_hw_omap gpt3_ick_hw = { - .hw = { - .clk = &gpt3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT4_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt4_ick; - -static struct clk_hw_omap gpt4_ick_hw = { - .hw = { - .clk = &gpt4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT5_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt5_ick; - -static struct clk_hw_omap gpt5_ick_hw = { - .hw = { - .clk = &gpt5_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT5_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT6_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt6_ick; - -static struct clk_hw_omap gpt6_ick_hw = { - .hw = { - .clk = &gpt6_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT6_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT7_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt7_ick; - -static struct clk_hw_omap gpt7_ick_hw = { - .hw = { - .clk = &gpt7_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT7_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk gpt8_fck; - -DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT8_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt8_ick; - -static struct clk_hw_omap gpt8_ick_hw = { - .hw = { - .clk = &gpt8_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT8_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT9_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt9_ick; - -static struct clk_hw_omap gpt9_ick_hw = { - .hw = { - .clk = &gpt9_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT9_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk hdq_fck; - -static struct clk_hw_omap hdq_fck_hw = { - .hw = { - .clk = &hdq_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk hdq_ick; - -static struct clk_hw_omap hdq_ick_hw = { - .hw = { - .clk = &hdq_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk i2c1_ick; - -static struct clk_hw_omap i2c1_ick_hw = { - .hw = { - .clk = &i2c1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_I2C1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk i2c2_ick; - -static struct clk_hw_omap i2c2_ick_hw = { - .hw = { - .clk = &i2c2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_I2C2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk i2chs1_fck; - -static struct clk_hw_omap i2chs1_fck_hw = { - .hw = { - .clk = &i2chs1_fck, - }, - .ops = &clkhwops_omap2430_i2chs_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk i2chs2_fck; - -static struct clk_hw_omap i2chs2_fck_hw = { - .hw = { - .clk = &i2chs2_fck, - }, - .ops = &clkhwops_omap2430_i2chs_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk icr_ick; - -static struct clk_hw_omap icr_ick_hw = { - .hw = { - .clk = &icr_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP2430_EN_ICR_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(icr_ick, gpios_ick_parent_names, aes_ick_ops); - -static const struct clksel dsp_ick_clksel[] = { - { .parent = &dsp_fck, .rates = dsp_ick_rates }, - { .parent = NULL }, -}; - -static const char *iva2_1_ick_parent_names[] = { - "dsp_fck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_DSP_IF_MASK, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, - iva2_1_ick_parent_names, dsp_fck_ops); - -static struct clk mailboxes_ick; - -static struct clk_hw_omap mailboxes_ick_hw = { - .hw = { - .clk = &mailboxes_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate common_mcbsp_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel mcbsp_fck_clksel[] = { - { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, - { .parent = NULL }, -}; - -static const char *mcbsp1_fck_parent_names[] = { - "func_96m_ck", "mcbsp_clks", -}; - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - OMAP2_MCBSP1_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp1_ick; - -static struct clk_hw_omap mcbsp1_ick_hw = { - .hw = { - .clk = &mcbsp1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - OMAP2_MCBSP2_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp2_ick; - -static struct clk_hw_omap mcbsp2_ick_hw = { - .hw = { - .clk = &mcbsp2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), - OMAP2_MCBSP3_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - OMAP2430_EN_MCBSP3_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp3_ick; - -static struct clk_hw_omap mcbsp3_ick_hw = { - .hw = { - .clk = &mcbsp3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp3_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), - OMAP2_MCBSP4_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - OMAP2430_EN_MCBSP4_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp4_ick; - -static struct clk_hw_omap mcbsp4_ick_hw = { - .hw = { - .clk = &mcbsp4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp4_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), - OMAP2_MCBSP5_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - OMAP2430_EN_MCBSP5_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp5_ick; - -static struct clk_hw_omap mcbsp5_ick_hw = { - .hw = { - .clk = &mcbsp5_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp5_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mcspi1_fck; - -static const char *mcspi1_fck_parent_names[] = { - "func_48m_ck", -}; - -static struct clk_hw_omap mcspi1_fck_hw = { - .hw = { - .clk = &mcspi1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk mcspi1_ick; - -static struct clk_hw_omap mcspi1_ick_hw = { - .hw = { - .clk = &mcspi1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mcspi2_fck; - -static struct clk_hw_omap mcspi2_fck_hw = { - .hw = { - .clk = &mcspi2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk mcspi2_ick; - -static struct clk_hw_omap mcspi2_ick_hw = { - .hw = { - .clk = &mcspi2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mcspi3_fck; - -static struct clk_hw_omap mcspi3_fck_hw = { - .hw = { - .clk = &mcspi3_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi3_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk mcspi3_ick; - -static struct clk_hw_omap mcspi3_ick_hw = { - .hw = { - .clk = &mcspi3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi3_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate mdm_ick_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_243X }, - { .div = 4, .val = 4, .flags = RATE_IN_243X }, - { .div = 6, .val = 6, .flags = RATE_IN_243X }, - { .div = 9, .val = 9, .flags = RATE_IN_243X }, - { .div = 0 } -}; - -static const struct clksel mdm_ick_clksel[] = { - { .parent = &core_ck, .rates = mdm_ick_core_rates }, - { .parent = NULL }, -}; - -static const char *mdm_ick_parent_names[] = { - "core_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(mdm_ick, "mdm_clkdm", mdm_ick_clksel, - OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), - OMAP2430_CLKSEL_MDM_MASK, - OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), - OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, - &clkhwops_iclk_wait, mdm_ick_parent_names, - dsp_fck_ops); - -static struct clk mdm_intc_ick; - -static struct clk_hw_omap mdm_intc_ick_hw = { - .hw = { - .clk = &mdm_intc_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mdm_intc_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mdm_osc_ck; - -static struct clk_hw_omap mdm_osc_ck_hw = { - .hw = { - .clk = &mdm_osc_ck, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), - .enable_bit = OMAP2430_EN_OSC_SHIFT, - .clkdm_name = "mdm_clkdm", -}; - -static const char *mdm_osc_ck_parent_names[] = { - "osc_ck", -}; - -DEFINE_STRUCT_CLK(mdm_osc_ck, mdm_osc_ck_parent_names, aes_ick_ops); - -static struct clk mmchs1_fck; - -static struct clk_hw_omap mmchs1_fck_hw = { - .hw = { - .clk = &mmchs1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchs1_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk mmchs1_ick; - -static struct clk_hw_omap mmchs1_ick_hw = { - .hw = { - .clk = &mmchs1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchs1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mmchs2_fck; - -static struct clk_hw_omap mmchs2_fck_hw = { - .hw = { - .clk = &mmchs2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchs2_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk mmchs2_ick; - -static struct clk_hw_omap mmchs2_ick_hw = { - .hw = { - .clk = &mmchs2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchs2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mmchsdb1_fck; - -static struct clk_hw_omap mmchsdb1_fck_hw = { - .hw = { - .clk = &mmchsdb1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchsdb1_fck, gpio5_fck_parent_names, aes_ick_ops); - -static struct clk mmchsdb2_fck; - -static struct clk_hw_omap mmchsdb2_fck_hw = { - .hw = { - .clk = &mmchsdb2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchsdb2_fck, gpio5_fck_parent_names, aes_ick_ops); - -DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, - OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -static struct clk mpu_wdt_fck; - -static struct clk_hw_omap mpu_wdt_fck_hw = { - .hw = { - .clk = &mpu_wdt_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(mpu_wdt_fck, gpio5_fck_parent_names, aes_ick_ops); - -static struct clk mpu_wdt_ick; - -static struct clk_hw_omap mpu_wdt_ick_hw = { - .hw = { - .clk = &mpu_wdt_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk mspro_fck; - -static struct clk_hw_omap mspro_fck_hw = { - .hw = { - .clk = &mspro_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk mspro_ick; - -static struct clk_hw_omap mspro_ick_hw = { - .hw = { - .clk = &mspro_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk omapctrl_ick; - -static struct clk_hw_omap omapctrl_ick_hw = { - .hw = { - .clk = &omapctrl_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk pka_ick; - -static struct clk_hw_omap pka_ick_hw = { - .hw = { - .clk = &pka_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_PKA_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk rng_ick; - -static struct clk_hw_omap rng_ick_hw = { - .hw = { - .clk = &rng_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_RNG_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk sdma_fck; - -DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); -DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); - -static struct clk sdma_ick; - -static struct clk_hw_omap sdma_ick_hw = { - .hw = { - .clk = &sdma_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); - -static struct clk sdrc_ick; - -static struct clk_hw_omap sdrc_ick_hw = { - .hw = { - .clk = &sdrc_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP2430_EN_SDRC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); - -static struct clk sha_ick; - -static struct clk_hw_omap sha_ick_hw = { - .hw = { - .clk = &sha_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_SHA_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk ssi_l4_ick; - -static struct clk_hw_omap ssi_l4_ick_hw = { - .hw = { - .clk = &ssi_l4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_SSI_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 5, .val = 5, .flags = RATE_IN_243X }, - { .div = 0 } -}; - -static const struct clksel ssi_ssr_sst_fck_clksel[] = { - { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *ssi_ssr_sst_fck_parent_names[] = { - "core_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", - ssi_ssr_sst_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_SSI_MASK, - OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, - ssi_ssr_sst_fck_parent_names, dsp_fck_ops); - -static struct clk sync_32k_ick; - -static struct clk_hw_omap sync_32k_ick_hw = { - .hw = { - .clk = &sync_32k_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate common_clkout_src_core_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_96m_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_54m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel common_clkout_src_clksel[] = { - { .parent = &core_ck, .rates = common_clkout_src_core_rates }, - { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, - { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, - { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, - { .parent = NULL }, -}; - -static const char *sys_clkout_src_parent_names[] = { - "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel, - OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK, - OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT, - NULL, sys_clkout_src_parent_names, gpt1_fck_ops); - -DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0, - OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT, - OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); - -static struct clk uart1_fck; - -static struct clk_hw_omap uart1_fck_hw = { - .hw = { - .clk = &uart1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_UART1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart1_ick; - -static struct clk_hw_omap uart1_ick_hw = { - .hw = { - .clk = &uart1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_UART1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk uart2_fck; - -static struct clk_hw_omap uart2_fck_hw = { - .hw = { - .clk = &uart2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_UART2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart2_ick; - -static struct clk_hw_omap uart2_ick_hw = { - .hw = { - .clk = &uart2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_UART2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk uart3_fck; - -static struct clk_hw_omap uart3_fck_hw = { - .hw = { - .clk = &uart3_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_UART3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart3_ick; - -static struct clk_hw_omap uart3_ick_hw = { - .hw = { - .clk = &uart3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_UART3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk usb_fck; - -static struct clk_hw_omap usb_fck_hw = { - .hw = { - .clk = &usb_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_USB_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel usb_l4_ick_clksel[] = { - { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, - { .parent = NULL }, -}; - -static const char *usb_l4_ick_parent_names[] = { - "core_l3_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_USB_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, - usb_l4_ick_parent_names, dsp_fck_ops); - -static struct clk usbhs_ick; - -static struct clk_hw_omap usbhs_ick_hw = { - .hw = { - .clk = &usbhs_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_USBHS_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(usbhs_ick, gfx_ick_parent_names, aes_ick_ops); - -static struct clk virt_prcm_set; - -static const char *virt_prcm_set_parent_names[] = { - "mpu_ck", -}; - -static const struct clk_ops virt_prcm_set_ops = { - .recalc_rate = &omap2_table_mpu_recalc, - .set_rate = &omap2_select_table_rate, - .round_rate = &omap2_round_to_table_rate, -}; - -DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL); -DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops); - -static struct clk wdt1_ick; - -static struct clk_hw_omap wdt1_ick_hw = { - .hw = { - .clk = &wdt1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_WDT1_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk wdt4_fck; - -static struct clk_hw_omap wdt4_fck_hw = { - .hw = { - .clk = &wdt4_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_WDT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt4_fck, gpio5_fck_parent_names, aes_ick_ops); - -static struct clk wdt4_ick; - -static struct clk_hw_omap wdt4_ick_hw = { - .hw = { - .clk = &wdt4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_WDT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); - -/* - * clkdev integration - */ - -static struct omap_clk omap2430_clks[] = { - /* external root sources */ - CLK(NULL, "func_32k_ck", &func_32k_ck), - CLK(NULL, "secure_32k_ck", &secure_32k_ck), - CLK(NULL, "virt_12m_ck", &virt_12m_ck), - CLK(NULL, "virt_13m_ck", &virt_13m_ck), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), - CLK(NULL, "virt_26m_ck", &virt_26m_ck), - CLK(NULL, "aplls_clkin_ck", &aplls_clkin_ck), - CLK(NULL, "aplls_clkin_x2_ck", &aplls_clkin_x2_ck), - CLK(NULL, "osc_ck", &osc_ck), - CLK("twl", "fck", &osc_ck), - CLK(NULL, "sys_ck", &sys_ck), - CLK(NULL, "alt_ck", &alt_ck), - CLK(NULL, "mcbsp_clks", &mcbsp_clks), - /* internal analog sources */ - CLK(NULL, "dpll_ck", &dpll_ck), - CLK(NULL, "apll96_ck", &apll96_ck), - CLK(NULL, "apll54_ck", &apll54_ck), - /* internal prcm root sources */ - CLK(NULL, "func_54m_ck", &func_54m_ck), - CLK(NULL, "core_ck", &core_ck), - CLK(NULL, "func_96m_ck", &func_96m_ck), - CLK(NULL, "func_48m_ck", &func_48m_ck), - CLK(NULL, "func_12m_ck", &func_12m_ck), - CLK(NULL, "sys_clkout_src", &sys_clkout_src), - CLK(NULL, "sys_clkout", &sys_clkout), - CLK(NULL, "emul_ck", &emul_ck), - /* mpu domain clocks */ - CLK(NULL, "mpu_ck", &mpu_ck), - /* dsp domain clocks */ - CLK(NULL, "dsp_fck", &dsp_fck), - CLK(NULL, "iva2_1_ick", &iva2_1_ick), - /* GFX domain clocks */ - CLK(NULL, "gfx_3d_fck", &gfx_3d_fck), - CLK(NULL, "gfx_2d_fck", &gfx_2d_fck), - CLK(NULL, "gfx_ick", &gfx_ick), - /* Modem domain clocks */ - CLK(NULL, "mdm_ick", &mdm_ick), - CLK(NULL, "mdm_osc_ck", &mdm_osc_ck), - /* DSS domain clocks */ - CLK("omapdss_dss", "ick", &dss_ick), - CLK(NULL, "dss_ick", &dss_ick), - CLK(NULL, "dss1_fck", &dss1_fck), - CLK(NULL, "dss2_fck", &dss2_fck), - CLK(NULL, "dss_54m_fck", &dss_54m_fck), - /* L3 domain clocks */ - CLK(NULL, "core_l3_ck", &core_l3_ck), - CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck), - CLK(NULL, "usb_l4_ick", &usb_l4_ick), - /* L4 domain clocks */ - CLK(NULL, "l4_ck", &l4_ck), - CLK(NULL, "ssi_l4_ick", &ssi_l4_ick), - /* virtual meta-group clock */ - CLK(NULL, "virt_prcm_set", &virt_prcm_set), - /* general l4 interface ck, multi-parent functional clk */ - CLK(NULL, "gpt1_ick", &gpt1_ick), - CLK(NULL, "gpt1_fck", &gpt1_fck), - CLK(NULL, "gpt2_ick", &gpt2_ick), - CLK(NULL, "gpt2_fck", &gpt2_fck), - CLK(NULL, "gpt3_ick", &gpt3_ick), - CLK(NULL, "gpt3_fck", &gpt3_fck), - CLK(NULL, "gpt4_ick", &gpt4_ick), - CLK(NULL, "gpt4_fck", &gpt4_fck), - CLK(NULL, "gpt5_ick", &gpt5_ick), - CLK(NULL, "gpt5_fck", &gpt5_fck), - CLK(NULL, "gpt6_ick", &gpt6_ick), - CLK(NULL, "gpt6_fck", &gpt6_fck), - CLK(NULL, "gpt7_ick", &gpt7_ick), - CLK(NULL, "gpt7_fck", &gpt7_fck), - CLK(NULL, "gpt8_ick", &gpt8_ick), - CLK(NULL, "gpt8_fck", &gpt8_fck), - CLK(NULL, "gpt9_ick", &gpt9_ick), - CLK(NULL, "gpt9_fck", &gpt9_fck), - CLK(NULL, "gpt10_ick", &gpt10_ick), - CLK(NULL, "gpt10_fck", &gpt10_fck), - CLK(NULL, "gpt11_ick", &gpt11_ick), - CLK(NULL, "gpt11_fck", &gpt11_fck), - CLK(NULL, "gpt12_ick", &gpt12_ick), - CLK(NULL, "gpt12_fck", &gpt12_fck), - CLK("omap-mcbsp.1", "ick", &mcbsp1_ick), - CLK(NULL, "mcbsp1_ick", &mcbsp1_ick), - CLK(NULL, "mcbsp1_fck", &mcbsp1_fck), - CLK("omap-mcbsp.2", "ick", &mcbsp2_ick), - CLK(NULL, "mcbsp2_ick", &mcbsp2_ick), - CLK(NULL, "mcbsp2_fck", &mcbsp2_fck), - CLK("omap-mcbsp.3", "ick", &mcbsp3_ick), - CLK(NULL, "mcbsp3_ick", &mcbsp3_ick), - CLK(NULL, "mcbsp3_fck", &mcbsp3_fck), - CLK("omap-mcbsp.4", "ick", &mcbsp4_ick), - CLK(NULL, "mcbsp4_ick", &mcbsp4_ick), - CLK(NULL, "mcbsp4_fck", &mcbsp4_fck), - CLK("omap-mcbsp.5", "ick", &mcbsp5_ick), - CLK(NULL, "mcbsp5_ick", &mcbsp5_ick), - CLK(NULL, "mcbsp5_fck", &mcbsp5_fck), - CLK("omap2_mcspi.1", "ick", &mcspi1_ick), - CLK(NULL, "mcspi1_ick", &mcspi1_ick), - CLK(NULL, "mcspi1_fck", &mcspi1_fck), - CLK("omap2_mcspi.2", "ick", &mcspi2_ick), - CLK(NULL, "mcspi2_ick", &mcspi2_ick), - CLK(NULL, "mcspi2_fck", &mcspi2_fck), - CLK("omap2_mcspi.3", "ick", &mcspi3_ick), - CLK(NULL, "mcspi3_ick", &mcspi3_ick), - CLK(NULL, "mcspi3_fck", &mcspi3_fck), - CLK(NULL, "uart1_ick", &uart1_ick), - CLK(NULL, "uart1_fck", &uart1_fck), - CLK(NULL, "uart2_ick", &uart2_ick), - CLK(NULL, "uart2_fck", &uart2_fck), - CLK(NULL, "uart3_ick", &uart3_ick), - CLK(NULL, "uart3_fck", &uart3_fck), - CLK(NULL, "gpios_ick", &gpios_ick), - CLK(NULL, "gpios_fck", &gpios_fck), - CLK("omap_wdt", "ick", &mpu_wdt_ick), - CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick), - CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck), - CLK(NULL, "sync_32k_ick", &sync_32k_ick), - CLK(NULL, "wdt1_ick", &wdt1_ick), - CLK(NULL, "omapctrl_ick", &omapctrl_ick), - CLK(NULL, "icr_ick", &icr_ick), - CLK("omap24xxcam", "fck", &cam_fck), - CLK(NULL, "cam_fck", &cam_fck), - CLK("omap24xxcam", "ick", &cam_ick), - CLK(NULL, "cam_ick", &cam_ick), - CLK(NULL, "mailboxes_ick", &mailboxes_ick), - CLK(NULL, "wdt4_ick", &wdt4_ick), - CLK(NULL, "wdt4_fck", &wdt4_fck), - CLK(NULL, "mspro_ick", &mspro_ick), - CLK(NULL, "mspro_fck", &mspro_fck), - CLK(NULL, "fac_ick", &fac_ick), - CLK(NULL, "fac_fck", &fac_fck), - CLK("omap_hdq.0", "ick", &hdq_ick), - CLK(NULL, "hdq_ick", &hdq_ick), - CLK("omap_hdq.1", "fck", &hdq_fck), - CLK(NULL, "hdq_fck", &hdq_fck), - CLK("omap_i2c.1", "ick", &i2c1_ick), - CLK(NULL, "i2c1_ick", &i2c1_ick), - CLK(NULL, "i2chs1_fck", &i2chs1_fck), - CLK("omap_i2c.2", "ick", &i2c2_ick), - CLK(NULL, "i2c2_ick", &i2c2_ick), - CLK(NULL, "i2chs2_fck", &i2chs2_fck), - CLK(NULL, "gpmc_fck", &gpmc_fck), - CLK(NULL, "sdma_fck", &sdma_fck), - CLK(NULL, "sdma_ick", &sdma_ick), - CLK(NULL, "sdrc_ick", &sdrc_ick), - CLK(NULL, "des_ick", &des_ick), - CLK("omap-sham", "ick", &sha_ick), - CLK(NULL, "sha_ick", &sha_ick), - CLK("omap_rng", "ick", &rng_ick), - CLK(NULL, "rng_ick", &rng_ick), - CLK("omap-aes", "ick", &aes_ick), - CLK(NULL, "aes_ick", &aes_ick), - CLK(NULL, "pka_ick", &pka_ick), - CLK(NULL, "usb_fck", &usb_fck), - CLK("musb-omap2430", "ick", &usbhs_ick), - CLK(NULL, "usbhs_ick", &usbhs_ick), - CLK("omap_hsmmc.0", "ick", &mmchs1_ick), - CLK(NULL, "mmchs1_ick", &mmchs1_ick), - CLK(NULL, "mmchs1_fck", &mmchs1_fck), - CLK("omap_hsmmc.1", "ick", &mmchs2_ick), - CLK(NULL, "mmchs2_ick", &mmchs2_ick), - CLK(NULL, "mmchs2_fck", &mmchs2_fck), - CLK(NULL, "gpio5_ick", &gpio5_ick), - CLK(NULL, "gpio5_fck", &gpio5_fck), - CLK(NULL, "mdm_intc_ick", &mdm_intc_ick), - CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck), - CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck), - CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck), - CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck), - CLK(NULL, "timer_32k_ck", &func_32k_ck), - CLK(NULL, "timer_sys_ck", &sys_ck), - CLK(NULL, "timer_ext_ck", &alt_ck), - CLK(NULL, "cpufreq_ck", &virt_prcm_set), -}; - -static const char *enable_init_clks[] = { - "apll96_ck", - "apll54_ck", - "sync_32k_ick", - "omapctrl_ick", - "gpmc_fck", - "sdrc_ick", -}; - -/* - * init code - */ - -int __init omap2430_clk_init(void) -{ - cpu_mask = RATE_IN_243X; - rate_table = omap2430_rate_table; - - omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw); - - omap2xxx_clkt_vps_check_bootloader_rates(); - - omap_clocks_register(omap2430_clks, ARRAY_SIZE(omap2430_clks)); - - omap2xxx_clkt_vps_late_init(); - - omap2_clk_disable_autoidle_all(); - - omap2_clk_enable_init_clocks(enable_init_clks, - ARRAY_SIZE(enable_init_clks)); - - pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(&sys_ck) / 1000000), - (clk_get_rate(&sys_ck) / 100000) % 10, - (clk_get_rate(&dpll_ck) / 1000000), - (clk_get_rate(&mpu_ck) / 1000000)); - - return 0; -} diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 80bf63359c24..1271fe902ca8 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -411,12 +411,8 @@ void __init omap2420_init_early(void) omap242x_clockdomains_init(); omap2420_hwmod_init(); omap_hwmod_init_postsetup(); - if (of_have_populated_dt()) { - omap_clk_soc_init = omap2420_dt_clk_init; - rate_table = omap2420_rate_table; - } else { - omap_clk_soc_init = omap2420_clk_init; - } + omap_clk_soc_init = omap2420_dt_clk_init; + rate_table = omap2420_rate_table; } void __init omap2420_init_late(void) @@ -445,12 +441,8 @@ void __init omap2430_init_early(void) omap243x_clockdomains_init(); omap2430_hwmod_init(); omap_hwmod_init_postsetup(); - if (of_have_populated_dt()) { - omap_clk_soc_init = omap2430_dt_clk_init; - rate_table = omap2430_rate_table; - } else { - omap_clk_soc_init = omap2430_clk_init; - } + omap_clk_soc_init = omap2430_dt_clk_init; + rate_table = omap2430_rate_table; } void __init omap2430_init_late(void) -- cgit v1.2.3 From 8e9842406c1889782613f31a81a579ba14ef9e0f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 26 Jun 2014 23:55:44 +0800 Subject: ARM: sun8i: Add basic clock nodes to the DTSI Now that we have support for sun8i specific clocks in the driver, add the corresponding clock nodes to the DTSI. Also update the existing peripherals with the correct clocks. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23.dtsi | 125 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 120 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index ac5f69afb595..79c40834bc0a 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -64,6 +64,121 @@ clock-frequency = <32768>; clock-output-names = "osc32k"; }; + + pll1: clk@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + + /* dummy clock until actually implemented */ + pll6: pll6_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <600000000>; + clock-output-names = "pll6"; + }; + + cpu: cpu_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-cpu-clk"; + reg = <0x01c20050 0x4>; + + /* + * PLL1 is listed twice here. + * While it looks suspicious, it's actually documented + * that way both in the datasheet and in the code from + * Allwinner. + */ + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; + clock-output-names = "cpu"; + }; + + axi: axi_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-axi-clk"; + reg = <0x01c20050 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + + ahb1_mux: ahb1_mux_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; + clock-output-names = "ahb1_mux"; + }; + + ahb1: ahb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-ahb-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb1_mux>; + clock-output-names = "ahb1"; + }; + + apb1: apb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb1>; + clock-output-names = "apb1"; + }; + + ahb1_gates: clk@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; + reg = <0x01c20060 0x8>; + clocks = <&ahb1>; + clock-output-names = "ahb1_mipidsi", "ahb1_dma", + "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2", + "ahb1_nand", "ahb1_sdram", + "ahb1_hstimer", "ahb1_spi0", + "ahb1_spi1", "ahb1_otg", "ahb1_ehci", + "ahb1_ohci", "ahb1_ve", "ahb1_lcd", + "ahb1_csi", "ahb1_be", "ahb1_fe", + "ahb1_gpu", "ahb1_spinlock", + "ahb1_drc"; + }; + + apb1_gates: clk@01c20068 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-a23-apb1-gates-clk"; + reg = <0x01c20068 0x4>; + clocks = <&apb1>; + clock-output-names = "apb1_codec", "apb1_pio", + "apb1_daudio0", "apb1_daudio1"; + }; + + apb2_mux: apb2_mux_clk@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-mux-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; + clock-output-names = "apb2_mux"; + }; + + apb2: apb2_clk@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-apb2-div-clk"; + reg = <0x01c20058 0x4>; + clocks = <&apb2_mux>; + clock-output-names = "apb2"; + }; + + apb2_gates: clk@01c2006c { + #clock-cells = <1>; + compatible = "allwinner,sun8i-a23-apb2-gates-clk"; + reg = <0x01c2006c 0x4>; + clocks = <&apb2>; + clock-output-names = "apb2_i2c0", "apb2_i2c1", + "apb2_i2c2", "apb2_uart0", + "apb2_uart1", "apb2_uart2", + "apb2_uart3", "apb2_uart4"; + }; }; soc@01c00000 { @@ -92,7 +207,7 @@ interrupts = <0 0 4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb2_gates 16>; status = "disabled"; }; @@ -102,7 +217,7 @@ interrupts = <0 1 4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb2_gates 17>; status = "disabled"; }; @@ -112,7 +227,7 @@ interrupts = <0 2 4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb2_gates 18>; status = "disabled"; }; @@ -122,7 +237,7 @@ interrupts = <0 3 4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb2_gates 19>; status = "disabled"; }; @@ -132,7 +247,7 @@ interrupts = <0 4 4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb2_gates 20>; status = "disabled"; }; -- cgit v1.2.3 From ae6b61840bfa36d4f1d89703a312ce29a52c3a76 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 3 Jul 2014 14:02:45 +0200 Subject: ARM: shmobile: genmai reference dts: Add RSPI node Add SPI device for RSPI on Genmai. On this board, only rspi4 is in use. Its bus contains a single device (a wm8978 audio codec), for which no bindings are defined yet. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-genmai.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index 56849b55e1c2..20705467f4c9 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -57,3 +57,13 @@ &scif2 { status = "okay"; }; + +&spi4 { + status = "okay"; + + codec: codec@0 { + compatible = "wlf,wm8978"; + reg = <0>; + spi-max-frequency = <5000000>; + }; +}; -- cgit v1.2.3 From c571111ac1d6e99a4ad49ae105325704e3381ccc Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 3 Jul 2014 22:55:49 +0800 Subject: ARM: sun8i: Add reset controller nodes to the DTSI The A23 has the same MMIO reset controllers matching the clocks gates, just like in the A31. This patch adds the reset controller nodes and the reset control phandles for the peripherals needing them to the DTSI. Unlike the sun6i DTSI, this patch uses sun6i-a31-clock-reset for ahb1_rst. sun6i-a31-ahb-reset is for early init, and requires some additions to the machine code. It is used to support the hstimer. However the hstimer on sun8i only has 1 timer, which is somewhat useless. Support for it will probably not be added. Hence the decision to use sun6i-a31-clock-reset here to avoid the changes to sun8i machine code. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 79c40834bc0a..886776d09c06 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -187,6 +187,24 @@ #size-cells = <1>; ranges; + ahb1_rst: reset@01c202c0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202c0 0xc>; + }; + + apb1_rst: reset@01c202d0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202d0 0x4>; + }; + + apb2_rst: reset@01c202d8 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202d8 0x4>; + }; + timer@01c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; @@ -208,6 +226,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 16>; + resets = <&apb2_rst 16>; status = "disabled"; }; @@ -218,6 +237,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 17>; + resets = <&apb2_rst 17>; status = "disabled"; }; @@ -228,6 +248,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 18>; + resets = <&apb2_rst 18>; status = "disabled"; }; @@ -238,6 +259,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 19>; + resets = <&apb2_rst 19>; status = "disabled"; }; @@ -248,6 +270,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 20>; + resets = <&apb2_rst 20>; status = "disabled"; }; -- cgit v1.2.3 From 4ada2129ebffb66624325ec6af738989937621a8 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 15 Apr 2014 17:31:00 +0200 Subject: ARM: ux500: add VCC and VIO regulators to STMPE IC Add a VCC and VIO regulator supplies to the the STMPE expander found on the STUIB UIB variants. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-stuib.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi index 1c3574435ea8..84d7c5d883f2 100644 --- a/arch/arm/boot/dts/ste-href-stuib.dtsi +++ b/arch/arm/boot/dts/ste-href-stuib.dtsi @@ -42,6 +42,8 @@ interrupts = <26 IRQ_TYPE_EDGE_FALLING>; interrupt-parent = <&gpio6>; interrupt-controller; + vcc-supply = <&db8500_vsmps2_reg>; + vio-supply = <&db8500_vsmps2_reg>; wakeup-source; st,autosleep-timeout = <1024>; -- cgit v1.2.3 From 14cdf8cbc73caf205226acb20b4fdd02f0a17f70 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 11 Jun 2014 10:45:50 +0200 Subject: ARM: ux500: add some DB8500 DMA channel info This adds some missing DMA channel information to the disabled MMC/SD/SDIO blocks number 3 and 5, and notes that the assignment of MSP channels vary with ASIC variant. Reviewed-by: Ulf Hansson Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index e41eedca3ce3..9d2323020d34 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -875,6 +875,10 @@ reg = <0x80119000 0x1000>; interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */ + <&dma 41 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; clock-names = "sdi", "apb_pclk"; @@ -901,6 +905,10 @@ reg = <0x80008000 0x1000>; interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */ + <&dma 43 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; clock-names = "sdi", "apb_pclk"; @@ -929,6 +937,7 @@ interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; + /* This DMA channel only exist on DB8500 v1 */ dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */ dma-names = "tx"; @@ -962,6 +971,7 @@ interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; + /* This DMA channel only exist on DB8500 v2 */ dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */ dma-names = "rx"; -- cgit v1.2.3 From d0e3bc813359360fb94098fec9403820846577f3 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 12 Apr 2014 17:13:23 +0200 Subject: ARM: ux500: add misc sensors to the device trees This adds the STMicroelectonics MEMS sensor devices to the Ux500 family device trees: - Accelerometer - Magnetometer - Gyroscope - Pressure (barometer) Cc: Lee Jones Cc: Denis CIOCCA Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-tvk1281618.dtsi | 59 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/ste-hrefv60plus.dtsi | 24 ------------ arch/arm/boot/dts/ste-snowball.dts | 38 +++++++++++++++++-- 3 files changed, 94 insertions(+), 27 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi index c40565320978..18b65d1b14f2 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi @@ -88,6 +88,43 @@ }; }; }; + /* Sensors mounted on this board variant */ + i2c@80128000 { + lsm303dlh@18 { + /* Accelerometer */ + compatible = "st,lsm303dlh-accel"; + st,drdy-int-pin = <1>; + reg = <0x18>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&accel_tvk_mode>; + }; + lsm303dlm@1e { + /* Magnetometer */ + compatible = "st,lsm303dlm-magn"; + reg = <0x1e>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&magneto_tvk_mode>; + }; + l3g4200d@68 { + /* Gyroscope */ + compatible = "st,l3g4200d-gyro"; + st,drdy-int-pin = <2>; + reg = <0x68>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + }; + lsp001wm@5c { + /* Barometer/pressure sensor */ + compatible = "st,lps001wp-press"; + reg = <0x5c>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + }; + }; pinctrl { /* Pull up this GPIO pin */ tc35893 { @@ -114,6 +151,28 @@ }; }; }; + accelerometer { + accel_tvk_mode: accel_tvk { + /* Accelerometer interrupt lines 1 & 2 */ + tvk_cfg { + ste,pins = "GPIO82_C1", "GPIO83_D3"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + magnetometer { + magneto_tvk_mode: magneto_tvk { + /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */ + tvk_cfg1 { + ste,pins = "GPIO31_V3"; + ste,config = <&gpio_in_pu>; + }; + tvk_cfg2 { + ste,pins = "GPIO32_V2"; + ste,config = <&gpio_in_pd>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi index c2341061b943..bcc1f0c37f49 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi @@ -35,8 +35,6 @@ */ pinctrl-names = "default"; pinctrl-0 = <&ipgpio_hrefv60_mode>, - <&accel_hrefv60_mode>, - <&magneto_hrefv60_mode>, <&etm_hrefv60_mode>, <&nahj_hrefv60_mode>, <&nfc_hrefv60_mode>, @@ -83,28 +81,6 @@ }; }; }; - accelerometer { - accel_hrefv60_mode: accel_hrefv60 { - /* Accelerometer interrupt lines 1 & 2 */ - hrefv60_cfg1 { - ste,pins = "GPIO82_C1", "GPIO83_D3"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - magnetometer { - magneto_hrefv60_mode: magneto_hrefv60 { - /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */ - hrefv60_cfg1 { - ste,pins = "GPIO31_V3"; - ste,config = <&gpio_in_pu>; - }; - hrefv60_cfg2 { - ste,pins = "GPIO32_V2"; - ste,config = <&gpio_in_pd>; - }; - }; - }; etm { /* * Drive D19-D23 for the ETM PTM trace interface low, diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 474ef83229cd..4a2000c620ad 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -241,6 +241,40 @@ pinctrl-names = "default","sleep"; pinctrl-0 = <&i2c2_default_mode>; pinctrl-1 = <&i2c2_sleep_mode>; + lsm303dlh@18 { + /* Accelerometer */ + compatible = "st,lsm303dlh-accel"; + st,drdy-int-pin = <1>; + reg = <0x18>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&accel_snowball_mode>; + }; + lsm303dlm@1e { + /* Magnetometer */ + compatible = "st,lsm303dlm-magn"; + reg = <0x1e>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&magneto_snowball_mode>; + }; + l3g4200d@68 { + /* Gyroscope */ + compatible = "st,l3g4200d-gyro"; + st,drdy-int-pin = <2>; + reg = <0x68>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + }; + lsp001wm@5c { + /* Barometer/pressure sensor */ + compatible = "st,lps001wp-press"; + reg = <0x5c>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + }; }; i2c@80110000 { @@ -361,9 +395,7 @@ * can be moved over to being controlled by respective device. */ pinctrl-names = "default"; - pinctrl-0 = <&accel_snowball_mode>, - <&magneto_snowball_mode>, - <&gbf_snowball_mode>, + pinctrl-0 = <&gbf_snowball_mode>, <&wlan_snowball_mode>; ethernet { -- cgit v1.2.3 From 22298d6a85cd7c5c037dd9f3b72e8234c3f09434 Mon Sep 17 00:00:00 2001 From: Andreas Faerber Date: Tue, 8 Jul 2014 08:17:14 +0900 Subject: ARM: dts: Fill in CPU clock-frequency for exynos5410 It's 1.6 GHz for the Cortex-A15. Avoids warnings like "/cpus/cpu@0 missing clock-frequency property". Signed-off-by: Andreas Faerber Reviewed-by: Tarek Dakhran Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5410.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 3839c26f467f..9d0b8cc1409c 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -28,24 +28,28 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; + clock-frequency = <1600000000>; }; CPU1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x1>; + clock-frequency = <1600000000>; }; CPU2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x2>; + clock-frequency = <1600000000>; }; CPU3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x3>; + clock-frequency = <1600000000>; }; }; -- cgit v1.2.3 From a8d80b6be83a45c80295cac6e9b9f4d6a279321f Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Tue, 8 Jul 2014 08:20:08 +0900 Subject: ARM: dts: Add sound-card name for Snow/Peach-Pit/Peach-Pi Add sound-card name property to Snow/Peach-Pit/Peach-Pi boards. Signed-off-by: Tushar Behera Acked-by: Mark Brown Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250-snow.dts | 1 + arch/arm/boot/dts/exynos5420-peach-pit.dts | 1 + arch/arm/boot/dts/exynos5800-peach-pi.dts | 1 + 3 files changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 079fdf9e3f18..6c36d412fd30 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -351,6 +351,7 @@ sound { compatible = "google,snow-audio-max98095"; + samsung,model = "Snow-I2S-MAX98095"; samsung,i2s-controller = <&i2s0>; samsung,audio-codec = <&max98095>; }; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 764998205354..6c7cab0eba25 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -62,6 +62,7 @@ sound { compatible = "google,snow-audio-max98090"; + samsung,model = "Peach-Pit-I2S-MAX98090"; samsung,i2s-controller = <&i2s0>; samsung,audio-codec = <&max98090>; }; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 2c2c1379519c..28f2a251aee5 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -60,6 +60,7 @@ sound { compatible = "google,snow-audio-max98091"; + samsung,model = "Peach-Pi-I2S-MAX98091"; samsung,i2s-controller = <&i2s0>; samsung,audio-codec = <&max98091>; }; -- cgit v1.2.3 From aace0809e9bbbfe1570a298a3284d9802fbf2d1a Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 24 Jun 2014 22:10:05 +0400 Subject: ARM: shmobile: r8a7791: add internal PCI bridge nodes Add device nodes for the R8A7791 internal PCI bridge devices. Signed-off-by: Sergei Shtylyov Acked-by: Arnd Bergmann [horms+renesas@verge.net.au: minor witespace changes] Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 336a6c03b510..6e9a556e1509 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -961,6 +961,46 @@ status = "disabled"; }; + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7791"; + device_type = "pci"; + clocks = <&mstp7_clks R8A7791_CLK_EHCI>; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; + }; + + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7791"; + device_type = "pci"; + clocks = <&mstp7_clks R8A7791_CLK_EHCI>; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; + }; + pciec: pcie@fe000000 { compatible = "renesas,pcie-r8a7791"; reg = <0 0xfe000000 0 0x80000>; -- cgit v1.2.3 From 7540aeb0dd2c830ed490e7227d51bc3050ac798c Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 24 Jun 2014 22:11:44 +0400 Subject: ARM: shmobile: koelsch: enable internal PCI Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to them. Signed-off-by: Sergei Shtylyov Acked-by: Arnd Bergmann [horms+renesas@verge.net.au: minor witespace changes] Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 5dac67395525..23486c081a69 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -279,6 +279,16 @@ renesas,groups = "i2c6"; renesas,function = "i2c6"; }; + + usb0_pins: usb0 { + renesas,groups = "usb0"; + renesas,function = "usb0"; + }; + + usb1_pins: usb1 { + renesas,groups = "usb1"; + renesas,function = "usb1"; + }; }; ðer { @@ -426,6 +436,18 @@ }; }; +&pci0 { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; + &pcie_bus_clk { status = "okay"; }; -- cgit v1.2.3 From 83ccfa8d0c6a734720ed8cd23b97256ffcae156a Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 24 Jun 2014 22:13:38 +0400 Subject: ARM: shmobile: henninger: enable internal PCI Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to them. Signed-off-by: Sergei Shtylyov Acked-by: Arnd Bergmann [horms+renesas@verge.net.au: minor witespace changes] Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-henninger.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts index bc48bccfff54..cfd1fa68d674 100644 --- a/arch/arm/boot/dts/r8a7791-henninger.dts +++ b/arch/arm/boot/dts/r8a7791-henninger.dts @@ -125,6 +125,16 @@ "msiof0_tx"; renesas,function = "msiof0"; }; + + usb0_pins: usb0 { + renesas,groups = "usb0"; + renesas,function = "usb0"; + }; + + usb1_pins: usb1 { + renesas,groups = "usb1"; + renesas,function = "usb1"; + }; }; &scif0 { @@ -231,6 +241,18 @@ }; }; +&pci0 { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; + &pcie_bus_clk { status = "okay"; }; -- cgit v1.2.3 From 2b7ef094a4e374cb2cfaf7f833ad67b911ae4736 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Tue, 8 Jul 2014 12:23:42 -0400 Subject: ARM: dts: keystone: fix netcp's clocks definitions The clocks tree for Keystone 2 NTCP devices should be defined as following: [refclk] - board dependent |- - PLL clock |- - fixed factor clock div=3 mul=1 |- - gated clock |- - gated clock |- - gated clock Hence, update Keystone 2 DT to follow HW specification. Signed-off-by: WingMan Kwok Signed-off-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/k2e-clocks.dtsi | 2 +- arch/arm/boot/dts/k2hk-clocks.dtsi | 2 +- arch/arm/boot/dts/k2l-clocks.dtsi | 2 +- arch/arm/boot/dts/keystone-clocks.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/k2e-clocks.dtsi b/arch/arm/boot/dts/k2e-clocks.dtsi index 90774d604bc1..598afe91c676 100644 --- a/arch/arm/boot/dts/k2e-clocks.dtsi +++ b/arch/arm/boot/dts/k2e-clocks.dtsi @@ -22,7 +22,7 @@ clocks { #clock-cells = <0>; compatible = "ti,keystone,pll-clock"; clocks = <&refclkpass>; - clock-output-names = "pa-pll-clk"; + clock-output-names = "papllclk"; reg = <0x02620358 4>; reg-names = "control"; }; diff --git a/arch/arm/boot/dts/k2hk-clocks.dtsi b/arch/arm/boot/dts/k2hk-clocks.dtsi index 96e65365afe3..d5adee3c0067 100644 --- a/arch/arm/boot/dts/k2hk-clocks.dtsi +++ b/arch/arm/boot/dts/k2hk-clocks.dtsi @@ -31,7 +31,7 @@ clocks { #clock-cells = <0>; compatible = "ti,keystone,pll-clock"; clocks = <&refclkpass>; - clock-output-names = "pa-pll-clk"; + clock-output-names = "papllclk"; reg = <0x02620358 4>; reg-names = "control"; }; diff --git a/arch/arm/boot/dts/k2l-clocks.dtsi b/arch/arm/boot/dts/k2l-clocks.dtsi index f584b80200f8..eb1e3e29f073 100644 --- a/arch/arm/boot/dts/k2l-clocks.dtsi +++ b/arch/arm/boot/dts/k2l-clocks.dtsi @@ -31,7 +31,7 @@ clocks { #clock-cells = <0>; compatible = "ti,keystone,pll-clock"; clocks = <&refclksys>; - clock-output-names = "pa-pll-clk"; + clock-output-names = "papllclk"; reg = <0x02620358 4>; reg-names = "control"; }; diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi index 93f82c7010ab..0c334b25781e 100644 --- a/arch/arm/boot/dts/keystone-clocks.dtsi +++ b/arch/arm/boot/dts/keystone-clocks.dtsi @@ -215,7 +215,7 @@ clocks { clkpa: clkpa { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; + clocks = <&paclk13>; clock-output-names = "pa"; reg = <0x0235001c 0xb00>, <0x02350008 0x400>; reg-names = "control", "domain"; -- cgit v1.2.3 From eb0f12e24f357f1663b4da8c571214d5a11eb011 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 7 Jul 2014 08:47:36 +0200 Subject: ARM: shmobile: henninger: Consistently use tabs for indentation Unify white space usage by consistently using tabs for indentation. Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-henninger.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts index cfd1fa68d674..3a2ef0a2a137 100644 --- a/arch/arm/boot/dts/r8a7791-henninger.dts +++ b/arch/arm/boot/dts/r8a7791-henninger.dts @@ -161,7 +161,7 @@ }; &sata0 { - status = "okay"; + status = "okay"; }; &sdhi0 { -- cgit v1.2.3 From cc703a59c0f8769456a7eb0d53a8d709e5c19387 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 7 Jul 2014 08:47:38 +0200 Subject: ARM: shmobile: r8a7779: Consistently use tabs for indentation Unify white space usage by consistently using tabs for indentation. Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index b517c8e6b420..13bf08ac6011 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -49,13 +49,13 @@ spi2 = &hspi2; }; - gic: interrupt-controller@f0001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xf0001000 0x1000>, - <0xf0000100 0x100>; - }; + gic: interrupt-controller@f0001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xf0001000 0x1000>, + <0xf0000100 0x100>; + }; gpio0: gpio@ffc40000 { compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; -- cgit v1.2.3 From b2386fa51696ffcae82f27ebbdc667b037be5048 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 7 Jul 2014 08:50:08 +0200 Subject: ARM: shmobile: armadillo800eva-reference: Remove early_printk from command line As early printk is not supported when devices are initialised using DT, so remove it from the command line. Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index f6ef73ff49e8..ba2e1806b3ad 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -20,7 +20,7 @@ compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740"; chosen { - bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; + bootargs = "console=tty0 console=ttySC1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; }; memory { -- cgit v1.2.3 From 0b7324706ea24489a0ddcbd9d472e232520aad80 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 7 Jul 2014 08:50:09 +0200 Subject: ARM: shmobile: kzm9g-reference: Remove early_printk from command line As early printk is not supported when devices are initialised using DT, so remove it from the command line. Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index a99171c8a782..838f93e44452 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -35,7 +35,7 @@ }; chosen { - bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200 rw"; + bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw"; }; memory { -- cgit v1.2.3 From 513006334fb01c7c19b5e005357d94de43a370dd Mon Sep 17 00:00:00 2001 From: R Sricharan Date: Thu, 26 Jun 2014 12:55:30 +0530 Subject: ARM: dts: dra7: add routable-irqs property for gic node There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Signed-off-by: Sricharan R Signed-off-by: Nishanth Menon Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c29945e07c5a..1cf4ee10acf5 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -45,6 +45,7 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; + arm,routable-irqs = <192>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>, <0x48214000 0x2000>, -- cgit v1.2.3 From a46631c4cda1488a69600efb93f38d84b7a57541 Mon Sep 17 00:00:00 2001 From: R Sricharan Date: Thu, 26 Jun 2014 12:55:31 +0530 Subject: ARM: dts: dra7: add crossbar device binding There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The Peripheral irq requests are connected to only one crossbar input and the output of the crossbar is connected to only one controller's input line. The crossbar device is used to map a peripheral input to a free mpu's interrupt controller line. Here, adding a new crossbar device node and replacing all the peripheral interrupt numbers with its fixed crossbar input lines. Signed-off-by: Sricharan R Signed-off-by: Nishanth Menon Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 138 +++++++++++++++++++++++++------------------- 1 file changed, 80 insertions(+), 58 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 1cf4ee10acf5..961be6b8ffbf 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -12,6 +12,9 @@ #include "skeleton.dtsi" +#define MAX_SOURCES 400 +#define DIRECT_IRQ(irq) (MAX_SOURCES + irq) + / { #address-cells = <1>; #size-cells = <1>; @@ -80,8 +83,8 @@ ti,hwmods = "l3_main_1", "l3_main_2"; reg = <0x44000000 0x1000000>, <0x45000000 0x1000>; - interrupts = , - ; + interrupts = , + ; prm: prm@4ae06000 { compatible = "ti,dra7-prm"; @@ -156,10 +159,10 @@ sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; #dma-cells = <1>; #dma-channels = <32>; #dma-requests = <127>; @@ -168,7 +171,7 @@ gpio1: gpio@4ae10000 { compatible = "ti,omap4-gpio"; reg = <0x4ae10000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio1"; gpio-controller; #gpio-cells = <2>; @@ -179,7 +182,7 @@ gpio2: gpio@48055000 { compatible = "ti,omap4-gpio"; reg = <0x48055000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>; @@ -190,7 +193,7 @@ gpio3: gpio@48057000 { compatible = "ti,omap4-gpio"; reg = <0x48057000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>; @@ -201,7 +204,7 @@ gpio4: gpio@48059000 { compatible = "ti,omap4-gpio"; reg = <0x48059000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>; @@ -212,7 +215,7 @@ gpio5: gpio@4805b000 { compatible = "ti,omap4-gpio"; reg = <0x4805b000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio5"; gpio-controller; #gpio-cells = <2>; @@ -223,7 +226,7 @@ gpio6: gpio@4805d000 { compatible = "ti,omap4-gpio"; reg = <0x4805d000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio6"; gpio-controller; #gpio-cells = <2>; @@ -234,7 +237,7 @@ gpio7: gpio@48051000 { compatible = "ti,omap4-gpio"; reg = <0x48051000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio7"; gpio-controller; #gpio-cells = <2>; @@ -245,7 +248,7 @@ gpio8: gpio@48053000 { compatible = "ti,omap4-gpio"; reg = <0x48053000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio8"; gpio-controller; #gpio-cells = <2>; @@ -256,7 +259,7 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; reg = <0x4806a000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart1"; clock-frequency = <48000000>; status = "disabled"; @@ -265,7 +268,7 @@ uart2: serial@4806c000 { compatible = "ti,omap4-uart"; reg = <0x4806c000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart2"; clock-frequency = <48000000>; status = "disabled"; @@ -274,7 +277,7 @@ uart3: serial@48020000 { compatible = "ti,omap4-uart"; reg = <0x48020000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart3"; clock-frequency = <48000000>; status = "disabled"; @@ -283,7 +286,7 @@ uart4: serial@4806e000 { compatible = "ti,omap4-uart"; reg = <0x4806e000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart4"; clock-frequency = <48000000>; status = "disabled"; @@ -292,7 +295,7 @@ uart5: serial@48066000 { compatible = "ti,omap4-uart"; reg = <0x48066000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart5"; clock-frequency = <48000000>; status = "disabled"; @@ -301,7 +304,7 @@ uart6: serial@48068000 { compatible = "ti,omap4-uart"; reg = <0x48068000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart6"; clock-frequency = <48000000>; status = "disabled"; @@ -310,6 +313,7 @@ uart7: serial@48420000 { compatible = "ti,omap4-uart"; reg = <0x48420000 0x100>; + interrupts = ; ti,hwmods = "uart7"; clock-frequency = <48000000>; status = "disabled"; @@ -318,6 +322,7 @@ uart8: serial@48422000 { compatible = "ti,omap4-uart"; reg = <0x48422000 0x100>; + interrupts = ; ti,hwmods = "uart8"; clock-frequency = <48000000>; status = "disabled"; @@ -326,6 +331,7 @@ uart9: serial@48424000 { compatible = "ti,omap4-uart"; reg = <0x48424000 0x100>; + interrupts = ; ti,hwmods = "uart9"; clock-frequency = <48000000>; status = "disabled"; @@ -334,6 +340,7 @@ uart10: serial@4ae2b000 { compatible = "ti,omap4-uart"; reg = <0x4ae2b000 0x100>; + interrupts = ; ti,hwmods = "uart10"; clock-frequency = <48000000>; status = "disabled"; @@ -342,7 +349,7 @@ timer1: timer@4ae18000 { compatible = "ti,omap5430-timer"; reg = <0x4ae18000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer1"; ti,timer-alwon; }; @@ -350,28 +357,28 @@ timer2: timer@48032000 { compatible = "ti,omap5430-timer"; reg = <0x48032000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer2"; }; timer3: timer@48034000 { compatible = "ti,omap5430-timer"; reg = <0x48034000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer3"; }; timer4: timer@48036000 { compatible = "ti,omap5430-timer"; reg = <0x48036000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer4"; }; timer5: timer@48820000 { compatible = "ti,omap5430-timer"; reg = <0x48820000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer5"; ti,timer-dsp; }; @@ -379,7 +386,7 @@ timer6: timer@48822000 { compatible = "ti,omap5430-timer"; reg = <0x48822000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer6"; ti,timer-dsp; ti,timer-pwm; @@ -388,7 +395,7 @@ timer7: timer@48824000 { compatible = "ti,omap5430-timer"; reg = <0x48824000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer7"; ti,timer-dsp; }; @@ -396,7 +403,7 @@ timer8: timer@48826000 { compatible = "ti,omap5430-timer"; reg = <0x48826000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer8"; ti,timer-dsp; ti,timer-pwm; @@ -405,21 +412,21 @@ timer9: timer@4803e000 { compatible = "ti,omap5430-timer"; reg = <0x4803e000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer9"; }; timer10: timer@48086000 { compatible = "ti,omap5430-timer"; reg = <0x48086000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer10"; }; timer11: timer@48088000 { compatible = "ti,omap5430-timer"; reg = <0x48088000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer11"; ti,timer-pwm; }; @@ -427,6 +434,7 @@ timer13: timer@48828000 { compatible = "ti,omap5430-timer"; reg = <0x48828000 0x80>; + interrupts = ; ti,hwmods = "timer13"; status = "disabled"; }; @@ -434,6 +442,7 @@ timer14: timer@4882a000 { compatible = "ti,omap5430-timer"; reg = <0x4882a000 0x80>; + interrupts = ; ti,hwmods = "timer14"; status = "disabled"; }; @@ -441,6 +450,7 @@ timer15: timer@4882c000 { compatible = "ti,omap5430-timer"; reg = <0x4882c000 0x80>; + interrupts = ; ti,hwmods = "timer15"; status = "disabled"; }; @@ -448,6 +458,7 @@ timer16: timer@4882e000 { compatible = "ti,omap5430-timer"; reg = <0x4882e000 0x80>; + interrupts = ; ti,hwmods = "timer16"; status = "disabled"; }; @@ -455,7 +466,7 @@ wdt2: wdt@4ae14000 { compatible = "ti,omap4-wdt"; reg = <0x4ae14000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "wd_timer2"; }; @@ -469,14 +480,14 @@ dmm@4e000000 { compatible = "ti,omap5-dmm"; reg = <0x4e000000 0x800>; - interrupts = <0 113 0x4>; + interrupts = ; ti,hwmods = "dmm"; }; i2c1: i2c@48070000 { compatible = "ti,omap4-i2c"; reg = <0x48070000 0x100>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; @@ -486,7 +497,7 @@ i2c2: i2c@48072000 { compatible = "ti,omap4-i2c"; reg = <0x48072000 0x100>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; @@ -496,7 +507,7 @@ i2c3: i2c@48060000 { compatible = "ti,omap4-i2c"; reg = <0x48060000 0x100>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; @@ -506,7 +517,7 @@ i2c4: i2c@4807a000 { compatible = "ti,omap4-i2c"; reg = <0x4807a000 0x100>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c4"; @@ -516,7 +527,7 @@ i2c5: i2c@4807c000 { compatible = "ti,omap4-i2c"; reg = <0x4807c000 0x100>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c5"; @@ -526,7 +537,7 @@ mmc1: mmc@4809c000 { compatible = "ti,omap4-hsmmc"; reg = <0x4809c000 0x400>; - interrupts = ; + interrupts = ; ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset; @@ -539,7 +550,7 @@ mmc2: mmc@480b4000 { compatible = "ti,omap4-hsmmc"; reg = <0x480b4000 0x400>; - interrupts = ; + interrupts = ; ti,hwmods = "mmc2"; ti,needs-special-reset; dmas = <&sdma 47>, <&sdma 48>; @@ -550,7 +561,7 @@ mmc3: mmc@480ad000 { compatible = "ti,omap4-hsmmc"; reg = <0x480ad000 0x400>; - interrupts = ; + interrupts = ; ti,hwmods = "mmc3"; ti,needs-special-reset; dmas = <&sdma 77>, <&sdma 78>; @@ -561,7 +572,7 @@ mmc4: mmc@480d1000 { compatible = "ti,omap4-hsmmc"; reg = <0x480d1000 0x400>; - interrupts = ; + interrupts = ; ti,hwmods = "mmc4"; ti,needs-special-reset; dmas = <&sdma 57>, <&sdma 58>; @@ -704,7 +715,7 @@ mcspi1: spi@48098000 { compatible = "ti,omap4-mcspi"; reg = <0x48098000 0x200>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi1"; @@ -725,7 +736,7 @@ mcspi2: spi@4809a000 { compatible = "ti,omap4-mcspi"; reg = <0x4809a000 0x200>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi2"; @@ -741,7 +752,7 @@ mcspi3: spi@480b8000 { compatible = "ti,omap4-mcspi"; reg = <0x480b8000 0x200>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi3"; @@ -754,7 +765,7 @@ mcspi4: spi@480ba000 { compatible = "ti,omap4-mcspi"; reg = <0x480ba000 0x200>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi4"; @@ -774,7 +785,7 @@ clocks = <&qspi_gfclk_div>; clock-names = "fck"; num-cs = <4>; - interrupts = <0 343 0x4>; + interrupts = ; status = "disabled"; }; @@ -810,7 +821,7 @@ sata: sata@4a141100 { compatible = "snps,dwc-ahci"; reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; - interrupts = ; + interrupts = ; phys = <&sata_phy>; phy-names = "sata-phy"; clocks = <&sata_ref_clk>; @@ -887,7 +898,7 @@ compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss1"; reg = <0x48880000 0x10000>; - interrupts = <0 77 4>; + interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; @@ -895,7 +906,7 @@ usb1: usb@48890000 { compatible = "snps,dwc3"; reg = <0x48890000 0x17000>; - interrupts = <0 76 4>; + interrupts = ; phys = <&usb2_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; tx-fifo-resize; @@ -908,7 +919,7 @@ compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss2"; reg = <0x488c0000 0x10000>; - interrupts = <0 92 4>; + interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; @@ -916,7 +927,7 @@ usb2: usb@488d0000 { compatible = "snps,dwc3"; reg = <0x488d0000 0x17000>; - interrupts = <0 78 4>; + interrupts = ; phys = <&usb2_phy2>; phy-names = "usb2-phy"; tx-fifo-resize; @@ -930,7 +941,7 @@ compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss3"; reg = <0x48900000 0x10000>; - /* interrupts = <0 TBD 4>; */ + interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; @@ -939,7 +950,7 @@ usb3: usb@48910000 { compatible = "snps,dwc3"; reg = <0x48910000 0x17000>; - /* interrupts = <0 93 4>; */ + interrupts = ; tx-fifo-resize; maximum-speed = "high-speed"; dr_mode = "otg"; @@ -950,7 +961,7 @@ compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss4"; reg = <0x48940000 0x10000>; - /* interrupts = <0 TBD 4>; */ + interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; @@ -959,7 +970,7 @@ usb4: usb@48950000 { compatible = "snps,dwc3"; reg = <0x48950000 0x17000>; - /* interrupts = <0 TBD 4>; */ + interrupts = ; tx-fifo-resize; maximum-speed = "high-speed"; dr_mode = "otg"; @@ -969,7 +980,7 @@ elm: elm@48078000 { compatible = "ti,am3352-elm"; reg = <0x48078000 0xfc0>; /* device IO registers */ - interrupts = ; + interrupts = ; ti,hwmods = "elm"; status = "disabled"; }; @@ -978,13 +989,24 @@ compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; reg = <0x50000000 0x37c>; /* device IO registers */ - interrupts = ; + interrupts = ; gpmc,num-cs = <8>; gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; status = "disabled"; }; + + crossbar_mpu: crossbar@4a020000 { + compatible = "ti,irq-crossbar"; + reg = <0x4a002a48 0x130>; + ti,max-irqs = <160>; + ti,max-crossbar-sources = ; + ti,reg-size = <2>; + ti,irqs-reserved = <0 1 2 3 5 6 131 132>; + ti,irqs-skip = <10 133 139 140>; + ti,irqs-safe-map = <0>; + }; }; }; -- cgit v1.2.3 From 4341881d0562309ca9fd5e0bc5a2a85f2945f74a Mon Sep 17 00:00:00 2001 From: Ash Charles Date: Tue, 10 Jun 2014 15:22:00 -0700 Subject: ARM: dts: Add devicetree for Gumstix Pepper board This adds the Gumstix Pepper[1] single-board computer based on the TI AM335x processor. Schematics are available [2]. [1] https://store.gumstix.com/index.php/products/344/ [2] https://pubs.gumstix.com/boards/PEPPER/ Signed-off-by: Ash Charles Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/am335x-pepper.dts | 653 ++++++++++++++++++++++++++++++++++++ 2 files changed, 655 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/am335x-pepper.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 63d1e5399629..b19f0c89f452 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -291,7 +291,8 @@ dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \ am335x-boneblack.dtb \ am335x-evm.dtb \ am335x-evmsk.dtb \ - am335x-nano.dtb + am335x-nano.dtb \ + am335x-pepper.dtb dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \ omap4-panda.dtb \ omap4-panda-a4.dtb \ diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts new file mode 100644 index 000000000000..0d35ab64641c --- /dev/null +++ b/arch/arm/boot/dts/am335x-pepper.dts @@ -0,0 +1,653 @@ +/* + * Copyright (C) 2014 Gumstix, Inc. - https://www.gumstix.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include +#include "am33xx.dtsi" + +/ { + model = "Gumstix Pepper"; + compatible = "gumstix,am335x-pepper", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc3_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + buttons: user_buttons { + compatible = "gpio-keys"; + }; + + leds: user_leds { + compatible = "gpio-leds"; + }; + + panel: lcd_panel { + compatible = "ti,tilcdc,panel"; + }; + + sound: sound_iface { + compatible = "ti,da830-evm-audio"; + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + }; + + v3v3c_reg: fixedregulator@1 { + compatible = "regulator-fixed"; + }; + + vdd5_reg: fixedregulator@2 { + compatible = "regulator-fixed"; + }; +}; + +/* I2C Busses */ +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + + eeprom: eeprom@50 { + compatible = "at,24c256"; + reg = <0x50>; + }; + + audio_codec: tlv320aic3106@1b { + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + }; + + accel: lis331dlh@1d { + compatible = "st,lis3lv02d"; + reg = <0x1d>; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; +}; + +&am33xx_pinmux { + i2c0_pins: pinmux_i2c0 { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + i2c1_pins: pinmux_i2c1 { + pinctrl-single,pins = < + 0x10C (PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_crs,i2c1_sda */ + 0x110 (PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_rxerr,i2c1_scl */ + >; + }; +}; + +/* Accelerometer */ +&accel { + pinctrl-names = "default"; + pinctrl-0 = <&accel_pins>; + + Vdd-supply = <&ldo3_reg>; + Vdd_IO-supply = <&ldo3_reg>; + st,irq1-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <92>; + st,max-limit-x = <14>; + st,min-limit-y = <14>; + st,max-limit-y = <92>; + st,min-limit-z = <92>; + st,max-limit-z = <14>; +}; + +&am33xx_pinmux { + accel_pins: pinmux_accel { + pinctrl-single,pins = < + 0x98 (PIN_INPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */ + >; + }; +}; + +/* Audio */ +&audio_codec { + status = "okay"; + + gpio-reset = <&gpio1 16 GPIO_ACTIVE_LOW>; + AVDD-supply = <&ldo3_reg>; + IOVDD-supply = <&ldo3_reg>; + DRVDD-supply = <&ldo3_reg>; + DVDD-supply = <&dcdc1_reg>; +}; + +&sound { + ti,model = "AM335x-EVM"; + ti,audio-codec = <&audio_codec>; + ti,mcasp-controller = <&mcasp0>; + ti,codec-clock-rate = <12000000>; + ti,audio-routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In"; +}; + +&mcasp0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; + + op-mode = <0>; /* MCASP_ISS_MODE */ + tdm-slots = <2>; + serial-dir = < + 1 2 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <1>; + rx-num-evt = <1>; +}; + +&am33xx_pinmux { + audio_pins: pinmux_audio { + pinctrl-single,pins = < + 0x1AC (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ + 0x194 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ + 0x190 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ + 0x198 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ + 0x1A8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */ + 0x40 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a0.gpio1_16 */ + >; + }; +}; + +/* Display: 24-bit LCD Screen */ +&panel { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <32>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + display-timings { + native-mode = <&timing0>; + timing0: 480x272 { + clock-frequency = <18400000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vfront-porch = <4>; + vback-porch = <2>; + vsync-len = <10>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; +}; + +&lcdc { + status = "okay"; +}; + +&am33xx_pinmux { + lcd_pins: pinmux_lcd { + pinctrl-single,pins = < + 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data16 */ + 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data17 */ + 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data18 */ + 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data19 */ + 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data20 */ + 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data21 */ + 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data22 */ + 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data23 */ + 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + /* Display Enable */ + 0x6c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a11.gpio1_27 */ + >; + }; +}; + +/* Ethernet */ +&cpsw_emac0 { + status = "okay"; + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rgmii"; +}; + +&cpsw_emac1 { + status = "okay"; + phy_id = <&davinci_mdio>, <1>; + phy-mode = "rgmii"; +}; + +&davinci_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; +}; + +&mac { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_pins>; +}; + + +&am33xx_pinmux { + ethernet_pins: pinmux_ethernet { + pinctrl-single,pins = < + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + 0x118 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + 0x12c (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + 0x130 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + 0x134 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd3.rgmii1_rxd3 */ + 0x138 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd2.rgmii1_rxd2 */ + 0x13c (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ + 0x140 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ + /* ethernet interrupt */ + 0x144 (PIN_INPUT_PULLUP | MUX_MODE7) /* rmii2_refclk.gpio0_29 */ + /* ethernet PHY nReset */ + 0x108 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mii1_col.gpio3_0 */ + >; + }; + + mdio_pins: pinmux_mdio { + pinctrl-single,pins = < + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; +}; + +/* MMC */ +&mmc1 { + /* Bootable SD card slot */ + status = "okay"; + vmmc-supply = <&ldo3_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&mmc2 { + /* eMMC (not populated) on MMC #2 */ + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + vmmc-supply = <&ldo3_reg>; + bus-width = <8>; + ti,non-removable; +}; + +&edma { + /* Map eDMA MMC2 Events from Crossbar */ + ti,edma-xbar-event-map = /bits/ 16 <1 12 + 2 13>; +}; + + +&mmc3 { + /* Wifi & Bluetooth on MMC #3 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wireless_pins>; + vmmmc-supply = <&v3v3c_reg>; + bus-width = <4>; + ti,non-removable; + dmas = <&edma 12 + &edma 13>; + dma-names = "tx", "rx"; +}; + + +&am33xx_pinmux { + sd_pins: pinmux_sd_card { + pinctrl-single,pins = < + 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + 0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + 0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + 0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + emmc_pins: pinmux_emmc { + pinctrl-single,pins = < + 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + /* EMMC nReset */ + 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + >; + }; + wireless_pins: pinmux_wireless { + pinctrl-single,pins = < + 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ + 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ + 0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ + 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3 */ + 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ + 0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc1_clk */ + /* WLAN nReset */ + 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + /* WLAN nPower down */ + 0x70 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ + /* 32kHz Clock */ + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; +}; + +/* Power */ +&vbat { + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; +}; + +&v3v3c_reg { + regulator-name = "v3v3c_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vbat>; +}; + +&vdd5_reg { + regulator-name = "vdd5_reg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbat>; +}; + +/include/ "tps65217.dtsi" + +&tps { + backlight { + isel = <1>; /* ISET1 */ + fdim = <200>; /* TPS65217_BL_FDIM_200HZ */ + default-brightness = <80>; + }; + + regulators { + dcdc1_reg: regulator@0 { + /* VDD_1V8 system supply */ + }; + + dcdc2_reg: regulator@1 { + /* VDD_CORE voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + }; + + ldo1_reg: regulator@3 { + /* VRTC 1.8V always-on supply */ + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + /* 3.3V rail */ + }; + + ldo3_reg: regulator@5 { + /* VDD_3V3A 3.3V rail */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo4_reg: regulator@6 { + /* VDD_3V3B 3.3V rail */ + }; + }; +}; + +/* SPI Busses */ +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; +}; + +&am33xx_pinmux { + spi0_pins: pinmux_spi0 { + pinctrl-single,pins = < + 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */ + 0x15C (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */ + 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ + >; + }; +}; + +/* Touch Screen */ +&tscadc { + status = "okay"; + tsc { + ti,wires = <4>; + ti,x-plate-resistance = <200>; + ti,coordinate-readouts = <5>; + ti,wire-config = <0x00 0x11 0x22 0x33>; + }; + + adc { + ti,adc-channels = <4 5 6 7>; + }; +}; + +/* UARTs */ +&uart0 { + /* Serial Console */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart1 { + /* Broken out to J6 header */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&am33xx_pinmux { + uart0_pins: pinmux_uart0 { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + uart1_pins: pinmux_uart1 { + pinctrl-single,pins = < + 0x178 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ + 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ + 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ + 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ + >; + }; +}; + +/* USB */ +&usb { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins>; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +&am33xx_pinmux { + usb_pins: pinmux_usb { + pinctrl-single,pins = < + /* USB0 Over-Current (active low) */ + 0x64 (PIN_INPUT | MUX_MODE7) /* gpmc_a9.gpio1_25 */ + /* USB1 Over-Current (active low) */ + 0x68 (PIN_INPUT | MUX_MODE7) /* gpmc_a10.gpio1_26 */ + >; + }; +}; + +/* User IO */ +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_pins>; + + led@0 { + label = "pepper:user0:blue"; + gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + }; + + led@1 { + label = "pepper:user1:red"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + }; +}; + +&buttons { + pinctrl-names = "default"; + pinctrl-0 = <&user_buttons_pins>; + #address-cells = <1>; + #size-cells = <0>; + + button@0 { + label = "home"; + linux,code = ; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + }; + + button@1 { + label = "menu"; + linux,code = ; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + }; + + buttons@2 { + label = "power"; + linux,code = ; + gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + }; +}; + +&am33xx_pinmux { + user_leds_pins: pinmux_user_leds { + pinctrl-single,pins = < + 0x50 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a4.gpio1_20 */ + 0x54 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */ + >; + }; + + user_buttons_pins: pinmux_user_buttons { + pinctrl-single,pins = < + 0x58 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ + 0x5C (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a7.gpio1_21 */ + 0x164 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio0_7 */ + >; + }; +}; -- cgit v1.2.3 From 497d64a34bbd7fad024c38c4a0efaa2d92664ca1 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 9 Jul 2014 11:06:30 +0530 Subject: ARM: dts: AM43x: Add TPS65218 device tree nodes Add TPS65218 device tree nodes. i2c clock frequency setting also added as part of tps65218 nodes addition. As i2c clock enabling is required. Signed-off-by: Keerthy Reviewed-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am43x-epos-evm.dts | 59 ++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 19f1f7e87597..11ffb50374e2 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -323,6 +323,65 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + + tps65218: tps65218@24 { + reg = <0x24>; + compatible = "ti,tps65218"; + interrupts = ; /* NMIn */ + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + compatible = "ti,tps65218-dcdc1"; + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + compatible = "ti,tps65218-dcdc2"; + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + compatible = "ti,tps65218-dcdc3"; + regulator-name = "vdcdc3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc5: regulator-dcdc5 { + compatible = "ti,tps65218-dcdc5"; + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + dcdc6: regulator-dcdc6 { + compatible = "ti,tps65218-dcdc6"; + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,tps65218-ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; at24@50 { compatible = "at24,24c256"; -- cgit v1.2.3 From 1fc98144cd7325af8a7d6325776bbb71b1c17c3b Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 9 Jul 2014 11:06:31 +0530 Subject: ARM: dts: AM437x: Fix i2c nodes indentation Fix i2c nodes indentation. Signed-off-by: Keerthy Reviewed-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 003766c47bbf..85ca430cb874 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -257,16 +257,15 @@ }; &i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; }; &i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; pixcir_ts@5c { compatible = "pixcir,pixcir_tangoc"; pinctrl-names = "default"; -- cgit v1.2.3 From 0e2da5e661002330dee480731d8877d5c342ac65 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 9 Jul 2014 11:06:32 +0530 Subject: ARM: dts: AM437x: Add TPS65218 device tree nodes Add TPS65218 device tree nodes. i2c clock frequency setting also added as part of tps65218 nodes addition. As i2c clock enabling is required. Signed-off-by: Keerthy Reviewed-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 58 +++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 85ca430cb874..f0422c2a7468 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -260,6 +260,64 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + + tps65218: tps65218@24 { + reg = <0x24>; + compatible = "ti,tps65218"; + interrupts = ; /* NMIn */ + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + compatible = "ti,tps65218-dcdc1"; + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + compatible = "ti,tps65218-dcdc2"; + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + compatible = "ti,tps65218-dcdc3"; + regulator-name = "vdcdc3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + dcdc5: regulator-dcdc5 { + compatible = "ti,tps65218-dcdc5"; + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + dcdc6: regulator-dcdc6 { + compatible = "ti,tps65218-dcdc6"; + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,tps65218-ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; }; &i2c1 { -- cgit v1.2.3 From a186cf10da84a50358f813de0edebf45ddadf624 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 9 Jul 2014 11:06:33 +0530 Subject: ARM: omap2plus_defconfig: enable TPS65218 configs Enable TPS65218 config options. Signed-off-by: Keerthy Acked-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/configs/omap2plus_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 59066cf0271a..2b53efa417fc 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -179,6 +179,7 @@ CONFIG_TWL4030_WATCHDOG=y CONFIG_MFD_SYSCON=y CONFIG_MFD_PALMAS=y CONFIG_MFD_TPS65217=y +CONFIG_MFD_TPS65218=y CONFIG_MFD_TPS65910=y CONFIG_TWL6040_CORE=y CONFIG_REGULATOR_FIXED_VOLTAGE=y @@ -187,6 +188,7 @@ CONFIG_REGULATOR_TI_ABB=y CONFIG_REGULATOR_TPS65023=y CONFIG_REGULATOR_TPS6507X=y CONFIG_REGULATOR_TPS65217=y +CONFIG_REGULATOR_TPS65218=y CONFIG_REGULATOR_TPS65910=y CONFIG_REGULATOR_TWL4030=y CONFIG_REGULATOR_PBIAS=y -- cgit v1.2.3 From ae28ea88a38decac2a0dc1abc23936e59a08b6f3 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 30 Jun 2014 14:00:38 +0300 Subject: ARM: dts: dra7-evm: Add regulator information to USB2 PHYs The ldousb_reg regulator provides power to the USB1 and USB2 High Speed PHYs. Signed-off-by: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-evm.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 4adc28039c30..fd96cedf3a07 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -495,3 +495,11 @@ }; }; }; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldousb_reg>; +}; -- cgit v1.2.3 From 73b173e5c59f0114546f16ab807fef9f9404d221 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 17 Jun 2014 15:30:18 +0200 Subject: ARM: at91/dt: sam9261 crystals under the clocks node Having clocks grouped in a subnode is common practice, so move the crystals under a clocks node for the at91sam9261 SoC and at91sam9261 based boards. Signed-off-by: Alexandre Belloni Acked-by: Boris BREZILLON Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9261.dtsi | 20 +++++++++++--------- arch/arm/boot/dts/at91sam9261ek.dts | 16 ++++++++-------- 2 files changed, 19 insertions(+), 17 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 04927db1d6bf..a81aab4281a7 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -46,16 +46,18 @@ reg = <0x20000000 0x08000000>; }; - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + clocks { + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; }; ahb { diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts index aa35a7aec9a8..f4a765729c7a 100644 --- a/arch/arm/boot/dts/at91sam9261ek.dts +++ b/arch/arm/boot/dts/at91sam9261ek.dts @@ -20,14 +20,6 @@ reg = <0x20000000 0x4000000>; }; - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - clocks { #address-cells = <1>; #size-cells = <1>; @@ -37,6 +29,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <18432000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; }; ahb { -- cgit v1.2.3 From 6503ab5fc702b932f64fe090f8c8cc01e2255a9b Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 17 Jun 2014 15:30:18 +0200 Subject: ARM: at91/dt: sam9n12 crystals under the clocks node Having clocks grouped in a subnode is common practice, so move the crystals under a clocks node for the at91sam9n12 SoC and at91sam9n12 based boards. Signed-off-by: Alexandre Belloni Acked-by: Boris BREZILLON Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9n12.dtsi | 20 +++++++++++--------- arch/arm/boot/dts/at91sam9n12ek.dts | 16 ++++++++-------- 2 files changed, 19 insertions(+), 17 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 287795985e32..67efd442fd85 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -50,16 +50,18 @@ reg = <0x20000000 0x10000000>; }; - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; }; ahb { diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 64bbe46e4f90..32f1aad889d2 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -21,14 +21,6 @@ reg = <0x20000000 0x8000000>; }; - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <16000000>; - }; - clocks { #address-cells = <1>; #size-cells = <1>; @@ -38,6 +30,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <16000000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <16000000>; + }; }; ahb { -- cgit v1.2.3 From c2c9e78e2fae81befe0a93418295f6cef17f1575 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 17 Jun 2014 15:30:19 +0200 Subject: ARM: at91/dt: sam9rl crystals under the clocks node Having clocks grouped in a subnode is common practice, so move the crystals under a clocks node for the at91sam9rl SoC and at91sam9rl based boards. Signed-off-by: Alexandre Belloni Acked-by: Boris BREZILLON Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9rl.dtsi | 22 +++++++++++----------- arch/arm/boot/dts/at91sam9rlek.dts | 17 ++++++++--------- 2 files changed, 19 insertions(+), 20 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 1da183155eee..8d6751a00074 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -50,19 +50,19 @@ reg = <0x20000000 0x04000000>; }; - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - clocks { adc_op_clk: adc_op_clk{ compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts index d4a010e40fe3..9be5b540eebf 100644 --- a/arch/arm/boot/dts/at91sam9rlek.dts +++ b/arch/arm/boot/dts/at91sam9rlek.dts @@ -20,15 +20,6 @@ reg = <0x20000000 0x4000000>; }; - - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - clocks { #address-cells = <1>; #size-cells = <1>; @@ -38,6 +29,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <12000000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; }; ahb { -- cgit v1.2.3 From 12dde44998a30fff18a43999934f0abedfe4c16a Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 17 Jun 2014 15:30:19 +0200 Subject: ARM: at91/dt: sam9x5 crystals under the clocks node Having clocks grouped in a subnode is common practice, so move the crystals and the ADC clock under a clocks node for the at91sam9x5 SoC and at91sam9x5 based boards. Signed-off-by: Alexandre Belloni Acked-by: Boris BREZILLON Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9x5.dtsi | 30 ++++++++++++++++-------------- arch/arm/boot/dts/at91sam9x5cm.dtsi | 12 +++++++----- 2 files changed, 23 insertions(+), 19 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index d6133f497207..ed9251324c90 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -52,22 +52,24 @@ reg = <0x20000000 0x10000000>; }; - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <5000000>; + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <5000000>; + }; }; ahb { diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi index 8413e21192eb..229d6c24a9c4 100644 --- a/arch/arm/boot/dts/at91sam9x5cm.dtsi +++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi @@ -23,12 +23,14 @@ }; }; - slow_xtal { - clock-frequency = <32768>; - }; + clocks { + slow_xtal { + clock-frequency = <32768>; + }; - main_xtal { - clock-frequency = <12000000>; + main_xtal { + clock-frequency = <12000000>; + }; }; ahb { -- cgit v1.2.3 From 334394c0d853c52f857a4584866ca8ec442fd05f Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 17 Jun 2014 15:30:20 +0200 Subject: ARM: at91/dt: sama5d3 crystals under the clocks node Having clocks grouped in a subnode is common practice, so move the crystals under a clocks node for the sama5d3 SoC and sama5d3 based boards. Signed-off-by: Alexandre Belloni Acked-by: Boris BREZILLON Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91-sama5d3_xplained.dts | 12 +++++++----- arch/arm/boot/dts/sama5d3.dtsi | 22 +++++++++++----------- arch/arm/boot/dts/sama5d3xcm.dtsi | 12 +++++++----- 3 files changed, 25 insertions(+), 21 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index 5b8e40400bec..fec1fca2ad66 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -21,12 +21,14 @@ reg = <0x20000000 0x10000000>; }; - slow_xtal { - clock-frequency = <32768>; - }; + clocks { + slow_xtal { + clock-frequency = <32768>; + }; - main_xtal { - clock-frequency = <12000000>; + main_xtal { + clock-frequency = <12000000>; + }; }; ahb { diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index e0b15a6e8897..45013b867c8d 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -58,19 +58,19 @@ reg = <0x20000000 0x8000000>; }; - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - clocks { adc_op_clk: adc_op_clk{ compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index b0b1331c1974..f7d8583eef82 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -18,12 +18,14 @@ reg = <0x20000000 0x20000000>; }; - slow_xtal { - clock-frequency = <32768>; - }; + clocks { + slow_xtal { + clock-frequency = <32768>; + }; - main_xtal { - clock-frequency = <12000000>; + main_xtal { + clock-frequency = <12000000>; + }; }; ahb { -- cgit v1.2.3 From 18f44d7bd6f80c94f4d2af3cb90cfe07ea1f9d7b Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 9 Jun 2014 11:31:46 +0800 Subject: ARM: at91: sama5d3xek: switch sound to CCF As the sama5d3xek board has switch to CCF, so add clock for wm8904 Signed-off-by: Bo Shen Reviwed-by: Mark Brown Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3xmb.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index 306eef0f97ef..b8c6f20e780c 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -45,6 +45,8 @@ wm8904: wm8904@1a { compatible = "wm8904"; reg = <0x1a>; + clocks = <&pck0>; + clock-names = "mclk"; }; }; -- cgit v1.2.3 From 38324358c58eb1f4d38ab48d6e62a1f086970c2e Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 9 Jun 2014 11:31:47 +0800 Subject: ARM: at91: at91sam9n12ek: switch sound to CCF As the at91sam9n12ek has switch to CCF, so add clock for wm8904 Signed-off-by: Bo Shen Reviwed-by: Mark Brown Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9n12ek.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 32f1aad889d2..83d723711ae1 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -56,6 +56,8 @@ wm8904: codec@1a { compatible = "wm8904"; reg = <0x1a>; + clocks = <&pck0>; + clock-names = "mclk"; }; qt1070: keyboard@1b { -- cgit v1.2.3 From 4cd9292926901c0e80207a53cb37ea634b2bb09f Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 15 May 2014 17:08:32 +0200 Subject: ARM: at91/dt: add DMA controller node to at91sam9rl Signed-off-by: Nicolas Ferre Acked-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9rl.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 8d6751a00074..2327462f2278 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -348,6 +348,15 @@ }; }; + dma0: dma-controller@ffffe600 { + compatible = "atmel,at91sam9rl-dma"; + reg = <0xffffe600 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&dma0_clk>; + clock-names = "dma_clk"; + }; + ramc0: ramc@ffffea00 { compatible = "atmel,at91sam9260-sdramc"; reg = <0xffffea00 0x200>; -- cgit v1.2.3 From ad7c56aa2d08f9b4e182e8294cfd5896864e4db0 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 15 May 2014 17:09:28 +0200 Subject: ARM: at91/dt: add NAND + DMA property for at91sam9rl Add the "atmel,nand-has-dma" property to NAND node Signed-off-by: Nicolas Ferre Acked-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9rl.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 2327462f2278..ab56c8b81dfa 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -95,6 +95,7 @@ <0xffffe800 0x200>; atmel,nand-addr-offset = <21>; atmel,nand-cmd-offset = <22>; + atmel,nand-has-dma; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; gpios = <&pioD 17 GPIO_ACTIVE_HIGH>, -- cgit v1.2.3 From 152f3003f055465b16e16ee98de3c2080814bd97 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Sat, 14 Jun 2014 02:18:24 +0200 Subject: ARM: at91/dt: ariag25: define crystals frequencies Define Acme Systems Aria G25 board main and slow crystals frequencies. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/at91-ariag25.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts index 55ab6180e350..e9ced30159a7 100644 --- a/arch/arm/boot/dts/at91-ariag25.dts +++ b/arch/arm/boot/dts/at91-ariag25.dts @@ -42,6 +42,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <12000000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; }; ahb { -- cgit v1.2.3 From 36c203f1cac7b1ea8131b07a7839b79918ad3bae Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 10 Apr 2014 20:18:19 +0200 Subject: ARM: at91: prepare common clk transition for rm9200 Enclose the rm9200 old clk registration in "#if defined(CONFIG_OLD_CLK_AT91) #endif" Signed-off-by: Alexandre Belloni Acked-by: Boris BREZILLON Acked-by: Nicolas Ferre --- arch/arm/mach-at91/at91rm9200.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index 787bb50a4dff..038702ee8bc6 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c @@ -26,10 +26,11 @@ #include "at91_aic.h" #include "soc.h" #include "generic.h" -#include "clock.h" #include "sam9_smc.h" #include "pm.h" +#if defined(CONFIG_OLD_CLK_AT91) +#include "clock.h" /* -------------------------------------------------------------------- * Clocks * -------------------------------------------------------------------- */ @@ -277,6 +278,9 @@ static void __init at91rm9200_register_clocks(void) clk_register(&pck2); clk_register(&pck3); } +#else +#define at91rm9200_register_clocks NULL +#endif /* -------------------------------------------------------------------- * GPIO -- cgit v1.2.3 From 68580013adeb3f83a4d37a2620b7d6c72307d2a4 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Sat, 3 May 2014 00:46:36 +0200 Subject: ARM: at91/dt: rm9200: define clocks Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/at91rm9200.dtsi | 304 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 304 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index c61b16fba79b..65ccf564b9a5 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include / { model = "Atmel AT91RM9200 family SoC"; @@ -51,6 +52,20 @@ reg = <0x20000000 0x04000000>; }; + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; @@ -79,6 +94,260 @@ pmc: pmc@fffffc00 { compatible = "atmel,at91rm9200-pmc"; reg = <0xfffffc00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCS>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91rm9200-clk-main"; + #clock-cells = <0>; + clocks = <&main_osc>; + }; + + plla: pllack { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <1000000 32000000>; + #atmel,pll-clk-output-range-cells = <3>; + atmel,pll-clk-output-ranges = <80000000 160000000 0>, + <150000000 180000000 2>; + }; + + pllb: pllbck { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKB>; + clocks = <&main>; + reg = <1>; + atmel,clk-input-range = <1000000 32000000>; + #atmel,pll-clk-output-range-cells = <3>; + atmel,pll-clk-output-ranges = <80000000 160000000 0>, + <150000000 180000000 2>; + }; + + mck: masterck { + compatible = "atmel,at91rm9200-clk-master"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; + clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; + atmel,clk-output-range = <0 80000000>; + atmel,clk-divisors = <1 2 3 4>; + }; + + usb: usbck { + compatible = "atmel,at91rm9200-clk-usb"; + #clock-cells = <0>; + atmel,clk-divisors = <1 2>; + clocks = <&pllb>; + }; + + prog: progck { + compatible = "atmel,at91rm9200-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; + + prog0: prog0 { + #clock-cells = <0>; + reg = <0>; + interrupts = ; + }; + + prog1: prog1 { + #clock-cells = <0>; + reg = <1>; + interrupts = ; + }; + + prog2: prog2 { + #clock-cells = <0>; + reg = <2>; + interrupts = ; + }; + + prog3: prog3 { + #clock-cells = <0>; + reg = <3>; + interrupts = ; + }; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + udpck: udpck { + #clock-cells = <0>; + reg = <2>; + clocks = <&usb>; + }; + + uhpck: uhpck { + #clock-cells = <0>; + reg = <4>; + clocks = <&usb>; + }; + + pck0: pck0 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + + pck2: pck2 { + #clock-cells = <0>; + reg = <10>; + clocks = <&prog2>; + }; + + pck3: pck3 { + #clock-cells = <0>; + reg = <11>; + clocks = <&prog3>; + }; + }; + + periphck { + compatible = "atmel,at91rm9200-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + pioA_clk: pioA_clk { + #clock-cells = <0>; + reg = <2>; + }; + + pioB_clk: pioB_clk { + #clock-cells = <0>; + reg = <3>; + }; + + pioC_clk: pioC_clk { + #clock-cells = <0>; + reg = <4>; + }; + + pioD_clk: pioD_clk { + #clock-cells = <0>; + reg = <5>; + }; + + usart0_clk: usart0_clk { + #clock-cells = <0>; + reg = <6>; + }; + + usart1_clk: usart1_clk { + #clock-cells = <0>; + reg = <7>; + }; + + usart2_clk: usart2_clk { + #clock-cells = <0>; + reg = <8>; + }; + + usart3_clk: usart3_clk { + #clock-cells = <0>; + reg = <9>; + }; + + mci0_clk: mci0_clk { + #clock-cells = <0>; + reg = <10>; + }; + + udc_clk: udc_clk { + #clock-cells = <0>; + reg = <11>; + }; + + twi0_clk: twi0_clk { + reg = <12>; + #clock-cells = <0>; + }; + + spi0_clk: spi0_clk { + #clock-cells = <0>; + reg = <13>; + }; + + ssc0_clk: ssc0_clk { + #clock-cells = <0>; + reg = <14>; + }; + + ssc1_clk: ssc1_clk { + #clock-cells = <0>; + reg = <15>; + }; + + ssc2_clk: ssc2_clk { + #clock-cells = <0>; + reg = <16>; + }; + + tc0_clk: tc0_clk { + #clock-cells = <0>; + reg = <17>; + }; + + tc1_clk: tc1_clk { + #clock-cells = <0>; + reg = <18>; + }; + + tc2_clk: tc2_clk { + #clock-cells = <0>; + reg = <19>; + }; + + tc3_clk: tc3_clk { + #clock-cells = <0>; + reg = <20>; + }; + + tc4_clk: tc4_clk { + #clock-cells = <0>; + reg = <21>; + }; + + tc5_clk: tc5_clk { + #clock-cells = <0>; + reg = <22>; + }; + + ohci_clk: ohci_clk { + #clock-cells = <0>; + reg = <23>; + }; + + macb0_clk: macb0_clk { + #clock-cells = <0>; + reg = <24>; + }; + }; }; st: timer@fffffd00 { @@ -93,6 +362,8 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 18 IRQ_TYPE_LEVEL_HIGH 0 19 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; + clock-names = "t0_clk", "t1_clk", "t2_clk"; }; tcb1: timer@fffa4000 { @@ -101,6 +372,8 @@ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 21 IRQ_TYPE_LEVEL_HIGH 0 22 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>; + clock-names = "t0_clk", "t1_clk", "t2_clk"; }; i2c0: i2c@fffb8000 { @@ -109,6 +382,7 @@ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_twi>; + clocks = <&twi0_clk>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -118,6 +392,8 @@ compatible = "atmel,hsmci"; reg = <0xfffb4000 0x4000>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -130,6 +406,8 @@ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&ssc0_clk>; + clock-names = "pclk"; status = "disable"; }; @@ -139,6 +417,8 @@ interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + clocks = <&ssc1_clk>; + clock-names = "pclk"; status = "disable"; }; @@ -148,6 +428,8 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; + clocks = <&ssc2_clk>; + clock-names = "pclk"; status = "disable"; }; @@ -158,6 +440,8 @@ phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; + clocks = <&macb0_clk>; + clock-names = "ether_clk"; status = "disabled"; }; @@ -496,6 +780,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioA_clk>; }; pioB: gpio@fffff600 { @@ -506,6 +791,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioB_clk>; }; pioC: gpio@fffff800 { @@ -516,6 +802,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioC_clk>; }; pioD: gpio@fffffa00 { @@ -526,6 +813,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioD_clk>; }; }; @@ -535,6 +823,8 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&mck>; + clock-names = "usart"; status = "disabled"; }; @@ -546,6 +836,8 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; + clocks = <&usart0_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -557,6 +849,8 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + clocks = <&usart1_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -568,6 +862,8 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; + clocks = <&usart2_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -579,6 +875,8 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; + clocks = <&usart3_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -586,6 +884,8 @@ compatible = "atmel,at91rm9200-udc"; reg = <0xfffb0000 0x4000>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udc_clk>, <&udpck>; + clock-names = "pclk", "hclk"; status = "disabled"; }; @@ -597,6 +897,8 @@ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; status = "disabled"; }; }; @@ -622,6 +924,8 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00300000 0x100000>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>; + clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; }; -- cgit v1.2.3 From 93af052da51ed5fa5c74078a625e9ba11d95edd3 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 29 May 2014 20:44:44 +0200 Subject: ARM: at91: move at91rm9200 SoC to the CCF This patch removes the selection of AT91_USE_OLD_CLK when selecting at91rm9200 SoC support. This will automatically enable COMMON_CLK_AT91 option and add support for at91 common clk implementation. Signed-off-by: Alexandre Belloni Acked-by: Boris BREZILLON Acked-by: Nicolas Ferre --- arch/arm/mach-at91/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 45b55e0f0db6..c818136a74b8 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -113,7 +113,6 @@ config SOC_AT91RM9200 select HAVE_AT91_DBGU0 select MULTI_IRQ_HANDLER select SPARSE_IRQ - select AT91_USE_OLD_CLK select HAVE_AT91_USB_CLK config SOC_AT91SAM9260 -- cgit v1.2.3 From 94788118efc9546f1eb446bec325f17814cec884 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 18 Jun 2014 21:11:37 +0200 Subject: ARM: at91/dt: at91rm9200ek: define crystals frequencies Define at91rm9200ek main and slow crystals frequencies. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/at91rm9200ek.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index df6b0aa0e4dd..43eb779dd6f6 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts @@ -25,6 +25,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <18432000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; }; ahb { -- cgit v1.2.3 From 57b37ed5199bde590c8fc92bbe12e099163ad070 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 10 Apr 2014 20:18:47 +0200 Subject: ARM: at91: prepare common clk transition for sam9260 Enclose the sam9260 old clk registration in "#if defined(CONFIG_OLD_CLK_AT91) #endif" Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/mach-at91/at91sam9260.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index c3d22be73b7c..3477ba94c4c5 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -27,10 +27,11 @@ #include "at91_rstc.h" #include "soc.h" #include "generic.h" -#include "clock.h" #include "sam9_smc.h" #include "pm.h" +#if defined(CONFIG_OLD_CLK_AT91) +#include "clock.h" /* -------------------------------------------------------------------- * Clocks * -------------------------------------------------------------------- */ @@ -288,6 +289,9 @@ static void __init at91sam9260_register_clocks(void) clk_register(&pck0); clk_register(&pck1); } +#else +#define at91sam9260_register_clocks NULL +#endif /* -------------------------------------------------------------------- * GPIO -- cgit v1.2.3 From 684b8fb5a0bde16ae05a5dc790695b0907926666 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Fri, 18 Apr 2014 12:44:20 +0200 Subject: ARM: at91/dt: sam9260: define clocks Define the at91sam9260 clocks in the SoC dtsi file. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9260.dtsi | 314 ++++++++++++++++++++++++++++++++++++- 1 file changed, 313 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index c0e0eae16a27..cb100b03a362 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { model = "Atmel AT91SAM9260 family SoC"; @@ -48,6 +49,26 @@ reg = <0x20000000 0x04000000>; }; + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <5000000>; + }; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; @@ -74,8 +95,260 @@ }; pmc: pmc@fffffc00 { - compatible = "atmel,at91rm9200-pmc"; + compatible = "atmel,at91sam9260-pmc"; reg = <0xfffffc00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCS>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91rm9200-clk-main"; + #clock-cells = <0>; + clocks = <&main_osc>; + }; + + slow_rc_osc: slow_rc_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + }; + + clk32k: slck { + compatible = "atmel,at91sam9260-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc>, <&slow_xtal>; + }; + + plla: pllack { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <1000000 32000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <80000000 160000000 0 1>, + <150000000 240000000 2 1>; + }; + + pllb: pllbck { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKB>; + clocks = <&main>; + reg = <1>; + atmel,clk-input-range = <1000000 5000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; + }; + + mck: masterck { + compatible = "atmel,at91rm9200-clk-master"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; + clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; + atmel,clk-output-range = <0 105000000>; + atmel,clk-divisors = <1 2 4 0>; + }; + + usb: usbck { + compatible = "atmel,at91rm9200-clk-usb"; + #clock-cells = <0>; + atmel,clk-divisors = <1 2 4 0>; + clocks = <&pllb>; + }; + + prog: progck { + compatible = "atmel,at91rm9200-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; + + prog0: prog0 { + #clock-cells = <0>; + reg = <0>; + interrupts = ; + }; + + prog1: prog1 { + #clock-cells = <0>; + reg = <1>; + interrupts = ; + }; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + uhpck: uhpck { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck0 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + }; + + periphck { + compatible = "atmel,at91rm9200-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + pioA_clk: pioA_clk { + #clock-cells = <0>; + reg = <2>; + }; + + pioB_clk: pioB_clk { + #clock-cells = <0>; + reg = <3>; + }; + + pioC_clk: pioC_clk { + #clock-cells = <0>; + reg = <4>; + }; + + adc_clk: adc_clk { + #clock-cells = <0>; + reg = <5>; + }; + + usart0_clk: usart0_clk { + #clock-cells = <0>; + reg = <6>; + }; + + usart1_clk: usart1_clk { + #clock-cells = <0>; + reg = <7>; + }; + + usart2_clk: usart2_clk { + #clock-cells = <0>; + reg = <8>; + }; + + mci0_clk: mci0_clk { + #clock-cells = <0>; + reg = <9>; + }; + + udc_clk: udc_clk { + #clock-cells = <0>; + reg = <10>; + }; + + twi0_clk: twi0_clk { + reg = <11>; + #clock-cells = <0>; + }; + + spi0_clk: spi0_clk { + #clock-cells = <0>; + reg = <12>; + }; + + spi1_clk: spi1_clk { + #clock-cells = <0>; + reg = <13>; + }; + + ssc0_clk: ssc0_clk { + #clock-cells = <0>; + reg = <14>; + }; + + tc0_clk: tc0_clk { + #clock-cells = <0>; + reg = <17>; + }; + + tc1_clk: tc1_clk { + #clock-cells = <0>; + reg = <18>; + }; + + tc2_clk: tc2_clk { + #clock-cells = <0>; + reg = <19>; + }; + + ohci_clk: ohci_clk { + #clock-cells = <0>; + reg = <20>; + }; + + macb0_clk: macb0_clk { + #clock-cells = <0>; + reg = <21>; + }; + + isi_clk: isi_clk { + #clock-cells = <0>; + reg = <22>; + }; + + usart3_clk: usart3_clk { + #clock-cells = <0>; + reg = <23>; + }; + + uart0_clk: uart0_clk { + #clock-cells = <0>; + reg = <24>; + }; + + uart1_clk: uart1_clk { + #clock-cells = <0>; + reg = <25>; + }; + + tc3_clk: tc3_clk { + #clock-cells = <0>; + reg = <26>; + }; + + tc4_clk: tc4_clk { + #clock-cells = <0>; + reg = <27>; + }; + + tc5_clk: tc5_clk { + #clock-cells = <0>; + reg = <28>; + }; + }; }; rstc@fffffd00 { @@ -92,6 +365,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&mck>; }; tcb0: timer@fffa0000 { @@ -100,6 +374,8 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 18 IRQ_TYPE_LEVEL_HIGH 0 19 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; + clock-names = "t0_clk", "t1_clk", "t2_clk"; }; tcb1: timer@fffdc000 { @@ -108,6 +384,8 @@ interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 27 IRQ_TYPE_LEVEL_HIGH 0 28 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>; + clock-names = "t0_clk", "t1_clk", "t2_clk"; }; pinctrl@fffff400 { @@ -443,6 +721,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioA_clk>; }; pioB: gpio@fffff600 { @@ -453,6 +732,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioB_clk>; }; pioC: gpio@fffff800 { @@ -463,6 +743,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioC_clk>; }; }; @@ -472,6 +753,8 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&mck>; + clock-names = "usart"; status = "disabled"; }; @@ -483,6 +766,8 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; + clocks = <&usart0_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -494,6 +779,8 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; + clocks = <&usart1_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -505,6 +792,8 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; + clocks = <&usart2_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -516,6 +805,8 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; + clocks = <&usart3_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -527,6 +818,8 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart0_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -538,6 +831,8 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + clocks = <&uart1_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -547,6 +842,8 @@ interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; + clocks = <&macb0_clk>, <&macb0_clk>; + clock-names = "hclk", "pclk"; status = "disabled"; }; @@ -554,6 +851,8 @@ compatible = "atmel,at91rm9200-udc"; reg = <0xfffa4000 0x4000>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udc_clk>, <&udpck>; + clock-names = "pclk", "hclk"; status = "disabled"; }; @@ -563,6 +862,7 @@ interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; #address-cells = <1>; #size-cells = <0>; + clocks = <&twi0_clk>; status = "disabled"; }; @@ -573,6 +873,8 @@ #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; status = "disabled"; }; @@ -582,6 +884,8 @@ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&ssc0_clk>; + clock-names = "pclk"; status = "disabled"; }; @@ -593,6 +897,8 @@ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; status = "disabled"; }; @@ -604,6 +910,8 @@ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; status = "disabled"; }; @@ -613,6 +921,8 @@ compatible = "atmel,at91sam9260-adc"; reg = <0xfffe0000 0x100>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&adc_clk>, <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; atmel,adc-use-external-triggers; atmel,adc-channels-used = <0xf>; atmel,adc-vref = <3300>; @@ -680,6 +990,8 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>; + clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; }; -- cgit v1.2.3 From 09d773cea829db7dfa64dc7b07a14f40e86dfd64 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 16 Jun 2014 19:22:40 +0200 Subject: ARM: at91/dt: sam9g20: define clocks Define the at91sam9g20 clocks that differ from at91sam9260 in the SoC dtsi file. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9g20.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index b8e79466014f..31f7652612fc 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -25,6 +25,30 @@ adc0: adc@fffe0000 { atmel,adc-startup-time = <40>; }; + + pmc: pmc@fffffc00 { + plla: pllack { + atmel,clk-input-range = <2000000 32000000>; + atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, + <695000000 750000000 1 0>, + <645000000 700000000 2 0>, + <595000000 650000000 3 0>, + <545000000 600000000 0 1>, + <495000000 550000000 1 1>, + <445000000 500000000 2 1>, + <400000000 450000000 3 1>; + }; + + pllb: pllbck { + atmel,clk-input-range = <2000000 32000000>; + atmel,pll-clk-output-ranges = <30000000 100000000 0 0>; + }; + + mck: masterck { + atmel,clk-output-range = <0 133000000>; + atmel,clk-divisors = <1 2 4 6>; + }; + }; }; }; }; -- cgit v1.2.3 From 20183110a81d39aee9a2a80be7fb9b0035cb8b22 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 29 May 2014 20:42:30 +0200 Subject: ARM: at91: move at91sam9260 SoCs to the CCF This patch removes the selection of AT91_USE_OLD_CLK when selecting at91sam9260 SoCs support. This will automatically enable COMMON_CLK_AT91 option and add support for at91 common clk implementation. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/mach-at91/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index c818136a74b8..a2efe6e1e224 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -119,7 +119,6 @@ config SOC_AT91SAM9260 bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20" select HAVE_AT91_DBGU0 select SOC_AT91SAM9 - select AT91_USE_OLD_CLK select HAVE_AT91_USB_CLK help Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE -- cgit v1.2.3 From f48a8335343a8bdba3d1b0c3ae81a02bfc8123db Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 18 Jun 2014 21:10:25 +0200 Subject: ARM: at91/dt: at91sam9g20ek: define crystals frequencies Define at91sam9g20ek main and slow crystals frequencies. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index cb2c010e08e2..d2919108e92d 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -26,6 +26,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <18432000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; }; ahb { -- cgit v1.2.3 From 32cc703a23e717b70fd5c166e0058bb2962b2ef2 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 17 Jun 2014 11:12:11 +0200 Subject: ARM: at91/dt: foxg20: define crystals frequencies Define Acme Systems srl Fox G20 main and slow crystals frequencies. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/at91-foxg20.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts index cbe967343997..f89598af4c2b 100644 --- a/arch/arm/boot/dts/at91-foxg20.dts +++ b/arch/arm/boot/dts/at91-foxg20.dts @@ -31,6 +31,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <18432000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; }; ahb { -- cgit v1.2.3 From f1e78615189b56a291c01a0cc85de09fd05dd029 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 16 Jun 2014 20:12:19 +0200 Subject: ARM: at91/dt: usb_a9260: define crystals frequencies Define Calao USB-A9260, USB-A9G20 and USB-A9G20-LPW main and slow crystals frequencies. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/usb_a9260_common.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi index 285977682cf3..12edafefd44a 100644 --- a/arch/arm/boot/dts/usb_a9260_common.dtsi +++ b/arch/arm/boot/dts/usb_a9260_common.dtsi @@ -16,6 +16,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <12000000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; }; ahb { -- cgit v1.2.3 From 90de7ccc818dbc7635ff197298e6ab24da9dea1f Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 18 Jun 2014 21:01:51 +0200 Subject: ARM: at91/dt: tny_a9260: define crystals frequencies Define Calao TNY-A9260 and TNY-A9G20 main and slow crystals frequencies. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/tny_a9260_common.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi index 0e6d3de2e09e..ce7138c3af1b 100644 --- a/arch/arm/boot/dts/tny_a9260_common.dtsi +++ b/arch/arm/boot/dts/tny_a9260_common.dtsi @@ -24,6 +24,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <12000000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; }; ahb { -- cgit v1.2.3 From 322192640b1052635494cc5330c3215251a07a14 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 18 Jun 2014 21:12:26 +0200 Subject: ARM: at91/dt: qil_a9260: define crystals frequencies Define Calao QIL-A9260 main and slow crystals frequencies. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/at91-qil_a9260.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts index 5576ae8786c0..a9aef53ab764 100644 --- a/arch/arm/boot/dts/at91-qil_a9260.dts +++ b/arch/arm/boot/dts/at91-qil_a9260.dts @@ -28,6 +28,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <12000000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; }; ahb { -- cgit v1.2.3 From 80994f0a735a9618058a2bd560924260f5c02929 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 18 Jun 2014 21:03:19 +0200 Subject: ARM: at91/dt: mpa1600: define crytals frequencies Define Phontech MPA 1600 main and slow crystals frequencies. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/mpa1600.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts index ccf9ea242f72..f0f5e1098928 100644 --- a/arch/arm/boot/dts/mpa1600.dts +++ b/arch/arm/boot/dts/mpa1600.dts @@ -25,6 +25,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <18432000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; }; ahb { -- cgit v1.2.3 From cea5c34dfbe977e2f7134964b17f06ecac72d788 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 18 Jun 2014 21:07:22 +0200 Subject: ARM: at91/dt: ge863-pro3: define main crystal frequency Define Telit GE863-PRO3 main crystal frequency. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/ge863-pro3.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi index 230099bb31c8..0d0e62489d93 100644 --- a/arch/arm/boot/dts/ge863-pro3.dtsi +++ b/arch/arm/boot/dts/ge863-pro3.dtsi @@ -19,6 +19,10 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <6000000>; }; + + main_xtal { + clock-frequency = <6000000>; + }; }; ahb { -- cgit v1.2.3 From c544bc7a43f5161325aeeea442b931c7e4d71bcb Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 9 Jul 2014 15:22:15 +0200 Subject: ARM: at91/dt: aks-cdu: define slow crytal frequency Define AK signal CDU slow crystal frequency Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/aks-cdu.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts index 54cb5cf8604a..d9c50fbb49d2 100644 --- a/arch/arm/boot/dts/aks-cdu.dts +++ b/arch/arm/boot/dts/aks-cdu.dts @@ -16,6 +16,12 @@ bootargs = "console=ttyS0,115200 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs"; }; + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + }; + ahb { apb { usart0: serial@fffb0000 { -- cgit v1.2.3 From 2421d1c6d22fd6fbd1533f704f5813a76a46f2cd Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 9 Jul 2014 15:23:05 +0200 Subject: ARM: at91/dt: evk-pro3: define slow crytal frequency Define Telit EVK-PRO3 slow crystal frequency Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/evk-pro3.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts index 4d829685fdfb..f72969efe6d7 100644 --- a/arch/arm/boot/dts/evk-pro3.dts +++ b/arch/arm/boot/dts/evk-pro3.dts @@ -15,6 +15,12 @@ model = "Telit EVK-PRO3 for Telit GE863-PRO3"; compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9"; + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + }; + ahb { apb { macb0: ethernet@fffc4000 { -- cgit v1.2.3 From b77d635007f2553c1837d9b0fb56c5ac669c49b8 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 18 Jun 2014 21:09:19 +0200 Subject: ARM: at91/dt: ethernut5: define crystals frequencies Define egnite Ethernut 5 main and slow crystals frequencies. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/ethernut5.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts index 143b6d25bc80..8f941c2db7c6 100644 --- a/arch/arm/boot/dts/ethernut5.dts +++ b/arch/arm/boot/dts/ethernut5.dts @@ -20,6 +20,16 @@ reg = <0x20000000 0x08000000>; }; + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + ahb { apb { dbgu: serial@fffff200 { -- cgit v1.2.3 From 650defcf9689a0ec551f4eca0a090c27da47332c Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 18 Jun 2014 21:13:54 +0200 Subject: ARM: at91/dt: animeo_ip: define crystals frequencies Define Somfy Animeo IP main and slow crystals frequencies. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/animeo_ip.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts index 3c4f6d983cbd..4e0ad3b82796 100644 --- a/arch/arm/boot/dts/animeo_ip.dts +++ b/arch/arm/boot/dts/animeo_ip.dts @@ -40,6 +40,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <18432000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; }; ahb { -- cgit v1.2.3 From d738989f08d8fe4934bd46920d183802ebf1544e Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 18 Jun 2014 21:05:05 +0200 Subject: ARM: at91/dt: kizbox: define main crystal frequency Define kizbox board's main crystal frequency. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/kizbox.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts index 928f6eef2d59..e83e4f9310b8 100644 --- a/arch/arm/boot/dts/kizbox.dts +++ b/arch/arm/boot/dts/kizbox.dts @@ -30,6 +30,10 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <18432000>; }; + + main_xtal { + clock-frequency = <18432000>; + }; }; ahb { -- cgit v1.2.3 From 003b45e287faa6304f4d77a3c456e0c024563a51 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 10 Apr 2014 20:19:33 +0200 Subject: ARM: at91: prepare common clk transition for sam9g45 Enclose the sam9g45 old clk registration in "#if defined(CONFIG_OLD_CLK_AT91) #endif" Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/mach-at91/at91sam9g45.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 9d3d544ac19c..0d5d85797cd6 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -25,10 +25,11 @@ #include "at91_aic.h" #include "soc.h" #include "generic.h" -#include "clock.h" #include "sam9_smc.h" #include "pm.h" +#if defined(CONFIG_OLD_CLK_AT91) +#include "clock.h" /* -------------------------------------------------------------------- * Clocks * -------------------------------------------------------------------- */ @@ -331,6 +332,9 @@ static void __init at91sam9g45_register_clocks(void) clk_register(&pck0); clk_register(&pck1); } +#else +#define at91sam9g45_register_clocks NULL +#endif /* -------------------------------------------------------------------- * GPIO -- cgit v1.2.3 From 6f368c3089c1ec3827fd1f136b18161634479013 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 11 Jun 2014 22:39:06 +0200 Subject: ARM: at91/dt: sam9g45: define clocks Define the at91sam9g45 clocks in the SoC dtsi file. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9g45.dtsi | 342 ++++++++++++++++++++++++++++++++++++- 1 file changed, 341 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index ace6bf197b70..932a669156af 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include / { model = "Atmel AT91SAM9G45 family SoC"; @@ -53,6 +54,26 @@ reg = <0x70000000 0x10000000>; }; + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000>; + }; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; @@ -77,11 +98,279 @@ compatible = "atmel,at91sam9g45-ddramc"; reg = <0xffffe400 0x200 0xffffe600 0x200>; + clocks = <&ddrck>; + clock-names = "ddrck"; }; pmc: pmc@fffffc00 { - compatible = "atmel,at91rm9200-pmc"; + compatible = "atmel,at91sam9g45-pmc"; reg = <0xfffffc00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCS>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91rm9200-clk-main"; + #clock-cells = <0>; + clocks = <&main_osc>; + }; + + plla: pllack { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <2000000 32000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <745000000 800000000 0 0 + 695000000 750000000 1 0 + 645000000 700000000 2 0 + 595000000 650000000 3 0 + 545000000 600000000 0 1 + 495000000 555000000 1 1 + 445000000 500000000 2 1 + 400000000 450000000 3 1>; + }; + + plladiv: plladivck { + compatible = "atmel,at91sam9x5-clk-plldiv"; + #clock-cells = <0>; + clocks = <&plla>; + }; + + utmi: utmick { + compatible = "atmel,at91sam9x5-clk-utmi"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKU>; + clocks = <&main>; + }; + + mck: masterck { + compatible = "atmel,at91rm9200-clk-master"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; + clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>; + atmel,clk-output-range = <0 133333333>; + atmel,clk-divisors = <1 2 4 3>; + }; + + usb: usbck { + compatible = "atmel,at91sam9x5-clk-usb"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + prog: progck { + compatible = "atmel,at91sam9g45-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>, <&mck>; + + prog0: prog0 { + #clock-cells = <0>; + reg = <0>; + interrupts = ; + }; + + prog1: prog1 { + #clock-cells = <0>; + reg = <1>; + interrupts = ; + }; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + ddrck: ddrck { + #clock-cells = <0>; + reg = <2>; + clocks = <&mck>; + }; + + uhpck: uhpck { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + pck0: pck0 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + }; + + periphck { + compatible = "atmel,at91rm9200-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + pioA_clk: pioA_clk { + #clock-cells = <0>; + reg = <2>; + }; + + pioB_clk: pioB_clk { + #clock-cells = <0>; + reg = <3>; + }; + + pioC_clk: pioC_clk { + #clock-cells = <0>; + reg = <4>; + }; + + pioDE_clk: pioDE_clk { + #clock-cells = <0>; + reg = <5>; + }; + + trng_clk: trng_clk { + #clock-cells = <0>; + reg = <6>; + }; + + usart0_clk: usart0_clk { + #clock-cells = <0>; + reg = <7>; + }; + + usart1_clk: usart1_clk { + #clock-cells = <0>; + reg = <8>; + }; + + usart2_clk: usart2_clk { + #clock-cells = <0>; + reg = <9>; + }; + + usart3_clk: usart3_clk { + #clock-cells = <0>; + reg = <10>; + }; + + mci0_clk: mci0_clk { + #clock-cells = <0>; + reg = <11>; + }; + + twi0_clk: twi0_clk { + #clock-cells = <0>; + reg = <12>; + }; + + twi1_clk: twi1_clk { + #clock-cells = <0>; + reg = <13>; + }; + + spi0_clk: spi0_clk { + #clock-cells = <0>; + reg = <14>; + }; + + spi1_clk: spi1_clk { + #clock-cells = <0>; + reg = <15>; + }; + + ssc0_clk: ssc0_clk { + #clock-cells = <0>; + reg = <16>; + }; + + ssc1_clk: ssc1_clk { + #clock-cells = <0>; + reg = <17>; + }; + + tcb0_clk: tcb0_clk { + #clock-cells = <0>; + reg = <18>; + }; + + pwm_clk: pwm_clk { + #clock-cells = <0>; + reg = <19>; + }; + + adc_clk: adc_clk { + #clock-cells = <0>; + reg = <20>; + }; + + dma0_clk: dma0_clk { + #clock-cells = <0>; + reg = <21>; + }; + + uhphs_clk: uhphs_clk { + #clock-cells = <0>; + reg = <22>; + }; + + lcd_clk: lcd_clk { + #clock-cells = <0>; + reg = <23>; + }; + + ac97_clk: ac97_clk { + #clock-cells = <0>; + reg = <24>; + }; + + macb0_clk: macb0_clk { + #clock-cells = <0>; + reg = <25>; + }; + + isi_clk: isi_clk { + #clock-cells = <0>; + reg = <26>; + }; + + udphs_clk: udphs_clk { + #clock-cells = <0>; + reg = <27>; + }; + + aestdessha_clk: aestdessha_clk { + #clock-cells = <0>; + reg = <28>; + }; + + mci1_clk: mci1_clk { + #clock-cells = <0>; + reg = <29>; + }; + + vdec_clk: vdec_clk { + #clock-cells = <0>; + reg = <30>; + }; + }; }; rstc@fffffd00 { @@ -93,6 +382,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&mck>; }; @@ -105,12 +395,16 @@ compatible = "atmel,at91rm9200-tcb"; reg = <0xfff7c000 0x100>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>; + clock-names = "t0_clk", "t1_clk", "t2_clk"; }; tcb1: timer@fffd4000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfffd4000 0x100>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>; + clock-names = "t0_clk", "t1_clk", "t2_clk"; }; dma: dma-controller@ffffec00 { @@ -118,6 +412,8 @@ reg = <0xffffec00 0x200>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; + clocks = <&dma0_clk>; + clock-names = "dma_clk"; }; pinctrl@fffff200 { @@ -516,6 +812,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioA_clk>; }; pioB: gpio@fffff400 { @@ -526,6 +823,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioB_clk>; }; pioC: gpio@fffff600 { @@ -536,6 +834,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioC_clk>; }; pioD: gpio@fffff800 { @@ -546,6 +845,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioDE_clk>; }; pioE: gpio@fffffa00 { @@ -556,6 +856,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioDE_clk>; }; }; @@ -565,6 +866,8 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&mck>; + clock-names = "usart"; status = "disabled"; }; @@ -576,6 +879,8 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; + clocks = <&usart0_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -587,6 +892,8 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; + clocks = <&usart1_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -598,6 +905,8 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; + clocks = <&usart2_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -609,6 +918,8 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; + clocks = <&usart3_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -618,6 +929,8 @@ interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; + clocks = <&macb0_clk>, <&macb0_clk>; + clock-names = "hclk", "pclk"; status = "disabled"; }; @@ -629,6 +942,7 @@ pinctrl-0 = <&pinctrl_i2c0>; #address-cells = <1>; #size-cells = <0>; + clocks = <&twi0_clk>; status = "disabled"; }; @@ -640,6 +954,7 @@ pinctrl-0 = <&pinctrl_i2c1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&twi1_clk>; status = "disabled"; }; @@ -649,6 +964,8 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&ssc0_clk>; + clock-names = "pclk"; status = "disabled"; }; @@ -658,6 +975,8 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + clocks = <&ssc1_clk>; + clock-names = "pclk"; status = "disabled"; }; @@ -667,6 +986,8 @@ compatible = "atmel,at91sam9g45-adc"; reg = <0xfffb0000 0x100>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&adc_clk>, <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; atmel,adc-channels-used = <0xff>; atmel,adc-vref = <3300>; atmel,adc-startup-time = <40>; @@ -706,6 +1027,7 @@ reg = <0xfffb8000 0x300>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; #pwm-cells = <3>; + clocks = <&pwm_clk>; status = "disabled"; }; @@ -718,6 +1040,8 @@ dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; status = "disabled"; }; @@ -730,6 +1054,8 @@ dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; + clocks = <&mci1_clk>; + clock-names = "mci_clk"; status = "disabled"; }; @@ -752,6 +1078,8 @@ interrupts = <14 4 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; status = "disabled"; }; @@ -763,6 +1091,8 @@ interrupts = <15 4 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; status = "disabled"; }; @@ -773,6 +1103,8 @@ reg = <0x00600000 0x80000 0xfff78000 0x400>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&udphs_clk>, <&utmi>; + clock-names = "pclk", "hclk"; status = "disabled"; ep0 { @@ -835,6 +1167,8 @@ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fb>; + clocks = <&lcd_clk>, <&lcd_clk>; + clock-names = "hclk", "lcdc_clk"; status = "disabled"; }; @@ -861,6 +1195,9 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + //TODO + clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -868,6 +1205,9 @@ compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00800000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + //TODO + clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck"; status = "disabled"; }; }; -- cgit v1.2.3 From 5c5a57a45e7d475575544892d45004d13930b6c8 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 11 Jun 2014 22:35:59 +0200 Subject: ARM: at91: move at91sam9g45 SoC to the CCF This patch removes the selection of AT91_USE_OLD_CLK when selecting at91sam9g45 SoC support. This will automatically enable COMMON_CLK_AT91 option and add support for at91 common clock implementation. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/mach-at91/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index a2efe6e1e224..461966d0ee4d 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -153,7 +153,6 @@ config SOC_AT91SAM9G45 select HAVE_AT91_DBGU1 select HAVE_FB_ATMEL select SOC_AT91SAM9 - select AT91_USE_OLD_CLK select HAVE_AT91_UTMI select HAVE_AT91_USB_CLK help -- cgit v1.2.3 From 4c67a1319b79bc758425fea458f697ae528348d8 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Fri, 13 Jun 2014 20:01:51 +0200 Subject: ARM: at91/dt: sam9m10g45ek: define crystals frequencies Define at91sam9m10g45ek main and slow crystals frequencies. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9m10g45ek.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 9f5b0a674995..96ccc7de4f0a 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -31,6 +31,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <12000000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; }; ahb { -- cgit v1.2.3 From 57314956cc4530ff85b0b966a465ababce06c164 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Sat, 14 Jun 2014 02:13:16 +0200 Subject: ARM: at91/dt: pm9g45: crystals frequencies Define Ronetix pm9g45 main and slow crystals frequencies. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/pm9g45.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts index 33ffabe9c4c8..66afcff67fde 100644 --- a/arch/arm/boot/dts/pm9g45.dts +++ b/arch/arm/boot/dts/pm9g45.dts @@ -29,6 +29,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <12000000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; }; ahb { -- cgit v1.2.3 From a0747caccd05740601552ae58942192d8866163f Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Sat, 14 Jun 2014 02:14:32 +0200 Subject: ARM: at91/dt: cosino define crystals frequencies Define Cosino boards main and slow crystals frequencies. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/at91-cosino.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi index df4b78695695..b6ea3f4a7206 100644 --- a/arch/arm/boot/dts/at91-cosino.dtsi +++ b/arch/arm/boot/dts/at91-cosino.dtsi @@ -34,6 +34,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <12000000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; }; ahb { -- cgit v1.2.3 From b81ccb3293c0914dbaf331705ff9323e614939c6 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 10 Apr 2014 20:19:05 +0200 Subject: ARM: at91: prepare common clk transition for sam9263 Enclose the sam9263 old clk registration in "#if defined(CONFIG_OLD_CLK_AT91) #endif" Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/mach-at91/at91sam9263.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index f30290572293..c07465361947 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -25,10 +25,11 @@ #include "at91_rstc.h" #include "soc.h" #include "generic.h" -#include "clock.h" #include "sam9_smc.h" #include "pm.h" +#if defined(CONFIG_OLD_CLK_AT91) +#include "clock.h" /* -------------------------------------------------------------------- * Clocks * -------------------------------------------------------------------- */ @@ -280,6 +281,9 @@ static void __init at91sam9263_register_clocks(void) clk_register(&pck2); clk_register(&pck3); } +#else +#define at91sam9263_register_clocks NULL +#endif /* -------------------------------------------------------------------- * GPIO -- cgit v1.2.3 From c2375821c9925637eddb2082ad597971efd9d7a4 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 23 Jun 2014 06:03:37 +0200 Subject: ARM: at91/dt: sam9263: define clocks Define the at91sam9263 clocks in the SoC dtsi file. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9263.dtsi | 311 +++++++++++++++++++++++++++++++++++++ 1 file changed, 311 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index fece8665fb63..bb23c2d33cf8 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { model = "Atmel AT91SAM9263 family SoC"; @@ -32,6 +33,7 @@ ssc1 = &ssc1; pwm0 = &pwm0; }; + cpus { #address-cells = <0>; #size-cells = <0>; @@ -46,6 +48,20 @@ reg = <0x20000000 0x08000000>; }; + clocks { + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; @@ -69,6 +85,264 @@ pmc: pmc@fffffc00 { compatible = "atmel,at91rm9200-pmc"; reg = <0xfffffc00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCS>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91rm9200-clk-main"; + #clock-cells = <0>; + clocks = <&main_osc>; + }; + + plla: pllack { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <1000000 32000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, + <190000000 240000000 2 1>; + }; + + pllb: pllbck { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKB>; + clocks = <&main>; + reg = <1>; + atmel,clk-input-range = <1000000 5000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; + }; + + mck: masterck { + compatible = "atmel,at91rm9200-clk-master"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; + clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; + atmel,clk-output-range = <0 120000000>; + atmel,clk-divisors = <1 2 4 0>; + }; + + usb: usbck { + compatible = "atmel,at91rm9200-clk-usb"; + #clock-cells = <0>; + atmel,clk-divisors = <1 2 4 0>; + clocks = <&pllb>; + }; + + prog: progck { + compatible = "atmel,at91rm9200-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; + + prog0: prog0 { + #clock-cells = <0>; + reg = <0>; + interrupts = ; + }; + + prog1: prog1 { + #clock-cells = <0>; + reg = <1>; + interrupts = ; + }; + + prog2: prog2 { + #clock-cells = <0>; + reg = <2>; + interrupts = ; + }; + + prog3: prog3 { + #clock-cells = <0>; + reg = <3>; + interrupts = ; + }; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + uhpck: uhpck { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck0 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + + pck2: pck2 { + #clock-cells = <0>; + reg = <10>; + clocks = <&prog2>; + }; + + pck3: pck3 { + #clock-cells = <0>; + reg = <11>; + clocks = <&prog3>; + }; + }; + + periphck { + compatible = "atmel,at91rm9200-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + pioA_clk: pioA_clk { + #clock-cells = <0>; + reg = <2>; + }; + + pioB_clk: pioB_clk { + #clock-cells = <0>; + reg = <3>; + }; + + pioCDE_clk: pioCDE_clk { + #clock-cells = <0>; + reg = <4>; + }; + + usart0_clk: usart0_clk { + #clock-cells = <0>; + reg = <7>; + }; + + usart1_clk: usart1_clk { + #clock-cells = <0>; + reg = <8>; + }; + + usart2_clk: usart2_clk { + #clock-cells = <0>; + reg = <9>; + }; + + mci0_clk: mci0_clk { + #clock-cells = <0>; + reg = <10>; + }; + + mci1_clk: mci1_clk { + #clock-cells = <0>; + reg = <11>; + }; + + can_clk: can_clk { + #clock-cells = <0>; + reg = <12>; + }; + + twi0_clk: twi0_clk { + #clock-cells = <0>; + reg = <13>; + }; + + spi0_clk: spi0_clk { + #clock-cells = <0>; + reg = <14>; + }; + + spi1_clk: spi1_clk { + #clock-cells = <0>; + reg = <15>; + }; + + ssc0_clk: ssc0_clk { + #clock-cells = <0>; + reg = <16>; + }; + + ssc1_clk: ssc1_clk { + #clock-cells = <0>; + reg = <17>; + }; + + ac91_clk: ac97_clk { + #clock-cells = <0>; + reg = <18>; + }; + + tcb_clk: tcb_clk { + #clock-cells = <0>; + reg = <19>; + }; + + pwm_clk: pwm_clk { + #clock-cells = <0>; + reg = <20>; + }; + + macb0_clk: macb0_clk { + #clock-cells = <0>; + reg = <21>; + }; + + g2de_clk: g2de_clk { + #clock-cells = <0>; + reg = <23>; + }; + + udc_clk: udc_clk { + #clock-cells = <0>; + reg = <24>; + }; + + isi_clk: isi_clk { + #clock-cells = <0>; + reg = <25>; + }; + + lcd_clk: lcd_clk { + #clock-cells = <0>; + reg = <26>; + }; + + dma_clk: dma_clk { + #clock-cells = <0>; + reg = <27>; + }; + + ohci_clk: ohci_clk { + #clock-cells = <0>; + reg = <29>; + }; + }; }; ramc: ramc@ffffe200 { @@ -81,12 +355,15 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&mck>; }; tcb0: timer@fff7c000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfff7c000 0x100>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb_clk>; + clock-names = "t0_clk"; }; rstc@fffffd00 { @@ -403,6 +680,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioA_clk>; }; pioB: gpio@fffff400 { @@ -413,6 +691,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioB_clk>; }; pioC: gpio@fffff600 { @@ -423,6 +702,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioCDE_clk>; }; pioD: gpio@fffff800 { @@ -433,6 +713,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioCDE_clk>; }; pioE: gpio@fffffa00 { @@ -443,6 +724,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioCDE_clk>; }; }; @@ -452,6 +734,8 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&mck>; + clock-names = "usart"; status = "disabled"; }; @@ -463,6 +747,8 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; + clocks = <&usart0_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -474,6 +760,8 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; + clocks = <&usart1_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -485,6 +773,8 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; + clocks = <&usart2_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -494,6 +784,8 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&ssc0_clk>; + clock-names = "pclk"; status = "disabled"; }; @@ -503,6 +795,8 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + clocks = <&ssc1_clk>; + clock-names = "pclk"; status = "disabled"; }; @@ -512,6 +806,8 @@ interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; + clocks = <&macb0_clk>, <&macb0_clk>; + clock-names = "hclk", "pclk"; status = "disabled"; }; @@ -519,6 +815,8 @@ compatible = "atmel,at91rm9200-udc"; reg = <0xfff78000 0x4000>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udc_clk>, <&udpck>; + clock-names = "pclk", "hclk"; status = "disabled"; }; @@ -528,6 +826,7 @@ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; #address-cells = <1>; #size-cells = <0>; + clocks = <&twi0_clk>; status = "disabled"; }; @@ -537,6 +836,8 @@ interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; status = "disabled"; }; @@ -546,6 +847,8 @@ interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; + clocks = <&mci1_clk>; + clock-names = "mci_clk"; status = "disabled"; }; @@ -568,6 +871,8 @@ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; status = "disabled"; }; @@ -579,6 +884,8 @@ interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; status = "disabled"; }; @@ -587,6 +894,8 @@ reg = <0xfffb8000 0x300>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>; #pwm-cells = <3>; + clocks = <&pwm_clk>; + clock-names = "pwm_clk"; status = "disabled"; }; }; @@ -622,6 +931,8 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00a00000 0x100000>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>; + clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; }; -- cgit v1.2.3 From c2bddbd6f48cf660d5783af5883c7402ba33fef4 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 24 Jun 2014 08:09:44 +0200 Subject: ARM: at91: move at91sam9263 SoC to the CCF This patch removes the selection of AT91_USE_OLD_CLK when selecting at91sam9263 SoC support. This will automatically enable COMMON_CLK_AT91 option and add support for at91 common clock implementation. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/mach-at91/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 461966d0ee4d..6cc6f7aebdae 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -138,7 +138,6 @@ config SOC_AT91SAM9263 select HAVE_AT91_DBGU1 select HAVE_FB_ATMEL select SOC_AT91SAM9 - select AT91_USE_OLD_CLK select HAVE_AT91_USB_CLK config SOC_AT91SAM9RL -- cgit v1.2.3 From c8b41e005ffd02b16e9588d5a72a6a641bfb5e0f Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 24 Jun 2014 08:21:46 +0200 Subject: ARM: at91/dt: sam9263ek: define crystals frequencies Define at91sam9263ek main and slow crystals frequencies. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9263ek.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index 15009c9f2293..5cf93eecd8f1 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts @@ -29,6 +29,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <16367660>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <16367660>; + }; }; ahb { -- cgit v1.2.3 From edc4a8349d8dc2912f9b9b8e7f1abe69e209f3a6 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 24 Jun 2014 08:22:51 +0200 Subject: ARM: at91/dt: tny_a9263: define crystals frequencies Define Calao TNY-A9263 main and slow crystals frequencies. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/tny_a9263.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts index 0751a6a979a8..3043296345b7 100644 --- a/arch/arm/boot/dts/tny_a9263.dts +++ b/arch/arm/boot/dts/tny_a9263.dts @@ -29,6 +29,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <12000000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; }; ahb { -- cgit v1.2.3 From 447025e96d54e32a4e60050cc430705d4e532917 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 24 Jun 2014 08:23:42 +0200 Subject: ARM: at91/dt: usb_a9263: define crystals frequencies Define Calao USB-A9263 main and slow crystals frequencies. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- arch/arm/boot/dts/usb_a9263.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts index 290e60383baf..68c0de36c339 100644 --- a/arch/arm/boot/dts/usb_a9263.dts +++ b/arch/arm/boot/dts/usb_a9263.dts @@ -29,6 +29,14 @@ compatible = "atmel,osc", "fixed-clock"; clock-frequency = <12000000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; }; ahb { -- cgit v1.2.3 From 5179ffd099446e65a1e094b9cb17cc7edab45583 Mon Sep 17 00:00:00 2001 From: Khiem Nguyen Date: Fri, 4 Jul 2014 09:19:51 +0900 Subject: ARM: shmobile: Lager: Correct I2C bus for VDD MPU regulator I2C bus for VDD MPU regulator is IIC3, not I2C3. Signed-off-by: Khiem Nguyen Reviewed-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 544202bab9fa..ffe0523ff16f 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -215,9 +215,9 @@ renesas,function = "i2c2"; }; - i2c3_pins: i2c3 { - renesas,groups = "i2c3"; - renesas,function = "i2c3"; + iic3_pins: iic3 { + renesas,groups = "iic3"; + renesas,function = "iic3"; }; usb0_pins: usb0 { @@ -368,9 +368,9 @@ pinctrl-names = "default"; }; -&i2c3 { +&iic3 { pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; + pinctrl-0 = <&iic3_pins>; status = "okay"; vdd_dvfs: regulator@68 { -- cgit v1.2.3 From cb9a2b12e0cb524022c9a81d8ed29f2453ec240d Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 10 Jul 2014 12:50:56 +0200 Subject: ARM: shmobile: r8a7790: lager: use iic cores instead of i2c On Lager board, i2c and iic cores can be interchanged since they can be muxed to the same wires. Commit e489c2a9bc82713167d9f721ca764f4b0d37e543 ("ARM: shmobile: lager: enable i2c devices") activated the i2c cores, yet the iic cores should be default since they have the more interesting features for generic use cases, i.e. SMBUS_QUICK and DMA (yet to be supported). Reported-by: Khiem Nguyen Signed-off-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index ffe0523ff16f..856b4236b674 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -205,14 +205,14 @@ renesas,function = "msiof1"; }; - i2c1_pins: i2c1 { - renesas,groups = "i2c1"; - renesas,function = "i2c1"; + iic1_pins: iic1 { + renesas,groups = "iic1"; + renesas,function = "iic1"; }; - i2c2_pins: i2c2 { - renesas,groups = "i2c2"; - renesas,function = "i2c2"; + iic2_pins: iic2 { + renesas,groups = "iic2"; + renesas,function = "iic2"; }; iic3_pins: iic3 { @@ -352,19 +352,19 @@ cpu0-supply = <&vdd_dvfs>; }; -&i2c0 { +&iic0 { status = "ok"; }; -&i2c1 { +&iic1 { status = "ok"; - pinctrl-0 = <&i2c1_pins>; + pinctrl-0 = <&iic1_pins>; pinctrl-names = "default"; }; -&i2c2 { +&iic2 { status = "ok"; - pinctrl-0 = <&i2c2_pins>; + pinctrl-0 = <&iic2_pins>; pinctrl-names = "default"; }; -- cgit v1.2.3 From 9930dc8ee1f59271a54ed4b4922c9c944625a8d6 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 7 Jul 2014 09:54:27 +0200 Subject: ARM: shmobile: r8a7778: Add SCIF nodes This describes all of the SCIF hardware of the r8a7778. Each node is disabled and may be enabled as necessary by board DTS files. Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 3af0a2187493..ecfdf4b01b5a 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -156,6 +156,48 @@ status = "disabled"; }; + scif0: serial@ffe40000 { + compatible = "renesas,scif-r8a7778", "renesas,scif"; + reg = <0xffe40000 0x100>; + interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scif1: serial@ffe41000 { + compatible = "renesas,scif-r8a7778", "renesas,scif"; + reg = <0xffe41000 0x100>; + interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scif2: serial@ffe42000 { + compatible = "renesas,scif-r8a7778", "renesas,scif"; + reg = <0xffe42000 0x100>; + interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scif3: serial@ffe43000 { + compatible = "renesas,scif-r8a7778", "renesas,scif"; + reg = <0xffe43000 0x100>; + interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scif4: serial@ffe44000 { + compatible = "renesas,scif-r8a7778", "renesas,scif"; + reg = <0xffe44000 0x100>; + interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scif5: serial@ffe45000 { + compatible = "renesas,scif-r8a7778", "renesas,scif"; + reg = <0xffe45000 0x100>; + interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + mmcif: mmc@ffe4e000 { compatible = "renesas,sh-mmcif"; reg = <0xffe4e000 0x100>; -- cgit v1.2.3 From 5be97ca4a4f6e11c4a839ec3c08dea25589dfeb4 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 7 Jul 2014 09:54:28 +0200 Subject: ARM: shmobile: bockw-reference: Initialise SCIF device using DT Initialise SCIF device using DT when booting bockw using DT reference. Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778-bockw-reference.dts | 14 +++++++++++--- arch/arm/mach-shmobile/setup-r8a7778.c | 12 ++++++------ 2 files changed, 17 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index f76f6ec01e19..3342c74c5de8 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -23,6 +23,10 @@ model = "bockw"; compatible = "renesas,bockw-reference", "renesas,r8a7778"; + aliases { + serial0 = &scif0; + }; + chosen { bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; }; @@ -70,9 +74,6 @@ }; &pfc { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - scif0_pins: serial0 { renesas,groups = "scif0_data_a", "scif0_ctrl"; renesas,function = "scif0"; @@ -124,3 +125,10 @@ }; }; }; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index d311ef903b39..3d5a5ae619bf 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -292,12 +292,6 @@ void __init r8a7778_add_dt_devices(void) } #endif - r8a7778_register_scif(0); - r8a7778_register_scif(1); - r8a7778_register_scif(2); - r8a7778_register_scif(3); - r8a7778_register_scif(4); - r8a7778_register_scif(5); r8a7778_register_tmu(0); } @@ -506,6 +500,12 @@ static void __init r8a7778_register_hpb_dmae(void) void __init r8a7778_add_standard_devices(void) { r8a7778_add_dt_devices(); + r8a7778_register_scif(0); + r8a7778_register_scif(1); + r8a7778_register_scif(2); + r8a7778_register_scif(3); + r8a7778_register_scif(4); + r8a7778_register_scif(5); r8a7778_register_i2c(0); r8a7778_register_i2c(1); r8a7778_register_i2c(2); -- cgit v1.2.3 From 94f1a03db6988c64601dc84eaf6c8ef1b956d9e7 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 7 Jul 2014 09:54:33 +0200 Subject: ARM: shmobile: r8a73a4: Add SCIF nodes This describes all of the SCIF hardware of the r8a73a4. Each node is disabled and may be enabled as necessary by board DTS files. Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 82c5ac825386..d8ec5058c351 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -252,6 +252,48 @@ status = "disabled"; }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x100>; + interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x100>; + interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifb2: serial@e6c20000 { + compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifb3: serial@e6c30000 { + compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifb4: serial@e6ce0000 { + compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifb5: serial@e6cf0000 { + compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; + reg = <0 0xe6cf0000 0 0x100>; + interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + mmcif0: mmc@ee200000 { compatible = "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; -- cgit v1.2.3 From 27bc82353a3f214a383d7f3b1ccaefdb70d6c94f Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 7 Jul 2014 09:54:34 +0200 Subject: ARM: shmobile: ape6evm-reference: Initialise SCIF device using DT Initialise SCIF device using DT when booting ape6evm using DT reference. Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 14 +++++++++++--- arch/arm/mach-shmobile/setup-r8a73a4.c | 12 ++++++------ 2 files changed, 17 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts index 70b1fff8f4a3..a860f32bca27 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts @@ -16,6 +16,10 @@ model = "APE6EVM"; compatible = "renesas,ape6evm-reference", "renesas,r8a73a4"; + aliases { + serial0 = &scifa0; + }; + chosen { bootargs = "console=ttySC0,115200 ignore_loglevel rw"; }; @@ -90,9 +94,6 @@ }; &pfc { - pinctrl-0 = <&scifa0_pins>; - pinctrl-names = "default"; - scifa0_pins: serial0 { renesas,groups = "scifa0_data"; renesas,function = "scifa0"; @@ -123,6 +124,13 @@ status = "okay"; }; +&scifa0 { + pinctrl-0 = <&scifa0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + &sdhi0 { vmmc-supply = <&vcc_sdhi0>; bus-width = <4>; diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index 9333770cfac2..e84b6a5e4b19 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -187,12 +187,6 @@ static struct resource cmt1_resources[] = { void __init r8a73a4_add_dt_devices(void) { - r8a73a4_register_scif(0); - r8a73a4_register_scif(1); - r8a73a4_register_scif(2); - r8a73a4_register_scif(3); - r8a73a4_register_scif(4); - r8a73a4_register_scif(5); r8a7790_register_cmt(1); } @@ -287,6 +281,12 @@ static struct resource dma_resources[] = { void __init r8a73a4_add_standard_devices(void) { r8a73a4_add_dt_devices(); + r8a73a4_register_scif(0); + r8a73a4_register_scif(1); + r8a73a4_register_scif(2); + r8a73a4_register_scif(3); + r8a73a4_register_scif(4); + r8a73a4_register_scif(5); r8a73a4_register_irqc(0); r8a73a4_register_irqc(1); r8a73a4_register_thermal(); -- cgit v1.2.3 From fa12355b24a430729f34c349473b9c0a3d125679 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 7 Jul 2014 09:54:41 +0200 Subject: ARM: shmobile: r8a7740: Add SCIF nodes This describes all of the SCIF hardware of the r8a7740. Each node is disabled and may be enabled as necessary by board DTS files. Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7740.dtsi | 63 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 55d29f4d2ed6..bda18fb3d9e5 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -156,6 +156,69 @@ status = "disabled"; }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7740", "renesas,scifa"; + reg = <0xe6c40000 0x100>; + interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7740", "renesas,scifa"; + reg = <0xe6c50000 0x100>; + interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7740", "renesas,scifa"; + reg = <0xe6c60000 0x100>; + interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7740", "renesas,scifa"; + reg = <0xe6c70000 0x100>; + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifa4: serial@e6c80000 { + compatible = "renesas,scifa-r8a7740", "renesas,scifa"; + reg = <0xe6c80000 0x100>; + interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifa5: serial@e6cb0000 { + compatible = "renesas,scifa-r8a7740", "renesas,scifa"; + reg = <0xe6cb0000 0x100>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifa6: serial@e6cc0000 { + compatible = "renesas,scifa-r8a7740", "renesas,scifa"; + reg = <0xe6cc0000 0x100>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifa7: serial@e6cd0000 { + compatible = "renesas,scifa-r8a7740", "renesas,scifa"; + reg = <0xe6cd0000 0x100>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifb8: serial@e6c30000 { + compatible = "renesas,scifb-r8a7740", "renesas,scifb"; + reg = <0xe6c30000 0x100>; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + pfc: pfc@e6050000 { compatible = "renesas,pfc-r8a7740"; reg = <0xe6050000 0x8000>, -- cgit v1.2.3 From c4fac6f2f92331fa5788811357f8b8c3352e5ad8 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 7 Jul 2014 09:54:42 +0200 Subject: ARM: shmobile: armadillo800eva-reference: Initialise SCIF device using DT Initialise SCIF device using DT when booting armadillo800eva using DT reference. Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 14 +++++++++++--- arch/arm/mach-shmobile/setup-r8a7740.c | 8 ++++---- 2 files changed, 15 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index ba2e1806b3ad..ee9e7d5c97a9 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -19,6 +19,10 @@ model = "armadillo 800 eva reference"; compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740"; + aliases { + serial1 = &scifa1; + }; + chosen { bootargs = "console=tty0 console=ttySC1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; }; @@ -202,9 +206,6 @@ }; &pfc { - pinctrl-0 = <&scifa1_pins>; - pinctrl-names = "default"; - ether_pins: ether { renesas,groups = "gether_mii", "gether_int"; renesas,function = "gether"; @@ -256,6 +257,13 @@ status = "okay"; }; +&scifa1 { + pinctrl-0 = <&scifa1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + &sdhi0 { pinctrl-0 = <&sdhi0_pins>; pinctrl-names = "default"; diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index 35dec233301e..d0f51f1f697d 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@ -310,6 +310,10 @@ static struct platform_device ipmmu_device = { }; static struct platform_device *r8a7740_devices_dt[] __initdata = { + &cmt1_device, +}; + +static struct platform_device *r8a7740_early_devices[] __initdata = { &scif0_device, &scif1_device, &scif2_device, @@ -319,10 +323,6 @@ static struct platform_device *r8a7740_devices_dt[] __initdata = { &scif6_device, &scif7_device, &scif8_device, - &cmt1_device, -}; - -static struct platform_device *r8a7740_early_devices[] __initdata = { &irqpin0_device, &irqpin1_device, &irqpin2_device, -- cgit v1.2.3 From 2131421b85c9f25082a2b0ec371c7ad0c47cc943 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 7 Jul 2014 09:54:51 +0200 Subject: ARM: shmobile: sh73a0: Add SCIF nodes This describes all of the SCIF hardware of the sh73a0. Each node is disabled and may be enabled as necessary by board DTS files. Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0.dtsi | 72 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 5ecf552e1c00..910b79079d5a 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -235,6 +235,78 @@ status = "disabled"; }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-sh73a0", "renesas,scifa"; + reg = <0xe6c40000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-sh73a0", "renesas,scifa"; + reg = <0xe6c50000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-sh73a0", "renesas,scifa"; + reg = <0xe6c60000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-sh73a0", "renesas,scifa"; + reg = <0xe6c70000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifa4: serial@e6c80000 { + compatible = "renesas,scifa-sh73a0", "renesas,scifa"; + reg = <0xe6c80000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifa5: serial@e6cb0000 { + compatible = "renesas,scifa-sh73a0", "renesas,scifa"; + reg = <0xe6cb0000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifa6: serial@e6cc0000 { + compatible = "renesas,scifa-sh73a0", "renesas,scifa"; + reg = <0xe6cc0000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifa7: serial@e6cd0000 { + compatible = "renesas,scifa-sh73a0", "renesas,scifa"; + reg = <0xe6cd0000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifb8: serial@e6c30000 { + compatible = "renesas,scifb-sh73a0", "renesas,scifb"; + reg = <0xe6c30000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + pfc: pfc@e6050000 { compatible = "renesas,pfc-sh73a0"; reg = <0xe6050000 0x8000>, -- cgit v1.2.3 From 700ce7c2bb2a4963472d95eba1436d6b0945918e Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 7 Jul 2014 09:54:52 +0200 Subject: ARM: shmobile: kzm9g-reference: Initialise SCIF device using DT Initialise SCIF device using DT when booting armadillo800eva using DT reference. Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 14 +++++++++++--- arch/arm/mach-shmobile/setup-sh73a0.c | 8 ++++---- 2 files changed, 15 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 838f93e44452..18662aec2ec4 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -21,6 +21,10 @@ model = "KZM-A9-GT"; compatible = "renesas,kzm9g-reference", "renesas,sh73a0"; + aliases { + serial4 = &scifa4; + }; + cpus { cpu@0 { cpu0-supply = <&vdd_dvfs>; @@ -276,9 +280,6 @@ }; &pfc { - pinctrl-0 = <&scifa4_pins>; - pinctrl-names = "default"; - i2c3_pins: i2c3 { renesas,groups = "i2c3_1"; renesas,function = "i2c3"; @@ -318,6 +319,13 @@ }; }; +&scifa4 { + pinctrl-0 = <&scifa4_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + &sdhi0 { pinctrl-0 = <&sdhi0_pins>; pinctrl-names = "default"; diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index ad00724a2269..2e1e2894a784 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -696,6 +696,10 @@ static struct platform_device irqpin3_device = { }; static struct platform_device *sh73a0_devices_dt[] __initdata = { + &cmt1_device, +}; + +static struct platform_device *sh73a0_early_devices[] __initdata = { &scif0_device, &scif1_device, &scif2_device, @@ -705,10 +709,6 @@ static struct platform_device *sh73a0_devices_dt[] __initdata = { &scif6_device, &scif7_device, &scif8_device, - &cmt1_device, -}; - -static struct platform_device *sh73a0_early_devices[] __initdata = { &tmu0_device, &ipmmu_device, }; -- cgit v1.2.3 From 2d4cd2cafaea529948de9ac9f04d88254e473c61 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Tue, 8 Jul 2014 16:42:24 +0200 Subject: ARM: Kirkwood: allow to use netxbig DTSI for d2net_v2 DTS The d2 Network v2 board (d2net_v2) shares a lot of hardware characteristics with the 2Big and 5Big Network v2 boards. This patch prepares the kirkwood-netxbig.dtsi file in order to allow to include it from the d2net_v2 DTS file. The DT nodes only relevant for the 2Big and 5Big Network v2 boards are moved into their respective DTS files. Signed-off-by: Simon Guinot Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1404830545-15581-2-git-send-email-simon.guinot@sequanux.org Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-net2big.dts | 30 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/kirkwood-net5big.dts | 28 ++++++++++++++++++++++++++++ arch/arm/boot/dts/kirkwood-netxbig.dtsi | 26 -------------------------- 3 files changed, 58 insertions(+), 26 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/kirkwood-net2big.dts b/arch/arm/boot/dts/kirkwood-net2big.dts index a98deccee59f..53dc37a3b687 100644 --- a/arch/arm/boot/dts/kirkwood-net2big.dts +++ b/arch/arm/boot/dts/kirkwood-net2big.dts @@ -28,3 +28,33 @@ reg = <0x00000000 0x10000000>; }; }; + +®ulators { + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; + }; + + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; + +&i2c0 { + g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-net5big.dts b/arch/arm/boot/dts/kirkwood-net5big.dts index d2887ed493f2..36155b749d9f 100644 --- a/arch/arm/boot/dts/kirkwood-net5big.dts +++ b/arch/arm/boot/dts/kirkwood-net5big.dts @@ -31,6 +31,18 @@ }; ®ulators { + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; + }; + regulator@3 { compatible = "regulator-fixed"; reg = <3>; @@ -66,6 +78,14 @@ regulator-boot-on; gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; }; + + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; }; &mdio { @@ -81,3 +101,11 @@ }; }; + +&i2c0 { + g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-netxbig.dtsi b/arch/arm/boot/dts/kirkwood-netxbig.dtsi index fd75720547e3..b0cfb7cd30b9 100644 --- a/arch/arm/boot/dts/kirkwood-netxbig.dtsi +++ b/arch/arm/boot/dts/kirkwood-netxbig.dtsi @@ -104,26 +104,6 @@ regulator-boot-on; gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; }; }; @@ -171,10 +151,4 @@ pagesize = <16>; reg = <0x50>; }; - - g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; - }; }; -- cgit v1.2.3 From 18ba7e4fe51d15a0ec94de1f3cf74c3cc82b5f90 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Tue, 8 Jul 2014 16:42:25 +0200 Subject: ARM: Kirkwood: add DT support for d2 Network v2 This patch adds DT support for the LaCie NAS d2 Network v2 (d2net_v2). Most of the hardware characteristics are shared with the 2Big and 5Big Network v2 boards. - CPU: Marvell 88F6281 1200Mhz - SDRAM memory: 256MB DDR2 400Mhz - 2 SATA ports: internal and eSATA - Gigabit ethernet: PHY Marvell 88E1116R - Flash memory: SPI NOR 512KB (Macronix MX25L4005A) - i2c EEPROM: 512 bytes (24C04 type) - 2 USB2 ports: host and host/device - 1 push button - 1 power switch - 1 SATA LED (bi-color, blue and red) Signed-off-by: Simon Guinot Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1404830545-15581-3-git-send-email-simon.guinot@sequanux.org Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/kirkwood-d2net.dts | 42 ++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-d2net.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8e75c1f7fa23..abf47db584ac 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -93,6 +93,7 @@ dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \ kirkwood := \ kirkwood-b3.dtb \ kirkwood-cloudbox.dtb \ + kirkwood-d2net.dtb \ kirkwood-db-88f6281.dtb \ kirkwood-db-88f6282.dtb \ kirkwood-dns320.dtb \ diff --git a/arch/arm/boot/dts/kirkwood-d2net.dts b/arch/arm/boot/dts/kirkwood-d2net.dts new file mode 100644 index 000000000000..6b7856025001 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-d2net.dts @@ -0,0 +1,42 @@ +/* + * Device Tree file for d2 Network v2 + * + * Copyright (C) 2014 Simon Guinot + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +/dts-v1/; + +#include "kirkwood-netxbig.dtsi" + +/ { + model = "LaCie d2 Network v2"; + compatible = "lacie,d2net_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + ns2-leds { + compatible = "lacie,ns2-leds"; + + blue-sata { + label = "d2net_v2:blue:sata"; + slow-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; + cmd-gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + red-fail { + label = "d2net_v2:red:fail"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + }; +}; -- cgit v1.2.3 From ff10e2cda1072b85713c95fddd87da41adec9e7f Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 10 Jul 2014 16:52:14 -0300 Subject: ARM: mvebu: Add support for the network controller in Armada 375 SoC This commit adds the support for the network controller in Marvell Armada 375 SoC devicetree. Signed-off-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1405021936-28658-3-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-375.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index fb92551a1e71..d4619ad6e35c 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -151,6 +151,37 @@ <0xc100 0x100>; }; + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0xc0054 0x4>; + }; + + /* Network controller */ + ethernet@f0000 { + compatible = "marvell,armada-375-pp2"; + reg = <0xf0000 0xa000>, /* Packet Processor regs */ + <0xc0000 0x3060>, /* LMS regs */ + <0xc4000 0x100>, /* eth0 regs */ + <0xc5000 0x100>; /* eth1 regs */ + clocks = <&gateclk 3>, <&gateclk 19>; + clock-names = "pp_clk", "gop_clk"; + status = "disabled"; + + eth0: eth0@c4000 { + interrupts = ; + port-id = <0>; + status = "disabled"; + }; + + eth1: eth1@c5000 { + interrupts = ; + port-id = <1>; + status = "disabled"; + }; + }; + spi0: spi@10600 { compatible = "marvell,orion-spi"; reg = <0x10600 0x50>; -- cgit v1.2.3 From 9495898ffd2075d0fd42b573cb40c23eaea7b18e Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 10 Jul 2014 16:52:15 -0300 Subject: ARM: mvebu: Enable the network controller in Armada 375 DB board This commit enables the network controller in the Armada 375 DB board, and configures the two available ethernet interfaces. Signed-off-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1405021936-28658-4-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-375-db.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts index 772fec2d26ce..cfab2170d518 100644 --- a/arch/arm/boot/dts/armada-375-db.dts +++ b/arch/arm/boot/dts/armada-375-db.dts @@ -121,6 +121,32 @@ cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; + + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy3: ethernet-phy@3 { + reg = <3>; + }; + }; + + ethernet@f0000 { + status = "okay"; + + eth0@c4000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + eth1@c5000 { + status = "okay"; + phy = <&phy3>; + phy-mode = "gmii"; + }; + }; }; pcie-controller { -- cgit v1.2.3 From 0985f38d1379291c8701572e761c809f0d5f6476 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 7 Jul 2014 09:54:29 +0200 Subject: ARM: shmobile: r8a7778: add TMU clock support for DT This will be used when initialising TMU devices using DT until common clock framework support is added. Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7778.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c index a6dd601165e2..9407bac6fa61 100644 --- a/arch/arm/mach-shmobile/clock-r8a7778.c +++ b/arch/arm/mach-shmobile/clock-r8a7778.c @@ -244,7 +244,9 @@ static struct clk_lookup lookups[] = { CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP524]), CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP523]), CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP016]), + CLKDEV_ICK_ID("fck", "ffd80000.timer", &mstp_clks[MSTP016]), CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP015]), + CLKDEV_ICK_ID("fck", "ffd81000.timer", &mstp_clks[MSTP015]), }; void __init r8a7778_clock_init(void) -- cgit v1.2.3 From ef9cb75ca70c8d31b2493d1fd6cbf8b3dd1dec95 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 7 Jul 2014 09:54:43 +0200 Subject: ARM: shmobile: r8a7740: add TMU clock support for DT This will be used when initialising TMU devices using DT until common clock framework support is added. Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7740.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index 68592b7109f7..3f34b3fe3bb8 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -598,7 +598,9 @@ static struct clk_lookup lookups[] = { /* ICK */ CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP111]), + CLKDEV_ICK_ID("fck", "fff90000.timer", &mstp_clks[MSTP111]), CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]), + CLKDEV_ICK_ID("fck", "fff80000.timer", &mstp_clks[MSTP125]), CLKDEV_ICK_ID("fck", "sh-cmt-48.1", &mstp_clks[MSTP329]), CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]), CLKDEV_ICK_ID("func", "renesas_usbhs", &mstp_clks[MSTP407]), -- cgit v1.2.3 From aad64dc31954dbbb84cd8fcfaf1bc028f3bc2616 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 7 Jul 2014 09:54:35 +0200 Subject: ARM: shmobile: r8a73a4: add CMT1 clock support for DT This will be used when initialising CMT1 device using DT until common clock framework support is added. Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a73a4.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index 1d2fe056fa20..9629851a9b5d 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -604,6 +604,7 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]), CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]), CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.1", &mstp_clks[MSTP329]), + CLKDEV_ICK_ID("fck", "e6130000.timer", &mstp_clks[MSTP329]), CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]), CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]), CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]), -- cgit v1.2.3 From 2e11179da78a56c2a44fc3fe097f2af8dc18f9d6 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 7 Jul 2014 09:54:46 +0200 Subject: ARM: shmobile: r8a7740: add CMT1 clock support for DT This will be used when initialising CMT1 device using DT until common clock framework support is added. Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7740.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index 3f34b3fe3bb8..2ffb56016e0f 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -602,6 +602,7 @@ static struct clk_lookup lookups[] = { CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]), CLKDEV_ICK_ID("fck", "fff80000.timer", &mstp_clks[MSTP125]), CLKDEV_ICK_ID("fck", "sh-cmt-48.1", &mstp_clks[MSTP329]), + CLKDEV_ICK_ID("fck", "e6138000.timer", &mstp_clks[MSTP329]), CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]), CLKDEV_ICK_ID("func", "renesas_usbhs", &mstp_clks[MSTP407]), CLKDEV_ICK_ID("phy", "renesas_usbhs", &mstp_clks[MSTP406]), -- cgit v1.2.3 From a0f7e7496d56ac2da7c684e2035815318c17973a Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 7 Jul 2014 09:54:53 +0200 Subject: ARM: shmobile: sh73a0: add CMT1 clock support for DT This will be used when initialising CMT1 device using DT until common clock framework support is added. Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-sh73a0.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 4990e03482d2..0d77f652f30c 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -690,6 +690,7 @@ static struct clk_lookup lookups[] = { CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk), CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk), CLKDEV_ICK_ID("fck", "sh-cmt-48.1", &mstp_clks[MSTP329]), /* CMT1 */ + CLKDEV_ICK_ID("fck", "e6138000.timer", &mstp_clks[MSTP329]), /* CMT1 */ CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]), /* TMU0 */ }; -- cgit v1.2.3 From dc8fbed5d9cc169ce0d50e2003416a43dda45ba6 Mon Sep 17 00:00:00 2001 From: Vince Bridgers Date: Mon, 23 Jun 2014 13:32:11 -0500 Subject: ARM: socfpga: Add missing #reset-cells to socfpga device tree add #reset-cells to socfpga.dtsi. This was missing from the latest updates and caused the socfpga reset controller to fail to load like so: ffd05000.rstmgr: /soc/rstmgr@ffd05000 missing #reset-cells property probe of ffd05000.rstmgr failed with error -22 Signed-off-by: Vince Bridgers Signed-off-by: Dinh Nguyen Signed-off-by: Olof Johansson --- arch/arm/boot/dts/socfpga.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 4676f25e87a7..0a66d8a9457c 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -683,6 +683,7 @@ }; rst: rstmgr@ffd05000 { + #reset-cells = <1>; compatible = "altr,rst-mgr"; reg = <0xffd05000 0x1000>; }; -- cgit v1.2.3 From df02dd828c4ef2311c7c271f2c95384fc555961b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 9 Jul 2014 15:54:39 +0800 Subject: ARM: sun8i: Add PRCM clock and reset controller nodes to the DTSI With sun8i PRCM support available, we can add the PRCM clock and reset controller nodes to the DTSI. Also update R_UART's clock phandle and add it's reset control phandle. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23.dtsi | 47 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 886776d09c06..54ac0787216a 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -285,13 +285,58 @@ interrupts = <1 9 0xf04>; }; + prcm@01f01400 { + compatible = "allwinner,sun8i-a23-prcm"; + reg = <0x01f01400 0x200>; + + ar100: ar100_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "ar100"; + }; + + ahb0: ahb0_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&ar100>; + clock-output-names = "ahb0"; + }; + + apb0: apb0_clk { + compatible = "allwinner,sun8i-a23-apb0-clk"; + #clock-cells = <0>; + clocks = <&ahb0>; + clock-output-names = "apb0"; + }; + + apb0_gates: apb0_gates_clk { + compatible = "allwinner,sun8i-a23-apb0-gates-clk"; + #clock-cells = <1>; + clocks = <&apb0>; + clock-output-names = "apb0_pio", "apb0_timer", + "apb0_rsb", "apb0_uart", + "apb0_i2c"; + }; + + apb0_rst: apb0_rst { + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; + }; + r_uart: serial@01f02800 { compatible = "snps,dw-apb-uart"; reg = <0x01f02800 0x400>; interrupts = <0 38 4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb0_gates 4>; + resets = <&apb0_rst 4>; status = "disabled"; }; }; -- cgit v1.2.3 From 147e5413696c3d385283ceda73efb2b098657477 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Mon, 14 Jul 2014 16:12:16 +0530 Subject: ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div clock Add divider table to optfclk_pciephy_div clock. The 8th bit of CM_CLKMODE_APLL_PCIE can be programmed to either 0x0 or 0x1 based on if the divider value is 0x2 or 0x1. Figure 26-21. PCIe PHY Clock Generator Overview in vE of DRA7xx ES1.0 shows the block diagram of Clock Generator Subsystem of PCIe PHY module. The divider value if '1' should be programmed in order to get the correct PCIE_PHY_DIV_GCLK frequency (2.5GHz). Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Signed-off-by: Keerthy Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index b03cfe49d22b..7148e7c75397 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1170,6 +1170,7 @@ clocks = <&apll_pcie_ck>; #clock-cells = <0>; reg = <0x021c>; + ti,dividers = <2>, <1>; ti,bit-shift = <8>; ti,max-div = <2>; }; -- cgit v1.2.3 From 4310e90847f18e09559b65c1897e5a88313e3fea Mon Sep 17 00:00:00 2001 From: Keerthy Date: Mon, 14 Jul 2014 16:12:17 +0530 Subject: ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck from dpll_pcie_ref_ck. Figure 26-22. DPLL_PCIE_REF Functional Block Diagram in vE of DRA7xx ES1.0 TRM shows the signal name for the output of post divider (M2) is CLKOUTLDO. Figure 26-21. PCIe PHY Clock Generator Overview shows CLKOUTLDO is used as input to apll mux. So the actual output of dpll is dpll_pcie_ref_m2ldo_ck which is also the input of apll. Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Signed-off-by: Keerthy Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 7148e7c75397..f5dca1ff1d6e 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1152,7 +1152,7 @@ apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { compatible = "ti,mux-clock"; - clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>; + clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; #clock-cells = <0>; reg = <0x021c 0x4>; ti,bit-shift = <7>; -- cgit v1.2.3 From ba5137b27281f9016a5b2f6177f02595252305bd Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Jul 2014 16:12:18 +0530 Subject: ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY Added missing 32KHz clock used by PCIe PHY. Figure 26-19. PCIe PHY Subsystem Integration in vE of DRA7xx ES1.0 TRM shows 32KHz is used by PCIe PHY. Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index f5dca1ff1d6e..3ff6d7c3857c 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1165,6 +1165,14 @@ reg = <0x021c>, <0x0220>; }; + optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 { + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + #clock-cells = <0>; + reg = <0x13b0>; + ti,bit-shift = <8>; + }; + optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { compatible = "ti,divider-clock"; clocks = <&apll_pcie_ck>; -- cgit v1.2.3 From b700f42c863e17569ca4d864e369210d9ff00b8a Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Jul 2014 16:12:19 +0530 Subject: ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance There are two instances of PCIe PHY in DRA7xx. So renamed optfclk_pciephy_32khz, optfclk_pciephy_clk and optfclk_pciephy_div_clk to optfclk_pciephy1_32khz, optfclk_pciephy1_clk and optfclk_pciephy1_div_clk respectively. This is needed for adding the clocks for second PCIe PHY instance. Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Keerthy Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 3ff6d7c3857c..fe5db55aeede 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1165,7 +1165,7 @@ reg = <0x021c>, <0x0220>; }; - optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 { + optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 { compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; #clock-cells = <0>; @@ -1183,7 +1183,7 @@ ti,max-div = <2>; }; - optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 { + optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 { compatible = "ti,gate-clock"; clocks = <&apll_pcie_ck>; #clock-cells = <0>; @@ -1191,7 +1191,7 @@ ti,bit-shift = <9>; }; - optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 { + optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 { compatible = "ti,gate-clock"; clocks = <&optfclk_pciephy_div>; #clock-cells = <0>; -- cgit v1.2.3 From 00b0af5b68fc8bde724f7d491099179253bc4da8 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Jul 2014 16:12:20 +0530 Subject: ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance Added missing clocks used by second instance of PCIe PHY. The documention for this nodes can be found @ ../bindings/clock/ti/gate.txt. Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index fe5db55aeede..b48f18b234b3 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1173,6 +1173,14 @@ ti,bit-shift = <8>; }; + optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 { + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + #clock-cells = <0>; + reg = <0x13b8>; + ti,bit-shift = <8>; + }; + optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { compatible = "ti,divider-clock"; clocks = <&apll_pcie_ck>; @@ -1191,6 +1199,14 @@ ti,bit-shift = <9>; }; + optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 { + compatible = "ti,gate-clock"; + clocks = <&apll_pcie_ck>; + #clock-cells = <0>; + reg = <0x13b8>; + ti,bit-shift = <9>; + }; + optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 { compatible = "ti,gate-clock"; clocks = <&optfclk_pciephy_div>; @@ -1199,6 +1215,14 @@ ti,bit-shift = <10>; }; + optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 { + compatible = "ti,gate-clock"; + clocks = <&optfclk_pciephy_div>; + #clock-cells = <0>; + reg = <0x13b8>; + ti,bit-shift = <10>; + }; + apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; -- cgit v1.2.3 From d1ff66b52dbe6ac7c13c77767759d1ac84f5da9d Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Jul 2014 16:12:21 +0530 Subject: ARM: dts: dra7: Add dt data for PCIe PHY control module Added dt data for PCIe PHY control module used by PCIe PHY. The documention for this node can be found @ ../bindings/phy/ti-phy.txt Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 961be6b8ffbf..e4999e4b7b65 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -828,6 +828,23 @@ ti,hwmods = "sata"; }; + omap_control_pcie1phy: control-phy@0x4a003c40 { + compatible = "ti,control-phy-pcie"; + reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; + reg-names = "power", "control_sma", "pcie_pcs"; + clocks = <&sys_clkin1>; + clock-names = "sysclk"; + }; + + omap_control_pcie2phy: control-pcie@0x4a003c44 { + compatible = "ti,control-phy-pcie"; + reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; + reg-names = "power", "control_sma", "pcie_pcs"; + clocks = <&sys_clkin1>; + clock-names = "sysclk"; + status = "disabled"; + }; + omap_control_usb2phy1: control-phy@4a002300 { compatible = "ti,control-phy-usb2"; reg = <0x4a002300 0x4>; -- cgit v1.2.3 From 692df0ef5abb7d8b36d70762134b842b70a55c31 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Jul 2014 16:12:22 +0530 Subject: ARM: dts: dra7: Add dt data for PCIe PHY Added dt data for PCIe PHY as a child node of ocp2scp3. The documention for this node can be found @ ../bindings/phy/ti-phy.txt. 26.3.3 PCIe Shared PHY Subsystem Integration in vE of DRA7xx ES1.0 describes the PCIe PHY subsystem-related components integrated in the device. Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index e4999e4b7b65..cbaf47db2b6e 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -816,6 +816,47 @@ clock-names = "sysclk"; #phy-cells = <0>; }; + + pcie1_phy: pciephy@4a094000 { + compatible = "ti,phy-pipe3-pcie"; + reg = <0x4a094000 0x80>, /* phy_rx */ + <0x4a094400 0x64>; /* phy_tx */ + reg-names = "phy_rx", "phy_tx"; + ctrl-module = <&omap_control_pcie1phy>; + clocks = <&dpll_pcie_ref_ck>, + <&dpll_pcie_ref_m2ldo_ck>, + <&optfclk_pciephy1_32khz>, + <&optfclk_pciephy1_clk>, + <&optfclk_pciephy1_div_clk>, + <&optfclk_pciephy_div>; + clock-names = "dpll_ref", "dpll_ref_m2", + "wkupclk", "refclk", + "div-clk", "phy-div"; + #phy-cells = <0>; + id = <1>; + ti,hwmods = "pcie1-phy"; + }; + + pcie2_phy: pciephy@4a095000 { + compatible = "ti,phy-pipe3-pcie"; + reg = <0x4a095000 0x80>, /* phy_rx */ + <0x4a095400 0x64>; /* phy_tx */ + reg-names = "phy_rx", "phy_tx"; + ctrl-module = <&omap_control_pcie2phy>; + clocks = <&dpll_pcie_ref_ck>, + <&dpll_pcie_ref_m2ldo_ck>, + <&optfclk_pciephy2_32khz>, + <&optfclk_pciephy2_clk>, + <&optfclk_pciephy2_div_clk>, + <&optfclk_pciephy_div>; + clock-names = "dpll_ref", "dpll_ref_m2", + "wkupclk", "refclk", + "div-clk", "phy-div"; + #phy-cells = <0>; + ti,hwmods = "pcie2-phy"; + id = <2>; + status = "disabled"; + }; }; sata: sata@4a141100 { -- cgit v1.2.3 From 18dcd79db798f710a25dee203b765ef62389f0e1 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Jul 2014 16:12:23 +0530 Subject: ARM: dts: dra7: Add dt data for PCIe controller Added dt data for PCIe controller. This node contains dt data for both the DRA7 part of designware controller and for the designware core. The documention for this node can be found @ ../bindings/pci/ti-pci.txt. Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Cc: Bjorn Helgaas Cc: Jingoo Han Cc: Jason Gunthorpe Cc: Marek Vasut Cc: Arnd Bergmann Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 69 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index cbaf47db2b6e..b6060d37d1cf 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -99,6 +99,75 @@ }; }; + axi@0 { + compatible = "simple-bus"; + #size-cells = <1>; + #address-cells = <1>; + ranges = <0x51000000 0x51000000 0x3000 + 0x0 0x20000000 0x10000000>; + pcie@51000000 { + compatible = "ti,dra7-pcie"; + reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; + reg-names = "rc_dbics", "ti_conf", "config"; + interrupts = <0 232 0x4>, <0 233 0x4>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x03000 0 0x00010000 + 0x82000000 0 0x20013000 0x13000 0 0xffed000>; + #interrupt-cells = <1>; + num-lanes = <1>; + ti,hwmods = "pcie1"; + phys = <&pcie1_phy>; + phy-names = "pcie-phy0"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 1>, + <0 0 0 2 &pcie1_intc 2>, + <0 0 0 3 &pcie1_intc 3>, + <0 0 0 4 &pcie1_intc 4>; + pcie1_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + axi@1 { + compatible = "simple-bus"; + #size-cells = <1>; + #address-cells = <1>; + ranges = <0x51800000 0x51800000 0x3000 + 0x0 0x30000000 0x10000000>; + status = "disabled"; + pcie@51000000 { + compatible = "ti,dra7-pcie"; + reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; + reg-names = "rc_dbics", "ti_conf", "config"; + interrupts = <0 355 0x4>, <0 356 0x4>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x03000 0 0x00010000 + 0x82000000 0 0x30013000 0x13000 0 0xffed000>; + #interrupt-cells = <1>; + num-lanes = <1>; + ti,hwmods = "pcie2"; + phys = <&pcie2_phy>; + phy-names = "pcie-phy0"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 1>, + <0 0 0 2 &pcie2_intc 2>, + <0 0 0 3 &pcie2_intc 3>, + <0 0 0 4 &pcie2_intc 4>; + pcie2_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + cm_core_aon: cm_core_aon@4a005000 { compatible = "ti,dra7-cm-core-aon"; reg = <0x4a005000 0x2000>; -- cgit v1.2.3 From 55be2c5376df16933219bbec98bfdfe2db158f69 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 10 Jul 2014 14:24:01 +0300 Subject: ARM: DTS: omap5-uevm: Enable palmas clk32kgaudio clock clk32kg-audio clock is needed for twl6040 codec. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-uevm.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 1e1b05768cec..9166d479ac1b 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -306,6 +306,11 @@ ti,wakeup; }; + clk32kgaudio: palmas_clk32k@1 { + compatible = "ti,palmas-clk32kgaudio"; + #clock-cells = <0>; + }; + palmas_pmic { compatible = "ti,palmas-pmic"; interrupt-parent = <&palmas>; -- cgit v1.2.3 From 4b54a2cb14c370ee388d17a3ac084c4839a7933e Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 10 Jul 2014 14:24:02 +0300 Subject: ARM: DTS: omap5-uevm: Add node for twl6040 audio codec The board uses twl6040 as audio codec. Move the corresponding pinctrl as well under the node. twl6040 needs 32k clock from palams. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-uevm.dts | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 9166d479ac1b..c9286166fad5 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -105,7 +105,6 @@ &omap5_pmx_core { pinctrl-names = "default"; pinctrl-0 = < - &twl6040_pins &mcpdm_pins &mcbsp1_pins &mcbsp2_pins @@ -494,6 +493,25 @@ }; }; }; + + twl6040: twl@4b { + compatible = "ti,twl6040"; + reg = <0x4b>; + + pinctrl-names = "default"; + pinctrl-0 = <&twl6040_pins>; + + interrupts = ; /* IRQ_SYS_2N cascaded to gic */ + interrupt-parent = <&gic>; + ti,audpwron-gpio = <&gpio5 13 0>; /* gpio line 141 */ + + vio-supply = <&smps7_reg>; + v2v1-supply = <&smps9_reg>; + enable-active-high; + + clocks = <&clk32kgaudio>; + clock-names = "clk32k"; + }; }; &i2c5 { -- cgit v1.2.3 From 3c9464ed75d6c15ee864da6d8f6a4cd3b0f2c934 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 10 Jul 2014 14:24:03 +0300 Subject: ARM: DTS: omap5-uevm: Enable basic audio (McPDM <-> twl6040) The board uses twl6040 codec connected via McPDM link. McBSP1 and McBSP2 can be used for FM/BT. At the same time move the pinctrl handling to the correct place - under the corresponding nodes. Audio connectors on the board: Headset in/out Stereo Line out Stereo Line in. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-uevm.dts | 43 +++++++++++++++++++++++++++++++++++----- 1 file changed, 38 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index c9286166fad5..159720d6c956 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -100,14 +100,33 @@ }; }; }; + + sound: sound { + compatible = "ti,abe-twl6040"; + ti,model = "omap5-uevm"; + + ti,mclk-freq = <19200000>; + + ti,mcpdm = <&mcpdm>; + + ti,twl6040 = <&twl6040>; + + /* Audio routing */ + ti,audio-routing = + "Headset Stereophone", "HSOL", + "Headset Stereophone", "HSOR", + "Line Out", "AUXL", + "Line Out", "AUXR", + "HSMIC", "Headset Mic", + "Headset Mic", "Headset Mic Bias", + "AFML", "Line In", + "AFMR", "Line In"; + }; }; &omap5_pmx_core { pinctrl-names = "default"; pinctrl-0 = < - &mcpdm_pins - &mcbsp1_pins - &mcbsp2_pins &usbhost_pins &led_gpio_pins >; @@ -528,8 +547,22 @@ }; }; -&mcbsp3 { - status = "disabled"; +&mcpdm { + pinctrl-names = "default"; + pinctrl-0 = <&mcpdm_pins>; + status = "okay"; +}; + +&mcbsp1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp1_pins>; + status = "okay"; +}; + +&mcbsp2 { + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; + status = "okay"; }; &usbhshost { -- cgit v1.2.3 From ac5ce09e140c0238a8fb61d1c198ce9945e8be47 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Wed, 16 Jul 2014 02:38:39 +0900 Subject: ARM: dts: Add mask-tpm-reset node in exynos5420-peach-pit The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from being reset across sleep/wake. If we don't set it to anything then the TPM will be reset. U-Boot will detect this as invalid and will reset the system on resume time. This GPIO can always be low and not hurt anything. It will get pulled back high again during a normal warm reset when it will default back to an input. To properly preserve the TPM state across suspend/resume and to make the chrome U-Boot happy, properly set the GPIO to mask the reset to the TPM. Signed-off-by: Doug Anderson Signed-off-by: Vikas Sajjan Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420-peach-pit.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 6c7cab0eba25..c7b2bbae71a9 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -211,6 +211,9 @@ &pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&mask_tpm_reset>; + max98090_irq: max98090-irq { samsung,pins = "gpx0-2"; samsung,pin-function = <0>; @@ -218,6 +221,15 @@ samsung,pin-drv = <0>; }; + /* We need GPX0_6 to be low at sleep time; just keep it low always */ + mask_tpm_reset: mask-tpm-reset { + samsung,pins = "gpx0-6"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + samsung,pin-val = <0>; + }; + tpm_irq: tpm-irq { samsung,pins = "gpx1-0"; samsung,pin-function = <0>; -- cgit v1.2.3 From 73a9bb2e7a48bb47c092f407812a0100c79d5180 Mon Sep 17 00:00:00 2001 From: Vikas Sajjan Date: Wed, 16 Jul 2014 02:38:44 +0900 Subject: ARM: dts: Add mask-tpm-reset node in exynos5800-peach-pi The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from being reset across sleep/wake. If we don't set it to anything then the TPM will be reset. U-Boot will detect this as invalid and will reset the system on resume time. This GPIO can always be low and not hurt anything. It will get pulled back high again during a normal warm reset when it will default back to an input. To properly preserve the TPM state across suspend/resume and to make the chrome U-Boot happy, properly set the GPIO to mask the reset to the TPM. Signed-off-by: Vikas Sajjan Reviewed-by: Doug Anderson Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5800-peach-pi.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 28f2a251aee5..0bc97d94474c 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -209,6 +209,9 @@ &pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&mask_tpm_reset>; + max98091_irq: max98091-irq { samsung,pins = "gpx0-2"; samsung,pin-function = <0>; @@ -216,6 +219,15 @@ samsung,pin-drv = <0>; }; + /* We need GPX0_6 to be low at sleep time; just keep it low always */ + mask_tpm_reset: mask-tpm-reset { + samsung,pins = "gpx0-6"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + samsung,pin-val = <0>; + }; + tpm_irq: tpm-irq { samsung,pins = "gpx1-0"; samsung,pin-function = <0>; -- cgit v1.2.3 From 366126d5c6a5d9381a5f6a4e061ad0aba33e789e Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 16 Jul 2014 02:54:06 +0900 Subject: ARM: dts: add port sub-nodes to exynos usb host modules for exynos4 This patch adds port sub-nodes to exynos4 ehci and ohci modules, which are required by recently merged new exynos4 usb2 phy support. Signed-off-by: Marek Szyprowski Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index b8ece4be41ca..c91284441694 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -322,6 +322,23 @@ clocks = <&clock CLK_USB_HOST>; clock-names = "usbhost"; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&exynos_usbphy 1>; + status = "disabled"; + }; + port@1 { + reg = <1>; + phys = <&exynos_usbphy 2>; + status = "disabled"; + }; + port@2 { + reg = <2>; + phys = <&exynos_usbphy 3>; + status = "disabled"; + }; }; ohci@12590000 { @@ -331,6 +348,13 @@ clocks = <&clock CLK_USB_HOST>; clock-names = "usbhost"; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&exynos_usbphy 1>; + status = "disabled"; + }; }; i2s1: i2s@13960000 { -- cgit v1.2.3 From 0c80244f25de719814ef010633ccf6d3b2f1192a Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 16 Jul 2014 02:54:06 +0900 Subject: ARM: dts: enable common hardware blocks for exynos4412-odroidx This patch adds support for common hardware modules available on all Exynos4412-based Odroid boards, which already have complete support in mainline kernel. This includes secure firmware calls, watchdog, g2d and fimc (mem2mem) multimedia accelerators. Signed-off-by: Marek Szyprowski Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4412-odroidx.dts | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 31db28a4bb33..fda9ac23dd55 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -22,6 +22,11 @@ reg = <0x40000000 0x40000000>; }; + firmware@0204F000 { + compatible = "samsung,secure-firmware"; + reg = <0x0204F000 0x1000>; + }; + leds { compatible = "gpio-leds"; led1 { @@ -68,10 +73,40 @@ regulator-boot-on; }; + watchdog@10060000 { + status = "okay"; + }; + rtc@10070000 { status = "okay"; }; + g2d@10800000 { + status = "okay"; + }; + + camera { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + + fimc_0: fimc@11800000 { + status = "okay"; + }; + + fimc_1: fimc@11810000 { + status = "okay"; + }; + + fimc_2: fimc@11820000 { + status = "okay"; + }; + + fimc_3: fimc@11830000 { + status = "okay"; + }; + }; + sdhci@12530000 { bus-width = <4>; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; -- cgit v1.2.3 From 5eb3019355517c43d13ed989212346f1406dbb48 Mon Sep 17 00:00:00 2001 From: Kamil Debski Date: Wed, 16 Jul 2014 02:54:06 +0900 Subject: ARM: dts: add support for USB phy, host and device for exynos4412-odroidx This patch adds basic support for USB modules (host and device) on OdroidX board. Signed-off-by: Kamil Debski [removed incorrect port@2 node] Signed-off-by: Marek Szyprowski Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4412-odroidx.dts | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index fda9ac23dd55..4c853fbf7202 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -148,6 +148,16 @@ pinctrl-names = "default"; status = "okay"; + usb3503@08 { + compatible = "smsc,usb3503"; + reg = <0x08>; + + intn-gpios = <&gpx3 0 0>; + connect-gpios = <&gpx3 4 0>; + reset-gpios = <&gpx3 5 0>; + initial-mode = <1>; + }; + max77686: pmic@09 { compatible = "maxim,max77686"; reg = <0x09>; @@ -338,4 +348,21 @@ }; }; }; + + exynos-usbphy@125B0000 { + status = "okay"; + }; + + hsotg@12480000 { + status = "okay"; + vusb_d-supply = <&ldo15_reg>; + vusb_a-supply = <&ldo12_reg>; + }; + + ehci@12580000 { + status = "okay"; + port@1 { + status = "okay"; + }; + }; }; -- cgit v1.2.3 From f9e45a69b7bb2d436741f79fc5a372c104f7b68b Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 16 Jul 2014 02:54:06 +0900 Subject: ARM: dts: correct memory size for exynos4412-odroidx Last megabyte of RAM is used by secure firmware and should not be accessed by Linux kernel, so correct available memory size in DTS file. Signed-off-by: Marek Szyprowski Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4412-odroidx.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 4c853fbf7202..bcf331543fb0 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -19,7 +19,7 @@ compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4"; memory { - reg = <0x40000000 0x40000000>; + reg = <0x40000000 0x3FF00000>; }; firmware@0204F000 { -- cgit v1.2.3 From ec601ff3394af5045cbfbd02b2e0197a93b97723 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 16 Jul 2014 02:54:07 +0900 Subject: ARM: dts: refactor Odroid DTS file and add support for Odroid X2 and U2/U3 This patch moves some parts of exynos4412-odroidx.dts to common exynos4412-odroid-common.dtsi file and adds support for Odroid X2 and U2/U3 boards. X2 is same as X, but it has faster SoC module (1.7GHz instead of 1.4GHz), while U2/U3 differs from X2 by different way of routing signals to host USB hub. It also lacks some hw modules not yet supported by those dts files (i.e. LCD & touch panel). Signed-off-by: Marek Szyprowski Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 319 +++++++++++++++++++++++ arch/arm/boot/dts/exynos4412-odroidu3.dts | 49 ++++ arch/arm/boot/dts/exynos4412-odroidx.dts | 326 +----------------------- arch/arm/boot/dts/exynos4412-odroidx2.dts | 23 ++ 5 files changed, 404 insertions(+), 315 deletions(-) create mode 100644 arch/arm/boot/dts/exynos4412-odroid-common.dtsi create mode 100644 arch/arm/boot/dts/exynos4412-odroidu3.dts create mode 100644 arch/arm/boot/dts/exynos4412-odroidx2.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5986ff63b901..28b354936685 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -66,7 +66,9 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-trats.dtb \ exynos4210-universal_c210.dtb \ + exynos4412-odroidu3.dtb \ exynos4412-odroidx.dtb \ + exynos4412-odroidx2.dtb \ exynos4412-origen.dtb \ exynos4412-smdk4412.dtb \ exynos4412-tiny4412.dtb \ diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi new file mode 100644 index 000000000000..f793f3b8f0b9 --- /dev/null +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -0,0 +1,319 @@ +/* + * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards + * device tree source + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include "exynos4412.dtsi" + +/ { + firmware@0204F000 { + compatible = "samsung,secure-firmware"; + reg = <0x0204F000 0x1000>; + }; + + mmc@12550000 { + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; + pinctrl-names = "default"; + vmmc-supply = <&ldo20_reg &buck8_reg>; + status = "okay"; + + num-slots = <1>; + supports-highspeed; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; + }; + + watchdog@10060000 { + status = "okay"; + }; + + rtc@10070000 { + status = "okay"; + }; + + g2d@10800000 { + status = "okay"; + }; + + camera { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + + fimc_0: fimc@11800000 { + status = "okay"; + }; + + fimc_1: fimc@11810000 { + status = "okay"; + }; + + fimc_2: fimc@11820000 { + status = "okay"; + }; + + fimc_3: fimc@11830000 { + status = "okay"; + }; + }; + + sdhci@12530000 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&ldo4_reg &ldo21_reg>; + status = "okay"; + }; + + serial@13800000 { + status = "okay"; + }; + + serial@13810000 { + status = "okay"; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; + + i2c@13860000 { + pinctrl-0 = <&i2c0_bus>; + pinctrl-names = "default"; + status = "okay"; + + usb3503: usb3503@08 { + compatible = "smsc,usb3503"; + reg = <0x08>; + + intn-gpios = <&gpx3 0 0>; + connect-gpios = <&gpx3 4 0>; + reset-gpios = <&gpx3 5 0>; + initial-mode = <1>; + }; + + max77686: pmic@09 { + compatible = "maxim,max77686"; + reg = <0x09>; + #clock-cells = <1>; + + voltage-regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDDQ_M1_2_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "VDDQ_EXT_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDDQ_MMC2_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "VDDQ_MMC1_3_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD10_MPLL_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD10_XPLL_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD18_ABB1_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD33_USB_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "VDDQ_C2C_W_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD18_ABB0_2_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD10_HSIC_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD18_HSIC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo20_reg: LDO20 { + regulator-name = "LDO20_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + ldo21_reg: LDO21 { + regulator-name = "LDO21_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo25_reg: LDO25 { + regulator-name = "VDDQ_LCD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-microvolt-offset = <50000>; + }; + + buck5_reg: BUCK5 { + regulator-name = "VDDQ_CKEM1_2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "BUCK6_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "BUCK7_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "BUCK8_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + }; + }; + }; + + exynos-usbphy@125B0000 { + status = "okay"; + }; + + hsotg@12480000 { + status = "okay"; + vusb_d-supply = <&ldo15_reg>; + vusb_a-supply = <&ldo12_reg>; + }; + + ehci: ehci@12580000 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts new file mode 100644 index 000000000000..287aa0d1f978 --- /dev/null +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -0,0 +1,49 @@ +/* + * Hardkernel's Exynos4412 based ODROID-U3 board device tree source + * + * Copyright (c) 2014 Marek Szyprowski + * + * Device tree source file for Hardkernel's ODROID-U3 board which is based + * on Samsung's Exynos4412 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "exynos4412-odroid-common.dtsi" + +/ { + model = "Hardkernel ODROID-U3 board based on Exynos4412"; + compatible = "hardkernel,odroid-u3", "samsung,exynos4412", "samsung,exynos4"; + + memory { + reg = <0x40000000 0x7FF00000>; + }; + + leds { + compatible = "gpio-leds"; + led1 { + label = "led1:heart"; + gpios = <&gpc1 0 1>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&usb3503 { + clock-names = "refclk"; + clocks = <&pmu_system_controller 0>; + refclk-frequency = <24000000>; +}; + +&ehci { + port@1 { + status = "okay"; + }; + port@2 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index bcf331543fb0..8b453a31410d 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -3,8 +3,8 @@ * * Copyright (c) 2012 Dongjin Kim * - * Device tree source file for Hardkernel's ODROID-X board which is based on - * Samsung's Exynos4412 SoC. + * Device tree source file for Hardkernel's ODROID-X board which is based + * on Samsung's Exynos4412 SoC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -12,7 +12,7 @@ */ /dts-v1/; -#include "exynos4412.dtsi" +#include "exynos4412-odroid-common.dtsi" / { model = "Hardkernel ODROID-X board based on Exynos4412"; @@ -22,11 +22,6 @@ reg = <0x40000000 0x3FF00000>; }; - firmware@0204F000 { - compatible = "samsung,secure-firmware"; - reg = <0x0204F000 0x1000>; - }; - leds { compatible = "gpio-leds"; led1 { @@ -43,24 +38,12 @@ }; }; - mmc@12550000 { - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - vmmc-supply = <&ldo20_reg &buck8_reg>; + serial@13820000 { status = "okay"; + }; - num-slots = <1>; - supports-highspeed; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + serial@13830000 { + status = "okay"; }; regulator_p3v3 { @@ -70,299 +53,12 @@ regulator-max-microvolt = <3300000>; gpio = <&gpa1 1 1>; enable-active-high; - regulator-boot-on; - }; - - watchdog@10060000 { - status = "okay"; - }; - - rtc@10070000 { - status = "okay"; - }; - - g2d@10800000 { - status = "okay"; - }; - - camera { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - - fimc_0: fimc@11800000 { - status = "okay"; - }; - - fimc_1: fimc@11810000 { - status = "okay"; - }; - - fimc_2: fimc@11820000 { - status = "okay"; - }; - - fimc_3: fimc@11830000 { - status = "okay"; - }; - }; - - sdhci@12530000 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&ldo4_reg &ldo21_reg>; - status = "okay"; - }; - - serial@13800000 { - status = "okay"; - }; - - serial@13810000 { - status = "okay"; - }; - - serial@13820000 { - status = "okay"; - }; - - serial@13830000 { - status = "okay"; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; - - i2c@13860000 { - pinctrl-0 = <&i2c0_bus>; - pinctrl-names = "default"; - status = "okay"; - - usb3503@08 { - compatible = "smsc,usb3503"; - reg = <0x08>; - - intn-gpios = <&gpx3 0 0>; - connect-gpios = <&gpx3 4 0>; - reset-gpios = <&gpx3 5 0>; - initial-mode = <1>; - }; - - max77686: pmic@09 { - compatible = "maxim,max77686"; - reg = <0x09>; - #clock-cells = <1>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDDQ_M1_2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VDDQ_EXT_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDDQ_MMC2_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "VDDQ_MMC1_3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD10_MPLL_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD10_XPLL_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD18_ABB1_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD33_USB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "VDDQ_C2C_W_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB0_2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD10_HSIC_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo20_reg: LDO20 { - regulator-name = "LDO20_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - ldo21_reg: LDO21 { - regulator-name = "LDO21_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo25_reg: LDO25 { - regulator-name = "VDDQ_LCD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-microvolt-offset = <50000>; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDDQ_CKEM1_2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "BUCK6_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "BUCK7_2.0V"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "BUCK8_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - }; - }; - }; - - exynos-usbphy@125B0000 { - status = "okay"; - }; - - hsotg@12480000 { - status = "okay"; - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; + regulator-always-on; }; +}; - ehci@12580000 { +&ehci { + port@1 { status = "okay"; - port@1 { - status = "okay"; - }; }; }; diff --git a/arch/arm/boot/dts/exynos4412-odroidx2.dts b/arch/arm/boot/dts/exynos4412-odroidx2.dts new file mode 100644 index 000000000000..e9ae161a4117 --- /dev/null +++ b/arch/arm/boot/dts/exynos4412-odroidx2.dts @@ -0,0 +1,23 @@ +/* + * Hardkernel's Exynos4412 based ODROID-X2 board device tree source + * + * Copyright (c) 2012 Dongjin Kim + * + * Device tree source file for Hardkernel's ODROID-X2 board which is based + * on Samsung's Exynos4412 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include "exynos4412-odroidx.dts" + +/ { + model = "Hardkernel ODROID-X2 board based on Exynos4412"; + compatible = "hardkernel,odroid-x2", "samsung,exynos4412", "samsung,exynos4"; + + memory { + reg = <0x40000000 0x7FF00000>; + }; +}; -- cgit v1.2.3 From 13681526bb0451f526e8b1872e9ea3842d579d98 Mon Sep 17 00:00:00 2001 From: Kamil Debski Date: Wed, 16 Jul 2014 02:54:07 +0900 Subject: ARM: dts: disable 'always on' for BUCK8 regulator for exynos4412-odroid-common On Odroid U2/U3 BUCK8 is used for providing power to also to P3V3 source, which is also connected to LAN9730 chip's nRESET signal. To reset lan chip on system reboot, the BUCK8 output should not be used in 'always on' mode. This change has no impact on X/X2 boards. Signed-off-by: Kamil Debski Signed-off-by: Marek Szyprowski Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index f793f3b8f0b9..ad2cb32a3439 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -297,7 +297,6 @@ regulator-name = "BUCK8_2.8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - regulator-always-on; }; }; }; -- cgit v1.2.3 From 081a15e3fe926d88d3eb9f3a4161c1121a2a7d0b Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 16 Jul 2014 02:54:07 +0900 Subject: ARM: dts: add support for GPIO buttons for exynos4412-odroid This patch adds support for simple GPIO-based button availabled on Exynos4 based Odroid boards. All supported boards have POWER button, which has been defined in exynos4412-odroid-common.dtsi. X/X2 boards also have additional user-configurable button which has been mapped to KEY_HOME. All defined keys have been marked as possible wakeup source. Signed-off-by: Marek Szyprowski Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 24 ++++++++++++++++++++++++ arch/arm/boot/dts/exynos4412-odroidx.dts | 21 +++++++++++++++++++++ 2 files changed, 45 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index ad2cb32a3439..d1b33a8efa9d 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -7,6 +7,7 @@ * published by the Free Software Foundation. */ +#include #include "exynos4412.dtsi" / { @@ -15,6 +16,22 @@ reg = <0x0204F000 0x1000>; }; + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_power_key>; + + power_key { + interrupt-parent = <&gpx1>; + interrupts = <3 0>; + gpios = <&gpx1 3 1>; + linux,code = ; + label = "power key"; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + mmc@12550000 { pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; pinctrl-names = "default"; @@ -316,3 +333,10 @@ status = "okay"; }; }; + +&pinctrl_1 { + gpio_power_key: power_key { + samsung,pins = "gpx1-3"; + samsung,pin-pud = <0>; + }; +}; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 8b453a31410d..cb1cfe7239c4 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -46,6 +46,20 @@ status = "okay"; }; + gpio_keys { + pinctrl-0 = <&gpio_power_key &gpio_home_key>; + + home_key { + interrupt-parent = <&gpx2>; + interrupts = <2 0>; + gpios = <&gpx2 2 0>; + linux,code = ; + label = "home key"; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + regulator_p3v3 { compatible = "regulator-fixed"; regulator-name = "p3v3_en"; @@ -62,3 +76,10 @@ status = "okay"; }; }; + +&pinctrl_1 { + gpio_home_key: home_key { + samsung,pins = "gpx2-2"; + samsung,pin-pud = <0>; + }; +}; -- cgit v1.2.3 From 78f54db13364b9622c8734c45f774d99536da819 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 16 Jul 2014 02:54:07 +0900 Subject: ARM: dts: fix T-FLASH hotplug detection for exynos4412-odroid-common TFLASH (SDHCI2 controller) uses internal card detect line, but it looks that the driver fails to operate it properly. Use GPIO interrupt on SD_CDn line for detecting SD card state. Signed-off-by: Marek Szyprowski Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index d1b33a8efa9d..0bc1a9b94f47 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -91,6 +91,8 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; pinctrl-names = "default"; vmmc-supply = <&ldo4_reg &ldo21_reg>; + cd-gpios = <&gpk2 2 0>; + cd-inverted; status = "okay"; }; -- cgit v1.2.3 From 5a852743a495b8628ad6c848a74254ec8fcc9c27 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Wed, 16 Jul 2014 03:16:44 +0900 Subject: ARM: dts: Add sound nodes for Odroid-X2/U3 boards Add MAX98090 audio codec, I2S interface and the sound complex nodes to enable audio on Odroid-X2/U3 boards. Signed-off-by: Sylwester Nawrocki Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 27 +++++++++++++++++++++++++ arch/arm/boot/dts/exynos4412-odroidu3.dts | 12 +++++++++++ arch/arm/boot/dts/exynos4412-odroidx2.dts | 9 +++++++++ 3 files changed, 48 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 0bc1a9b94f47..6d6d23c83d30 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -32,6 +32,21 @@ }; }; + i2s0: i2s@03830000 { + pinctrl-0 = <&i2s0_bus>; + pinctrl-names = "default"; + status = "okay"; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>; + clock-names = "iis", "i2s_opclk0"; + }; + + sound: sound { + compatible = "samsung,odroidx2-audio"; + samsung,i2s-controller = <&i2s0>; + samsung,audio-codec = <&max98090>; + }; + mmc@12550000 { pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; pinctrl-names = "default"; @@ -321,6 +336,18 @@ }; }; + i2c@13870000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; + status = "okay"; + max98090: max98090@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpx0>; + interrupts = <0 0>; + }; + }; + exynos-usbphy@125B0000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index 287aa0d1f978..c8a64be55d07 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -47,3 +47,15 @@ status = "okay"; }; }; + +&sound { + compatible = "samsung,odroidu3-audio"; + samsung,model = "Odroid-U3"; + samsung,audio-routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Headphone Jack", "MICBIAS", + "IN1", "Headphone Jack", + "Speakers", "SPKL", + "Speakers", "SPKR"; +}; diff --git a/arch/arm/boot/dts/exynos4412-odroidx2.dts b/arch/arm/boot/dts/exynos4412-odroidx2.dts index e9ae161a4117..96b43f4497cc 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx2.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx2.dts @@ -21,3 +21,12 @@ reg = <0x40000000 0x7FF00000>; }; }; + +&sound { + samsung,model = "Odroid-X2"; + samsung,audio-routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "IN1", "Mic Jack", + "Mic Jack", "MICBIAS"; +}; -- cgit v1.2.3 From d51cad7df87119ab625ad8ba15eb3e8f9ea44fc9 Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Wed, 16 Jul 2014 08:37:00 +0900 Subject: ARM: dts: remove display power domain for exynos5420 Display domain is removed due to instability issues. Explaining the problem below: exynos_init_late triggers the pm_genpd_poweroff_unused which powers off the unused power domains. This call hits before the trigger to deferred probes. DRM DP Panel defers the probe due to supply get failure. By the time, deferred probe is scheduled again, Display Power Domain is powered off by pm_genpd_poweroff_unused. FIMD and DP drivers are accessing registers during Probe and Bind callbacks. If display domain is enabled/disabled around register accesses, display domain gets unstable and we are getting Power Domain Disable fail notification. Increasing the Timeout also didn't help. Signed-off-by: Rahul Sharma Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420.dtsi | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index e38532271ef9..3d528cffe943 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -262,11 +262,6 @@ reg = <0x10044060 0x20>; }; - disp_pd: power-domain@100440C0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100440C0 0x20>; - }; - msc_pd: power-domain@10044120 { compatible = "samsung,exynos4210-pd"; reg = <0x10044120 0x20>; @@ -518,7 +513,6 @@ }; fimd: fimd@14400000 { - samsung,power-domain = <&disp_pd>; clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; clock-names = "sclk_fimd", "fimd"; }; -- cgit v1.2.3 From d7f3ec2b69f692d215deb991d109a3341b0d8da9 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 9 Jul 2014 15:40:14 +0200 Subject: ARM: mvebu: add CA9 MPcore SoC Controller node The CA9 MPcore SoC Control block is a set of registers that allows to configure certain internal aspects of the core blocks of the SoC (Cortex-A9, L2 cache controller, etc.). In most cases, the default values are fine so they aren't many reasons to touch those registers, but there is one exception: to support cpuidle on Armada 38x, we need to modify the value of the CA9 MPcore Reset Control register. Therefore, this commit adds a new Device Tree binding for this hardware block, and uses this new binding for the Armada 38x Device Tree file. Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Petazzoni Cc: devicetree@vger.kernel.org Link: https://lkml.kernel.org/r/1404913221-17343-11-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-38x.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 3de364e81b52..b479eaa23fcc 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -286,6 +286,11 @@ reg = <0x20800 0x10>; }; + mpcore-soc-ctrl@20d20 { + compatible = "marvell,armada-380-mpcore-soc-ctrl"; + reg = <0x20d20 0x6c>; + }; + coherency-fabric@21010 { compatible = "marvell,armada-380-coherency-fabric"; reg = <0x21010 0x1c>; -- cgit v1.2.3 From 3843607838cc5436d02a6771e661969a54c2fee0 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 9 Jul 2014 17:45:12 +0200 Subject: ARM: mvebu: update Armada XP DT for dynamic frequency scaling In order to support dynamic frequency scaling: * the cpuclk Device Tree node needs to be updated to describe a second set of registers describing the PMU DFS registers. * the clock-latency property of the CPUs must be filled, otherwise the ondemand and conservative cpufreq governors refuse to work. The latency is high because the cost of a frequency transition is quite high on those CPUs. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1404920715-19834-5-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-xp-mv78230.dtsi | 2 ++ arch/arm/boot/dts/armada-xp-mv78260.dtsi | 2 ++ arch/arm/boot/dts/armada-xp-mv78460.dtsi | 4 ++++ arch/arm/boot/dts/armada-xp.dtsi | 2 +- 4 files changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index 1257ff1ed278..2592e1c13560 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -34,6 +34,7 @@ compatible = "marvell,sheeva-v7"; reg = <0>; clocks = <&cpuclk 0>; + clock-latency = <1000000>; }; cpu@1 { @@ -41,6 +42,7 @@ compatible = "marvell,sheeva-v7"; reg = <1>; clocks = <&cpuclk 1>; + clock-latency = <1000000>; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 3396b25b39e1..480e237a870f 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -36,6 +36,7 @@ compatible = "marvell,sheeva-v7"; reg = <0>; clocks = <&cpuclk 0>; + clock-latency = <1000000>; }; cpu@1 { @@ -43,6 +44,7 @@ compatible = "marvell,sheeva-v7"; reg = <1>; clocks = <&cpuclk 1>; + clock-latency = <1000000>; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 6da84bf40aaf..2c7b1fef4703 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -37,6 +37,7 @@ compatible = "marvell,sheeva-v7"; reg = <0>; clocks = <&cpuclk 0>; + clock-latency = <1000000>; }; cpu@1 { @@ -44,6 +45,7 @@ compatible = "marvell,sheeva-v7"; reg = <1>; clocks = <&cpuclk 1>; + clock-latency = <1000000>; }; cpu@2 { @@ -51,6 +53,7 @@ compatible = "marvell,sheeva-v7"; reg = <2>; clocks = <&cpuclk 2>; + clock-latency = <1000000>; }; cpu@3 { @@ -58,6 +61,7 @@ compatible = "marvell,sheeva-v7"; reg = <3>; clocks = <&cpuclk 3>; + clock-latency = <1000000>; }; }; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 5902e8359c91..bff9f6c18db1 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -99,7 +99,7 @@ cpuclk: clock-complex@18700 { #clock-cells = <1>; compatible = "marvell,armada-xp-cpu-clock"; - reg = <0x18700 0xA0>; + reg = <0x18700 0xA0>, <0x1c054 0x10>; clocks = <&coreclk 1>; }; -- cgit v1.2.3 From 72ceddda632e1b66935e5a430af70a0e1fe21500 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Wed, 30 Apr 2014 10:44:10 -0700 Subject: ARM: tegra: Add the EC i2c tunnel to tegra124-venice2 This adds the EC i2c tunnel (and devices under it) to the tegra124-venice2 device tree. Signed-off-by: Doug Anderson Tested-by: Andrew Bresticker Tested-by: Stephen Warren Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 72585c82a307..233070c462bc 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -824,6 +824,32 @@ reg = <0>; google,cros-ec-spi-msg-delay = <2000>; + + i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + + google,remote-bus = <0>; + + charger: bq24735@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + interrupt-parent = <&gpio>; + interrupts = ; + ti,ac-detect-gpios = <&gpio + TEGRA_GPIO(J, 0) + GPIO_ACTIVE_HIGH>; + }; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <1>; + }; + }; }; }; -- cgit v1.2.3 From 6389cb3bf6ae7da61c44c408b855248e12c5e76c Mon Sep 17 00:00:00 2001 From: Dylan Reid Date: Mon, 19 May 2014 19:35:45 -0700 Subject: ARM: tegra: Add Tegra124 HDA support Add a device node for the HDA controller found on Tegra124. Signed-off-by: Dylan Reid Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 226941c07d15..d675186d8eba 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -464,6 +464,21 @@ reset-names = "fuse"; }; + hda@0,70030000 { + compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; + reg = <0x0 0x70030000 0x0 0x10000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_HDA>, + <&tegra_car TEGRA124_CLK_HDA2HDMI>, + <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; + clock-names = "hda", "hda2hdmi", "hdacodec_2x"; + resets = <&tegra_car 125>, /* hda */ + <&tegra_car 128>, /* hda2hdmi */ + <&tegra_car 111>; /* hda2codec_2x */ + reset-names = "hda", "hda2hdmi", "hdacodec_2x"; + status = "disabled"; + }; + sdhci@0,700b0000 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; -- cgit v1.2.3 From 0f3d3bf8ba3d22c1eaa92c10dfd0f6b002edbdc1 Mon Sep 17 00:00:00 2001 From: Dylan Reid Date: Mon, 19 May 2014 19:35:46 -0700 Subject: ARM: tegra: venice2 - Enable HDA Turn on the HDA controller in Venice2, it is used for HDMI audio. Signed-off-by: Dylan Reid Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 233070c462bc..f1a5bac43c55 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -874,6 +874,10 @@ nvidia,sys-clock-req-active-high; }; + hda@0,70030000 { + status = "okay"; + }; + sdhci@0,700b0400 { cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; -- cgit v1.2.3 From 33f34f0ca9be50885045d22fa40ddccc2c7ca520 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Tue, 3 Jun 2014 14:48:46 +0200 Subject: ARM: tegra: jetson-tk1: mark eMMC as non-removable The eMMC is soldered to the board, reflect this in the DT. Signed-off-by: Lucas Stach Reviewed-by: Alexandre Courbot Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index e31fb61a81d3..16082c0bdaca 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1633,6 +1633,7 @@ sdhci@0,700b0600 { status = "okay"; bus-width = <8>; + non-removable; }; ahub@0,70300000 { -- cgit v1.2.3 From 6d0a067ff0f879a3a569c00219af25ba643727cb Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Tue, 10 Jun 2014 00:52:46 +0200 Subject: ARM: tegra: initial support for apalis t30 This patch adds the device tree to support Toradex Apalis T30, a computer on module which can be used on different carrier boards. The module consists of a Tegra 3 SoC, two PMICs, 1 or 2 GB of DDR3L RAM, eMMC, an LM95245 temperature sensor chip, an i210 resp. i211 gigabit Ethernet controller, an STMPE811 ADC/touch controller as well as two MCP2515 CAN controllers. Furthermore, there is an SGTL5000 audio codec which is not yet supported. Anything that is not self contained on the module is disabled by default. The device tree for the Evaluation Board includes the modules device tree and enables the supported peripherals of the carrier board (the Evaluation Board supports almost all of them). While at it also add the device tree binding documentation for Apalis T30. Signed-off-by: Marcel Ziswiler [swarren: fixed some node sort orders] Signed-off-by: Stephen Warren --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra30-apalis-eval.dts | 260 ++++++++++++ arch/arm/boot/dts/tegra30-apalis.dtsi | 673 ++++++++++++++++++++++++++++++ 3 files changed, 934 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-apalis-eval.dts create mode 100644 arch/arm/boot/dts/tegra30-apalis.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5986ff63b901..906fb672df44 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -390,6 +390,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra20-trimslice.dtb \ tegra20-ventana.dtb \ tegra20-whistler.dtb \ + tegra30-apalis-eval.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts new file mode 100644 index 000000000000..992143372af0 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -0,0 +1,260 @@ +/dts-v1/; + +#include +#include "tegra30-apalis.dtsi" + +/ { + model = "Toradex Apalis T30 on Apalis Evaluation Board"; + compatible = "toradex,apalis_t30-eval", "nvidia,tegra30"; + + aliases { + rtc0 = "/i2c@7000c000/rtc@68"; + rtc1 = "/i2c@7000d000/tps65911@2d"; + rtc2 = "/rtc@7000e000"; + }; + + pcie-controller@00003000 { + status = "okay"; + + pci@1,0 { + status = "okay"; + }; + + pci@2,0 { + status = "okay"; + }; + + pci@3,0 { + status = "okay"; + }; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + nvidia,panel = <&panel>; + }; + }; + hdmi@54280000 { + status = "okay"; + }; + }; + + serial@70006000 { + status = "okay"; + }; + + serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + }; + + serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + }; + + serial@70006300 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + /* + * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + + pcie-switch@58 { + compatible = "plx,pex8605"; + reg = <0x58>; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc@68 { + compatible = "st,m41t00"; + reg = <0x68>; + }; + }; + + /* GEN2_I2C: unused */ + + /* + * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on + * carrier board) + */ + cami2c: i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ + hdmiddc: i2c@7000c700 { + status = "okay"; + }; + + /* SPI1: Apalis SPI1 */ + spi@7000d400 { + status = "okay"; + spi-max-frequency = <25000000>; + spidev0: spidev@1 { + compatible = "spidev"; + reg = <1>; + spi-max-frequency = <25000000>; + }; + }; + + /* SPI5: Apalis SPI2 */ + spi@7000dc00 { + status = "okay"; + spi-max-frequency = <25000000>; + spidev1: spidev@2 { + compatible = "spidev"; + reg = <2>; + spi-max-frequency = <25000000>; + }; + }; + + sd1: sdhci@78000000 { + status = "okay"; + bus-width = <4>; + /* SD1_CD# */ + cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; + no-1-8-v; + }; + + mmc1: sdhci@78000400 { + status = "okay"; + bus-width = <8>; + /* MMC1_CD# */ + cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + no-1-8-v; + }; + + /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ + usb@7d000000 { + status = "okay"; + }; + + usb-phy@7d000000 { + status = "okay"; + vbus-supply = <&usbo1_vbus_reg>; + }; + + /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ + usb@7d004000 { + status = "okay"; + }; + + usb-phy@7d004000 { + status = "okay"; + vbus-supply = <&usbh_vbus_reg>; + }; + + /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&usbh_vbus_reg>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + /* PWM0 */ + pwms = <&pwm 0 5000000>; + brightness-levels = <255 231 223 207 191 159 127 0>; + default-brightness-level = <6>; + /* BKL1_ON */ + enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu", "simple-panel"; + + backlight = <&backlight>; + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm1 { + label = "PWM1"; + pwms = <&pwm 3 19600>; + max-brightness = <255>; + }; + + pwm2 { + label = "PWM2"; + pwms = <&pwm 2 19600>; + max-brightness = <255>; + }; + + pwm3 { + label = "PWM3"; + pwms = <&pwm 1 19600>; + max-brightness = <255>; + }; + }; + + regulators { + sys_5v0_reg: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + /* USBO1_EN */ + usbo1_vbus_reg: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usbo1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&sys_5v0_reg>; + }; + + /* USBH_EN */ + usbh_vbus_reg: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usbh_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&sys_5v0_reg>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi new file mode 100644 index 000000000000..d04efcf8e3cf --- /dev/null +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -0,0 +1,673 @@ +#include "tegra30.dtsi" + +/* + * Toradex Apalis T30 Device Tree + * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C + */ +/ { + model = "Toradex Apalis T30"; + compatible = "toradex,apalis_t30", "nvidia,tegra30"; + + pcie-controller@00003000 { + pex-clk-supply = <&sys_3v3_reg>; + vdd-supply = <&vdd2_reg>; + avdd-supply = <&ldo6_reg>; + + pci@1,0 { + nvidia,num-lanes = <4>; + }; + + pci@2,0 { + nvidia,num-lanes = <1>; + }; + + pci@3,0 { + nvidia,num-lanes = <1>; + }; + }; + + host1x@50000000 { + hdmi@54280000 { + vdd-supply = <&sys_3v3_reg>; + pll-supply = <&vio_reg>; + + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + nvidia,ddc-i2c-bus = <&hdmiddc>; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* Apalis BKL1_ON */ + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis BKL1_PWM */ + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis CAN1 on SPI6 */ + spi2_cs0_n_px3 { + nvidia,pins = "spi2_cs0_n_px3", + "spi2_miso_px1", + "spi2_mosi_px0", + "spi2_sck_px2"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* CAN_INT1 */ + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis CAN2 on SPI4 */ + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a17_pb0", + "gmi_a18_pb1", + "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* CAN_INT2 */ + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis I2C3 */ + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + + /* Apalis MMC1 */ + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6", + "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_dat4_pd1", + "sdmmc3_dat5_pd0", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* Apalis MMC1_CD# */ + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis PWM1 */ + gpio_pu6 { + nvidia,pins = "gpio_pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis PWM2 */ + gpio_pu5 { + nvidia,pins = "gpio_pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis PWM3 */ + gpio_pu4 { + nvidia,pins = "gpio_pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis PWM4 */ + gpio_pu3 { + nvidia,pins = "gpio_pu3"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis RESET_MOCI# */ + gmi_rst_n_pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis SD1 */ + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* Apalis SD1_CD# */ + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPI1 */ + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5", + "spi1_mosi_px4", + "spi1_miso_px7", + "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis SPI2 */ + lcd_sck_pz4 { + nvidia,pins = "lcd_sck_pz4", + "lcd_sdout_pn5", + "lcd_sdin_pz2", + "lcd_cs0_n_pn4"; + nvidia,function = "spi5"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis UART1 */ + ulpi_data0 { + nvidia,pins = "ulpi_data0_po1", + "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data5_po6", + "ulpi_data6_po7", + "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis UART2 */ + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis UART3 */ + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3", + "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis UART4 */ + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis USBO1_EN */ + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "rsvd4"; + nvidia,open-drain = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis USBO1_OC# */ + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "rsvd4"; + nvidia,open-drain = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis WAKE1_MICO */ + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* eMMC (On-module) */ + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4", + "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* LVDS Transceiver Configuration */ + pbb0 { + nvidia,pins = "pbb0", + "pbb7", + "pcc1", + "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + }; + pbb3 { + nvidia,pins = "pbb3", + "pbb4", + "pbb5", + "pbb6"; + nvidia,function = "displayb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + }; + + /* Power I2C (On-module) */ + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + + /* + * THERMD_ALERT#, unlatched I2C address pin of LM95245 + * temperature sensor therefore requires disabling for + * now + */ + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* TOUCH_PEN_INT# */ + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + hdmiddc: i2c@7000c700 { + clock-frequency = <100000>; + }; + + /* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&sys_3v3_reg>; + vcc2-supply = <&sys_3v3_reg>; + vcc3-supply = <&vio_reg>; + vcc4-supply = <&sys_3v3_reg>; + vcc5-supply = <&sys_3v3_reg>; + vcc6-supply = <&vio_reg>; + vcc7-supply = <&sys_5v0_reg>; + vccio-supply = <&sys_3v3_reg>; + + regulators { + /* SW1: +V1.35_VDDIO_DDR */ + vdd1_reg: vdd1 { + regulator-name = "vddio_ddr_1v35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + /* SW2: +V1.05 */ + vdd2_reg: vdd2 { + regulator-name = + "vdd_pexa,vdd_pexb,vdd_sata"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + /* SW CTRL: +V1.0_VDD_CPU */ + vddctrl_reg: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + }; + + /* SWIO: +V1.8 */ + vio_reg: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + /* LDO1: unused */ + + /* + * EN_+V3.3 switching via FET: + * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN + * see also v3_3 fixed supply + */ + ldo2_reg: ldo2 { + regulator-name = "en_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* +V1.2_CSI */ + ldo3_reg: ldo3 { + regulator-name = + "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + /* +V1.2_VDD_RTC */ + ldo4_reg: ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* + * +V2.8_AVDD_VDAC: + * only required for analog RGB + */ + ldo5_reg: ldo5 { + regulator-name = "avdd_vdac"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + /* + * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V + * but LDO6 can't set voltage in 50mV + * granularity + */ + ldo6_reg: ldo6 { + regulator-name = "avdd_plle"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + /* +V1.2_AVDD_PLL */ + ldo7_reg: ldo7 { + regulator-name = "avdd_pll"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* +V1.0_VDD_DDR_HS */ + ldo8_reg: ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + + /* STMPE811 touch screen controller */ + stmpe811@41 { + compatible = "st,stmpe811"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41>; + interrupts = ; + interrupt-parent = <&gpio>; + interrupt-controller; + id = <0>; + blocks = <0x5>; + irq-trigger = <0x1>; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + reg = <0>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + }; + }; + + /* + * LM95245 temperature sensor + * Note: OVERT_N directly connected to PMIC PWRDN + */ + temp-sensor@4c { + compatible = "national,lm95245"; + reg = <0x4c>; + }; + + /* SW: +V1.2_VDD_CORE */ + tps62362@60 { + compatible = "ti,tps62362"; + reg = <0x60>; + + regulator-name = "tps62362-vout"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-low; + /* VSEL1: EN_CORE_DVFS_N low for DVFS */ + ti,vsel1-state-low; + }; + }; + + /* SPI4: CAN2 */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <10000000>; + + can@1 { + compatible = "microchip,mcp2515"; + reg = <1>; + clocks = <&clk16m>; + interrupt-parent = <&gpio>; + interrupts = ; + spi-max-frequency = <10000000>; + }; + }; + + /* SPI6: CAN1 */ + spi@7000de00 { + status = "okay"; + spi-max-frequency = <10000000>; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio>; + interrupts = ; + spi-max-frequency = <10000000>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <5000>; + nvidia,cpu-pwr-off-time = <5000>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clk@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + clk16m: clk@1 { + compatible = "fixed-clock"; + reg=<1>; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "clk16m"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + sys_3v3_reg: regulator@100 { + compatible = "regulator-fixed"; + reg = <100>; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; -- cgit v1.2.3 From 23e633450c14cfe79c9f0f02e15f155b733976cf Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Thu, 19 Jun 2014 15:25:49 +0200 Subject: ARM: tegra: tamonten: add the base board regulators Currently the Tamonten DTS define a fixed regulator for the 5V supply. However this regulator is in fact on the base board. Fix this by properly defining the regulators found on the base boards. Signed-off-by: Alban Bedel Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-medcom-wide.dts | 41 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/tegra20-plutux.dts | 41 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/tegra20-tamonten.dtsi | 10 +------- arch/arm/boot/dts/tegra20-tec.dts | 41 +++++++++++++++++++++++++++++++ 4 files changed, 124 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index 6d3a4cbc36cc..0318b84cb207 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -64,4 +64,45 @@ <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + regulators { + vcc_24v_reg: regulator@100 { + compatible = "regulator-fixed"; + reg = <100>; + regulator-name = "vcc_24v"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-always-on; + }; + + vdd_5v0_reg: regulator@101 { + compatible = "regulator-fixed"; + reg = <101>; + regulator-name = "vdd_5v0"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_3v3_reg: regulator@102 { + compatible = "regulator-fixed"; + reg = <102>; + regulator-name = "vdd_3v3"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_1v8_reg: regulator@103 { + compatible = "regulator-fixed"; + reg = <103>; + regulator-name = "vdd_1v8"; + vin-supply = <&vdd_3v3_reg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts index 29051a2ae0ae..a10b415bbdee 100644 --- a/arch/arm/boot/dts/tegra20-plutux.dts +++ b/arch/arm/boot/dts/tegra20-plutux.dts @@ -58,4 +58,45 @@ <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + regulators { + vcc_24v_reg: regulator@100 { + compatible = "regulator-fixed"; + reg = <100>; + regulator-name = "vcc_24v"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-always-on; + }; + + vdd_5v0_reg: regulator@101 { + compatible = "regulator-fixed"; + reg = <101>; + regulator-name = "vdd_5v0"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_3v3_reg: regulator@102 { + compatible = "regulator-fixed"; + reg = <102>; + regulator-name = "vdd_3v3"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_1v8_reg: regulator@103 { + compatible = "regulator-fixed"; + reg = <103>; + regulator-name = "vdd_1v8"; + vin-supply = <&vdd_3v3_reg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index a1b0d965757f..9c8318538a11 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -334,6 +334,7 @@ #gpio-cells = <2>; gpio-controller; + /* vdd_5v0_reg must be provided by the base board */ sys-supply = <&vdd_5v0_reg>; vin-sm0-supply = <&sys_reg>; vin-sm1-supply = <&sys_reg>; @@ -511,15 +512,6 @@ #address-cells = <1>; #size-cells = <0>; - vdd_5v0_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - pci_vdd_reg: regulator@1 { compatible = "regulator-fixed"; reg = <1>; diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts index 890562c667fb..c12d8bead2ee 100644 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -67,4 +67,45 @@ <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + regulators { + vcc_24v_reg: regulator@100 { + compatible = "regulator-fixed"; + reg = <100>; + regulator-name = "vcc_24v"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-always-on; + }; + + vdd_5v0_reg: regulator@101 { + compatible = "regulator-fixed"; + reg = <101>; + regulator-name = "vdd_5v0"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_3v3_reg: regulator@102 { + compatible = "regulator-fixed"; + reg = <102>; + regulator-name = "vdd_3v3"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_1v8_reg: regulator@103 { + compatible = "regulator-fixed"; + reg = <103>; + regulator-name = "vdd_1v8"; + vin-supply = <&vdd_3v3_reg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; }; -- cgit v1.2.3 From f6826156025f610bf6236ef020f9ade90e043960 Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Thu, 19 Jun 2014 15:25:50 +0200 Subject: ARM: tegra: tamonten: add the display to the Medcom Wide Enable the RGB output and add the panel definition to the Medcom Wide DTS. Also add a label to the backlight defintion to reference it in the panel definition. Signed-off-by: Alban Bedel Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-medcom-wide.dts | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index 0318b84cb207..1b7c56b33aca 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -10,6 +10,15 @@ status = "okay"; }; + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + nvidia,panel = <&panel>; + }; + }; + }; + i2c@7000c000 { wm8903: wm8903@1a { compatible = "wlf,wm8903"; @@ -30,7 +39,7 @@ }; }; - backlight { + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm 0 5000000>; @@ -38,6 +47,15 @@ default-brightness-level = <6>; }; + panel: panel { + compatible = "innolux,n156bge-l21", "simple-panel"; + + power-supply = <&vdd_1v8_reg>, <&vdd_3v3_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + }; + sound { compatible = "ad,tegra-audio-wm8903-medcom-wide", "nvidia,tegra-audio-wm8903"; -- cgit v1.2.3 From b607b19af6a8bf9892501c1ea7ae469fb96fd1c9 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 25 Jun 2014 22:10:01 +0200 Subject: ARM: tegra: Migrate Apalis T30 PCIe power supply scheme This migration is required for continued PCIe operation after commit d3c7e24b84fc "PCI: tegra: Implement accurate power supply scheme". Signed-off-by: Marcel Ziswiler [swarren: added commit subject and shortened hash] Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30-apalis.dtsi | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index d04efcf8e3cf..8adaa7871dd3 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -9,9 +9,14 @@ compatible = "toradex,apalis_t30", "nvidia,tegra30"; pcie-controller@00003000 { - pex-clk-supply = <&sys_3v3_reg>; - vdd-supply = <&vdd2_reg>; - avdd-supply = <&ldo6_reg>; + avdd-pexa-supply = <&vdd2_reg>; + vdd-pexa-supply = <&vdd2_reg>; + avdd-pexb-supply = <&vdd2_reg>; + vdd-pexb-supply = <&vdd2_reg>; + avdd-pex-pll-supply = <&vdd2_reg>; + avdd-plle-supply = <&ldo6_reg>; + vddio-pex-ctl-supply = <&sys_3v3_reg>; + hvdd-pex-supply = <&sys_3v3_reg>; pci@1,0 { nvidia,num-lanes = <4>; -- cgit v1.2.3 From 6982c0702909ba9df038ca868fc65fe29d03824e Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Mon, 23 Jun 2014 16:32:58 +0900 Subject: ARM: tegra: roth: fix unsupported pinmux properties The pinmux subsystem complained that the nvidia,low-power-mode property is not supported by the sdio1, sdio3 and gma drive groups. In addition gma also does not support nvidia,drive-type. Remove these properties so the pinmux configuration can properly be applied. Signed-off-by: Alexandre Courbot Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114-roth.dts | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 0b0e8e07d965..a67885250f81 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -730,7 +730,6 @@ nvidia,pins = "drive_sdio1"; nvidia,high-speed-mode = ; nvidia,schmitt = ; - nvidia,low-power-mode = ; nvidia,pull-down-strength = <36>; nvidia,pull-up-strength = <20>; nvidia,slew-rate-rising = ; @@ -740,7 +739,6 @@ nvidia,pins = "drive_sdio3"; nvidia,high-speed-mode = ; nvidia,schmitt = ; - nvidia,low-power-mode = ; nvidia,pull-down-strength = <36>; nvidia,pull-up-strength = <20>; nvidia,slew-rate-rising = ; @@ -750,12 +748,10 @@ nvidia,pins = "drive_gma"; nvidia,high-speed-mode = ; nvidia,schmitt = ; - nvidia,low-power-mode = ; nvidia,pull-down-strength = <2>; nvidia,pull-up-strength = <2>; nvidia,slew-rate-rising = ; nvidia,slew-rate-falling = ; - nvidia,drive-type = <1>; }; }; }; -- cgit v1.2.3 From 49f2747bb3ee5ca7a2dc438876b976fb3fcafb3c Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Mon, 23 Jun 2014 16:32:59 +0900 Subject: ARM: tegra: roth: enable input on mmc clock pins Input had been disabled by mistake on these pins, leading to issues with SDIO devices like the Wifi module not being probed or random errors occuring on the SD card. Signed-off-by: Alexandre Courbot Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114-roth.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index a67885250f81..ba210c6e189f 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -244,7 +244,7 @@ nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; sdmmc1_cmd_pz1 { nvidia,pins = "sdmmc1_cmd_pz1", @@ -262,7 +262,7 @@ nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; sdmmc3_cmd_pa7 { nvidia,pins = "sdmmc3_cmd_pa7", @@ -290,7 +290,7 @@ nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; sdmmc4_cmd_pt7 { nvidia,pins = "sdmmc4_cmd_pt7", -- cgit v1.2.3 From d86b1e8dcb26f38757bfd307478fa45285aac004 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 26 Jun 2014 14:33:34 +0900 Subject: ARM: tegra: add GK20A GPU to Tegra124 DT Add the GK20A device node to Tegra124's device tree. Signed-off-by: Thierry Reding Signed-off-by: Alexandre Courbot Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index d675186d8eba..cc9e7504c2da 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -102,6 +102,21 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + gpu@0,57000000 { + compatible = "nvidia,gk20a"; + reg = <0x0 0x57000000 0x0 0x01000000>, + <0x0 0x58000000 0x0 0x01000000>; + interrupts = , + ; + interrupt-names = "stall", "nonstall"; + clocks = <&tegra_car TEGRA124_CLK_GPU>, + <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; + clock-names = "gpu", "pwr"; + resets = <&tegra_car 184>; + reset-names = "gpu"; + status = "disabled"; + }; + timer@0,60005000 { compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; reg = <0x0 0x60005000 0x0 0x400>; -- cgit v1.2.3 From ce90d32d1377a121b11eefdfb1518aa2726f8d0b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 19 Jun 2014 13:37:09 +0200 Subject: ARM: tegra: tegra124: Add XUSB pad controller The device tree node in the SoC file contains only the resources (such as registers, resets, ...) but none of the lane assignment information since that's board specific and belongs in the board file. Tested-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index cc9e7504c2da..3af46d3bfbd5 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -1,6 +1,7 @@ #include #include #include +#include #include #include "skeleton.dtsi" @@ -494,6 +495,15 @@ status = "disabled"; }; + padctl: padctl@0,7009f000 { + compatible = "nvidia,tegra124-xusb-padctl"; + reg = <0x0 0x7009f000 0x0 0x1000>; + resets = <&tegra_car 142>; + reset-names = "padctl"; + + #phy-cells = <1>; + }; + sdhci@0,700b0000 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; -- cgit v1.2.3 From 62b8db08e7d5741adc17069fe5bec8edf3c4c2af Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 19 Jun 2014 13:37:10 +0200 Subject: ARM: tegra: jetson-tk1: Add XUSB pad controller Assign lanes to the XUSB pads as used on the Jetson TK1. Tested-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 16082c0bdaca..11c1650624b2 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1619,6 +1619,32 @@ nvidia,sys-clock-req-active-high; }; + padctl@0,7009f000 { + pinctrl-0 = <&padctl_default>; + pinctrl-names = "default"; + + padctl_default: pinmux { + usb3 { + nvidia,lanes = "pcie-0", "pcie-1"; + nvidia,function = "usb3"; + nvidia,iddq = <0>; + }; + + pcie { + nvidia,lanes = "pcie-2", "pcie-3", + "pcie-4"; + nvidia,function = "pcie"; + nvidia,iddq = <0>; + }; + + sata { + nvidia,lanes = "sata-0"; + nvidia,function = "sata"; + nvidia,iddq = <0>; + }; + }; + }; + /* SD card */ sdhci@0,700b0400 { status = "okay"; -- cgit v1.2.3 From ee913f7a15124d85db46833889561eb876f29de0 Mon Sep 17 00:00:00 2001 From: Tuomas Tynkkynen Date: Wed, 9 Jul 2014 21:53:17 +0300 Subject: ARM: tegra: Fix typoed ams,ext-control properties The property for enabling external rail control on the AS3722 is ams,ext-control, not ams,external-control. Since the external rail control property was previously being ignored, LP1 suspend on these boards wasn't actually turning the CPU rail off at all. Signed-off-by: Tuomas Tynkkynen Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 6 +++--- arch/arm/boot/dts/tegra124-venice2.dts | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 11c1650624b2..624b0fba2d0a 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1461,7 +1461,7 @@ regulator-max-microamp = <3500000>; regulator-always-on; regulator-boot-on; - ams,external-control = <2>; + ams,ext-control = <2>; }; sd1 { @@ -1472,7 +1472,7 @@ regulator-max-microamp = <2500000>; regulator-always-on; regulator-boot-on; - ams,external-control = <1>; + ams,ext-control = <1>; }; vdd_1v35_lp0: sd2 { @@ -1521,7 +1521,7 @@ regulator-max-microvolt = <1050000>; regulator-boot-on; regulator-always-on; - ams,external-control = <1>; + ams,ext-control = <1>; }; ldo1 { diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index f1a5bac43c55..70ad91d1a20b 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -682,7 +682,7 @@ regulator-max-microamp = <3500000>; regulator-always-on; regulator-boot-on; - ams,external-control = <2>; + ams,ext-control = <2>; }; sd1 { @@ -693,7 +693,7 @@ regulator-max-microamp = <2500000>; regulator-always-on; regulator-boot-on; - ams,external-control = <1>; + ams,ext-control = <1>; }; vdd_1v35_lp0: sd2 { @@ -742,7 +742,7 @@ regulator-max-microvolt = <1050000>; regulator-boot-on; regulator-always-on; - ams,external-control = <1>; + ams,ext-control = <1>; }; ldo1 { -- cgit v1.2.3 From 2236927d9820199bb6f29f2a89b1783c4513d34f Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 8 Jul 2014 21:32:14 +0900 Subject: ARM: tegra: roth: add display DT node Tegra DSI support has been fixed to support continuous clock behavior that the panel used on SHIELD requires, so finally add its device tree node since it is functional. Signed-off-by: Alexandre Courbot Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-roth.dts | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index ba210c6e189f..c7c6825f11fb 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -28,6 +28,22 @@ reg = <0x80000000 0x79600000>; }; + host1x@50000000 { + dsi@54300000 { + status = "okay"; + + vdd-supply = <&vdd_1v2_ap>; + + panel@0 { + compatible = "lg,lh500wx1-sd03"; + reg = <0>; + + power-supply = <&vdd_lcd>; + backlight = <&backlight>; + }; + }; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -811,7 +827,6 @@ regulator-name = "vdd-1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-always-on; regulator-boot-on; }; @@ -858,10 +873,11 @@ regulator-name = "vdd-2v8-display"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; + regulator-always-on; regulator-boot-on; }; - ldo3 { + vdd_1v2_ap: ldo3 { regulator-name = "avdd-1v2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -1048,7 +1064,7 @@ regulator-boot-on; }; - regulator@1 { + vdd_lcd: regulator@1 { compatible = "regulator-fixed"; reg = <1>; regulator-name = "vdd_lcd_1v8"; -- cgit v1.2.3 From 979c36c850726043a5004c2d8a50290cfb3bfdcf Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Thu, 17 Jul 2014 17:58:07 +0300 Subject: ARM: dts: keystone: add mdio devices entries The Keystone 2 has MDIO HW block which are compatible to Davinci SoCs: See "Gigabit Ethernet (GbE) Switch Subsystem" See http://www.ti.com/lit/ug/sprugv9d/sprugv9d.pdf Hence, add corresponding DT entry for Keystone 2. Signed-off-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index c1414cb81fd4..9e31fe7d31f8 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -266,5 +266,16 @@ ranges = <0 0 0x30000000 0x10000000 1 0 0x21000A00 0x00000100>; }; + + mdio: mdio@02090300 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x02090300 0x100>; + status = "disabled"; + clocks = <&clkpa>; + clock-names = "fck"; + bus_freq = <2500000>; + }; }; }; -- cgit v1.2.3 From 6592f671a4e6ee6308ddd67c2459dd71836770df Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 9 Jul 2014 16:14:19 +0300 Subject: ARM: dts: keystone-evm: add 1g ethernet phys nodes Keystone EVMK2HX has two 1G Marvell 88E1111 Ethernet PHYs installed, so add corresponding child nodes for 1G MDIO bus and enable it. For more information see schematics: http://wfcache.advantech.com/www/support/TI-EVM/download/Schematics/PDF/K2H_K2EVM-HK_SCH_A102_Rev1_0.pdf Signed-off-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/k2hk-evm.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts index 1f90cbf27fd7..3223cc152a85 100644 --- a/arch/arm/boot/dts/k2hk-evm.dts +++ b/arch/arm/boot/dts/k2hk-evm.dts @@ -167,3 +167,15 @@ }; }; }; + +&mdio { + ethphy0: ethernet-phy@0 { + compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; -- cgit v1.2.3 From 743636f25f1da95d05483d8b986dc6a4166fed91 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sun, 11 May 2014 21:59:26 +0800 Subject: ARM: dts: imx: add pin function header for imx6sx Add pin function header for i.MX6 SoloX SoC. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-pinfunc.h | 1544 ++++++++++++++++++++++++++++++++++++ 1 file changed, 1544 insertions(+) create mode 100644 arch/arm/boot/dts/imx6sx-pinfunc.h (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/imx6sx-pinfunc.h new file mode 100644 index 000000000000..3e0b816dac08 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-pinfunc.h @@ -0,0 +1,1544 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_IMX6SX_PINFUNC_H +#define __DTS_IMX6SX_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1 +#define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1 +#define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO01__SPDIF_SR_CLK 0x0018 0x0360 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO01__CCM_STOP 0x0018 0x0360 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO01__WDOG3_WDOG_B 0x0018 0x0360 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x0018 0x0360 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL 0x0018 0x0360 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO01__PHY_DTB_0 0x0018 0x0360 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x001C 0x0364 0x07B0 0x0 0x1 +#define MX6SX_PAD_GPIO1_IO02__USDHC1_CD_B 0x001C 0x0364 0x0864 0x1 0x1 +#define MX6SX_PAD_GPIO1_IO02__CSI2_MCLK 0x001C 0x0364 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK 0x001C 0x0364 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO02__WDOG1_WDOG_B 0x001C 0x0364 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x001C 0x0364 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO02__CCM_REF_EN_B 0x001C 0x0364 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO02__PHY_TDI 0x001C 0x0364 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x0020 0x0368 0x07B4 0x0 0x1 +#define MX6SX_PAD_GPIO1_IO03__USDHC1_WP 0x0020 0x0368 0x0868 0x1 0x1 +#define MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M 0x0020 0x0368 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK 0x0020 0x0368 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO03__WDOG2_WDOG_B 0x0020 0x0368 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x0020 0x0368 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO03__CCM_PLL3_BYP 0x0020 0x0368 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO03__PHY_TCK 0x0020 0x0368 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO04__UART1_RX 0x0024 0x036C 0x0830 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO04__UART1_TX 0x0024 0x036C 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO04__USDHC2_RESET_B 0x0024 0x036C 0x0000 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024 0x036C 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO04__OSC32K_32K_OUT 0x0024 0x036C 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO04__ENET2_REF_CLK2 0x0024 0x036C 0x076C 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4 0x0024 0x036C 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO04__CCM_PLL2_BYP 0x0024 0x036C 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO04__PHY_TMS 0x0024 0x036C 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO05__UART1_RX 0x0028 0x0370 0x0830 0x0 0x1 +#define MX6SX_PAD_GPIO1_IO05__UART1_TX 0x0028 0x0370 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO05__USDHC2_VSELECT 0x0028 0x0370 0x0000 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028 0x0370 0x0764 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK 0x0028 0x0370 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO05__ENET1_REF_CLK1 0x0028 0x0370 0x0760 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5 0x0028 0x0370 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO05__SRC_TESTER_ACK 0x0028 0x0370 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO05__PHY_TDO 0x0028 0x0370 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO06__UART2_RX 0x002C 0x0374 0x0838 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO06__UART2_TX 0x002C 0x0374 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO06__USDHC2_CD_B 0x002C 0x0374 0x086C 0x1 0x1 +#define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B 0x002C 0x0374 0x082C 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO07__UART2_RX 0x0030 0x0378 0x0838 0x0 0x1 +#define MX6SX_PAD_GPIO1_IO07__UART2_TX 0x0030 0x0378 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1 +#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x082C 0x4 0x1 +#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO07__VDEC_DEBUG_44 0x0030 0x0378 0x0000 0x8 0x0 +#define MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x0034 0x037C 0x0860 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0034 0x037C 0x0000 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1 +#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B 0x0034 0x037C 0x0834 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO08__VDEC_DEBUG_43 0x0034 0x037C 0x0000 0x8 0x0 +#define MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR 0x0038 0x0380 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0834 0x4 0x1 +#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO09__VDEC_DEBUG_42 0x0038 0x0380 0x0000 0x8 0x0 +#define MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x003C 0x0384 0x0624 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO10__SPDIF_EXT_CLK 0x003C 0x0384 0x0828 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO10__PWM1_OUT 0x003C 0x0384 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO10__CCM_OUT1 0x003C 0x0384 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO10__CSI1_FIELD 0x003C 0x0384 0x070C 0x4 0x1 +#define MX6SX_PAD_GPIO1_IO10__GPIO1_IO_10 0x003C 0x0384 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO10__CSU_CSU_INT_DEB 0x003C 0x0384 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3 0x003C 0x0384 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO10__VDEC_DEBUG_41 0x003C 0x0384 0x0000 0x8 0x0 +#define MX6SX_PAD_GPIO1_IO11__USB_OTG2_OC 0x0040 0x0388 0x085C 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO11__SPDIF_IN 0x0040 0x0388 0x0824 0x1 0x2 +#define MX6SX_PAD_GPIO1_IO11__PWM2_OUT 0x0040 0x0388 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x0040 0x0388 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO11__MLB_DATA 0x0040 0x0388 0x07EC 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO11__GPIO1_IO_11 0x0040 0x0388 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0 0x0040 0x0388 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2 0x0040 0x0388 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO11__VDEC_DEBUG_40 0x0040 0x0388 0x0000 0x8 0x0 +#define MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR 0x0044 0x038C 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO12__SPDIF_OUT 0x0044 0x038C 0x0000 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x0044 0x038C 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x0044 0x038C 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO12__MLB_CLK 0x0044 0x038C 0x07E8 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x0044 0x038C 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1 0x0044 0x038C 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1 0x0044 0x038C 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO12__VDEC_DEBUG_39 0x0044 0x038C 0x0000 0x8 0x0 +#define MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x0048 0x0390 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x0048 0x0390 0x0628 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x0048 0x0390 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO13__CCM_OUT2 0x0048 0x0390 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO13__MLB_SIG 0x0048 0x0390 0x07F0 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 0x0048 0x0390 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2 0x0048 0x0390 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0 0x0048 0x0390 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO13__VDEC_DEBUG_38 0x0048 0x0390 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x004C 0x0394 0x06A8 0x0 0x0 +#define MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x004C 0x0394 0x078C 0x1 0x1 +#define MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x004C 0x0394 0x0684 0x2 0x1 +#define MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x004C 0x0394 0x07A8 0x3 0x0 +#define MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x004C 0x0394 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA00__GPIO1_IO_14 0x004C 0x0394 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_DATA00__WEIM_DATA_23 0x004C 0x0394 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x004C 0x0394 0x0800 0x7 0x0 +#define MX6SX_PAD_CSI_DATA00__VADC_DATA_4 0x004C 0x0394 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA00__MMDC_DEBUG_37 0x004C 0x0394 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x0050 0x0398 0x06AC 0x0 0x0 +#define MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x0050 0x0398 0x077C 0x1 0x1 +#define MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x0050 0x0398 0x0688 0x2 0x1 +#define MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x0050 0x0398 0x07AC 0x3 0x0 +#define MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x0050 0x0398 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA01__GPIO1_IO_15 0x0050 0x0398 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_DATA01__WEIM_DATA_22 0x0050 0x0398 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x0050 0x0398 0x0804 0x7 0x0 +#define MX6SX_PAD_CSI_DATA01__VADC_DATA_5 0x0050 0x0398 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA01__MMDC_DEBUG_38 0x0050 0x0398 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x0054 0x039C 0x06B0 0x0 0x0 +#define MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x0054 0x039C 0x0788 0x1 0x1 +#define MX6SX_PAD_CSI_DATA02__AUDMUX_AUD6_RXC 0x0054 0x039C 0x067C 0x2 0x1 +#define MX6SX_PAD_CSI_DATA02__KPP_COL_5 0x0054 0x039C 0x07C8 0x3 0x0 +#define MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x0054 0x039C 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA02__GPIO1_IO_16 0x0054 0x039C 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_DATA02__WEIM_DATA_21 0x0054 0x039C 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x0054 0x039C 0x07F4 0x7 0x0 +#define MX6SX_PAD_CSI_DATA02__VADC_DATA_6 0x0054 0x039C 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA02__MMDC_DEBUG_39 0x0054 0x039C 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x0058 0x03A0 0x06B4 0x0 0x0 +#define MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x0058 0x03A0 0x0778 0x1 0x1 +#define MX6SX_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS 0x0058 0x03A0 0x0680 0x2 0x1 +#define MX6SX_PAD_CSI_DATA03__KPP_ROW_5 0x0058 0x03A0 0x07D4 0x3 0x0 +#define MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x0058 0x03A0 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x0058 0x03A0 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_DATA03__WEIM_DATA_20 0x0058 0x03A0 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x0058 0x03A0 0x07FC 0x7 0x0 +#define MX6SX_PAD_CSI_DATA03__VADC_DATA_7 0x0058 0x03A0 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA03__MMDC_DEBUG_40 0x0058 0x03A0 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x005C 0x03A4 0x06B8 0x0 0x0 +#define MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x005C 0x03A4 0x0794 0x1 0x1 +#define MX6SX_PAD_CSI_DATA04__SPDIF_OUT 0x005C 0x03A4 0x0000 0x2 0x0 +#define MX6SX_PAD_CSI_DATA04__KPP_COL_6 0x005C 0x03A4 0x07CC 0x3 0x0 +#define MX6SX_PAD_CSI_DATA04__UART6_RX 0x005C 0x03A4 0x0858 0x4 0x0 +#define MX6SX_PAD_CSI_DATA04__UART6_TX 0x005C 0x03A4 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x005C 0x03A4 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_DATA04__WEIM_DATA_19 0x005C 0x03A4 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_DATA04__PWM5_OUT 0x005C 0x03A4 0x0000 0x7 0x0 +#define MX6SX_PAD_CSI_DATA04__VADC_DATA_8 0x005C 0x03A4 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA04__MMDC_DEBUG_41 0x005C 0x03A4 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x0060 0x03A8 0x06BC 0x0 0x0 +#define MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x0060 0x03A8 0x07A0 0x1 0x1 +#define MX6SX_PAD_CSI_DATA05__SPDIF_IN 0x0060 0x03A8 0x0824 0x2 0x1 +#define MX6SX_PAD_CSI_DATA05__KPP_ROW_6 0x0060 0x03A8 0x07D8 0x3 0x0 +#define MX6SX_PAD_CSI_DATA05__UART6_RX 0x0060 0x03A8 0x0858 0x4 0x1 +#define MX6SX_PAD_CSI_DATA05__UART6_TX 0x0060 0x03A8 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x0060 0x03A8 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_DATA05__WEIM_DATA_18 0x0060 0x03A8 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_DATA05__PWM6_OUT 0x0060 0x03A8 0x0000 0x7 0x0 +#define MX6SX_PAD_CSI_DATA05__VADC_DATA_9 0x0060 0x03A8 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA05__MMDC_DEBUG_42 0x0060 0x03A8 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x0064 0x03AC 0x06C0 0x0 0x0 +#define MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x0064 0x03AC 0x0798 0x1 0x1 +#define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2 +#define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0 +#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x0064 0x03AC 0x0854 0x4 0x0 +#define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0 +#define MX6SX_PAD_CSI_DATA06__VADC_DATA_10 0x0064 0x03AC 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA06__MMDC_DEBUG_43 0x0064 0x03AC 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x0068 0x03B0 0x06C4 0x0 0x0 +#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1 +#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2 +#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0 +#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0854 0x4 0x1 +#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0 +#define MX6SX_PAD_CSI_DATA07__VADC_DATA_11 0x0068 0x03B0 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA07__MMDC_DEBUG_44 0x0068 0x03B0 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x006C 0x03B4 0x0700 0x0 0x0 +#define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1 +#define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1 +#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C 0x03B4 0x0844 0x3 0x2 +#define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x006C 0x03B4 0x0000 0x7 0x0 +#define MX6SX_PAD_CSI_HSYNC__VADC_DATA_2 0x006C 0x03B4 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_HSYNC__MMDC_DEBUG_35 0x006C 0x03B4 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x0070 0x03B8 0x0000 0x0 0x0 +#define MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x0070 0x03B8 0x0784 0x1 0x1 +#define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x0070 0x03B8 0x0000 0x2 0x0 +#define MX6SX_PAD_CSI_MCLK__UART4_RX 0x0070 0x03B8 0x0848 0x3 0x2 +#define MX6SX_PAD_CSI_MCLK__UART4_TX 0x0070 0x03B8 0x0000 0x3 0x0 +#define MX6SX_PAD_CSI_MCLK__ANATOP_32K_OUT 0x0070 0x03B8 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_MCLK__GPIO1_IO_23 0x0070 0x03B8 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_MCLK__WEIM_DATA_26 0x0070 0x03B8 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_MCLK__CSI1_FIELD 0x0070 0x03B8 0x070C 0x7 0x0 +#define MX6SX_PAD_CSI_MCLK__VADC_DATA_1 0x0070 0x03B8 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_MCLK__MMDC_DEBUG_34 0x0070 0x03B8 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x0074 0x03BC 0x0704 0x0 0x0 +#define MX6SX_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK 0x0074 0x03BC 0x0780 0x1 0x1 +#define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x0074 0x03BC 0x0000 0x2 0x0 +#define MX6SX_PAD_CSI_PIXCLK__UART4_RX 0x0074 0x03BC 0x0848 0x3 0x3 +#define MX6SX_PAD_CSI_PIXCLK__UART4_TX 0x0074 0x03BC 0x0000 0x3 0x0 +#define MX6SX_PAD_CSI_PIXCLK__ANATOP_24M_OUT 0x0074 0x03BC 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x0074 0x03BC 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_PIXCLK__WEIM_DATA_27 0x0074 0x03BC 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK 0x0074 0x03BC 0x0784 0x7 0x2 +#define MX6SX_PAD_CSI_PIXCLK__VADC_CLK 0x0074 0x03BC 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_PIXCLK__MMDC_DEBUG_33 0x0074 0x03BC 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0 +#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1 +#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1 +#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0844 0x3 0x3 +#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x0078 0x03C0 0x07F8 0x7 0x0 +#define MX6SX_PAD_CSI_VSYNC__VADC_DATA_3 0x0078 0x03C0 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_VSYNC__MMDC_DEBUG_36 0x0078 0x03C0 0x0000 0x9 0x0 +#define MX6SX_PAD_ENET1_COL__ENET1_COL 0x007C 0x03C4 0x0000 0x0 0x0 +#define MX6SX_PAD_ENET1_COL__ENET2_MDC 0x007C 0x03C4 0x0000 0x1 0x0 +#define MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x007C 0x03C4 0x0654 0x2 0x1 +#define MX6SX_PAD_ENET1_COL__UART1_RI_B 0x007C 0x03C4 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET1_COL__SPDIF_EXT_CLK 0x007C 0x03C4 0x0828 0x4 0x1 +#define MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x007C 0x03C4 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET1_COL__CSI2_DATA_23 0x007C 0x03C4 0x0000 0x6 0x0 +#define MX6SX_PAD_ENET1_COL__LCDIF2_DATA_16 0x007C 0x03C4 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET1_COL__VDEC_DEBUG_37 0x007C 0x03C4 0x0000 0x8 0x0 +#define MX6SX_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31 0x007C 0x03C4 0x0000 0x9 0x0 +#define MX6SX_PAD_ENET1_CRS__ENET1_CRS 0x0080 0x03C8 0x0000 0x0 0x0 +#define MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0x0080 0x03C8 0x0770 0x1 0x1 +#define MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x0080 0x03C8 0x0648 0x2 0x1 +#define MX6SX_PAD_ENET1_CRS__UART1_DCD_B 0x0080 0x03C8 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET1_CRS__SPDIF_LOCK 0x0080 0x03C8 0x0000 0x4 0x0 +#define MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x0080 0x03C8 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET1_CRS__CSI2_DATA_22 0x0080 0x03C8 0x0000 0x6 0x0 +#define MX6SX_PAD_ENET1_CRS__LCDIF2_DATA_17 0x0080 0x03C8 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET1_CRS__VDEC_DEBUG_36 0x0080 0x03C8 0x0000 0x8 0x0 +#define MX6SX_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30 0x0080 0x03C8 0x0000 0x9 0x0 +#define MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x0084 0x03CC 0x0000 0x0 0x0 +#define MX6SX_PAD_ENET1_MDC__ENET2_MDC 0x0084 0x03CC 0x0000 0x1 0x0 +#define MX6SX_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS 0x0084 0x03CC 0x0638 0x2 0x1 +#define MX6SX_PAD_ENET1_MDC__ANATOP_24M_OUT 0x0084 0x03CC 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET1_MDC__EPIT2_OUT 0x0084 0x03CC 0x0000 0x4 0x0 +#define MX6SX_PAD_ENET1_MDC__GPIO2_IO_2 0x0084 0x03CC 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET1_MDC__USB_OTG1_PWR 0x0084 0x03CC 0x0000 0x6 0x0 +#define MX6SX_PAD_ENET1_MDC__PWM7_OUT 0x0084 0x03CC 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x0088 0x03D0 0x0764 0x0 0x1 +#define MX6SX_PAD_ENET1_MDIO__ENET2_MDIO 0x0088 0x03D0 0x0770 0x1 0x2 +#define MX6SX_PAD_ENET1_MDIO__AUDMUX_MCLK 0x0088 0x03D0 0x0000 0x2 0x0 +#define MX6SX_PAD_ENET1_MDIO__OSC32K_32K_OUT 0x0088 0x03D0 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET1_MDIO__EPIT1_OUT 0x0088 0x03D0 0x0000 0x4 0x0 +#define MX6SX_PAD_ENET1_MDIO__GPIO2_IO_3 0x0088 0x03D0 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET1_MDIO__USB_OTG1_OC 0x0088 0x03D0 0x0860 0x6 0x1 +#define MX6SX_PAD_ENET1_MDIO__PWM8_OUT 0x0088 0x03D0 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x008C 0x03D4 0x0768 0x0 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M 0x008C 0x03D4 0x0000 0x1 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x008C 0x03D4 0x0658 0x2 0x1 +#define MX6SX_PAD_ENET1_RX_CLK__UART1_DSR_B 0x008C 0x03D4 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x008C 0x03D4 0x0000 0x4 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0x008C 0x03D4 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__CSI2_DATA_21 0x008C 0x03D4 0x0000 0x6 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__LCDIF2_DATA_18 0x008C 0x03D4 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0 +#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0 +#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1 +#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1 +#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET1_TX_CLK__SPDIF_SR_CLK 0x0090 0x03D8 0x0000 0x4 0x0 +#define MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0x0090 0x03D8 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET1_TX_CLK__CSI2_DATA_20 0x0090 0x03D8 0x0000 0x6 0x0 +#define MX6SX_PAD_ENET1_TX_CLK__LCDIF2_DATA_19 0x0090 0x03D8 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET1_TX_CLK__VDEC_DEBUG_34 0x0090 0x03D8 0x0000 0x8 0x0 +#define MX6SX_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28 0x0090 0x03D8 0x0000 0x9 0x0 +#define MX6SX_PAD_ENET2_COL__ENET2_COL 0x0094 0x03DC 0x0000 0x0 0x0 +#define MX6SX_PAD_ENET2_COL__ENET1_MDC 0x0094 0x03DC 0x0000 0x1 0x0 +#define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC 0x0094 0x03DC 0x064C 0x2 0x1 +#define MX6SX_PAD_ENET2_COL__UART1_RX 0x0094 0x03DC 0x0830 0x3 0x2 +#define MX6SX_PAD_ENET2_COL__UART1_TX 0x0094 0x03DC 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET2_COL__SPDIF_IN 0x0094 0x03DC 0x0824 0x4 0x3 +#define MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x0094 0x03DC 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x0094 0x03DC 0x0624 0x6 0x1 +#define MX6SX_PAD_ENET2_COL__LCDIF2_DATA_20 0x0094 0x03DC 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET2_COL__VDEC_DEBUG_33 0x0094 0x03DC 0x0000 0x8 0x0 +#define MX6SX_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27 0x0094 0x03DC 0x0000 0x9 0x0 +#define MX6SX_PAD_ENET2_CRS__ENET2_CRS 0x0098 0x03E0 0x0000 0x0 0x0 +#define MX6SX_PAD_ENET2_CRS__ENET1_MDIO 0x0098 0x03E0 0x0764 0x1 0x2 +#define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS 0x0098 0x03E0 0x0650 0x2 0x1 +#define MX6SX_PAD_ENET2_CRS__UART1_RX 0x0098 0x03E0 0x0830 0x3 0x3 +#define MX6SX_PAD_ENET2_CRS__UART1_TX 0x0098 0x03E0 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET2_CRS__MLB_SIG 0x0098 0x03E0 0x07F0 0x4 0x1 +#define MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x0098 0x03E0 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x0098 0x03E0 0x0628 0x6 0x1 +#define MX6SX_PAD_ENET2_CRS__LCDIF2_DATA_21 0x0098 0x03E0 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET2_CRS__VDEC_DEBUG_32 0x0098 0x03E0 0x0000 0x8 0x0 +#define MX6SX_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26 0x0098 0x03E0 0x0000 0x9 0x0 +#define MX6SX_PAD_ENET2_RX_CLK__ENET2_RX_CLK 0x009C 0x03E4 0x0774 0x0 0x0 +#define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0 +#define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1 +#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C 0x03E4 0x082C 0x3 0x2 +#define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1 +#define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1 +#define MX6SX_PAD_ENET2_RX_CLK__LCDIF2_DATA_22 0x009C 0x03E4 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET2_RX_CLK__VDEC_DEBUG_31 0x009C 0x03E4 0x0000 0x8 0x0 +#define MX6SX_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25 0x009C 0x03E4 0x0000 0x9 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1 +#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1 +#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x082C 0x3 0x3 +#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1 +#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__LCDIF2_DATA_23 0x00A0 0x03E8 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__VDEC_DEBUG_30 0x00A0 0x03E8 0x0000 0x8 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 0x00A0 0x03E8 0x0000 0x9 0x0 +#define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0 +#define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4 0x03EC 0x0854 0x2 0x2 +#define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0 +#define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0 +#define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_COL0__SDMA_EXT_EVENT_1 0x00A4 0x03EC 0x0820 0x6 0x1 +#define MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x00A4 0x03EC 0x0814 0x7 0x0 +#define MX6SX_PAD_KEY_COL0__VADC_DATA_0 0x00A4 0x03EC 0x0000 0x8 0x0 +#define MX6SX_PAD_KEY_COL1__KPP_COL_1 0x00A8 0x03F0 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_COL1__USDHC3_RESET_B 0x00A8 0x03F0 0x0000 0x1 0x0 +#define MX6SX_PAD_KEY_COL1__UART6_RX 0x00A8 0x03F0 0x0858 0x2 0x2 +#define MX6SX_PAD_KEY_COL1__UART6_TX 0x00A8 0x03F0 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x00A8 0x03F0 0x0714 0x3 0x0 +#define MX6SX_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x00A8 0x03F0 0x0670 0x4 0x0 +#define MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x00A8 0x03F0 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_COL1__USDHC3_RESET 0x00A8 0x03F0 0x0000 0x6 0x0 +#define MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x00A8 0x03F0 0x0818 0x7 0x0 +#define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1 +#define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC 0x03F4 0x084C 0x2 0x2 +#define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0 +#define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0 +#define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_COL2__WEIM_DATA_30 0x00AC 0x03F4 0x0000 0x6 0x0 +#define MX6SX_PAD_KEY_COL2__ECSPI1_RDY 0x00AC 0x03F4 0x0000 0x7 0x0 +#define MX6SX_PAD_KEY_COL3__KPP_COL_3 0x00B0 0x03F8 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_COL3__USDHC4_LCTL 0x00B0 0x03F8 0x0000 0x1 0x0 +#define MX6SX_PAD_KEY_COL3__UART5_RX 0x00B0 0x03F8 0x0850 0x2 0x2 +#define MX6SX_PAD_KEY_COL3__UART5_TX 0x00B0 0x03F8 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_COL3__CAN2_TX 0x00B0 0x03F8 0x0000 0x3 0x0 +#define MX6SX_PAD_KEY_COL3__CANFD_TX2 0x00B0 0x03F8 0x0000 0x4 0x0 +#define MX6SX_PAD_KEY_COL3__GPIO2_IO_13 0x00B0 0x03F8 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_COL3__WEIM_DATA_28 0x00B0 0x03F8 0x0000 0x6 0x0 +#define MX6SX_PAD_KEY_COL3__ECSPI1_SS2 0x00B0 0x03F8 0x0000 0x7 0x0 +#define MX6SX_PAD_KEY_COL4__KPP_COL_4 0x00B4 0x03FC 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_COL4__ENET2_MDC 0x00B4 0x03FC 0x0000 0x1 0x0 +#define MX6SX_PAD_KEY_COL4__I2C3_SCL 0x00B4 0x03FC 0x07B8 0x2 0x2 +#define MX6SX_PAD_KEY_COL4__USDHC2_LCTL 0x00B4 0x03FC 0x0000 0x3 0x0 +#define MX6SX_PAD_KEY_COL4__AUDMUX_AUD5_RXC 0x00B4 0x03FC 0x0664 0x4 0x0 +#define MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x00B4 0x03FC 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_COL4__WEIM_CRE 0x00B4 0x03FC 0x0000 0x6 0x0 +#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0 +#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0 +#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0854 0x2 0x3 +#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0 +#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0 +#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_ROW0__SDMA_EXT_EVENT_0 0x00B8 0x0400 0x081C 0x6 0x1 +#define MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x00B8 0x0400 0x0000 0x7 0x0 +#define MX6SX_PAD_KEY_ROW0__GPU_IDLE 0x00B8 0x0400 0x0000 0x8 0x0 +#define MX6SX_PAD_KEY_ROW1__KPP_ROW_1 0x00BC 0x0404 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_ROW1__USDHC4_VSELECT 0x00BC 0x0404 0x0000 0x1 0x0 +#define MX6SX_PAD_KEY_ROW1__UART6_RX 0x00BC 0x0404 0x0858 0x2 0x3 +#define MX6SX_PAD_KEY_ROW1__UART6_TX 0x00BC 0x0404 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW1__ECSPI1_SS0 0x00BC 0x0404 0x071C 0x3 0x0 +#define MX6SX_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x00BC 0x0404 0x065C 0x4 0x0 +#define MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x00BC 0x0404 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_ROW1__WEIM_DATA_31 0x00BC 0x0404 0x0000 0x6 0x0 +#define MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x00BC 0x0404 0x080C 0x7 0x0 +#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0 +#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1 +#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x084C 0x2 0x3 +#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1 +#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1 +#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_ROW2__WEIM_DATA_29 0x00C0 0x0408 0x0000 0x6 0x0 +#define MX6SX_PAD_KEY_ROW2__ECSPI1_SS3 0x00C0 0x0408 0x0000 0x7 0x0 +#define MX6SX_PAD_KEY_ROW3__KPP_ROW_3 0x00C4 0x040C 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_ROW3__USDHC3_LCTL 0x00C4 0x040C 0x0000 0x1 0x0 +#define MX6SX_PAD_KEY_ROW3__UART5_RX 0x00C4 0x040C 0x0850 0x2 0x3 +#define MX6SX_PAD_KEY_ROW3__UART5_TX 0x00C4 0x040C 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW3__CAN2_RX 0x00C4 0x040C 0x0690 0x3 0x1 +#define MX6SX_PAD_KEY_ROW3__CANFD_RX2 0x00C4 0x040C 0x0698 0x4 0x1 +#define MX6SX_PAD_KEY_ROW3__GPIO2_IO_18 0x00C4 0x040C 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_ROW3__WEIM_DTACK_B 0x00C4 0x040C 0x0000 0x6 0x0 +#define MX6SX_PAD_KEY_ROW3__ECSPI1_SS1 0x00C4 0x040C 0x0000 0x7 0x0 +#define MX6SX_PAD_KEY_ROW4__KPP_ROW_4 0x00C8 0x0410 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_ROW4__ENET2_MDIO 0x00C8 0x0410 0x0770 0x1 0x3 +#define MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x00C8 0x0410 0x07BC 0x2 0x2 +#define MX6SX_PAD_KEY_ROW4__USDHC1_LCTL 0x00C8 0x0410 0x0000 0x3 0x0 +#define MX6SX_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS 0x00C8 0x0410 0x0668 0x4 0x0 +#define MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x00C8 0x0410 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_ROW4__WEIM_ACLK_FREERUN 0x00C8 0x0410 0x0000 0x6 0x0 +#define MX6SX_PAD_KEY_ROW4__SAI2_RX_SYNC 0x00C8 0x0410 0x0810 0x7 0x0 +#define MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x00CC 0x0414 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_CLK__LCDIF1_WR_RWN 0x00CC 0x0414 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_CLK__AUDMUX_AUD3_RXC 0x00CC 0x0414 0x0634 0x2 0x1 +#define MX6SX_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN 0x00CC 0x0414 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_CLK__CSI1_DATA_16 0x00CC 0x0414 0x06DC 0x4 0x0 +#define MX6SX_PAD_LCD1_CLK__GPIO3_IO_0 0x00CC 0x0414 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_CLK__USDHC1_WP 0x00CC 0x0414 0x0868 0x6 0x0 +#define MX6SX_PAD_LCD1_CLK__SIM_M_HADDR_16 0x00CC 0x0414 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_CLK__VADC_TEST_0 0x00CC 0x0414 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_CLK__MMDC_DEBUG_0 0x00CC 0x0414 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x00D0 0x0418 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA00__WEIM_CS1_B 0x00D0 0x0418 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA00__M4_TRACE_0 0x00D0 0x0418 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA00__KITTEN_TRACE_0 0x00D0 0x0418 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA00__CSI1_DATA_20 0x00D0 0x0418 0x06EC 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1 0x00D0 0x0418 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA00__SRC_BT_CFG_0 0x00D0 0x0418 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA00__SIM_M_HADDR_21 0x00D0 0x0418 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA00__VADC_TEST_5 0x00D0 0x0418 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA00__MMDC_DEBUG_5 0x00D0 0x0418 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x00D4 0x041C 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA01__WEIM_CS2_B 0x00D4 0x041C 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA01__M4_TRACE_1 0x00D4 0x041C 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA01__KITTEN_TRACE_1 0x00D4 0x041C 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA01__CSI1_DATA_21 0x00D4 0x041C 0x06F0 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA01__GPIO3_IO_2 0x00D4 0x041C 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA01__SRC_BT_CFG_1 0x00D4 0x041C 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA01__SIM_M_HADDR_22 0x00D4 0x041C 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA01__VADC_TEST_6 0x00D4 0x041C 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA01__MMDC_DEBUG_6 0x00D4 0x041C 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x00D8 0x0420 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA02__WEIM_CS3_B 0x00D8 0x0420 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA02__M4_TRACE_2 0x00D8 0x0420 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA02__KITTEN_TRACE_2 0x00D8 0x0420 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA02__CSI1_DATA_22 0x00D8 0x0420 0x06F4 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3 0x00D8 0x0420 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA02__SRC_BT_CFG_2 0x00D8 0x0420 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA02__SIM_M_HADDR_23 0x00D8 0x0420 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA02__VADC_TEST_7 0x00D8 0x0420 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA02__MMDC_DEBUG_7 0x00D8 0x0420 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x00DC 0x0424 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0x00DC 0x0424 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA03__M4_TRACE_3 0x00DC 0x0424 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA03__KITTEN_TRACE_3 0x00DC 0x0424 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA03__CSI1_DATA_23 0x00DC 0x0424 0x06F8 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA03__GPIO3_IO_4 0x00DC 0x0424 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA03__SRC_BT_CFG_3 0x00DC 0x0424 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA03__SIM_M_HADDR_24 0x00DC 0x0424 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA03__VADC_TEST_8 0x00DC 0x0424 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA03__MMDC_DEBUG_8 0x00DC 0x0424 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x00E0 0x0428 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0x00E0 0x0428 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA04__KITTEN_TRACE_4 0x00E0 0x0428 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x00E0 0x0428 0x0708 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA04__GPIO3_IO_5 0x00E0 0x0428 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA04__SRC_BT_CFG_4 0x00E0 0x0428 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA04__SIM_M_HADDR_25 0x00E0 0x0428 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA04__VADC_TEST_9 0x00E0 0x0428 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA04__MMDC_DEBUG_9 0x00E0 0x0428 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x00E4 0x042C 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0x00E4 0x042C 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA05__KITTEN_TRACE_5 0x00E4 0x042C 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x00E4 0x042C 0x0700 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA05__GPIO3_IO_6 0x00E4 0x042C 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA05__SRC_BT_CFG_5 0x00E4 0x042C 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA05__SIM_M_HADDR_26 0x00E4 0x042C 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA05__VADC_TEST_10 0x00E4 0x042C 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA05__MMDC_DEBUG_10 0x00E4 0x042C 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x00E8 0x0430 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA06__WEIM_EB_B_2 0x00E8 0x0430 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA06__KITTEN_TRACE_6 0x00E8 0x0430 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x00E8 0x0430 0x0704 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA06__GPIO3_IO_7 0x00E8 0x0430 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA06__SRC_BT_CFG_6 0x00E8 0x0430 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA06__SIM_M_HADDR_27 0x00E8 0x0430 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA06__VADC_TEST_11 0x00E8 0x0430 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA06__MMDC_DEBUG_11 0x00E8 0x0430 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x00EC 0x0434 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA07__WEIM_EB_B_3 0x00EC 0x0434 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA07__KITTEN_TRACE_7 0x00EC 0x0434 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x00EC 0x0434 0x0000 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA07__GPIO3_IO_8 0x00EC 0x0434 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA07__SRC_BT_CFG_7 0x00EC 0x0434 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA07__SIM_M_HADDR_28 0x00EC 0x0434 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA07__VADC_TEST_12 0x00EC 0x0434 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA07__MMDC_DEBUG_12 0x00EC 0x0434 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x00F0 0x0438 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0x00F0 0x0438 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA08__KITTEN_TRACE_8 0x00F0 0x0438 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x00F0 0x0438 0x06C4 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA08__GPIO3_IO_9 0x00F0 0x0438 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA08__SRC_BT_CFG_8 0x00F0 0x0438 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA08__SIM_M_HADDR_29 0x00F0 0x0438 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA08__VADC_TEST_13 0x00F0 0x0438 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA08__MMDC_DEBUG_13 0x00F0 0x0438 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x00F4 0x043C 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0x00F4 0x043C 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA09__KITTEN_TRACE_9 0x00F4 0x043C 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x00F4 0x043C 0x06C0 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA09__GPIO3_IO_10 0x00F4 0x043C 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA09__SRC_BT_CFG_9 0x00F4 0x043C 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA09__SIM_M_HADDR_30 0x00F4 0x043C 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA09__VADC_TEST_14 0x00F4 0x043C 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA09__MMDC_DEBUG_14 0x00F4 0x043C 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x00F8 0x0440 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0x00F8 0x0440 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA10__KITTEN_TRACE_10 0x00F8 0x0440 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x00F8 0x0440 0x06BC 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA10__GPIO3_IO_11 0x00F8 0x0440 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA10__SRC_BT_CFG_10 0x00F8 0x0440 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA10__SIM_M_HADDR_31 0x00F8 0x0440 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA10__VADC_TEST_15 0x00F8 0x0440 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA10__MMDC_DEBUG_15 0x00F8 0x0440 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x00FC 0x0444 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0x00FC 0x0444 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA11__KITTEN_TRACE_11 0x00FC 0x0444 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x00FC 0x0444 0x06B8 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA11__GPIO3_IO_12 0x00FC 0x0444 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA11__SRC_BT_CFG_11 0x00FC 0x0444 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA11__SIM_M_HBURST_0 0x00FC 0x0444 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA11__VADC_TEST_16 0x00FC 0x0444 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA11__MMDC_DEBUG_16 0x00FC 0x0444 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x0100 0x0448 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0x0100 0x0448 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA12__KITTEN_TRACE_12 0x0100 0x0448 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x0100 0x0448 0x06B4 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA12__GPIO3_IO_13 0x0100 0x0448 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA12__SRC_BT_CFG_12 0x0100 0x0448 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA12__SIM_M_HBURST_1 0x0100 0x0448 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA12__VADC_TEST_17 0x0100 0x0448 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA12__MMDC_DEBUG_17 0x0100 0x0448 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x0104 0x044C 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0x0104 0x044C 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA13__KITTEN_TRACE_13 0x0104 0x044C 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x0104 0x044C 0x06B0 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA13__GPIO3_IO_14 0x0104 0x044C 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA13__SRC_BT_CFG_13 0x0104 0x044C 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA13__SIM_M_HBURST_2 0x0104 0x044C 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA13__VADC_TEST_18 0x0104 0x044C 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA13__MMDC_DEBUG_18 0x0104 0x044C 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x0108 0x0450 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0x0108 0x0450 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA14__KITTEN_TRACE_14 0x0108 0x0450 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x0108 0x0450 0x06AC 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA14__GPIO3_IO_15 0x0108 0x0450 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA14__SRC_BT_CFG_14 0x0108 0x0450 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA14__SIM_M_HMASTLOCK 0x0108 0x0450 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA14__VADC_TEST_19 0x0108 0x0450 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA14__MMDC_DEBUG_19 0x0108 0x0450 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x010C 0x0454 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0x010C 0x0454 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA15__KITTEN_TRACE_15 0x010C 0x0454 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x010C 0x0454 0x06A8 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA15__GPIO3_IO_16 0x010C 0x0454 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA15__SRC_BT_CFG_15 0x010C 0x0454 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA15__SIM_M_HPROT_0 0x010C 0x0454 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA15__VDEC_DEBUG_0 0x010C 0x0454 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA15__MMDC_DEBUG_20 0x010C 0x0454 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x0110 0x0458 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0x0110 0x0458 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA16__M4_TRACE_CLK 0x0110 0x0458 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA16__KITTEN_TRACE_CLK 0x0110 0x0458 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x0110 0x0458 0x06A4 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA16__GPIO3_IO_17 0x0110 0x0458 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA16__SRC_BT_CFG_24 0x0110 0x0458 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA16__SIM_M_HPROT_1 0x0110 0x0458 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA16__VDEC_DEBUG_1 0x0110 0x0458 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA16__MMDC_DEBUG_21 0x0110 0x0458 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x0114 0x045C 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0x0114 0x045C 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA17__KITTEN_TRACE_CTL 0x0114 0x045C 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x0114 0x045C 0x06A0 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA17__GPIO3_IO_18 0x0114 0x045C 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA17__SRC_BT_CFG_25 0x0114 0x045C 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA17__SIM_M_HPROT_2 0x0114 0x045C 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA17__VDEC_DEBUG_2 0x0114 0x045C 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA17__MMDC_DEBUG_22 0x0114 0x045C 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x0118 0x0460 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0x0118 0x0460 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA18__M4_EVENTO 0x0118 0x0460 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA18__KITTEN_EVENTO 0x0118 0x0460 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA18__CSI1_DATA_15 0x0118 0x0460 0x06D8 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x0118 0x0460 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA18__SRC_BT_CFG_26 0x0118 0x0460 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA18__SIM_M_HPROT_3 0x0118 0x0460 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA18__VDEC_DEBUG_3 0x0118 0x0460 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA18__MMDC_DEBUG_23 0x0118 0x0460 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x011C 0x0464 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0x011C 0x0464 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA19__M4_TRACE_SWO 0x011C 0x0464 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA19__CSI1_DATA_14 0x011C 0x0464 0x06D4 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA19__GPIO3_IO_20 0x011C 0x0464 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA19__SRC_BT_CFG_27 0x011C 0x0464 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA19__SIM_M_HREADYOUT 0x011C 0x0464 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA19__VDEC_DEBUG_4 0x011C 0x0464 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA19__MMDC_DEBUG_24 0x011C 0x0464 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x0120 0x0468 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0x0120 0x0468 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA20__PWM8_OUT 0x0120 0x0468 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT 0x0120 0x0468 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA20__CSI1_DATA_13 0x0120 0x0468 0x06D0 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA20__GPIO3_IO_21 0x0120 0x0468 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA20__SRC_BT_CFG_28 0x0120 0x0468 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA20__SIM_M_HRESP 0x0120 0x0468 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA20__VDEC_DEBUG_5 0x0120 0x0468 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA20__MMDC_DEBUG_25 0x0120 0x0468 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x0124 0x046C 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0x0124 0x046C 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA21__PWM7_OUT 0x0124 0x046C 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT 0x0124 0x046C 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA21__CSI1_DATA_12 0x0124 0x046C 0x06CC 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA21__GPIO3_IO_22 0x0124 0x046C 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA21__SRC_BT_CFG_29 0x0124 0x046C 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA21__SIM_M_HSIZE_0 0x0124 0x046C 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA21__VDEC_DEBUG_6 0x0124 0x046C 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA21__MMDC_DEBUG_26 0x0124 0x046C 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x0128 0x0470 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0x0128 0x0470 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA22__PWM6_OUT 0x0128 0x0470 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT 0x0128 0x0470 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA22__CSI1_DATA_11 0x0128 0x0470 0x06C8 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA22__GPIO3_IO_23 0x0128 0x0470 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA22__SRC_BT_CFG_30 0x0128 0x0470 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA22__SIM_M_HSIZE_1 0x0128 0x0470 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA22__VDEC_DEBUG_7 0x0128 0x0470 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA22__MMDC_DEBUG_27 0x0128 0x0470 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x012C 0x0474 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23 0x012C 0x0474 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA23__PWM5_OUT 0x012C 0x0474 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT 0x012C 0x0474 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA23__CSI1_DATA_10 0x012C 0x0474 0x06FC 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24 0x012C 0x0474 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA23__SRC_BT_CFG_31 0x012C 0x0474 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA23__SIM_M_HSIZE_2 0x012C 0x0474 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA23__VDEC_DEBUG_8 0x012C 0x0474 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA23__MMDC_DEBUG_28 0x012C 0x0474 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x0130 0x0478 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_RD_E 0x0130 0x0478 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC 0x0130 0x0478 0x063C 0x2 0x1 +#define MX6SX_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN 0x0130 0x0478 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_ENABLE__CSI1_DATA_17 0x0130 0x0478 0x06E0 0x4 0x0 +#define MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x0130 0x0478 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_ENABLE__USDHC1_CD_B 0x0130 0x0478 0x0864 0x6 0x0 +#define MX6SX_PAD_LCD1_ENABLE__SIM_M_HADDR_17 0x0130 0x0478 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_ENABLE__VADC_TEST_1 0x0130 0x0478 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_ENABLE__MMDC_DEBUG_1 0x0130 0x0478 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x0134 0x047C 0x07E0 0x0 0x0 +#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_RS 0x0134 0x047C 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD 0x0134 0x047C 0x0630 0x2 0x1 +#define MX6SX_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN 0x0134 0x047C 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_HSYNC__CSI1_DATA_18 0x0134 0x047C 0x06E4 0x4 0x0 +#define MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x0134 0x047C 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_HSYNC__USDHC2_WP 0x0134 0x047C 0x0870 0x6 0x0 +#define MX6SX_PAD_LCD1_HSYNC__SIM_M_HADDR_18 0x0134 0x047C 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_HSYNC__VADC_TEST_2 0x0134 0x047C 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_HSYNC__MMDC_DEBUG_2 0x0134 0x047C 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_RESET__LCDIF1_RESET 0x0138 0x0480 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_RESET__LCDIF1_CS 0x0138 0x0480 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_RESET__AUDMUX_AUD3_RXD 0x0138 0x0480 0x062C 0x2 0x1 +#define MX6SX_PAD_LCD1_RESET__KITTEN_EVENTI 0x0138 0x0480 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_RESET__M4_EVENTI 0x0138 0x0480 0x0000 0x4 0x0 +#define MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x0138 0x0480 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_RESET__CCM_PMIC_RDY 0x0138 0x0480 0x069C 0x6 0x0 +#define MX6SX_PAD_LCD1_RESET__SIM_M_HADDR_20 0x0138 0x0480 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_RESET__VADC_TEST_4 0x0138 0x0480 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_RESET__MMDC_DEBUG_4 0x0138 0x0480 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x013C 0x0484 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_BUSY 0x013C 0x0484 0x07E0 0x1 0x1 +#define MX6SX_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS 0x013C 0x0484 0x0640 0x2 0x1 +#define MX6SX_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN 0x013C 0x0484 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_VSYNC__CSI1_DATA_19 0x013C 0x0484 0x06E8 0x4 0x0 +#define MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x013C 0x0484 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_VSYNC__USDHC2_CD_B 0x013C 0x0484 0x086C 0x6 0x0 +#define MX6SX_PAD_LCD1_VSYNC__SIM_M_HADDR_19 0x013C 0x0484 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_VSYNC__VADC_TEST_3 0x013C 0x0484 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_VSYNC__MMDC_DEBUG_3 0x013C 0x0484 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0x0140 0x0488 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_ALE__I2C3_SDA 0x0140 0x0488 0x07BC 0x1 0x0 +#define MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x0140 0x0488 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_ALE__ECSPI2_SS0 0x0140 0x0488 0x072C 0x3 0x0 +#define MX6SX_PAD_NAND_ALE__ESAI_TX3_RX2 0x0140 0x0488 0x079C 0x4 0x0 +#define MX6SX_PAD_NAND_ALE__GPIO4_IO_0 0x0140 0x0488 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0x0140 0x0488 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_ALE__TPSMP_HDATA_0 0x0140 0x0488 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN 0x0140 0x0488 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_ALE__SDMA_DEBUG_PC_12 0x0140 0x0488 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0144 0x048C 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_CE0_B__USDHC2_VSELECT 0x0144 0x048C 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x0144 0x048C 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC 0x0144 0x048C 0x0654 0x3 0x0 +#define MX6SX_PAD_NAND_CE0_B__ESAI_TX_CLK 0x0144 0x048C 0x078C 0x4 0x0 +#define MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x0144 0x048C 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_CE0_B__WEIM_LBA_B 0x0144 0x048C 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_CE0_B__TPSMP_HDATA_3 0x0144 0x048C 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ 0x0144 0x048C 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9 0x0144 0x048C 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0148 0x0490 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_CE1_B__USDHC3_RESET_B 0x0148 0x0490 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x0148 0x0490 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD 0x0148 0x0490 0x0648 0x3 0x0 +#define MX6SX_PAD_NAND_CE1_B__ESAI_TX0 0x0148 0x0490 0x0790 0x4 0x0 +#define MX6SX_PAD_NAND_CE1_B__GPIO4_IO_2 0x0148 0x0490 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_CE1_B__WEIM_OE 0x0148 0x0490 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_CE1_B__TPSMP_HDATA_4 0x0148 0x0490 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE 0x0148 0x0490 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 0x0148 0x0490 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0x014C 0x0494 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_CLE__I2C3_SCL 0x014C 0x0494 0x07B8 0x1 0x0 +#define MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x014C 0x0494 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_CLE__ECSPI2_SCLK 0x014C 0x0494 0x0720 0x3 0x0 +#define MX6SX_PAD_NAND_CLE__ESAI_TX2_RX3 0x014C 0x0494 0x0798 0x4 0x0 +#define MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x014C 0x0494 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_CLE__WEIM_BCLK 0x014C 0x0494 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_CLE__TPSMP_CLK 0x014C 0x0494 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP 0x014C 0x0494 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_CLE__SDMA_DEBUG_PC_13 0x014C 0x0494 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0x0150 0x0498 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_DATA00__USDHC1_DATA4 0x0150 0x0498 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x0150 0x0498 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_DATA00__ECSPI5_MISO 0x0150 0x0498 0x0754 0x3 0x0 +#define MX6SX_PAD_NAND_DATA00__ESAI_RX_CLK 0x0150 0x0498 0x0788 0x4 0x0 +#define MX6SX_PAD_NAND_DATA00__GPIO4_IO_4 0x0150 0x0498 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0x0150 0x0498 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_DATA00__TPSMP_HDATA_7 0x0150 0x0498 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET 0x0150 0x0498 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5 0x0150 0x0498 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0x0154 0x049C 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_DATA01__USDHC1_DATA5 0x0154 0x049C 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x0154 0x049C 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_DATA01__ECSPI5_MOSI 0x0154 0x049C 0x0758 0x3 0x0 +#define MX6SX_PAD_NAND_DATA01__ESAI_RX_FS 0x0154 0x049C 0x0778 0x4 0x0 +#define MX6SX_PAD_NAND_DATA01__GPIO4_IO_5 0x0154 0x049C 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0x0154 0x049C 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_DATA01__TPSMP_HDATA_8 0x0154 0x049C 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD 0x0154 0x049C 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4 0x0154 0x049C 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0x0158 0x04A0 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_DATA02__USDHC1_DATA6 0x0158 0x04A0 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x0158 0x04A0 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_DATA02__ECSPI5_SCLK 0x0158 0x04A0 0x0750 0x3 0x0 +#define MX6SX_PAD_NAND_DATA02__ESAI_TX_HF_CLK 0x0158 0x04A0 0x0784 0x4 0x0 +#define MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x0158 0x04A0 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0x0158 0x04A0 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_DATA02__TPSMP_HDATA_9 0x0158 0x04A0 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV 0x0158 0x04A0 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3 0x0158 0x04A0 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0x015C 0x04A4 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_DATA03__USDHC1_DATA7 0x015C 0x04A4 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x015C 0x04A4 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_DATA03__ECSPI5_SS0 0x015C 0x04A4 0x075C 0x3 0x0 +#define MX6SX_PAD_NAND_DATA03__ESAI_RX_HF_CLK 0x015C 0x04A4 0x0780 0x4 0x0 +#define MX6SX_PAD_NAND_DATA03__GPIO4_IO_7 0x015C 0x04A4 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0x015C 0x04A4 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_DATA03__TPSMP_HDATA_10 0x015C 0x04A4 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH 0x015C 0x04A4 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6 0x015C 0x04A4 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0x0160 0x04A8 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x0160 0x04A8 0x083C 0x3 0x0 +#define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0 +#define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_DATA04__TPSMP_HDATA_11 0x0160 0x04A8 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH 0x0160 0x04A8 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0 0x0160 0x04A8 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x083C 0x3 0x1 +#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0 +#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_DATA05__TPSMP_HDATA_12 0x0164 0x04AC 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET 0x0164 0x04AC 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1 0x0164 0x04AC 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0x0168 0x04B0 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_DATA06__USDHC2_DATA6 0x0168 0x04B0 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B 0x0168 0x04B0 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_DATA06__UART3_RX 0x0168 0x04B0 0x0840 0x3 0x0 +#define MX6SX_PAD_NAND_DATA06__UART3_TX 0x0168 0x04B0 0x0000 0x3 0x0 +#define MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x0168 0x04B0 0x0000 0x4 0x0 +#define MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x0168 0x04B0 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0x0168 0x04B0 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_DATA06__TPSMP_HDATA_13 0x0168 0x04B0 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD 0x0168 0x04B0 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2 0x0168 0x04B0 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0x016C 0x04B4 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_DATA07__USDHC2_DATA7 0x016C 0x04B4 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS 0x016C 0x04B4 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_DATA07__UART3_RX 0x016C 0x04B4 0x0840 0x3 0x1 +#define MX6SX_PAD_NAND_DATA07__UART3_TX 0x016C 0x04B4 0x0000 0x3 0x0 +#define MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x016C 0x04B4 0x0000 0x4 0x0 +#define MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0x016C 0x04B4 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0x016C 0x04B4 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_DATA07__TPSMP_HDATA_14 0x016C 0x04B4 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD 0x016C 0x04B4 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3 0x016C 0x04B4 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0x0170 0x04B8 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_RE_B__USDHC2_RESET_B 0x0170 0x04B8 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x0170 0x04B8 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS 0x0170 0x04B8 0x0658 0x3 0x0 +#define MX6SX_PAD_NAND_RE_B__ESAI_TX_FS 0x0170 0x04B8 0x077C 0x4 0x0 +#define MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x0170 0x04B8 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_RE_B__WEIM_RW 0x0170 0x04B8 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_RE_B__TPSMP_HDATA_5 0x0170 0x04B8 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD 0x0170 0x04B8 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_RE_B__SDMA_DEBUG_PC_7 0x0170 0x04B8 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0x0174 0x04BC 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_READY_B__USDHC1_VSELECT 0x0174 0x04BC 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x0174 0x04BC 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_READY_B__ECSPI2_MISO 0x0174 0x04BC 0x0724 0x3 0x0 +#define MX6SX_PAD_NAND_READY_B__ESAI_TX1 0x0174 0x04BC 0x0794 0x4 0x0 +#define MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x0174 0x04BC 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_READY_B__WEIM_EB_B_1 0x0174 0x04BC 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_READY_B__TPSMP_HDATA_2 0x0174 0x04BC 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN 0x0174 0x04BC 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_READY_B__SDMA_DEBUG_PC_10 0x0174 0x04BC 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0x0178 0x04C0 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_WE_B__USDHC4_VSELECT 0x0178 0x04C0 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x0178 0x04C0 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_WE_B__AUDMUX_AUD4_RXD 0x0178 0x04C0 0x0644 0x3 0x0 +#define MX6SX_PAD_NAND_WE_B__ESAI_TX5_RX0 0x0178 0x04C0 0x07A4 0x4 0x0 +#define MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x0178 0x04C0 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0x0178 0x04C0 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_WE_B__TPSMP_HDATA_6 0x0178 0x04C0 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV 0x0178 0x04C0 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_WE_B__SDMA_DEBUG_PC_6 0x0178 0x04C0 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0x017C 0x04C4 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_WP_B__USDHC1_RESET_B 0x017C 0x04C4 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x017C 0x04C4 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_WP_B__ECSPI2_MOSI 0x017C 0x04C4 0x0728 0x3 0x0 +#define MX6SX_PAD_NAND_WP_B__ESAI_TX4_RX1 0x017C 0x04C4 0x07A0 0x4 0x0 +#define MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x017C 0x04C4 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_WP_B__WEIM_EB_B_0 0x017C 0x04C4 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_WP_B__TPSMP_HDATA_1 0x017C 0x04C4 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE 0x017C 0x04C4 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_WP_B__SDMA_DEBUG_PC_11 0x017C 0x04C4 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x0180 0x04C8 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x0180 0x04C8 0x085C 0x1 0x2 +#define MX6SX_PAD_QSPI1A_DATA0__ECSPI1_MOSI 0x0180 0x04C8 0x0718 0x2 0x1 +#define MX6SX_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 0x0180 0x04C8 0x07A0 0x3 0x2 +#define MX6SX_PAD_QSPI1A_DATA0__CSI1_DATA_14 0x0180 0x04C8 0x06D4 0x4 0x1 +#define MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x0180 0x04C8 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x0180 0x04C8 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1A_DATA0__SIM_M_HADDR_3 0x0180 0x04C8 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3 0x0180 0x04C8 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x0184 0x04CC 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x0184 0x04CC 0x0624 0x1 0x2 +#define MX6SX_PAD_QSPI1A_DATA1__ECSPI1_MISO 0x0184 0x04CC 0x0714 0x2 0x1 +#define MX6SX_PAD_QSPI1A_DATA1__ESAI_TX1 0x0184 0x04CC 0x0794 0x3 0x2 +#define MX6SX_PAD_QSPI1A_DATA1__CSI1_DATA_13 0x0184 0x04CC 0x06D0 0x4 0x1 +#define MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x0184 0x04CC 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x0184 0x04CC 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1A_DATA1__SIM_M_HADDR_4 0x0184 0x04CC 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0 0x0184 0x04CC 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x0188 0x04D0 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1A_DATA2__USB_OTG1_PWR 0x0188 0x04D0 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1A_DATA2__ECSPI5_SS1 0x0188 0x04D0 0x0000 0x2 0x0 +#define MX6SX_PAD_QSPI1A_DATA2__ESAI_TX_CLK 0x0188 0x04D0 0x078C 0x3 0x2 +#define MX6SX_PAD_QSPI1A_DATA2__CSI1_DATA_12 0x0188 0x04D0 0x06CC 0x4 0x1 +#define MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x0188 0x04D0 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x0188 0x04D0 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1A_DATA2__SIM_M_HADDR_6 0x0188 0x04D0 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1 0x0188 0x04D0 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x018C 0x04D4 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1A_DATA3__USB_OTG1_OC 0x018C 0x04D4 0x0860 0x1 0x2 +#define MX6SX_PAD_QSPI1A_DATA3__ECSPI5_SS2 0x018C 0x04D4 0x0000 0x2 0x0 +#define MX6SX_PAD_QSPI1A_DATA3__ESAI_TX0 0x018C 0x04D4 0x0790 0x3 0x2 +#define MX6SX_PAD_QSPI1A_DATA3__CSI1_DATA_11 0x018C 0x04D4 0x06C8 0x4 0x1 +#define MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x018C 0x04D4 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x018C 0x04D4 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1A_DATA3__SIM_M_HADDR_7 0x018C 0x04D4 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2 0x018C 0x04D4 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1A_DQS__QSPI1_A_DQS 0x0190 0x04D8 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x0190 0x04D8 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x0190 0x04D8 0x0000 0x2 0x0 +#define MX6SX_PAD_QSPI1A_DQS__ECSPI5_MOSI 0x0190 0x04D8 0x0758 0x3 0x1 +#define MX6SX_PAD_QSPI1A_DQS__CSI1_DATA_15 0x0190 0x04D8 0x06D8 0x4 0x1 +#define MX6SX_PAD_QSPI1A_DQS__GPIO4_IO_20 0x0190 0x04D8 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x0190 0x04D8 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1A_DQS__SIM_M_HADDR_13 0x0190 0x04D8 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4 0x0190 0x04D8 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x0194 0x04DC 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x0194 0x04DC 0x0628 0x1 0x2 +#define MX6SX_PAD_QSPI1A_SCLK__ECSPI1_SCLK 0x0194 0x04DC 0x0710 0x2 0x1 +#define MX6SX_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 0x0194 0x04DC 0x0798 0x3 0x2 +#define MX6SX_PAD_QSPI1A_SCLK__CSI1_DATA_1 0x0194 0x04DC 0x06A4 0x4 0x1 +#define MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 0x0194 0x04DC 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x0194 0x04DC 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1A_SCLK__SIM_M_HADDR_0 0x0194 0x04DC 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5 0x0194 0x04DC 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x0198 0x04E0 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1A_SS0_B__USB_OTG2_PWR 0x0198 0x04E0 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1A_SS0_B__ECSPI1_SS0 0x0198 0x04E0 0x071C 0x2 0x1 +#define MX6SX_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 0x0198 0x04E0 0x079C 0x3 0x2 +#define MX6SX_PAD_QSPI1A_SS0_B__CSI1_DATA_0 0x0198 0x04E0 0x06A0 0x4 0x1 +#define MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x0198 0x04E0 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x0198 0x04E0 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1 0x0198 0x04E0 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4 0x0198 0x04E0 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B 0x019C 0x04E4 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x019C 0x04E4 0x068C 0x1 0x2 +#define MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x019C 0x04E4 0x0694 0x2 0x2 +#define MX6SX_PAD_QSPI1A_SS1_B__ECSPI5_MISO 0x019C 0x04E4 0x0754 0x3 0x1 +#define MX6SX_PAD_QSPI1A_SS1_B__CSI1_DATA_10 0x019C 0x04E4 0x06FC 0x4 0x1 +#define MX6SX_PAD_QSPI1A_SS1_B__GPIO4_IO_23 0x019C 0x04E4 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x019C 0x04E4 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x083C 0x1 0x4 +#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1 +#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2 +#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1 +#define MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x01A0 0x04E8 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x01A0 0x04E8 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B 0x01A4 0x04EC 0x083C 0x1 0x5 +#define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1 +#define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2 +#define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1 +#define MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x01A4 0x04EC 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x01A4 0x04EC 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 0x01A4 0x04EC 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x01A8 0x04F0 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_DATA2__I2C2_SDA 0x01A8 0x04F0 0x07B4 0x1 0x2 +#define MX6SX_PAD_QSPI1B_DATA2__ECSPI5_RDY 0x01A8 0x04F0 0x0000 0x2 0x0 +#define MX6SX_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 0x01A8 0x04F0 0x07A4 0x3 0x2 +#define MX6SX_PAD_QSPI1B_DATA2__CSI1_DATA_20 0x01A8 0x04F0 0x06EC 0x4 0x1 +#define MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0x01A8 0x04F0 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x01A8 0x04F0 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 0x01A8 0x04F0 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x01AC 0x04F4 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_DATA3__I2C2_SCL 0x01AC 0x04F4 0x07B0 0x1 0x2 +#define MX6SX_PAD_QSPI1B_DATA3__ECSPI5_SS3 0x01AC 0x04F4 0x0000 0x2 0x0 +#define MX6SX_PAD_QSPI1B_DATA3__ESAI_TX_FS 0x01AC 0x04F4 0x077C 0x3 0x2 +#define MX6SX_PAD_QSPI1B_DATA3__CSI1_DATA_19 0x01AC 0x04F4 0x06E8 0x4 0x1 +#define MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x01AC 0x04F4 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x01AC 0x04F4 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1B_DATA3__SIM_M_HADDR_2 0x01AC 0x04F4 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1B_DQS__QSPI1_B_DQS 0x01B0 0x04F8 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x01B0 0x04F8 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x01B0 0x04F8 0x0000 0x2 0x0 +#define MX6SX_PAD_QSPI1B_DQS__ECSPI5_SS0 0x01B0 0x04F8 0x075C 0x3 0x1 +#define MX6SX_PAD_QSPI1B_DQS__CSI1_DATA_23 0x01B0 0x04F8 0x06F8 0x4 0x1 +#define MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28 0x01B0 0x04F8 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x01B0 0x04F8 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x01B4 0x04FC 0x0840 0x1 0x4 +#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX 0x01B4 0x04FC 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1 +#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2 +#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1 +#define MX6SX_PAD_QSPI1B_SCLK__GPIO4_IO_29 0x01B4 0x04FC 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x01B4 0x04FC 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 0x01B4 0x04FC 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x01B8 0x0500 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX 0x01B8 0x0500 0x0840 0x1 0x5 +#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x01B8 0x0500 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0 0x01B8 0x0500 0x073C 0x2 0x1 +#define MX6SX_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK 0x01B8 0x0500 0x0784 0x3 0x3 +#define MX6SX_PAD_QSPI1B_SS0_B__CSI1_DATA_17 0x01B8 0x0500 0x06E0 0x4 0x1 +#define MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x01B8 0x0500 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x01B8 0x0500 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10 0x01B8 0x0500 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B 0x01BC 0x0504 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x01BC 0x0504 0x0690 0x1 0x2 +#define MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x01BC 0x0504 0x0698 0x2 0x2 +#define MX6SX_PAD_QSPI1B_SS1_B__ECSPI5_SCLK 0x01BC 0x0504 0x0750 0x3 0x1 +#define MX6SX_PAD_QSPI1B_SS1_B__CSI1_DATA_18 0x01BC 0x0504 0x06E4 0x4 0x1 +#define MX6SX_PAD_QSPI1B_SS1_B__GPIO4_IO_31 0x01BC 0x0504 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x01BC 0x0504 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14 0x01BC 0x0504 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x01C0 0x0508 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_RD0__GPIO5_IO_0 0x01C0 0x0508 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_RD0__CSI2_DATA_10 0x01C0 0x0508 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_RD0__ANATOP_TESTI_0 0x01C0 0x0508 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER 0x01C0 0x0508 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0 0x01C0 0x0508 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x01C4 0x050C 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_RD1__GPIO5_IO_1 0x01C4 0x050C 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_RD1__CSI2_DATA_11 0x01C4 0x050C 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_RD1__ANATOP_TESTI_1 0x01C4 0x050C 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER 0x01C4 0x050C 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1 0x01C4 0x050C 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x01C8 0x0510 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_RD2__GPIO5_IO_2 0x01C8 0x0510 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_RD2__CSI2_DATA_12 0x01C8 0x0510 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_RD2__ANATOP_TESTI_2 0x01C8 0x0510 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER 0x01C8 0x0510 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2 0x01C8 0x0510 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x01CC 0x0514 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_RD3__GPIO5_IO_3 0x01CC 0x0514 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_RD3__CSI2_DATA_13 0x01CC 0x0514 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_RD3__ANATOP_TESTI_3 0x01CC 0x0514 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER 0x01CC 0x0514 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3 0x01CC 0x0514 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x01D0 0x0518 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_RX_CTL__GPIO5_IO_4 0x01D0 0x0518 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_RX_CTL__CSI2_DATA_14 0x01D0 0x0518 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0 0x01D0 0x0518 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER 0x01D0 0x0518 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4 0x01D0 0x0518 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x01D4 0x051C 0x0768 0x0 0x1 +#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x01D4 0x051C 0x0000 0x1 0x0 +#define MX6SX_PAD_RGMII1_RXC__GPIO5_IO_5 0x01D4 0x051C 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_RXC__CSI2_DATA_15 0x01D4 0x051C 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_RXC__ANATOP_TESTO_1 0x01D4 0x051C 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER 0x01D4 0x051C 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5 0x01D4 0x051C 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x01D8 0x0520 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_TD0__SAI2_RX_SYNC 0x01D8 0x0520 0x0810 0x2 0x1 +#define MX6SX_PAD_RGMII1_TD0__GPIO5_IO_6 0x01D8 0x0520 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_TD0__CSI2_DATA_16 0x01D8 0x0520 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_TD0__ANATOP_TESTO_2 0x01D8 0x0520 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER 0x01D8 0x0520 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6 0x01D8 0x0520 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x01DC 0x0524 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_TD1__SAI2_RX_BCLK 0x01DC 0x0524 0x0808 0x2 0x1 +#define MX6SX_PAD_RGMII1_TD1__GPIO5_IO_7 0x01DC 0x0524 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_TD1__CSI2_DATA_17 0x01DC 0x0524 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_TD1__ANATOP_TESTO_3 0x01DC 0x0524 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER 0x01DC 0x0524 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7 0x01DC 0x0524 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x01E0 0x0528 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_TD2__SAI2_TX_SYNC 0x01E0 0x0528 0x0818 0x2 0x1 +#define MX6SX_PAD_RGMII1_TD2__GPIO5_IO_8 0x01E0 0x0528 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_TD2__CSI2_DATA_18 0x01E0 0x0528 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_TD2__ANATOP_TESTO_4 0x01E0 0x0528 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER 0x01E0 0x0528 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8 0x01E0 0x0528 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x01E4 0x052C 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_TD3__SAI2_TX_BCLK 0x01E4 0x052C 0x0814 0x2 0x1 +#define MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x01E4 0x052C 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_TD3__CSI2_DATA_19 0x01E4 0x052C 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_TD3__ANATOP_TESTO_5 0x01E4 0x052C 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER 0x01E4 0x052C 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9 0x01E4 0x052C 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x01E8 0x0530 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 0x01E8 0x0530 0x080C 0x2 0x1 +#define MX6SX_PAD_RGMII1_TX_CTL__GPIO5_IO_10 0x01E8 0x0530 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_TX_CTL__CSI2_DATA_0 0x01E8 0x0530 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6 0x01E8 0x0530 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER 0x01E8 0x0530 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10 0x01E8 0x0530 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x01EC 0x0534 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_TXC__ENET1_TX_ER 0x01EC 0x0534 0x0000 0x1 0x0 +#define MX6SX_PAD_RGMII1_TXC__SAI2_TX_DATA_0 0x01EC 0x0534 0x0000 0x2 0x0 +#define MX6SX_PAD_RGMII1_TXC__GPIO5_IO_11 0x01EC 0x0534 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_TXC__CSI2_DATA_1 0x01EC 0x0534 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_TXC__ANATOP_TESTO_7 0x01EC 0x0534 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER 0x01EC 0x0534 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11 0x01EC 0x0534 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x01F0 0x0538 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_RD0__PWM4_OUT 0x01F0 0x0538 0x0000 0x2 0x0 +#define MX6SX_PAD_RGMII2_RD0__GPIO5_IO_12 0x01F0 0x0538 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_RD0__CSI2_DATA_2 0x01F0 0x0538 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_RD0__ANATOP_TESTO_8 0x01F0 0x0538 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_RD0__VDEC_DEBUG_18 0x01F0 0x0538 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12 0x01F0 0x0538 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x01F4 0x053C 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_RD1__PWM3_OUT 0x01F4 0x053C 0x0000 0x2 0x0 +#define MX6SX_PAD_RGMII2_RD1__GPIO5_IO_13 0x01F4 0x053C 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_RD1__CSI2_DATA_3 0x01F4 0x053C 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_RD1__ANATOP_TESTO_9 0x01F4 0x053C 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_RD1__VDEC_DEBUG_19 0x01F4 0x053C 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13 0x01F4 0x053C 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x01F8 0x0540 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x01F8 0x0540 0x0000 0x2 0x0 +#define MX6SX_PAD_RGMII2_RD2__GPIO5_IO_14 0x01F8 0x0540 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_RD2__CSI2_DATA_4 0x01F8 0x0540 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_RD2__ANATOP_TESTO_10 0x01F8 0x0540 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_RD2__VDEC_DEBUG_20 0x01F8 0x0540 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14 0x01F8 0x0540 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x01FC 0x0544 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x01FC 0x0544 0x0000 0x2 0x0 +#define MX6SX_PAD_RGMII2_RD3__GPIO5_IO_15 0x01FC 0x0544 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_RD3__CSI2_DATA_5 0x01FC 0x0544 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_RD3__ANATOP_TESTO_11 0x01FC 0x0544 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_RD3__VDEC_DEBUG_21 0x01FC 0x0544 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15 0x01FC 0x0544 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x0200 0x0548 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_RX_CTL__GPIO5_IO_16 0x0200 0x0548 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_RX_CTL__CSI2_DATA_6 0x0200 0x0548 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12 0x0200 0x0548 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22 0x0200 0x0548 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16 0x0200 0x0548 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x0204 0x054C 0x0774 0x0 0x1 +#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_ER 0x0204 0x054C 0x0000 0x1 0x0 +#define MX6SX_PAD_RGMII2_RXC__GPIO5_IO_17 0x0204 0x054C 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_RXC__CSI2_DATA_7 0x0204 0x054C 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_RXC__ANATOP_TESTO_13 0x0204 0x054C 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_RXC__VDEC_DEBUG_23 0x0204 0x054C 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17 0x0204 0x054C 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x0208 0x0550 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_TD0__SAI1_RX_SYNC 0x0208 0x0550 0x07FC 0x2 0x1 +#define MX6SX_PAD_RGMII2_TD0__PWM8_OUT 0x0208 0x0550 0x0000 0x3 0x0 +#define MX6SX_PAD_RGMII2_TD0__GPIO5_IO_18 0x0208 0x0550 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_TD0__CSI2_DATA_8 0x0208 0x0550 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_TD0__ANATOP_TESTO_14 0x0208 0x0550 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_TD0__VDEC_DEBUG_24 0x0208 0x0550 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18 0x0208 0x0550 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x020C 0x0554 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_TD1__SAI1_RX_BCLK 0x020C 0x0554 0x07F4 0x2 0x1 +#define MX6SX_PAD_RGMII2_TD1__PWM7_OUT 0x020C 0x0554 0x0000 0x3 0x0 +#define MX6SX_PAD_RGMII2_TD1__GPIO5_IO_19 0x020C 0x0554 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_TD1__CSI2_DATA_9 0x020C 0x0554 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_TD1__ANATOP_TESTO_15 0x020C 0x0554 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_TD1__VDEC_DEBUG_25 0x020C 0x0554 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19 0x020C 0x0554 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x0210 0x0558 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_TD2__SAI1_TX_SYNC 0x0210 0x0558 0x0804 0x2 0x1 +#define MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x0210 0x0558 0x0000 0x3 0x0 +#define MX6SX_PAD_RGMII2_TD2__GPIO5_IO_20 0x0210 0x0558 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_TD2__CSI2_VSYNC 0x0210 0x0558 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_TD2__SJC_FAIL 0x0210 0x0558 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_TD2__VDEC_DEBUG_26 0x0210 0x0558 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20 0x0210 0x0558 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x0214 0x055C 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_TD3__SAI1_TX_BCLK 0x0214 0x055C 0x0800 0x2 0x1 +#define MX6SX_PAD_RGMII2_TD3__PWM5_OUT 0x0214 0x055C 0x0000 0x3 0x0 +#define MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x0214 0x055C 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_TD3__CSI2_HSYNC 0x0214 0x055C 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_TD3__SJC_JTAG_ACT 0x0214 0x055C 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_TD3__VDEC_DEBUG_27 0x0214 0x055C 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21 0x0214 0x055C 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x0218 0x0560 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 0x0218 0x0560 0x07F8 0x2 0x1 +#define MX6SX_PAD_RGMII2_TX_CTL__GPIO5_IO_22 0x0218 0x0560 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_TX_CTL__CSI2_FIELD 0x0218 0x0560 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_TX_CTL__SJC_DE_B 0x0218 0x0560 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28 0x0218 0x0560 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22 0x0218 0x0560 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x021C 0x0564 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_TXC__ENET2_TX_ER 0x021C 0x0564 0x0000 0x1 0x0 +#define MX6SX_PAD_RGMII2_TXC__SAI1_TX_DATA_0 0x021C 0x0564 0x0000 0x2 0x0 +#define MX6SX_PAD_RGMII2_TXC__GPIO5_IO_23 0x021C 0x0564 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_TXC__CSI2_PIXCLK 0x021C 0x0564 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_TXC__SJC_DONE 0x021C 0x0564 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_TXC__VDEC_DEBUG_29 0x021C 0x0564 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23 0x021C 0x0564 0x0000 0x9 0x0 +#define MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x0220 0x0568 0x0000 0x0 0x0 +#define MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x0220 0x0568 0x0668 0x1 0x1 +#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_B 0x0220 0x0568 0x0000 0x2 0x0 +#define MX6SX_PAD_SD1_CLK__GPT_CLK 0x0220 0x0568 0x0000 0x3 0x0 +#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB 0x0220 0x0568 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_CLK__GPIO6_IO_0 0x0220 0x0568 0x0000 0x5 0x0 +#define MX6SX_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT 0x0220 0x0568 0x0000 0x6 0x0 +#define MX6SX_PAD_SD1_CLK__CCM_OUT1 0x0220 0x0568 0x0000 0x7 0x0 +#define MX6SX_PAD_SD1_CLK__VADC_ADC_PROC_CLK 0x0220 0x0568 0x0000 0x8 0x0 +#define MX6SX_PAD_SD1_CLK__MMDC_DEBUG_45 0x0220 0x0568 0x0000 0x9 0x0 +#define MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x0224 0x056C 0x0000 0x0 0x0 +#define MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x0224 0x056C 0x0664 0x1 0x1 +#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_B 0x0224 0x056C 0x0000 0x2 0x0 +#define MX6SX_PAD_SD1_CMD__GPT_COMPARE1 0x0224 0x056C 0x0000 0x3 0x0 +#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB 0x0224 0x056C 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_CMD__GPIO6_IO_1 0x0224 0x056C 0x0000 0x5 0x0 +#define MX6SX_PAD_SD1_CMD__ENET2_1588_EVENT1_IN 0x0224 0x056C 0x0000 0x6 0x0 +#define MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x0224 0x056C 0x0000 0x7 0x0 +#define MX6SX_PAD_SD1_CMD__VADC_EXT_SYSCLK 0x0224 0x056C 0x0000 0x8 0x0 +#define MX6SX_PAD_SD1_CMD__MMDC_DEBUG_46 0x0224 0x056C 0x0000 0x9 0x0 +#define MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x0228 0x0570 0x0000 0x0 0x0 +#define MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x0228 0x0570 0x065C 0x1 0x1 +#define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS 0x0228 0x0570 0x0000 0x2 0x0 +#define MX6SX_PAD_SD1_DATA0__GPT_CAPTURE1 0x0228 0x0570 0x0000 0x3 0x0 +#define MX6SX_PAD_SD1_DATA0__UART2_RX 0x0228 0x0570 0x0838 0x4 0x2 +#define MX6SX_PAD_SD1_DATA0__UART2_TX 0x0228 0x0570 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x0228 0x0570 0x0000 0x5 0x0 +#define MX6SX_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN 0x0228 0x0570 0x0000 0x6 0x0 +#define MX6SX_PAD_SD1_DATA0__CCM_OUT2 0x0228 0x0570 0x0000 0x7 0x0 +#define MX6SX_PAD_SD1_DATA0__VADC_CLAMP_UP 0x0228 0x0570 0x0000 0x8 0x0 +#define MX6SX_PAD_SD1_DATA0__MMDC_DEBUG_48 0x0228 0x0570 0x0000 0x9 0x0 +#define MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x022C 0x0574 0x0000 0x0 0x0 +#define MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x022C 0x0574 0x066C 0x1 0x1 +#define MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x022C 0x0574 0x0000 0x2 0x0 +#define MX6SX_PAD_SD1_DATA1__GPT_CAPTURE2 0x022C 0x0574 0x0000 0x3 0x0 +#define MX6SX_PAD_SD1_DATA1__UART2_RX 0x022C 0x0574 0x0838 0x4 0x3 +#define MX6SX_PAD_SD1_DATA1__UART2_TX 0x022C 0x0574 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 0x022C 0x0574 0x0000 0x5 0x0 +#define MX6SX_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT 0x022C 0x0574 0x0000 0x6 0x0 +#define MX6SX_PAD_SD1_DATA1__CCM_CLKO2 0x022C 0x0574 0x0000 0x7 0x0 +#define MX6SX_PAD_SD1_DATA1__VADC_CLAMP_DOWN 0x022C 0x0574 0x0000 0x8 0x0 +#define MX6SX_PAD_SD1_DATA1__MMDC_DEBUG_47 0x022C 0x0574 0x0000 0x9 0x0 +#define MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x0230 0x0578 0x0000 0x0 0x0 +#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1 +#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0 +#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0 +#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0834 0x4 0x2 +#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0 +#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0 +#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0 +#define MX6SX_PAD_SD1_DATA2__VADC_EXT_PD_N 0x0230 0x0578 0x0000 0x8 0x0 +#define MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x0234 0x057C 0x0000 0x0 0x0 +#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x0234 0x057C 0x0660 0x1 0x1 +#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2 +#define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0 +#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B 0x0234 0x057C 0x0834 0x4 0x3 +#define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0 +#define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0 +#define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2 +#define MX6SX_PAD_SD1_DATA3__VADC_RST_N 0x0234 0x057C 0x0000 0x8 0x0 +#define MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x0238 0x0580 0x0000 0x0 0x0 +#define MX6SX_PAD_SD2_CLK__AUDMUX_AUD6_RXFS 0x0238 0x0580 0x0680 0x1 0x2 +#define MX6SX_PAD_SD2_CLK__KPP_COL_5 0x0238 0x0580 0x07C8 0x2 0x1 +#define MX6SX_PAD_SD2_CLK__ECSPI4_SCLK 0x0238 0x0580 0x0740 0x3 0x1 +#define MX6SX_PAD_SD2_CLK__MLB_SIG 0x0238 0x0580 0x07F0 0x4 0x2 +#define MX6SX_PAD_SD2_CLK__GPIO6_IO_6 0x0238 0x0580 0x0000 0x5 0x0 +#define MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x0238 0x0580 0x0000 0x6 0x0 +#define MX6SX_PAD_SD2_CLK__WDOG1_WDOG_ANY 0x0238 0x0580 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5 0x0238 0x0580 0x0000 0x8 0x0 +#define MX6SX_PAD_SD2_CLK__MMDC_DEBUG_29 0x0238 0x0580 0x0000 0x9 0x0 +#define MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x023C 0x0584 0x0000 0x0 0x0 +#define MX6SX_PAD_SD2_CMD__AUDMUX_AUD6_RXC 0x023C 0x0584 0x067C 0x1 0x2 +#define MX6SX_PAD_SD2_CMD__KPP_ROW_5 0x023C 0x0584 0x07D4 0x2 0x1 +#define MX6SX_PAD_SD2_CMD__ECSPI4_MOSI 0x023C 0x0584 0x0748 0x3 0x1 +#define MX6SX_PAD_SD2_CMD__MLB_CLK 0x023C 0x0584 0x07E8 0x4 0x2 +#define MX6SX_PAD_SD2_CMD__GPIO6_IO_7 0x023C 0x0584 0x0000 0x5 0x0 +#define MX6SX_PAD_SD2_CMD__MQS_LEFT 0x023C 0x0584 0x0000 0x6 0x0 +#define MX6SX_PAD_SD2_CMD__WDOG3_WDOG_B 0x023C 0x0584 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4 0x023C 0x0584 0x0000 0x8 0x0 +#define MX6SX_PAD_SD2_CMD__MMDC_DEBUG_30 0x023C 0x0584 0x0000 0x9 0x0 +#define MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x0240 0x0588 0x0000 0x0 0x0 +#define MX6SX_PAD_SD2_DATA0__AUDMUX_AUD6_RXD 0x0240 0x0588 0x0674 0x1 0x2 +#define MX6SX_PAD_SD2_DATA0__KPP_ROW_7 0x0240 0x0588 0x07DC 0x2 0x1 +#define MX6SX_PAD_SD2_DATA0__PWM1_OUT 0x0240 0x0588 0x0000 0x3 0x0 +#define MX6SX_PAD_SD2_DATA0__I2C4_SDA 0x0240 0x0588 0x07C4 0x4 0x3 +#define MX6SX_PAD_SD2_DATA0__GPIO6_IO_8 0x0240 0x0588 0x0000 0x5 0x0 +#define MX6SX_PAD_SD2_DATA0__ECSPI4_SS3 0x0240 0x0588 0x0000 0x6 0x0 +#define MX6SX_PAD_SD2_DATA0__UART4_RX 0x0240 0x0588 0x0848 0x7 0x4 +#define MX6SX_PAD_SD2_DATA0__UART4_TX 0x0240 0x0588 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 0x0240 0x0588 0x0000 0x8 0x0 +#define MX6SX_PAD_SD2_DATA0__MMDC_DEBUG_50 0x0240 0x0588 0x0000 0x9 0x0 +#define MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x0244 0x058C 0x0000 0x0 0x0 +#define MX6SX_PAD_SD2_DATA1__AUDMUX_AUD6_TXC 0x0244 0x058C 0x0684 0x1 0x2 +#define MX6SX_PAD_SD2_DATA1__KPP_COL_7 0x0244 0x058C 0x07D0 0x2 0x1 +#define MX6SX_PAD_SD2_DATA1__PWM2_OUT 0x0244 0x058C 0x0000 0x3 0x0 +#define MX6SX_PAD_SD2_DATA1__I2C4_SCL 0x0244 0x058C 0x07C0 0x4 0x3 +#define MX6SX_PAD_SD2_DATA1__GPIO6_IO_9 0x0244 0x058C 0x0000 0x5 0x0 +#define MX6SX_PAD_SD2_DATA1__ECSPI4_SS2 0x0244 0x058C 0x0000 0x6 0x0 +#define MX6SX_PAD_SD2_DATA1__UART4_RX 0x0244 0x058C 0x0848 0x7 0x5 +#define MX6SX_PAD_SD2_DATA1__UART4_TX 0x0244 0x058C 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 0x0244 0x058C 0x0000 0x8 0x0 +#define MX6SX_PAD_SD2_DATA1__MMDC_DEBUG_49 0x0244 0x058C 0x0000 0x9 0x0 +#define MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x0248 0x0590 0x0000 0x0 0x0 +#define MX6SX_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS 0x0248 0x0590 0x0688 0x1 0x2 +#define MX6SX_PAD_SD2_DATA2__KPP_ROW_6 0x0248 0x0590 0x07D8 0x2 0x1 +#define MX6SX_PAD_SD2_DATA2__ECSPI4_SS0 0x0248 0x0590 0x074C 0x3 0x1 +#define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 0x0248 0x0590 0x081C 0x4 0x2 +#define MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 0x0248 0x0590 0x0000 0x5 0x0 +#define MX6SX_PAD_SD2_DATA2__SPDIF_OUT 0x0248 0x0590 0x0000 0x6 0x0 +#define MX6SX_PAD_SD2_DATA2__UART6_RX 0x0248 0x0590 0x0858 0x7 0x4 +#define MX6SX_PAD_SD2_DATA2__UART6_TX 0x0248 0x0590 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 0x0248 0x0590 0x0000 0x8 0x0 +#define MX6SX_PAD_SD2_DATA2__MMDC_DEBUG_32 0x0248 0x0590 0x0000 0x9 0x0 +#define MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x024C 0x0594 0x0000 0x0 0x0 +#define MX6SX_PAD_SD2_DATA3__AUDMUX_AUD6_TXD 0x024C 0x0594 0x0678 0x1 0x2 +#define MX6SX_PAD_SD2_DATA3__KPP_COL_6 0x024C 0x0594 0x07CC 0x2 0x1 +#define MX6SX_PAD_SD2_DATA3__ECSPI4_MISO 0x024C 0x0594 0x0744 0x3 0x1 +#define MX6SX_PAD_SD2_DATA3__MLB_DATA 0x024C 0x0594 0x07EC 0x4 0x2 +#define MX6SX_PAD_SD2_DATA3__GPIO6_IO_11 0x024C 0x0594 0x0000 0x5 0x0 +#define MX6SX_PAD_SD2_DATA3__SPDIF_IN 0x024C 0x0594 0x0824 0x6 0x4 +#define MX6SX_PAD_SD2_DATA3__UART6_RX 0x024C 0x0594 0x0858 0x7 0x5 +#define MX6SX_PAD_SD2_DATA3__UART6_TX 0x024C 0x0594 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0 +#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0844 0x1 0x0 +#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0 +#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0 +#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_CLK__GPIO7_IO_0 0x0250 0x0598 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_CLK__LCDIF2_BUSY 0x0250 0x0598 0x07E4 0x6 0x0 +#define MX6SX_PAD_SD3_CLK__TPSMP_HDATA_29 0x0250 0x0598 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 0x0250 0x0598 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x0254 0x059C 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_CMD__UART4_RX 0x0254 0x059C 0x0848 0x1 0x0 +#define MX6SX_PAD_SD3_CMD__UART4_TX 0x0254 0x059C 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x0254 0x059C 0x0748 0x2 0x0 +#define MX6SX_PAD_SD3_CMD__AUDMUX_AUD6_RXC 0x0254 0x059C 0x067C 0x3 0x0 +#define MX6SX_PAD_SD3_CMD__LCDIF2_HSYNC 0x0254 0x059C 0x07E4 0x4 0x1 +#define MX6SX_PAD_SD3_CMD__GPIO7_IO_1 0x0254 0x059C 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_CMD__LCDIF2_RS 0x0254 0x059C 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_CMD__TPSMP_HDATA_28 0x0254 0x059C 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 0x0254 0x059C 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x0258 0x05A0 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x0258 0x05A0 0x07C0 0x1 0x0 +#define MX6SX_PAD_SD3_DATA0__ECSPI2_SS1 0x0258 0x05A0 0x0000 0x2 0x0 +#define MX6SX_PAD_SD3_DATA0__AUDMUX_AUD6_RXD 0x0258 0x05A0 0x0674 0x3 0x0 +#define MX6SX_PAD_SD3_DATA0__LCDIF2_DATA_1 0x0258 0x05A0 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x0258 0x05A0 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_DATA0__DCIC1_OUT 0x0258 0x05A0 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_DATA0__TPSMP_HDATA_30 0x0258 0x05A0 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_DATA0__GPU_DEBUG_0 0x0258 0x05A0 0x0000 0x8 0x0 +#define MX6SX_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 0x0258 0x05A0 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x025C 0x05A4 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x025C 0x05A4 0x07C4 0x1 0x0 +#define MX6SX_PAD_SD3_DATA1__ECSPI2_SS2 0x025C 0x05A4 0x0000 0x2 0x0 +#define MX6SX_PAD_SD3_DATA1__AUDMUX_AUD6_TXC 0x025C 0x05A4 0x0684 0x3 0x0 +#define MX6SX_PAD_SD3_DATA1__LCDIF2_DATA_0 0x025C 0x05A4 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x025C 0x05A4 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_DATA1__DCIC2_OUT 0x025C 0x05A4 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_DATA1__TPSMP_HDATA_31 0x025C 0x05A4 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_DATA1__GPU_DEBUG_1 0x025C 0x05A4 0x0000 0x8 0x0 +#define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B 0x0260 0x05A8 0x0844 0x1 0x1 +#define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0 +#define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0 +#define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x0260 0x05A8 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_DATA2__LCDIF2_WR_RWN 0x0260 0x05A8 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_DATA2__TPSMP_HDATA_26 0x0260 0x05A8 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_DATA2__GPU_DEBUG_2 0x0260 0x05A8 0x0000 0x8 0x0 +#define MX6SX_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 0x0260 0x05A8 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x0264 0x05AC 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_DATA3__UART4_RX 0x0264 0x05AC 0x0848 0x1 0x1 +#define MX6SX_PAD_SD3_DATA3__UART4_TX 0x0264 0x05AC 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x0264 0x05AC 0x0744 0x2 0x0 +#define MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD 0x0264 0x05AC 0x0678 0x3 0x0 +#define MX6SX_PAD_SD3_DATA3__LCDIF2_ENABLE 0x0264 0x05AC 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_DATA3__GPIO7_IO_5 0x0264 0x05AC 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_DATA3__LCDIF2_RD_E 0x0264 0x05AC 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_DATA3__TPSMP_HDATA_27 0x0264 0x05AC 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_DATA3__GPU_DEBUG_3 0x0264 0x05AC 0x0000 0x8 0x0 +#define MX6SX_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3 0x0264 0x05AC 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x0268 0x05B0 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_DATA4__CAN2_RX 0x0268 0x05B0 0x0690 0x1 0x0 +#define MX6SX_PAD_SD3_DATA4__CANFD_RX2 0x0268 0x05B0 0x0698 0x2 0x0 +#define MX6SX_PAD_SD3_DATA4__UART3_RX 0x0268 0x05B0 0x0840 0x3 0x2 +#define MX6SX_PAD_SD3_DATA4__UART3_TX 0x0268 0x05B0 0x0000 0x3 0x0 +#define MX6SX_PAD_SD3_DATA4__LCDIF2_DATA_3 0x0268 0x05B0 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x0268 0x05B0 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN 0x0268 0x05B0 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_DATA4__TPSMP_HTRANS_1 0x0268 0x05B0 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_DATA4__GPU_DEBUG_4 0x0268 0x05B0 0x0000 0x8 0x0 +#define MX6SX_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0 0x0268 0x05B0 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x026C 0x05B4 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_DATA5__CAN1_TX 0x026C 0x05B4 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_DATA5__CANFD_TX1 0x026C 0x05B4 0x0000 0x2 0x0 +#define MX6SX_PAD_SD3_DATA5__UART3_RX 0x026C 0x05B4 0x0840 0x3 0x3 +#define MX6SX_PAD_SD3_DATA5__UART3_TX 0x026C 0x05B4 0x0000 0x3 0x0 +#define MX6SX_PAD_SD3_DATA5__LCDIF2_DATA_2 0x026C 0x05B4 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x026C 0x05B4 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT 0x026C 0x05B4 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_DATA5__SIM_M_HWRITE 0x026C 0x05B4 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_DATA5__GPU_DEBUG_5 0x026C 0x05B4 0x0000 0x8 0x0 +#define MX6SX_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1 0x026C 0x05B4 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x0270 0x05B8 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0 +#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270 0x05B8 0x083C 0x3 0x2 +#define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_DATA6__TPSMP_HTRANS_0 0x0270 0x05B8 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_DATA6__GPU_DEBUG_7 0x0270 0x05B8 0x0000 0x8 0x0 +#define MX6SX_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7 0x0270 0x05B8 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0 +#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0 +#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x083C 0x3 0x3 +#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_DATA7__TPSMP_HDATA_DIR 0x0274 0x05BC 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_DATA7__GPU_DEBUG_6 0x0274 0x05BC 0x0000 0x8 0x0 +#define MX6SX_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2 0x0274 0x05BC 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x0278 0x05C0 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_CLK__RAWNAND_DATA15 0x0278 0x05C0 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_CLK__ECSPI2_MISO 0x0278 0x05C0 0x0724 0x2 0x1 +#define MX6SX_PAD_SD4_CLK__AUDMUX_AUD3_RXFS 0x0278 0x05C0 0x0638 0x3 0x0 +#define MX6SX_PAD_SD4_CLK__LCDIF2_DATA_13 0x0278 0x05C0 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_CLK__GPIO6_IO_12 0x0278 0x05C0 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_CLK__ECSPI3_SS2 0x0278 0x05C0 0x0000 0x6 0x0 +#define MX6SX_PAD_SD4_CLK__TPSMP_HDATA_20 0x0278 0x05C0 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_CLK__VDEC_DEBUG_12 0x0278 0x05C0 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x0278 0x05C0 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x027C 0x05C4 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_CMD__RAWNAND_DATA14 0x027C 0x05C4 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_CMD__ECSPI2_MOSI 0x027C 0x05C4 0x0728 0x2 0x1 +#define MX6SX_PAD_SD4_CMD__AUDMUX_AUD3_RXC 0x027C 0x05C4 0x0634 0x3 0x0 +#define MX6SX_PAD_SD4_CMD__LCDIF2_DATA_14 0x027C 0x05C4 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_CMD__GPIO6_IO_13 0x027C 0x05C4 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_CMD__ECSPI3_SS1 0x027C 0x05C4 0x0000 0x6 0x0 +#define MX6SX_PAD_SD4_CMD__TPSMP_HDATA_19 0x027C 0x05C4 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_CMD__VDEC_DEBUG_11 0x027C 0x05C4 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN 0x027C 0x05C4 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x0280 0x05C8 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_DATA0__RAWNAND_DATA10 0x0280 0x05C8 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_DATA0__ECSPI2_SS0 0x0280 0x05C8 0x072C 0x2 0x1 +#define MX6SX_PAD_SD4_DATA0__AUDMUX_AUD3_RXD 0x0280 0x05C8 0x062C 0x3 0x0 +#define MX6SX_PAD_SD4_DATA0__LCDIF2_DATA_12 0x0280 0x05C8 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_DATA0__GPIO6_IO_14 0x0280 0x05C8 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_DATA0__ECSPI3_SS3 0x0280 0x05C8 0x0000 0x6 0x0 +#define MX6SX_PAD_SD4_DATA0__TPSMP_HDATA_21 0x0280 0x05C8 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_DATA0__VDEC_DEBUG_13 0x0280 0x05C8 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_DATA0__SDMA_DEBUG_MODE 0x0280 0x05C8 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x0284 0x05CC 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_DATA1__RAWNAND_DATA11 0x0284 0x05CC 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_DATA1__ECSPI2_SCLK 0x0284 0x05CC 0x0720 0x2 0x1 +#define MX6SX_PAD_SD4_DATA1__AUDMUX_AUD3_TXC 0x0284 0x05CC 0x063C 0x3 0x0 +#define MX6SX_PAD_SD4_DATA1__LCDIF2_DATA_11 0x0284 0x05CC 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_DATA1__GPIO6_IO_15 0x0284 0x05CC 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_DATA1__ECSPI3_RDY 0x0284 0x05CC 0x0000 0x6 0x0 +#define MX6SX_PAD_SD4_DATA1__TPSMP_HDATA_22 0x0284 0x05CC 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_DATA1__VDEC_DEBUG_14 0x0284 0x05CC 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR 0x0284 0x05CC 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x0288 0x05D0 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_DATA2__RAWNAND_DATA12 0x0288 0x05D0 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_DATA2__I2C2_SDA 0x0288 0x05D0 0x07B4 0x2 0x0 +#define MX6SX_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS 0x0288 0x05D0 0x0640 0x3 0x0 +#define MX6SX_PAD_SD4_DATA2__LCDIF2_DATA_10 0x0288 0x05D0 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_DATA2__GPIO6_IO_16 0x0288 0x05D0 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_DATA2__ECSPI2_SS3 0x0288 0x05D0 0x0000 0x6 0x0 +#define MX6SX_PAD_SD4_DATA2__TPSMP_HDATA_23 0x0288 0x05D0 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_DATA2__VDEC_DEBUG_15 0x0288 0x05D0 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB 0x0288 0x05D0 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x028C 0x05D4 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_DATA3__RAWNAND_DATA13 0x028C 0x05D4 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_DATA3__I2C2_SCL 0x028C 0x05D4 0x07B0 0x2 0x0 +#define MX6SX_PAD_SD4_DATA3__AUDMUX_AUD3_TXD 0x028C 0x05D4 0x0630 0x3 0x0 +#define MX6SX_PAD_SD4_DATA3__LCDIF2_DATA_9 0x028C 0x05D4 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_DATA3__GPIO6_IO_17 0x028C 0x05D4 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_DATA3__ECSPI2_RDY 0x028C 0x05D4 0x0000 0x6 0x0 +#define MX6SX_PAD_SD4_DATA3__TPSMP_HDATA_24 0x028C 0x05D4 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_DATA3__VDEC_DEBUG_16 0x028C 0x05D4 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS 0x028C 0x05D4 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x0290 0x05D8 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_DATA4__RAWNAND_DATA09 0x0290 0x05D8 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_DATA4__UART5_RX 0x0290 0x05D8 0x0850 0x2 0x0 +#define MX6SX_PAD_SD4_DATA4__UART5_TX 0x0290 0x05D8 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK 0x0290 0x05D8 0x0730 0x3 0x0 +#define MX6SX_PAD_SD4_DATA4__LCDIF2_DATA_8 0x0290 0x05D8 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x0290 0x05D8 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x0290 0x05D8 0x0000 0x6 0x0 +#define MX6SX_PAD_SD4_DATA4__TPSMP_HDATA_16 0x0290 0x05D8 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_DATA4__USB_OTG_HOST_MODE 0x0290 0x05D8 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE 0x0290 0x05D8 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x0294 0x05DC 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_DATA5__RAWNAND_CE2_B 0x0294 0x05DC 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_DATA5__UART5_RX 0x0294 0x05DC 0x0850 0x2 0x1 +#define MX6SX_PAD_SD4_DATA5__UART5_TX 0x0294 0x05DC 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI 0x0294 0x05DC 0x0738 0x3 0x0 +#define MX6SX_PAD_SD4_DATA5__LCDIF2_DATA_7 0x0294 0x05DC 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_DATA5__GPIO6_IO_19 0x0294 0x05DC 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_DATA5__SPDIF_IN 0x0294 0x05DC 0x0824 0x6 0x0 +#define MX6SX_PAD_SD4_DATA5__TPSMP_HDATA_17 0x0294 0x05DC 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_DATA5__VDEC_DEBUG_9 0x0294 0x05DC 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 0x0294 0x05DC 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298 0x05E0 0x084C 0x2 0x0 +#define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0 +#define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_DATA6__USDHC4_WP 0x0298 0x05E0 0x0878 0x6 0x0 +#define MX6SX_PAD_SD4_DATA6__TPSMP_HDATA_18 0x0298 0x05E0 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_DATA6__VDEC_DEBUG_10 0x0298 0x05E0 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x084C 0x2 0x1 +#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0 +#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_DATA7__USDHC4_CD_B 0x029C 0x05E4 0x0874 0x6 0x0 +#define MX6SX_PAD_SD4_DATA7__TPSMP_HDATA_15 0x029C 0x05E4 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_DATA7__USB_OTG_PWR_WAKE 0x029C 0x05E4 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_DATA7__SDMA_DEBUG_YIELD 0x029C 0x05E4 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x02A0 0x05E8 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_RESET_B__RAWNAND_DQS 0x02A0 0x05E8 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET 0x02A0 0x05E8 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_RESET_B__AUDMUX_MCLK 0x02A0 0x05E8 0x0000 0x3 0x0 +#define MX6SX_PAD_SD4_RESET_B__LCDIF2_RESET 0x02A0 0x05E8 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x02A0 0x05E8 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_RESET_B__LCDIF2_CS 0x02A0 0x05E8 0x0000 0x6 0x0 +#define MX6SX_PAD_SD4_RESET_B__TPSMP_HDATA_25 0x02A0 0x05E8 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_RESET_B__VDEC_DEBUG_17 0x02A0 0x05E8 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2 0x02A0 0x05E8 0x0000 0x9 0x0 +#define MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x02A4 0x05EC 0x0000 0x0 0x0 +#define MX6SX_PAD_USB_H_DATA__PWM2_OUT 0x02A4 0x05EC 0x0000 0x1 0x0 +#define MX6SX_PAD_USB_H_DATA__ANATOP_24M_OUT 0x02A4 0x05EC 0x0000 0x2 0x0 +#define MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x02A4 0x05EC 0x07C4 0x3 0x1 +#define MX6SX_PAD_USB_H_DATA__WDOG3_WDOG_B 0x02A4 0x05EC 0x0000 0x4 0x0 +#define MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 0x02A4 0x05EC 0x0000 0x5 0x0 +#define MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x02A8 0x05F0 0x0000 0x0 0x0 +#define MX6SX_PAD_USB_H_STROBE__PWM1_OUT 0x02A8 0x05F0 0x0000 0x1 0x0 +#define MX6SX_PAD_USB_H_STROBE__ANATOP_32K_OUT 0x02A8 0x05F0 0x0000 0x2 0x0 +#define MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x02A8 0x05F0 0x07C0 0x3 0x1 +#define MX6SX_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB 0x02A8 0x05F0 0x0000 0x4 0x0 +#define MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x02A8 0x05F0 0x0000 0x5 0x0 + +#endif /* __DTS_IMX6SX_PINFUNC_H */ -- cgit v1.2.3 From b1d17f68e5c5ffe131c53be792f03996430d86cd Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 13 May 2014 20:21:35 +0800 Subject: ARM: dts: imx: add initial imx6sx device tree source Add initial device tree source for i.MX6 SoloX SoC. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx.dtsi | 1202 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 1202 insertions(+) create mode 100644 arch/arm/boot/dts/imx6sx.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi new file mode 100644 index 000000000000..ac3866c80727 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -0,0 +1,1202 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include "imx6sx-pinfunc.h" +#include "skeleton.dtsi" + +/ { + aliases { + can0 = &flexcan1; + can1 = &flexcan2; + ethernet0 = &fec1; + ethernet1 = &fec2; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + mmc3 = &usdhc4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; + spi4 = &ecspi5; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1075000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6SX_CLK_ARM>, + <&clks IMX6SX_CLK_PLL2_PFD2>, + <&clks IMX6SX_CLK_STEP>, + <&clks IMX6SX_CLK_PLL1_SW>, + <&clks IMX6SX_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + soc-supply = <®_soc>; + }; + }; + + intc: interrupt-controller@00a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a00100 0x100>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock@1 { + compatible = "fixed-clock"; + reg = <1>; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + ipp_di0: clock@2 { + compatible = "fixed-clock"; + reg = <2>; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di0"; + }; + + ipp_di1: clock@3 { + compatible = "fixed-clock"; + reg = <3>; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di1"; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = ; + }; + + ocram: sram@00900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; + clocks = <&clks IMX6SX_CLK_OCRAM>; + }; + + L2: l2-cache@00a02000 { + compatible = "arm,pl310-cache"; + reg = <0x00a02000 0x1000>; + interrupts = ; + cache-unified; + cache-level = <2>; + arm,tag-latency = <4 2 3>; + arm,data-latency = <4 2 3>; + }; + + dma_apbh: dma-apbh@01804000 { + compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x01804000 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clks IMX6SX_CLK_APBH_DMA>; + }; + + gpmi: gpmi-nand@01806000{ + compatible = "fsl,imx6sx-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01806000 0x2000>, <0x01808000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clks IMX6SX_CLK_GPMI_IO>, + <&clks IMX6SX_CLK_GPMI_APB>, + <&clks IMX6SX_CLK_GPMI_BCH>, + <&clks IMX6SX_CLK_GPMI_BCH_APB>, + <&clks IMX6SX_CLK_PER1_BCH>; + clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", + "gpmi_bch_apb", "per1_bch"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + aips1: aips-bus@02000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba-bus@02000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + spdif: spdif@02004000 { + compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; + reg = <0x02004000 0x4000>; + interrupts = ; + dmas = <&sdma 14 18 0>, + <&sdma 15 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SX_CLK_SPDIF>, + <&clks IMX6SX_CLK_OSC>, + <&clks IMX6SX_CLK_SPDIF>, + <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6SX_CLK_IPG>, + <&clks 0>, <&clks 0>, + <&clks IMX6SX_CLK_SPBA>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "dma"; + status = "disabled"; + }; + + ecspi1: ecspi@02008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_ECSPI1>, + <&clks IMX6SX_CLK_ECSPI1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: ecspi@0200c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_ECSPI2>, + <&clks IMX6SX_CLK_ECSPI2>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: ecspi@02010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_ECSPI3>, + <&clks IMX6SX_CLK_ECSPI3>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi4: ecspi@02014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_ECSPI4>, + <&clks IMX6SX_CLK_ECSPI4>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@02020000 { + compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_UART_IPG>, + <&clks IMX6SX_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + esai: esai@02024000 { + reg = <0x02024000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_ESAI_IPG>, + <&clks IMX6SX_CLK_ESAI_MEM>, + <&clks IMX6SX_CLK_ESAI_EXTAL>, + <&clks IMX6SX_CLK_ESAI_IPG>, + <&clks IMX6SX_CLK_SPBA>; + clock-names = "core", "mem", "extal", + "fsys", "dma"; + status = "disabled"; + }; + + ssi1: ssi@02028000 { + compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi"; + reg = <0x02028000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_SSI1_IPG>, + <&clks IMX6SX_CLK_SSI1>; + clock-names = "ipg", "baud"; + dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ssi2: ssi@0202c000 { + compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi"; + reg = <0x0202c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_SSI2_IPG>, + <&clks IMX6SX_CLK_SSI2>; + clock-names = "ipg", "baud"; + dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ssi3: ssi@02030000 { + compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi"; + reg = <0x02030000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_SSI3_IPG>, + <&clks IMX6SX_CLK_SSI3>; + clock-names = "ipg", "baud"; + dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + asrc: asrc@02034000 { + reg = <0x02034000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_ASRC_MEM>, + <&clks IMX6SX_CLK_ASRC_IPG>, + <&clks IMX6SX_CLK_SPDIF>, + <&clks IMX6SX_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck", "dma"; + dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, + <&sdma 19 20 1>, <&sdma 20 20 1>, + <&sdma 21 20 1>, <&sdma 22 20 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + status = "okay"; + }; + }; + + pwm1: pwm@02080000 { + compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; + reg = <0x02080000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PWM1>, + <&clks IMX6SX_CLK_PWM1>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm2: pwm@02084000 { + compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; + reg = <0x02084000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PWM2>, + <&clks IMX6SX_CLK_PWM2>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm3: pwm@02088000 { + compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; + reg = <0x02088000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PWM3>, + <&clks IMX6SX_CLK_PWM3>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm4: pwm@0208c000 { + compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; + reg = <0x0208c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PWM4>, + <&clks IMX6SX_CLK_PWM4>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + flexcan1: can@02090000 { + compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; + reg = <0x02090000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_CAN1_IPG>, + <&clks IMX6SX_CLK_CAN1_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + flexcan2: can@02094000 { + compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; + reg = <0x02094000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_CAN2_IPG>, + <&clks IMX6SX_CLK_CAN2_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt: gpt@02098000 { + compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt"; + reg = <0x02098000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_GPT_BUS>, + <&clks IMX6SX_CLK_GPT_SERIAL>; + clock-names = "ipg", "per"; + }; + + gpio1: gpio@0209c000 { + compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@020a0000 { + compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@020a4000 { + compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@020a8000 { + compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@020ac000 { + compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@020b0000 { + compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; + reg = <0x020b0000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@020b4000 { + compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; + reg = <0x020b4000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + kpp: kpp@020b8000 { + compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; + reg = <0x020b8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_DUMMY>; + status = "disabled"; + }; + + wdog1: wdog@020bc000 { + compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_DUMMY>; + }; + + wdog2: wdog@020c0000 { + compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_DUMMY>; + status = "disabled"; + }; + + clks: ccm@020c4000 { + compatible = "fsl,imx6sx-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + }; + + anatop: anatop@020c8000 { + compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x020c8000 0x1000>; + interrupts = , + , + ; + + regulator-1p1@110 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1375000>; + regulator-always-on; + anatop-reg-offset = <0x110>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <4>; + anatop-min-voltage = <800000>; + anatop-max-voltage = <1375000>; + }; + + regulator-3p0@120 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + }; + + regulator-2p5@130 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2875000>; + regulator-always-on; + anatop-reg-offset = <0x130>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2100000>; + anatop-max-voltage = <2875000>; + }; + + reg_arm: regulator-vddcore@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "cpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <0>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <24>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_pcie: regulator-vddpcie@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddpcie"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <9>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <26>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_soc: regulator-vddsoc@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddsoc"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <18>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <28>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + }; + + tempmon: tempmon { + compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; + interrupts = ; + fsl,tempmon = <&anatop>; + fsl,tempmon-data = <&ocotp>; + clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; + }; + + usbphy1: usbphy@020c9000 { + compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USBPHY1>; + fsl,anatop = <&anatop>; + }; + + usbphy2: usbphy@020ca000 { + compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USBPHY2>; + fsl,anatop = <&anatop>; + }; + + snvs: snvs@020cc000 { + compatible = "fsl,sec-v4.0-mon", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x020cc000 0x4000>; + + snvs-rtc-lp@34 { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + reg = <0x34 0x58>; + interrupts = , ; + }; + }; + + epit1: epit@020d0000 { + reg = <0x020d0000 0x4000>; + interrupts = ; + }; + + epit2: epit@020d4000 { + reg = <0x020d4000 0x4000>; + interrupts = ; + }; + + src: src@020d8000 { + compatible = "fsl,imx6sx-src", "fsl,imx51-src"; + reg = <0x020d8000 0x4000>; + interrupts = , + ; + #reset-cells = <1>; + }; + + gpc: gpc@020dc000 { + compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupts = ; + }; + + iomuxc: iomuxc@020e0000 { + compatible = "fsl,imx6sx-iomuxc"; + reg = <0x020e0000 0x4000>; + }; + + gpr: iomuxc-gpr@020e4000 { + compatible = "fsl,imx6sx-iomuxc-gpr", "syscon"; + reg = <0x020e4000 0x4000>; + }; + + sdma: sdma@020ec000 { + compatible = "fsl,imx6sx-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_SDMA>, + <&clks IMX6SX_CLK_SDMA>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + }; + }; + + aips2: aips-bus@02100000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + usbotg1: usb@02184000 { + compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + fsl,anatop = <&anatop>; + status = "disabled"; + }; + + usbotg2: usb@02184200 { + compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USBOH3>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; + status = "disabled"; + }; + + usbh: usb@02184400 { + compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; + reg = <0x02184400 0x200>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USBOH3>; + fsl,usbmisc = <&usbmisc 2>; + phy_type = "hsic"; + fsl,anatop = <&anatop>; + status = "disabled"; + }; + + usbmisc: usbmisc@02184800 { + #index-cells = <1>; + compatible = "fsl,imx6sx-usbmisc"; + reg = <0x02184800 0x200>; + clocks = <&clks IMX6SX_CLK_USBOH3>; + }; + + fec1: ethernet@02188000 { + compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; + reg = <0x02188000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6SX_CLK_ENET>, + <&clks IMX6SX_CLK_ENET_AHB>, + <&clks IMX6SX_CLK_ENET_PTP>, + <&clks IMX6SX_CLK_ENET_REF>, + <&clks IMX6SX_CLK_ENET_PTP>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + status = "disabled"; + }; + + mlb: mlb@0218c000 { + reg = <0x0218c000 0x4000>; + interrupts = , + , + ; + clocks = <&clks IMX6SX_CLK_MLB>; + status = "disabled"; + }; + + usdhc1: usdhc@02190000 { + compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USDHC1>, + <&clks IMX6SX_CLK_USDHC1>, + <&clks IMX6SX_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: usdhc@02194000 { + compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USDHC2>, + <&clks IMX6SX_CLK_USDHC2>, + <&clks IMX6SX_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: usdhc@02198000 { + compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x02198000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USDHC3>, + <&clks IMX6SX_CLK_USDHC3>, + <&clks IMX6SX_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc4: usdhc@0219c000 { + compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x0219c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USDHC4>, + <&clks IMX6SX_CLK_USDHC4>, + <&clks IMX6SX_CLK_USDHC4>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + i2c1: i2c@021a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@021a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@021a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_I2C3>; + status = "disabled"; + }; + + mmdc: mmdc@021b0000 { + compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + }; + + fec2: ethernet@021b4000 { + compatible = "fsl,imx6sx-fec"; + reg = <0x021b4000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6SX_CLK_ENET>, + <&clks IMX6SX_CLK_ENET_AHB>, + <&clks IMX6SX_CLK_ENET_PTP>, + <&clks IMX6SX_CLK_ENET2_REF_125M>, + <&clks IMX6SX_CLK_ENET_PTP>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + status = "disabled"; + }; + + weim: weim@021b8000 { + compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; + reg = <0x021b8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_EIM_SLOW>; + }; + + ocotp: ocotp@021bc000 { + compatible = "fsl,imx6sx-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6SX_CLK_OCOTP>; + }; + + sai1: sai@021d4000 { + compatible = "fsl,imx6sx-sai"; + reg = <0x021d4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_SAI1_IPG>, + <&clks IMX6SX_CLK_SAI1>, + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 31 23 0>, <&sdma 32 23 0>; + dma-source = <&gpr 0 15 0 16>; + status = "disabled"; + }; + + audmux: audmux@021d8000 { + compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; + reg = <0x021d8000 0x4000>; + status = "disabled"; + }; + + sai2: sai@021dc000 { + compatible = "fsl,imx6sx-sai"; + reg = <0x021dc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_SAI2_IPG>, + <&clks IMX6SX_CLK_SAI2>, + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 33 23 0>, <&sdma 34 23 0>; + dma-source = <&gpr 0 17 0 18>; + status = "disabled"; + }; + + qspi1: qspi@021e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-qspi"; + reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clks IMX6SX_CLK_QSPI1>, + <&clks IMX6SX_CLK_QSPI1>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + qspi2: qspi@021e4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-qspi"; + reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clks IMX6SX_CLK_QSPI2>, + <&clks IMX6SX_CLK_QSPI2>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + uart2: serial@021e8000 { + compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + reg = <0x021e8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_UART_IPG>, + <&clks IMX6SX_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@021ec000 { + compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + reg = <0x021ec000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_UART_IPG>, + <&clks IMX6SX_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart4: serial@021f0000 { + compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + reg = <0x021f0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_UART_IPG>, + <&clks IMX6SX_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial@021f4000 { + compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + reg = <0x021f4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_UART_IPG>, + <&clks IMX6SX_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c4: i2c@021f8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; + reg = <0x021f8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_I2C4>; + status = "disabled"; + }; + }; + + aips3: aips-bus@02200000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02200000 0x100000>; + ranges; + + spba-bus@02200000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02240000 0x40000>; + ranges; + + csi1: csi@02214000 { + reg = <0x02214000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, + <&clks IMX6SX_CLK_CSI>, + <&clks IMX6SX_CLK_DCIC1>; + clock-names = "disp-axi", "csi_mclk", "dcic"; + status = "disabled"; + }; + + pxp: pxp@02218000 { + reg = <0x02218000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PXP_AXI>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "pxp-axi", "disp-axi"; + status = "disabled"; + }; + + csi2: csi@0221c000 { + reg = <0x0221c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, + <&clks IMX6SX_CLK_CSI>, + <&clks IMX6SX_CLK_DCIC2>; + clock-names = "disp-axi", "csi_mclk", "dcic"; + status = "disabled"; + }; + + lcdif1: lcdif@02220000 { + reg = <0x02220000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, + <&clks IMX6SX_CLK_LCDIF_APB>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; + }; + + lcdif2: lcdif@02224000 { + reg = <0x02224000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, + <&clks IMX6SX_CLK_LCDIF_APB>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; + }; + + vadc: vadc@02228000 { + reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; + reg-names = "vadc-vafe", "vadc-vdec"; + clocks = <&clks IMX6SX_CLK_VADC>, + <&clks IMX6SX_CLK_CSI>; + clock-names = "vadc", "csi"; + status = "disabled"; + }; + }; + + adc1: adc@02280000 { + compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; + reg = <0x02280000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_IPG>; + clock-names = "adc"; + status = "disabled"; + }; + + adc2: adc@02284000 { + compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; + reg = <0x02284000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_IPG>; + clock-names = "adc"; + status = "disabled"; + }; + + wdog3: wdog@02288000 { + compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; + reg = <0x02288000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_DUMMY>; + status = "disabled"; + }; + + ecspi5: ecspi@0228c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; + reg = <0x0228c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_ECSPI5>, + <&clks IMX6SX_CLK_ECSPI5>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart6: serial@022a0000 { + compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + reg = <0x022a0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_UART_IPG>, + <&clks IMX6SX_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + pwm5: pwm@022a4000 { + compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; + reg = <0x022a4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PWM5>, + <&clks IMX6SX_CLK_PWM5>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm6: pwm@022a8000 { + compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; + reg = <0x022a8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PWM6>, + <&clks IMX6SX_CLK_PWM6>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm7: pwm@022ac000 { + compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; + reg = <0x022ac000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PWM7>, + <&clks IMX6SX_CLK_PWM7>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm8: pwm@0022b0000 { + compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; + reg = <0x0022b0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PWM8>, + <&clks IMX6SX_CLK_PWM8>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + }; + + pcie: pcie@0x08000000 { + compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; + reg = <0x08ffc000 0x4000>; /* DBI */ + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + /* configuration space */ + ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000 + /* downstream I/O */ + 0x81000000 0 0 0x08f80000 0 0x00010000 + /* non-prefetchable memory */ + 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; + num-lanes = <1>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>, + <&clks IMX6SX_CLK_PCIE_AXI>, + <&clks IMX6SX_CLK_LVDS1_OUT>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "pcie_ref_125m", "pcie_axi", + "lvds_gate", "display_axi"; + status = "disabled"; + }; + }; +}; -- cgit v1.2.3 From d2daa2f765f9972c61fa0b361dcdb2a81b45a278 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 13 May 2014 21:43:36 +0800 Subject: ARM: dts: imx: add initial imx6sx-sdb board support Add initial imx6sx-sdb board support with limited devices enabled. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6sx-sdb.dts | 210 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 211 insertions(+) create mode 100644 arch/arm/boot/dts/imx6sx-sdb.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index adb5ed9e269e..cc776fcea73a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -216,6 +216,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-udoo.dtb \ imx6q-wandboard.dtb \ imx6sl-evk.dtb \ + imx6sx-sdb.dtb \ vf610-colibri.dtb \ vf610-cosmic.dtb \ vf610-twr.dtb diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts new file mode 100644 index 000000000000..9906f654e494 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6sx.dtsi" + +/ { + model = "Freescale i.MX6 SoloX SDB Board"; + compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vcc_sd3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_sd3>; + regulator-name = "VCC_SD3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart5 { /* for bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <&vcc_sd3>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + imx6x-sdb { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_vcc_sd3: vccsd3grp { + fsl,pins = < + MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ + MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ + >; + }; + }; +}; -- cgit v1.2.3 From d8cae888aa2bc0fe0905fd24d859bad8ce77aaec Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Tue, 13 May 2014 18:48:15 +0400 Subject: ARM: dts: Add support for the cpuimx27 board from Eukrea and its baseboard This patch adds support for the cpuimx27 board from Eukrea and its baseboard. This change is intended to further remove non-DT support for this board. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi | 296 +++++++++++++++++++++ .../boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts | 274 +++++++++++++++++++ 3 files changed, 571 insertions(+) create mode 100644 arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi create mode 100644 arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index cc776fcea73a..677154184697 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -161,6 +161,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx25-pdk.dtb \ imx27-apf27.dtb \ imx27-apf27dev.dtb \ + imx27-eukrea-mbimxsd27-baseboard.dtb \ imx27-pdk.dtb \ imx27-phytec-phycore-rdk.dtb \ imx27-phytec-phycard-s-rdk.dtb \ diff --git a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi new file mode 100644 index 000000000000..e2242638ea0b --- /dev/null +++ b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi @@ -0,0 +1,296 @@ +/* + * Copyright (C) 2014 Alexander Shiyan + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx27.dtsi" + +/ { + model = "Eukrea CPUIMX27"; + compatible = "eukrea,cpuimx27", "fsl,imx27"; + + memory { + reg = <0xa0000000 0x04000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-bus"; + + clk14745600: clock@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <14745600>; + reg = <0>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&owire { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_owire>; + status = "okay"; +}; + +&sdhci2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhc2>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2>; + dr_mode = "host"; + phy_type = "ulpi"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + phy_type = "ulpi"; + disable-over-current; + status = "okay"; +}; + +&weim { + status = "okay"; + + nor: nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + linux,mtd-name = "physmap-flash.0"; + fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>; + }; + + uart8250@3,200000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8250_1>; + compatible = "ns8250"; + clocks = <&clk14745600>; + fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; + interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>; + reg = <3 0x200000 0x1000>; + reg-shift = <1>; + reg-io-width = <1>; + no-loopback-test; + }; + + uart8250@3,400000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8250_2>; + compatible = "ns8250"; + clocks = <&clk14745600>; + fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; + interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>; + reg = <3 0x400000 0x1000>; + reg-shift = <1>; + reg-io-width = <1>; + no-loopback-test; + }; + + uart8250@3,800000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8250_3>; + compatible = "ns8250"; + clocks = <&clk14745600>; + fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; + interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>; + reg = <3 0x800000 0x1000>; + reg-shift = <1>; + reg-io-width = <1>; + no-loopback-test; + }; + + uart8250@3,1000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8250_4>; + compatible = "ns8250"; + clocks = <&clk14745600>; + fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; + interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>; + reg = <3 0x1000000 0x1000>; + reg-shift = <1>; + reg-io-width = <1>; + no-loopback-test; + }; +}; + +&iomuxc { + imx27-eukrea-cpuimx27 { + pinctrl_fec: fecgrp { + fsl,pins = < + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX27_PAD_I2C_DATA__I2C_DATA 0x0 + MX27_PAD_I2C_CLK__I2C_CLK 0x0 + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + MX27_PAD_NFRB__NFRB 0x0 + MX27_PAD_NFCLE__NFCLE 0x0 + MX27_PAD_NFWP_B__NFWP_B 0x0 + MX27_PAD_NFCE_B__NFCE_B 0x0 + MX27_PAD_NFALE__NFALE 0x0 + MX27_PAD_NFRE_B__NFRE_B 0x0 + MX27_PAD_NFWE_B__NFWE_B 0x0 + >; + }; + + pinctrl_owire: owiregrp { + fsl,pins = < + MX27_PAD_RTCK__OWIRE 0x0 + >; + }; + + pinctrl_sdhc2: sdhc2grp { + fsl,pins = < + MX27_PAD_SD2_CLK__SD2_CLK 0x0 + MX27_PAD_SD2_CMD__SD2_CMD 0x0 + MX27_PAD_SD2_D0__SD2_D0 0x0 + MX27_PAD_SD2_D1__SD2_D1 0x0 + MX27_PAD_SD2_D2__SD2_D2 0x0 + MX27_PAD_SD2_D3__SD2_D3 0x0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX27_PAD_USBH1_TXDM__UART4_TXD 0x0 + MX27_PAD_USBH1_RXDP__UART4_RXD 0x0 + MX27_PAD_USBH1_TXDP__UART4_CTS 0x0 + MX27_PAD_USBH1_FS__UART4_RTS 0x0 + >; + }; + + pinctrl_uart8250_1: uart82501grp { + fsl,pins = < + MX27_PAD_USB_PWR__GPIO2_23 0x0 + >; + }; + + pinctrl_uart8250_2: uart82502grp { + fsl,pins = < + MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 + >; + }; + + pinctrl_uart8250_3: uart82503grp { + fsl,pins = < + MX27_PAD_USBH1_OE_B__GPIO2_27 0x0 + >; + }; + + pinctrl_uart8250_4: uart82504grp { + fsl,pins = < + MX27_PAD_USBH1_RXDM__GPIO2_30 0x0 + >; + }; + + pinctrl_usbh2: usbh2grp { + fsl,pins = < + MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 + MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 + MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 + MX27_PAD_USBH2_STP__USBH2_STP 0x0 + MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 + MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 + MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 + MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 + MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 + MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 + MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 + MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 + MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 + MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 + MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 + MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 + MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 + MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 + MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 + MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 + MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 + MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 + MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts new file mode 100644 index 000000000000..bb64ca1667f4 --- /dev/null +++ b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts @@ -0,0 +1,274 @@ +/* + * Copyright (C) 2014 Alexander Shiyan + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx27-eukrea-cpuimx27.dtsi" + +/ { + model = "Eukrea MBIMXSD27"; + compatible = "eukrea,mbimxsd27-baseboard", "eukrea,cpuimx27", "fsl,imx27"; + + display0: CMO-QVGA { + model = "CMO-QVGA"; + native-mode = <&timing0>; + bits-per-pixel = <16>; + fsl,pcr = <0xfad08b80>; + + display-timings { + timing0: 320x240 { + clock-frequency = <6500000>; + hactive = <320>; + vactive = <240>; + hback-porch = <20>; + hsync-len = <30>; + hfront-porch = <38>; + vback-porch = <4>; + vsync-len = <3>; + vfront-porch = <15>; + }; + }; + }; + + backlight { + compatible = "gpio-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioleds>; + + led1 { + label = "system::live"; + gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led2 { + label = "system::user"; + gpios = <&gpio6 19 GPIO_ACTIVE_LOW>; + }; + }; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-bus"; + + reg_lcd: regulator@0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdreg>; + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "LCD"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&cspi1 { + pinctrl-0 = <&pinctrl_cspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + status = "okay"; + + ads7846 { + compatible = "ti,ads7846"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + reg = <0>; + interrupts = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; + spi-cpol; + spi-max-frequency = <1500000>; + ti,keep-vref-on; + }; +}; + +&fb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imxfb>; + display = <&display0>; + lcd-supply = <®_lcd>; + fsl,dmacr = <0x00040060>; + fsl,lscr1 = <0x00120300>; + fsl,lpccr = <0x00a903ff>; + status = "okay"; +}; + +&i2c1 { + codec: codec@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + }; +}; + +&kpp { + linux,keymap = < + MATRIX_KEY(0, 0, KEY_UP) + MATRIX_KEY(0, 1, KEY_DOWN) + MATRIX_KEY(1, 0, KEY_RIGHT) + MATRIX_KEY(1, 1, KEY_LEFT) + >; + status = "okay"; +}; + +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&ssi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssi1>; + fsl,mode = "i2s-slave"; + codec-handle = <&codec>; + status = "okay"; +}; + +&uart1 { + fsl,uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + fsl,uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + fsl,uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&iomuxc { + imx27-eukrea-cpuimx27-baseboard { + pinctrl_cspi1: cspi1grp { + fsl,pins = < + MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 + MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 + MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 + MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* CS0 */ + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX27_PAD_PWMO__GPIO5_5 0x0 + >; + }; + + pinctrl_gpioleds: gpioledsgrp { + fsl,pins = < + MX27_PAD_PC_PWRON__GPIO6_16 0x0 + MX27_PAD_PC_CD2_B__GPIO6_19 0x0 + >; + }; + + pinctrl_imxfb: imxfbgrp { + fsl,pins = < + MX27_PAD_LD0__LD0 0x0 + MX27_PAD_LD1__LD1 0x0 + MX27_PAD_LD2__LD2 0x0 + MX27_PAD_LD3__LD3 0x0 + MX27_PAD_LD4__LD4 0x0 + MX27_PAD_LD5__LD5 0x0 + MX27_PAD_LD6__LD6 0x0 + MX27_PAD_LD7__LD7 0x0 + MX27_PAD_LD8__LD8 0x0 + MX27_PAD_LD9__LD9 0x0 + MX27_PAD_LD10__LD10 0x0 + MX27_PAD_LD11__LD11 0x0 + MX27_PAD_LD12__LD12 0x0 + MX27_PAD_LD13__LD13 0x0 + MX27_PAD_LD14__LD14 0x0 + MX27_PAD_LD15__LD15 0x0 + MX27_PAD_LD16__LD16 0x0 + MX27_PAD_LD17__LD17 0x0 + MX27_PAD_CONTRAST__CONTRAST 0x0 + MX27_PAD_OE_ACD__OE_ACD 0x0 + MX27_PAD_HSYNC__HSYNC 0x0 + MX27_PAD_VSYNC__VSYNC 0x0 + >; + }; + + pinctrl_lcdreg: lcdreggrp { + fsl,pins = < + MX27_PAD_CLS__GPIO1_25 0x0 + >; + }; + + pinctrl_sdhc1: sdhc1grp { + fsl,pins = < + MX27_PAD_SD1_CLK__SD1_CLK 0x0 + MX27_PAD_SD1_CMD__SD1_CMD 0x0 + MX27_PAD_SD1_D0__SD1_D0 0x0 + MX27_PAD_SD1_D1__SD1_D1 0x0 + MX27_PAD_SD1_D2__SD1_D2 0x0 + MX27_PAD_SD1_D3__SD1_D3 0x0 + >; + }; + + pinctrl_ssi1: ssi1grp { + fsl,pins = < + MX27_PAD_SSI4_CLK__SSI4_CLK 0x0 + MX27_PAD_SSI4_FS__SSI4_FS 0x0 + MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x1 + MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x1 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX27_PAD_CSPI1_RDY__GPIO4_25 0x0 /* IRQ */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + MX27_PAD_UART1_CTS__UART1_CTS 0x0 + MX27_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX27_PAD_UART2_TXD__UART2_TXD 0x0 + MX27_PAD_UART2_RXD__UART2_RXD 0x0 + MX27_PAD_UART2_CTS__UART2_CTS 0x0 + MX27_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX27_PAD_UART3_TXD__UART3_TXD 0x0 + MX27_PAD_UART3_RXD__UART3_RXD 0x0 + MX27_PAD_UART3_CTS__UART3_CTS 0x0 + MX27_PAD_UART3_RTS__UART3_RTS 0x0 + >; + }; + }; +}; -- cgit v1.2.3 From f3c723801cb7bf4b19bf5e155246bfd68c4c618f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 14 May 2014 16:53:55 -0300 Subject: ARM: dts: imx6qdl-sabresd: Configure the ECSPI1 chip select pin GPIO4_9 is used as ECSPI1 chip select and it needs to be configured as GPIO. Configure the pin functionality explicitly in the dts file instead of relying on the fact that it comes configured as GPIO from POR or from the bootloader. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 40ea36534643..e44619218bab 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -340,6 +340,7 @@ MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 >; }; -- cgit v1.2.3 From 01d41c9cdb08e3652529810e531704d6a445b4ca Mon Sep 17 00:00:00 2001 From: Fugang Duan Date: Tue, 20 May 2014 14:50:44 +0800 Subject: ARM: dts: imx6sl: add fec sleep pinctrl for pin PM state when system suspend, need to set pins to low power state to save IO power consumption, there are three states of pinctrl: "default", "idle" and "sleep". Currently enet supports default and sleep state. Signed-off-by: Fugang Duan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl-evk.dts | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index a8d9a93fab85..050786dc6df1 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -116,8 +116,9 @@ }; &fec { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; phy-mode = "rmii"; status = "okay"; }; @@ -300,6 +301,19 @@ >; }; + pinctrl_fec_sleep: fecgrp-sleep { + fsl,pins = < + MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080 + MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080 + MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080 + MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080 + MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080 + MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080 + MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080 + MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 -- cgit v1.2.3 From a3f8c564825d08db7daa8b703271dad96c74a946 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 15 May 2014 17:12:48 +0200 Subject: ARM: dt: imx28-cfa10036: introduce a regulator for mmc0 The PWM3 pinmux configuration conflicts with gpio 3.28. Introduce a regulator for mmc0 so that it conflicts with the pwm driver and fails gracefully. The kernel will then able to access mmc0 normally. Signed-off-by: Alexandre Belloni Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-cfa10036.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts index ae7c3390e65a..b04b6b8850a7 100644 --- a/arch/arm/boot/dts/imx28-cfa10036.dts +++ b/arch/arm/boot/dts/imx28-cfa10036.dts @@ -53,6 +53,17 @@ fsl,pull-up = ; }; + mmc_pwr_cfa10036: mmc_pwr_cfa10036@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x31c3 /* + MX28_PAD_PWM3__GPIO_3_28 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; ssp0: ssp@80010000 { @@ -60,6 +71,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_cd_cfg &mmc0_sck_cfg>; + vmmc-supply = <®_vddio_sd0>; bus-width = <4>; status = "okay"; }; @@ -116,4 +128,14 @@ default-state = "on"; }; }; + + reg_vddio_sd0: vddio-sd0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc_pwr_cfa10036>; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 28 0>; + }; }; -- cgit v1.2.3 From b12d1e94a341a542ef89a894572eeb3ea54822c5 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 21 May 2014 23:04:54 -0700 Subject: ARM: dts: imx6: ventana: change sound device name The 'model' property in the imx-audio-sgtl5000 binding specifies the user-visible name of the audio device. This should be something common and not baseboard specific. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-gw5400-a.dts | 4 ++-- arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index 3689eaa58826..fced8bbc2f38 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -115,9 +115,9 @@ }; sound { - compatible = "fsl,imx6q-sabrelite-sgtl5000", + compatible = "fsl,imx6q-ventana-sgtl5000", "fsl,imx-audio-sgtl5000"; - model = "imx6q-sabrelite-sgtl5000"; + model = "sgtl5000-audio"; ssi-controller = <&ssi1>; audio-codec = <&codec>; audio-routing = diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 744c8a2d81f6..7a247f30bca8 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -121,9 +121,9 @@ }; sound { - compatible = "fsl,imx6q-sabrelite-sgtl5000", + compatible = "fsl,imx6q-ventana-sgtl5000", "fsl,imx-audio-sgtl5000"; - model = "imx6q-sabrelite-sgtl5000"; + model = "sgtl5000-audio"; ssi-controller = <&ssi1>; audio-codec = <&codec>; audio-routing = diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index adf150c1be90..d3125f0faa77 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -124,9 +124,9 @@ }; sound { - compatible = "fsl,imx6q-sabrelite-sgtl5000", + compatible = "fsl,imx6q-ventana-sgtl5000", "fsl,imx-audio-sgtl5000"; - model = "imx6q-sabrelite-sgtl5000"; + model = "sgtl5000-audio"; ssi-controller = <&ssi1>; audio-codec = <&codec>; audio-routing = diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 698d3063b295..532347f3f7d3 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -114,9 +114,9 @@ }; sound { - compatible = "fsl,imx6q-sabrelite-sgtl5000", + compatible = "fsl,imx6q-ventana-sgtl5000", "fsl,imx-audio-sgtl5000"; - model = "imx6q-sabrelite-sgtl5000"; + model = "sgtl5000-audio"; ssi-controller = <&ssi1>; audio-codec = <&codec>; audio-routing = -- cgit v1.2.3 From 455f9fb4847d7194dfe4a8afd28afcc0f83926bc Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 21 May 2014 23:04:55 -0700 Subject: ARM: dts: imx6: ventana: update model to reflect Dual/Solo CPU types The imx6dl dts supports both DualLite and Solo CPU variants The imx6q dts supports both Dual and Quad CPU variants Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-gw51xx.dts | 2 +- arch/arm/boot/dts/imx6dl-gw52xx.dts | 2 +- arch/arm/boot/dts/imx6dl-gw53xx.dts | 2 +- arch/arm/boot/dts/imx6dl-gw54xx.dts | 2 +- arch/arm/boot/dts/imx6q-gw51xx.dts | 2 +- arch/arm/boot/dts/imx6q-gw52xx.dts | 2 +- arch/arm/boot/dts/imx6q-gw53xx.dts | 2 +- arch/arm/boot/dts/imx6q-gw54xx.dts | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6dl-gw51xx.dts b/arch/arm/boot/dts/imx6dl-gw51xx.dts index 4bd055f4c930..b2bd022fc6be 100644 --- a/arch/arm/boot/dts/imx6dl-gw51xx.dts +++ b/arch/arm/boot/dts/imx6dl-gw51xx.dts @@ -14,6 +14,6 @@ #include "imx6qdl-gw51xx.dtsi" / { - model = "Gateworks Ventana i.MX6 DualLite GW51XX"; + model = "Gateworks Ventana i.MX6 DualLite/Solo GW51XX"; compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl"; }; diff --git a/arch/arm/boot/dts/imx6dl-gw52xx.dts b/arch/arm/boot/dts/imx6dl-gw52xx.dts index c9136058f15e..a2e0b73fdd4a 100644 --- a/arch/arm/boot/dts/imx6dl-gw52xx.dts +++ b/arch/arm/boot/dts/imx6dl-gw52xx.dts @@ -14,6 +14,6 @@ #include "imx6qdl-gw52xx.dtsi" / { - model = "Gateworks Ventana i.MX6 DualLite GW52XX"; + model = "Gateworks Ventana i.MX6 DualLite/Solo GW52XX"; compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl"; }; diff --git a/arch/arm/boot/dts/imx6dl-gw53xx.dts b/arch/arm/boot/dts/imx6dl-gw53xx.dts index 61818a14fde6..6844b708d2f8 100644 --- a/arch/arm/boot/dts/imx6dl-gw53xx.dts +++ b/arch/arm/boot/dts/imx6dl-gw53xx.dts @@ -14,6 +14,6 @@ #include "imx6qdl-gw53xx.dtsi" / { - model = "Gateworks Ventana i.MX6 DualLite GW53XX"; + model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX"; compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl"; }; diff --git a/arch/arm/boot/dts/imx6dl-gw54xx.dts b/arch/arm/boot/dts/imx6dl-gw54xx.dts index ab38b6770a06..be915412f852 100644 --- a/arch/arm/boot/dts/imx6dl-gw54xx.dts +++ b/arch/arm/boot/dts/imx6dl-gw54xx.dts @@ -14,6 +14,6 @@ #include "imx6qdl-gw54xx.dtsi" / { - model = "Gateworks Ventana i.MX6 DualLite GW54XX"; + model = "Gateworks Ventana i.MX6 DualLite/Solo GW54XX"; compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl"; }; diff --git a/arch/arm/boot/dts/imx6q-gw51xx.dts b/arch/arm/boot/dts/imx6q-gw51xx.dts index 0e1406e58eff..8e8bcd8fe0fb 100644 --- a/arch/arm/boot/dts/imx6q-gw51xx.dts +++ b/arch/arm/boot/dts/imx6q-gw51xx.dts @@ -14,6 +14,6 @@ #include "imx6qdl-gw51xx.dtsi" / { - model = "Gateworks Ventana i.MX6 Quad GW51XX"; + model = "Gateworks Ventana i.MX6 Dual/Quad GW51XX"; compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q"; }; diff --git a/arch/arm/boot/dts/imx6q-gw52xx.dts b/arch/arm/boot/dts/imx6q-gw52xx.dts index 5f71ddbc7f05..a12c47e5ee05 100644 --- a/arch/arm/boot/dts/imx6q-gw52xx.dts +++ b/arch/arm/boot/dts/imx6q-gw52xx.dts @@ -14,7 +14,7 @@ #include "imx6qdl-gw52xx.dtsi" / { - model = "Gateworks Ventana i.MX6 Quad GW52XX"; + model = "Gateworks Ventana i.MX6 Dual/Quad GW52XX"; compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q"; }; diff --git a/arch/arm/boot/dts/imx6q-gw53xx.dts b/arch/arm/boot/dts/imx6q-gw53xx.dts index 360c316b4740..d76aaa83dad0 100644 --- a/arch/arm/boot/dts/imx6q-gw53xx.dts +++ b/arch/arm/boot/dts/imx6q-gw53xx.dts @@ -14,7 +14,7 @@ #include "imx6qdl-gw53xx.dtsi" / { - model = "Gateworks Ventana i.MX6 Quad GW53XX"; + model = "Gateworks Ventana i.MX6 Dual/Quad GW53XX"; compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q"; }; diff --git a/arch/arm/boot/dts/imx6q-gw54xx.dts b/arch/arm/boot/dts/imx6q-gw54xx.dts index ab518d66a75e..6e8f53e92a2d 100644 --- a/arch/arm/boot/dts/imx6q-gw54xx.dts +++ b/arch/arm/boot/dts/imx6q-gw54xx.dts @@ -14,7 +14,7 @@ #include "imx6qdl-gw54xx.dtsi" / { - model = "Gateworks Ventana i.MX6 Quad GW54XX"; + model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX"; compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q"; }; -- cgit v1.2.3 From f45114171b42e42d5438cebba5393d22f38c09c9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 22 May 2014 14:45:05 -0300 Subject: ARM: dts: imx51-babbage: Add PMIC RTC support Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 181d77fa2fa6..c1b9d435ebb0 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -203,6 +203,7 @@ reg = <0>; interrupt-parent = <&gpio1>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-rtc; regulators { sw1_reg: sw1 { -- cgit v1.2.3 From 54a9a3af6827a934f95ee53942bc1a409e7ab9b8 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 26 May 2014 14:42:56 +0200 Subject: ARM: dts: pfla02: Add ethernet phy supply regulator The 2.5V VDD_ETH_IO voltage supplied by the DA9063 LDO4 is used to power the KSZ9031 PHY DVDDH input and to pull the necessary pins (including bootstrap pins) high. It also powers the i.MX6 NVCC_RGMII and NVCC_ENET inputs. Signed-off-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index faa3494a69d4..2694aa84e187 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -301,6 +301,7 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + phy-supply = <&vdd_eth_io_reg>; status = "disabled"; }; -- cgit v1.2.3 From c0470c3812bdaae5a396d1ffbfebcc3cbf52fa01 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Tue, 27 May 2014 17:26:37 +0200 Subject: ARM: dts: imx6qdl: Add CSI device tree port nodes for IPU1 and IPU2 This patch adds CSI subnodes for IPU1 and IPU2 that will contain ports and endpoints connecting to external elements in the video pipeline. Signed-off-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q.dtsi | 8 ++++++++ arch/arm/boot/dts/imx6qdl.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index addd3f881ce2..fb6185fc9379 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -156,6 +156,14 @@ clock-names = "bus", "di0", "di1"; resets = <&src 4>; + ipu2_csi0: port@0 { + reg = <0>; + }; + + ipu2_csi1: port@1 { + reg = <1>; + }; + ipu2_di0: port@2 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index ce0599134a69..eef93536c9ec 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1048,6 +1048,14 @@ clock-names = "bus", "di0", "di1"; resets = <&src 2>; + ipu1_csi0: port@0 { + reg = <0>; + }; + + ipu1_csi1: port@1 { + reg = <1>; + }; + ipu1_di0: port@2 { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 04e151e8206e1e02e3246a0a4ecb8ad402a0d6e4 Mon Sep 17 00:00:00 2001 From: Denis Carikli Date: Thu, 22 May 2014 16:00:43 +0200 Subject: ARM: dts: imx25: mbimxsd25: Add displays support. The CMO-QVGA, DVI-VGA and DVI-SVGA displays were added. Signed-off-by: Denis Carikli Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 + .../imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts | 72 ++++++++++++++++++++++ .../imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts | 45 ++++++++++++++ .../imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts | 45 ++++++++++++++ 4 files changed, 165 insertions(+) create mode 100644 arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts create mode 100644 arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts create mode 100644 arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 677154184697..aa2b35ecd938 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -157,6 +157,9 @@ dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb dtb-$(CONFIG_ARCH_MXC) += \ imx25-eukrea-mbimxsd25-baseboard.dtb \ + imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \ + imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \ + imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \ imx25-karo-tx25.dtb \ imx25-pdk.dtb \ imx27-apf27.dtb \ diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts new file mode 100644 index 000000000000..9797280f0188 --- /dev/null +++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts @@ -0,0 +1,72 @@ +/* + * Copyright 2013 Eukréa Electromatique + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx25-eukrea-mbimxsd25-baseboard.dts" + +/ { + model = "Eukrea MBIMXSD25 with the CMO-QVGA Display"; + compatible = "eukrea,mbimxsd25-baseboard-cmo-qvga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; + + cmo_qvga: display { + model = "CMO-QVGA"; + bits-per-pixel = <16>; + fsl,pcr = <0xcad08b80>; + bus-width = <18>; + native-mode = <&qvga_timings>; + display-timings { + qvga_timings: 320x240 { + clock-frequency = <6500000>; + hactive = <320>; + vactive = <240>; + hback-porch = <30>; + hfront-porch = <38>; + vback-porch = <20>; + vfront-porch = <3>; + hsync-len = <15>; + vsync-len = <4>; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_lcd_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lcd_3v3>; + regulator-name = "lcd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&iomuxc { + imx25-eukrea-mbimxsd25-baseboard-cmo-qvga { + pinctrl_reg_lcd_3v3: reg_lcd_3v3 { + fsl,pins = ; + }; + }; +}; + +&lcdc { + display = <&cmo_qvga>; + fsl,lpccr = <0x00a903ff>; + lcd-supply = <®_lcd_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts new file mode 100644 index 000000000000..8eee2f65fe00 --- /dev/null +++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts @@ -0,0 +1,45 @@ +/* + * Copyright 2013 Eukréa Electromatique + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx25-eukrea-mbimxsd25-baseboard.dts" + +/ { + model = "Eukrea MBIMXSD25 with the DVI-SVGA Display"; + compatible = "eukrea,mbimxsd25-baseboard-dvi-svga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; + + dvi_svga: display { + model = "DVI-SVGA"; + bits-per-pixel = <16>; + fsl,pcr = <0xfa208b80>; + bus-width = <18>; + native-mode = <&dvi_svga_timings>; + display-timings { + dvi_svga_timings: 800x600 { + clock-frequency = <40000000>; + hactive = <800>; + vactive = <600>; + hback-porch = <75>; + hfront-porch = <75>; + vback-porch = <7>; + vfront-porch = <75>; + hsync-len = <7>; + vsync-len = <7>; + }; + }; + }; +}; + +&lcdc { + display = <&dvi_svga>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts new file mode 100644 index 000000000000..447da6263169 --- /dev/null +++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts @@ -0,0 +1,45 @@ +/* + * Copyright 2013 Eukréa Electromatique + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx25-eukrea-mbimxsd25-baseboard.dts" + +/ { + model = "Eukrea MBIMXSD25 with the DVI-VGA Display"; + compatible = "eukrea,mbimxsd25-baseboard-dvi-vga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; + + dvi_vga: display { + model = "DVI-VGA"; + bits-per-pixel = <16>; + fsl,pcr = <0xfa208b80>; + bus-width = <18>; + native-mode = <&dvi_vga_timings>; + display-timings { + dvi_vga_timings: 640x480 { + clock-frequency = <31250000>; + hactive = <640>; + vactive = <480>; + hback-porch = <100>; + hfront-porch = <100>; + vback-porch = <7>; + vfront-porch = <100>; + hsync-len = <7>; + vsync-len = <7>; + }; + }; + }; +}; + +&lcdc { + display = <&dvi_vga>; + status = "okay"; +}; -- cgit v1.2.3 From 524bf8c5185a01a3a2f84d19b3447c66f6e4d787 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 2 Jun 2014 19:56:21 -0300 Subject: ARM: dts: imx6q-udoo: Add USB Host support Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-udoo.dts | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts index 6c561060bf5c..e3bff2ac00db 100644 --- a/arch/arm/boot/dts/imx6q-udoo.dts +++ b/arch/arm/boot/dts/imx6q-udoo.dts @@ -23,6 +23,23 @@ memory { reg = <0x10000000 0x40000000>; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_h1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */ + gpio = <&gpio7 12 0>; + }; + }; }; &fec { @@ -81,6 +98,13 @@ >; }; + pinctrl_usbh: usbhgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 @@ -104,6 +128,14 @@ status = "okay"; }; +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh>; + vbus-supply = <®_usb_h1_vbus>; + clocks = <&clks 201>; + status = "okay"; +}; + &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; -- cgit v1.2.3 From 36d3a8f0f39db6fdf2e934ec2ddec8effaee3aad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lothar=20Wa=C3=9Fmann?= Date: Fri, 6 Jun 2014 13:02:59 +0200 Subject: ARM: dts: imx6: add missing compatible and clock properties for kpp MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Lothar Waßmann Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index eef93536c9ec..2fe1287d92f4 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -466,8 +466,10 @@ }; kpp: kpp@020b8000 { + compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 62>; }; wdog1: wdog@020bc000 { -- cgit v1.2.3 From 0ebda1d3f2769eb77df80e018341667cbb80768d Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 7 Jun 2014 16:34:18 +0400 Subject: ARM: dts: i.MX35: Add GPT node This patch adds the missing (General Purpose Timer) GPT devicetree node for i.MX35 CPUs. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx35.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 4759abb49436..442e216ca9d9 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -193,6 +193,14 @@ #clock-cells = <1>; }; + gpt: timer@53f90000 { + compatible = "fsl,imx35-gpt", "fsl,imx31-gpt"; + reg = <0x53f90000 0x4000>; + interrupts = <29>; + clocks = <&clks 9>, <&clks 50>; + clock-names = "ipg", "per"; + }; + gpio3: gpio@53fa4000 { compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; reg = <0x53fa4000 0x4000>; -- cgit v1.2.3 From c8787bae4b6694a012e1f2c3c82eb095f4c1c160 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lothar=20Wa=C3=9Fmann?= Date: Thu, 12 Jun 2014 15:05:17 +0200 Subject: ARM: dts: imx6: add support for Ka-Ro TX6 modules MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds support for the Ka-Ro electronics GmbH TX6 modules. There are five distinct module types with either i.MX6Q or i.MX6DL and LVDS or LCD display interface and one DTS file for a complete system with an i.MX6DL based TX6 module and a baseboard mounted on the back of a display (imx6dl-tx6dl-comtft.dts). Signed-off-by: Lothar Waßmann Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 8 + arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts | 103 ++++ arch/arm/boot/dts/imx6dl-tx6u-801x.dts | 177 +++++++ arch/arm/boot/dts/imx6dl-tx6u-811x.dts | 150 ++++++ arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts | 103 ++++ arch/arm/boot/dts/imx6q-tx6q-1010.dts | 177 +++++++ arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts | 136 ++++++ arch/arm/boot/dts/imx6q-tx6q-1020.dts | 210 ++++++++ arch/arm/boot/dts/imx6q-tx6q-1110.dts | 154 ++++++ arch/arm/boot/dts/imx6qdl-tx6.dtsi | 696 +++++++++++++++++++++++++++ 10 files changed, 1914 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts create mode 100644 arch/arm/boot/dts/imx6dl-tx6u-801x.dts create mode 100644 arch/arm/boot/dts/imx6dl-tx6u-811x.dts create mode 100644 arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts create mode 100644 arch/arm/boot/dts/imx6q-tx6q-1010.dts create mode 100644 arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts create mode 100644 arch/arm/boot/dts/imx6q-tx6q-1020.dts create mode 100644 arch/arm/boot/dts/imx6q-tx6q-1110.dts create mode 100644 arch/arm/boot/dts/imx6qdl-tx6.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index aa2b35ecd938..5393b5d09844 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -199,6 +199,9 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6dl-sabreauto.dtb \ imx6dl-sabrelite.dtb \ imx6dl-sabresd.dtb \ + imx6dl-tx6dl-comtft.dtb \ + imx6dl-tx6u-801x.dtb \ + imx6dl-tx6u-811x.dtb \ imx6dl-wandboard.dtb \ imx6q-arm2.dtb \ imx6q-cm-fx6.dtb \ @@ -219,6 +222,11 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-sbc6x.dtb \ imx6q-udoo.dtb \ imx6q-wandboard.dtb \ + imx6q-tx6q-1010.dtb \ + imx6q-tx6q-1010-comtft.dtb \ + imx6q-tx6q-1020.dtb \ + imx6q-tx6q-1020-comtft.dtb \ + imx6q-tx6q-1110.dtb \ imx6sl-evk.dtb \ imx6sx-sdb.dtb \ vf610-colibri.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts new file mode 100644 index 000000000000..913bb9a0466a --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts @@ -0,0 +1,103 @@ +/* + * Copyright 2014 Lothar Waßmann + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-tx6.dtsi" + +/ { + model = "Ka-Ro electronics TX6DL Module on CoMpact TFT"; + compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; + + aliases { + display = &display; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 0>; + power-supply = <®_3v3>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + display: display@di0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_1>; + status = "okay"; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + display-timings { + native-mode = <&ET070001DM6>; + + ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */ + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&can1 { + status = "disabled"; +}; + +&can2 { + xceiver-supply = <®_3v3>; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&kpp { + status = "disabled"; +}; + +®_can_xcvr { + status = "disabled"; +}; + +&touchscreen { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts new file mode 100644 index 000000000000..5fe465c2814e --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts @@ -0,0 +1,177 @@ +/* + * Copyright 2014 Lothar Waßmann + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-tx6.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-801x Module"; + compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; + + aliases { + display = &display; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + power-supply = <®_3v3>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + display: display@di0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_1>; + status = "okay"; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + display-timings { + VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hsync-len = <96>; + hfront-porch = <16>; + vback-porch = <31>; + vsync-len = <2>; + vfront-porch = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETV570 { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0350 { + clock-frequency = <6413760>; + hactive = <320>; + vactive = <240>; + hback-porch = <34>; + hsync-len = <34>; + hfront-porch = <20>; + vback-porch = <15>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0430 { + clock-frequency = <9009000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hsync-len = <41>; + hfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + vfront-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0500 { + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0700 { /* same as ET0500 */ + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETQ570 { + clock-frequency = <6596040>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hsync-len = <30>; + hfront-porch = <30>; + vback-porch = <16>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-811x.dts b/arch/arm/boot/dts/imx6dl-tx6u-811x.dts new file mode 100644 index 000000000000..c275eecc9472 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tx6u-811x.dts @@ -0,0 +1,150 @@ +/* + * Copyright 2014 Lothar Waßmann + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-tx6.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-811x Module"; + compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; + + aliases { + display = &lvds0; + lvds0 = &lvds0; + lvds1 = &lvds1; + }; + + backlight0: backlight0 { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 0>; + power-supply = <®_lcd0_pwr>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + backlight1: backlight1 { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 500000 0>; + power-supply = <®_lcd1_pwr>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; +}; + +&i2c3 { + polytouch2: eeti@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eeti>; + interrupt-parent = <&gpio3>; + interrupts = <22 0>; + wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + linux,wakeup; + }; +}; + +&iomuxc { + imx6dl-tx6u-811x { + pinctrl_eeti: eetigrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ + >; + }; + }; +}; + +&kpp { + status = "disabled"; /* pad conflict with backlight1 PWM */ +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&lvds_timing0>; + lvds_timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; + + lvds1: lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "disabled"; + + display-timings { + native-mode = <&lvds_timing1>; + lvds_timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts new file mode 100644 index 000000000000..b18fae10b2e3 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts @@ -0,0 +1,103 @@ +/* + * Copyright 2014 Lothar Waßmann + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-tx6.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1010 Module on CoMpact TFT"; + compatible = "karo,imx6q-tx6q", "fsl,imx6q"; + + aliases { + display = &display; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 0>; + power-supply = <®_3v3>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + display: display@di0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_1>; + status = "okay"; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + display-timings { + native-mode = <&ET070001DM6>; + + ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */ + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&can1 { + status = "disabled"; +}; + +&can2 { + xceiver-supply = <®_3v3>; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&kpp { + status = "disabled"; +}; + +®_can_xcvr { + status = "disabled"; +}; + +&touchscreen { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010.dts b/arch/arm/boot/dts/imx6q-tx6q-1010.dts new file mode 100644 index 000000000000..b58ec9c966c8 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-tx6q-1010.dts @@ -0,0 +1,177 @@ +/* + * Copyright 2014 Lothar Waßmann + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-tx6.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1010 Module"; + compatible = "karo,imx6q-tx6q", "fsl,imx6q"; + + aliases { + display = &display; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + power-supply = <®_3v3>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + display: display@di0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_1>; + status = "okay"; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + display-timings { + VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hsync-len = <96>; + hfront-porch = <16>; + vback-porch = <31>; + vsync-len = <2>; + vfront-porch = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETV570 { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0350 { + clock-frequency = <6413760>; + hactive = <320>; + vactive = <240>; + hback-porch = <34>; + hsync-len = <34>; + hfront-porch = <20>; + vback-porch = <15>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0430 { + clock-frequency = <9009000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hsync-len = <41>; + hfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + vfront-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0500 { + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0700 { /* same as ET0500 */ + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETQ570 { + clock-frequency = <6596040>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hsync-len = <30>; + hfront-porch = <30>; + vback-porch = <16>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts new file mode 100644 index 000000000000..0bb9a9de62a9 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts @@ -0,0 +1,136 @@ +/* + * Copyright 2014 Lothar Waßmann + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-tx6.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1020 Module on CoMpact TFT"; + compatible = "karo,imx6q-tx6q", "fsl,imx6q"; + + aliases { + display = &display; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 0>; + power-supply = <®_3v3>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + display: display@di0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_1>; + status = "okay"; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + display-timings { + native-mode = <&ET070001DM6>; + + ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */ + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&can1 { + status = "disabled"; +}; + +&can2 { + xceiver-supply = <®_3v3>; +}; + +&ds1339 { + status = "disabled"; +}; + +&gpmi { + status = "disabled"; +}; + +&iomuxc { + imx6qdl-tx6 { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&kpp { + status = "disabled"; +}; + +®_can_xcvr { + status = "disabled"; +}; + +&touchscreen { + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + no-1-8-v; + fsl,wp-controller; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020.dts b/arch/arm/boot/dts/imx6q-tx6q-1020.dts new file mode 100644 index 000000000000..b96d80a35d39 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-tx6q-1020.dts @@ -0,0 +1,210 @@ +/* + * Copyright 2014 Lothar Waßmann + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-tx6.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1020 Module"; + compatible = "karo,imx6q-tx6q", "fsl,imx6q"; + + aliases { + display = &display; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + power-supply = <®_3v3>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + display: display@di0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_1>; + status = "okay"; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + display-timings { + VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hsync-len = <96>; + hfront-porch = <16>; + vback-porch = <31>; + vsync-len = <2>; + vfront-porch = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETV570 { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0350 { + clock-frequency = <6413760>; + hactive = <320>; + vactive = <240>; + hback-porch = <34>; + hsync-len = <34>; + hfront-porch = <20>; + vback-porch = <15>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0430 { + clock-frequency = <9009000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hsync-len = <41>; + hfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + vfront-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0500 { + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0700 { /* same as ET0500 */ + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETQ570 { + clock-frequency = <6596040>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hsync-len = <30>; + hfront-porch = <30>; + vback-porch = <16>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&ds1339 { + status = "disabled"; +}; + +&gpmi { + status = "disabled"; +}; + +&iomuxc { + imx6qdl-tx6 { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + no-1-8-v; + fsl,wp-controller; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1110.dts b/arch/arm/boot/dts/imx6q-tx6q-1110.dts new file mode 100644 index 000000000000..88aa1e4c792d --- /dev/null +++ b/arch/arm/boot/dts/imx6q-tx6q-1110.dts @@ -0,0 +1,154 @@ +/* + * Copyright 2014 Lothar Waßmann + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-tx6.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1110 Module"; + compatible = "karo,imx6q-tx6q", "fsl,imx6q"; + + aliases { + display = &lvds0; + lvds0 = &lvds0; + lvds1 = &lvds1; + }; + + backlight0: backlight0 { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 0>; + power-supply = <®_lcd0_pwr>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + backlight1: backlight1 { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 500000 0>; + power-supply = <®_lcd1_pwr>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; +}; + +&i2c3 { + polytouch1: eeti@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eeti>; + interrupt-parent = <&gpio3>; + interrupts = <22 0>; + wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + linux,wakeup; + }; +}; + +&iomuxc { + imx6q-tx6q-1110 { + pinctrl_eeti: eetigrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ + >; + }; + }; +}; + +&kpp { + status = "disabled"; /* pad conflict with backlight1 PWM */ +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&lvds_timing0>; + lvds_timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; + + lvds1: lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "disabled"; + + display-timings { + native-mode = <&lvds_timing1>; + lvds_timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi new file mode 100644 index 000000000000..5c350a3c7a2f --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -0,0 +1,696 @@ +/* + * Copyright 2014 Lothar Waßmann + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include + +/ { + aliases { + can0 = &can2; + can1 = &can1; + ethernet0 = &fec; + lcdif_23bit_pins_a = &pinctrl_disp0_1; + lcdif_24bit_pins_a = &pinctrl_disp0_2; + pwm0 = &pwm1; + pwm1 = &pwm2; + reg_can_xcvr = ®_can_xcvr; + stk5led = &user_led; + usbotg = &usbotg; + sdhc0 = &usdhc1; + sdhc1 = &usdhc2; + }; + + memory { + reg = <0 0>; /* will be filled by U-Boot */ + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + mclk: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power Button"; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + linux,code = ; + gpio-key,wakeup; + }; + }; + + leds { + compatible = "gpio-leds"; + + user_led: user { + label = "Heartbeat"; + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3v3_etn: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3V3_ETN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etnphy_power>; + gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_2v5: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3v3: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_xcvr: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan_xcvr>; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + enable-active-low; + }; + + reg_lcd0_pwr: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "LCD0 POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0_pwr>; + gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + reg_lcd1_pwr: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "LCD1 POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd1_pwr>; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + reg_usbh1_vbus: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbotg_vbus: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + sound { + compatible = "karo,imx6qdl-tx6qdl-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <5>; + }; +}; + +&audmux { + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <2>; + cs-gpios = < + &gpio2 30 GPIO_ACTIVE_HIGH + &gpio3 19 GPIO_ACTIVE_HIGH + >; + status = "okay"; + + spidev0: spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <54000000>; + }; + + spidev1: spi@1 { + compatible = "spidev"; + reg = <1>; + spi-max-frequency = <54000000>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; + phy-supply = <®_3v3_etn>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + fsl,no-blockmark-swap; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + ds1339: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_2v5>; + VDDIO-supply = <®_3v3>; + clocks = <&mclk>; + }; + + polytouch: edt-ft5x06@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5x06>; + interrupt-parent = <&gpio6>; + interrupts = <15 0>; + reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + linux,wakeup; + }; + + touchscreen: tsc2007@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc2007>; + interrupt-parent = <&gpio3>; + interrupts = <26 0>; + gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + ti,x-plate-ohms = <660>; + linux,wakeup; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-tx6 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */ + MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */ + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */ + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */ + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */ + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */ + >; + }; + + pinctrl_disp0_1: disp0grp-1 { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */ + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_disp0_2: disp0grp-2 { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0 + MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */ + >; + }; + + pinctrl_edt_ft5x06: edt-ft5x06grp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + >; + }; + + pinctrl_etnphy_power: etnphy-pwrgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan_xcvr: flexcan-xcvrgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */ + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_kpp: kppgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1 + MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1 + MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1 + MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1 + MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1 + MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1 + MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1 + MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1 + >; + }; + + pinctrl_lcd0_pwr: lcd0-pwrgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */ + >; + }; + + pinctrl_lcd1_pwr: lcd1-pwrgrp { + fsl,pins = < + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_tsc2007: tsc2007grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart1_rtscts: uart1_rtsctsgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2_rtscts: uart2_rtsctsgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3_rtscts: uart3_rtsctsgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1_vbus: usbh1-vbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059 + >; + }; + + pinctrl_usbotg_vbus: usbotg-vbusgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1 + MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1 + MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */ + >; + }; + }; +}; + +&kpp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kpp>; + /* sample keymap */ + /* row/col 0,1 are mapped to KPP row/col 6,7 */ + linux,keymap = < + MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */ + MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */ + MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */ + MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */ + MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */ + MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */ + MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */ + MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */ + MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */ + MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */ + MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */ + >; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + #pwm-cells = <3>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + #pwm-cells = <3>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "peripheral"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + no-1-8-v; + cd-gpios = <&gpio7 2 0>; + fsl,wp-controller; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + no-1-8-v; + cd-gpios = <&gpio7 3 0>; + fsl,wp-controller; + status = "okay"; +}; -- cgit v1.2.3 From 1cd7ad973f5ae5136a01a22269f4afc0027ad434 Mon Sep 17 00:00:00 2001 From: Anssi Hannula Date: Mon, 16 Jun 2014 02:39:44 +0300 Subject: ARM: dts: imx6: remove wrong spdif rxtx2 clock The rxtx2 clock of i.MX6 S/PDIF is currently set to "asrc" clock. However, according to SoC documentation, rxtx2 is connected to ASRC_EXT_CLK, a different external clock. Testing on Cubox-i system seems to confirm that: when fsl_spdif is forced to select rxtx2 as input clock, audio playback fails with an I/O error. Set rxtx2 to the dummy clock by default to prevent fsl_spdif from selecting it. Signed-off-by: Anssi Hannula Cc: Mark Brown Acked-by: Nicolin Chen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 2fe1287d92f4..94d1b1349977 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -181,7 +181,7 @@ <&sdma 15 18 0>; dma-names = "rx", "tx"; clocks = <&clks 197>, <&clks 3>, - <&clks 197>, <&clks 107>, + <&clks 197>, <&clks 0>, <&clks 0>, <&clks 118>, <&clks 0>, <&clks 139>, <&clks 0>; -- cgit v1.2.3 From e4d20e76658f7ffad08bf3abe724a923a16bdea6 Mon Sep 17 00:00:00 2001 From: Anssi Hannula Date: Mon, 16 Jun 2014 02:39:45 +0300 Subject: ARM: dts: imx6: remove non-working spdif rxtx4 and rxtx6 clocks The S/PDIF rxtx4 and rxtx6 clock inputs are "ESAI_HCKT" and "MLB clock", respectively, according to the SoC documentation, and they are currently mapped to clocks "esai" and "mlb". However, they do not seem to actually work correctly. Testing on a Cubox-i system with fsl_spdif driver forced to select one of those as input will result in I/O errors on audio playback, which I believe means missing clock signal. Possibly the "ESAI_HCKT" and "MLB clock" refer to some other clocks related to ESAI and MLB, or we are missing something else. Since audio playback will not work if fsl_spdif selects these clocks (which happens rarely), set the inputs do dummy clocks, at least for now. Signed-off-by: Anssi Hannula Cc: Mark Brown Acked-by: Nicolin Chen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 94d1b1349977..59173c94e569 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -182,8 +182,8 @@ dma-names = "rx", "tx"; clocks = <&clks 197>, <&clks 3>, <&clks 197>, <&clks 0>, - <&clks 0>, <&clks 118>, - <&clks 0>, <&clks 139>, + <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>; clock-names = "core", "rxtx0", "rxtx1", "rxtx2", -- cgit v1.2.3 From f78a59753c783e8db072fa94bbd4fb19157e8603 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 17 Jun 2014 01:07:35 -0300 Subject: ARM: dts: imx6sx: Use "vddarm" as the regulator name The other i.mx6 variants use "vddarm" as the name of the internal regulator that powers the core. Use the same convention here for consistency. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index ac3866c80727..78ccf6151ab3 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -581,7 +581,7 @@ reg_arm: regulator-vddcore@140 { compatible = "fsl,anatop-regulator"; - regulator-name = "cpu"; + regulator-name = "vddarm"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1450000>; regulator-always-on; -- cgit v1.2.3 From d9a9f38f88fb065457c699266040b7a714e560e2 Mon Sep 17 00:00:00 2001 From: Markus Pargmann Date: Tue, 17 Jun 2014 11:06:30 +0200 Subject: ARM: dts: imx50: add ssi dma properties Replace old ssi dma properties by the generic dma properties. Signed-off-by: Markus Pargmann Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 6a201cf54366..c0e0f60ab6b2 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -151,8 +151,10 @@ reg = <0x50014000 0x4000>; interrupts = <30>; clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; + dmas = <&sdma 24 1 0>, + <&sdma 25 1 0>; + dma-names = "rx", "tx"; fsl,fifo-depth = <15>; - fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; @@ -457,8 +459,10 @@ reg = <0x63fcc000 0x4000>; interrupts = <29>; clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; + dmas = <&sdma 28 0 0>, + <&sdma 29 0 0>; + dma-names = "rx", "tx"; fsl,fifo-depth = <15>; - fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; -- cgit v1.2.3 From add32abc7a8ed87426d4cb9fe33cacd2177ba1df Mon Sep 17 00:00:00 2001 From: Markus Pargmann Date: Tue, 17 Jun 2014 11:06:31 +0200 Subject: ARM: dts: imx5: remove fsl,ssi-dma-events All imx5*.dtsi files define the generic dma bindings. Drop the old non-generic fsl,ssi-dma-events. Signed-off-by: Markus Pargmann Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 3 --- arch/arm/boot/dts/imx53.dtsi | 3 --- 2 files changed, 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index bebbf3ba0d5e..17c05a6fa776 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -218,7 +218,6 @@ <&sdma 25 1 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; - fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; @@ -508,7 +507,6 @@ <&sdma 29 0 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; - fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; @@ -564,7 +562,6 @@ <&sdma 47 0 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; - fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 6456a0084388..d8d3f979f599 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -231,7 +231,6 @@ <&sdma 25 1 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; - fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; @@ -661,7 +660,6 @@ <&sdma 29 0 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; - fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; @@ -689,7 +687,6 @@ <&sdma 47 0 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; - fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; -- cgit v1.2.3 From 6562c587b0413f864d162563d45edd7ba7e1b0f3 Mon Sep 17 00:00:00 2001 From: Markus Pargmann Date: Tue, 17 Jun 2014 11:06:32 +0200 Subject: ARM: dts: imx6qdl: remove fsl,ssi-dma-events All dtsi files where already moved to generic dma bindings. Remove the old non-generic DMA properties. Signed-off-by: Markus Pargmann Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 59173c94e569..b71be4b2b7f3 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -272,7 +272,6 @@ <&sdma 38 1 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; - fsl,ssi-dma-events = <38 37>; status = "disabled"; }; @@ -287,7 +286,6 @@ <&sdma 42 1 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; - fsl,ssi-dma-events = <42 41>; status = "disabled"; }; @@ -302,7 +300,6 @@ <&sdma 46 1 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; - fsl,ssi-dma-events = <46 45>; status = "disabled"; }; -- cgit v1.2.3 From 9eb0e5f9b2dd6d8ef2d988016bc9327bedde920d Mon Sep 17 00:00:00 2001 From: Markus Pargmann Date: Tue, 17 Jun 2014 11:06:33 +0200 Subject: ARM: dts: imx: remove ssi fsl,mode for audio cards The DAI mode is and should be configured by the sound card driver as codec and ssi have to be in the right modes to communicate with each other. It is possible to operate the ssi unit or the codec in master mode, sometimes even on the same board in different configurations. With the latest changes in the fsl-ssi driver, the 'fsl,mode' property is only handled as a fallback property. If the sound card sets the DAI mode correctly, this fallback configuration is dropped. Signed-off-by: Markus Pargmann Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts | 1 - arch/arm/boot/dts/imx25-pdk.dts | 1 - arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts | 1 - arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 1 - arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts | 1 - arch/arm/boot/dts/imx51-babbage.dts | 1 - arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts | 1 - arch/arm/boot/dts/imx53-m53evk.dts | 1 - arch/arm/boot/dts/imx53-mba53.dts | 1 - arch/arm/boot/dts/imx53-qsb-common.dtsi | 1 - arch/arm/boot/dts/imx53-tx53.dtsi | 1 - arch/arm/boot/dts/imx53-voipac-bsb.dts | 1 - arch/arm/boot/dts/imx6dl-riotboard.dts | 1 - arch/arm/boot/dts/imx6q-gw5400-a.dts | 1 - arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 1 - arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 1 - arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 2 -- arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 1 - arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 1 - arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 1 - arch/arm/boot/dts/imx6qdl-tx6.dtsi | 1 - arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 1 - arch/arm/boot/dts/imx6sl-evk.dts | 1 - 23 files changed, 24 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts index ad12da38fc92..ed1d0b4578ef 100644 --- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts +++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts @@ -155,7 +155,6 @@ &ssi1 { codec-handle = <&tlv320aic23>; - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index c608942b8a3b..8f9a424a80d6 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -233,7 +233,6 @@ &ssi1 { codec-handle = <&codec>; - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts index bb64ca1667f4..2ab65fc4c1e1 100644 --- a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts +++ b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts @@ -135,7 +135,6 @@ &ssi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssi1>; - fsl,mode = "i2s-slave"; codec-handle = <&codec>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index 31e9f7049f73..2e376edce972 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi @@ -310,7 +310,6 @@ &ssi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssi1>; - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts index f04ae91eea89..75b036700d31 100644 --- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts +++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts @@ -133,7 +133,6 @@ &ssi1 { codec-handle = <&tlv320aic23>; - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index c1b9d435ebb0..56569cecaa78 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -393,7 +393,6 @@ }; &ssi2 { - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts index 31cfb7f2b02e..34599c547459 100644 --- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts @@ -255,7 +255,6 @@ &ssi2 { codec-handle = <&tlv320aic23>; - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts index c4956b0ffb35..0689c1eaa9b1 100644 --- a/arch/arm/boot/dts/imx53-m53evk.dts +++ b/arch/arm/boot/dts/imx53-m53evk.dts @@ -427,7 +427,6 @@ }; &ssi2 { - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts index 3e3f17aa93a1..2e44d2aba14e 100644 --- a/arch/arm/boot/dts/imx53-mba53.dts +++ b/arch/arm/boot/dts/imx53-mba53.dts @@ -225,7 +225,6 @@ }; &ssi2 { - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi index fd8c60dde7de..181ae5ebf23f 100644 --- a/arch/arm/boot/dts/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi @@ -141,7 +141,6 @@ }; &ssi2 { - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi index e348796ba689..704bd72cbfec 100644 --- a/arch/arm/boot/dts/imx53-tx53.dtsi +++ b/arch/arm/boot/dts/imx53-tx53.dtsi @@ -502,7 +502,6 @@ }; &ssi1 { - fsl,mode = "i2s-slave"; codec-handle = <&sgtl5000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx53-voipac-bsb.dts b/arch/arm/boot/dts/imx53-voipac-bsb.dts index 7f6711a48615..c17d3ad6dba5 100644 --- a/arch/arm/boot/dts/imx53-voipac-bsb.dts +++ b/arch/arm/boot/dts/imx53-voipac-bsb.dts @@ -154,6 +154,5 @@ }; &ssi2 { - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 909fafc0b650..80c926894d1e 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -254,7 +254,6 @@ }; &ssi1 { - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index fced8bbc2f38..22e6f8e657d2 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -504,7 +504,6 @@ }; &ssi1 { - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 7a247f30bca8..234e7b755232 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -489,7 +489,6 @@ }; &ssi1 { - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index d3125f0faa77..143f84f7812c 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -533,7 +533,6 @@ }; &ssi1 { - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 532347f3f7d3..16e7ad3d98ad 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -555,12 +555,10 @@ }; &ssi1 { - fsl,mode = "i2s-slave"; status = "okay"; }; &ssi2 { - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 4c4b17596c8b..42ff525ebe13 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -381,7 +381,6 @@ }; &ssi1 { - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 6df6127bf835..0a36129152e0 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -381,7 +381,6 @@ }; &ssi1 { - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index e44619218bab..ec43dde78525 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -513,7 +513,6 @@ }; &ssi2 { - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index 5c350a3c7a2f..66a135392342 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -637,7 +637,6 @@ }; &ssi1 { - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index 5c6f10c43f65..13eae9e5bae8 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -233,7 +233,6 @@ }; &ssi1 { - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 050786dc6df1..3f9e041c0252 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -489,7 +489,6 @@ }; &ssi2 { - fsl,mode = "i2s-slave"; status = "okay"; }; -- cgit v1.2.3 From 52b3c29d969ce1ddad0223f7133a3bbc321a7f48 Mon Sep 17 00:00:00 2001 From: Denis Carikli Date: Tue, 17 Jun 2014 12:46:37 +0200 Subject: ARM: dts: mbimxsd25: cmo-qvga: Fix lcd regulator The fixed-regulator's enable-active-high property is needed to indicate that the GPIO regulator is active high. Before that the regulator state was inverted. Signed-off-by: Denis Carikli Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts index 9797280f0188..68d0834a2d1e 100644 --- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts +++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts @@ -52,6 +52,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + enable-active-high; }; }; }; -- cgit v1.2.3 From c64b874f0eac6f450e8834e407bc98ec402b81e7 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 20 Jun 2014 16:52:47 +0200 Subject: ARM: dts: imx6: add aristainetos board support This patch add support for the imx6dl based aristainetos board with following configuration: CPU: Freescale i.MX6DL rev1.1 at 792 MHz DRAM: 1 GiB NAND: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 SF: Detected N25Q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB As this board can used with 2 different display types, the differences between them are extracted into 2 DTS files, and the common settings are collected in a common file. Signed-off-by: Heiko Schocher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-aristainetos_4.dts | 85 ++++++ arch/arm/boot/dts/imx6dl-aristainetos_7.dts | 74 +++++ arch/arm/boot/dts/imx6qdl-aristainetos.dtsi | 418 ++++++++++++++++++++++++++++ 4 files changed, 579 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-aristainetos_4.dts create mode 100644 arch/arm/boot/dts/imx6dl-aristainetos_7.dts create mode 100644 arch/arm/boot/dts/imx6qdl-aristainetos.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5393b5d09844..644d4c2e58ec 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -186,6 +186,8 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx53-tx53-x03x.dtb \ imx53-tx53-x13x.dtb \ imx53-voipac-bsb.dtb \ + imx6dl-aristainetos_4.dtb \ + imx6dl-aristainetos_7.dtb \ imx6dl-cubox-i.dtb \ imx6dl-dfi-fs700-m60.dtb \ imx6dl-gw51xx.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts new file mode 100644 index 000000000000..9cd06e5e59f0 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts @@ -0,0 +1,85 @@ +/* + * support fot the imx6 based aristainetos board + * + * Copyright (C) 2014 Heiko Schocher + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-aristainetos.dtsi" + +/ { + model = "aristainetos i.MX6 Dual Lite Board 4"; + compatible = "fsl,imx6dl"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + status = "okay"; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + soc { + display0: display@di0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + status = "okay"; + + display-timings { + 480x800p60 { + native-mode; + clock-frequency = <30000000>; + hactive = <480>; + vactive = <800>; + hfront-porch = <59>; + hback-porch = <10>; + hsync-len = <10>; + vback-porch = <15>; + vfront-porch = <15>; + vsync-len = <15>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + }; + }; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts new file mode 100644 index 000000000000..b413e24288dc --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts @@ -0,0 +1,74 @@ +/* + * support fot the imx6 based aristainetos board + * + * Copyright (C) 2014 Heiko Schocher + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-aristainetos.dtsi" + +/ { + model = "aristainetos i.MX6 Dual Lite Board 7"; + compatible = "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x40000000>; + }; + + soc { + display0: display@di0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + status = "okay"; + + display-timings { + 800x480p60 { + native-mode; + clock-frequency = <33246000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <88>; + hback-porch = <88>; + hsync-len = <80>; + vback-porch = <10>; + vfront-porch = <10>; + vsync-len = <25>; + vsync-active = <1>; + }; + }; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 3000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi new file mode 100644 index 000000000000..e6d9195a1da7 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi @@ -0,0 +1,418 @@ +/* + * support fot the imx6 based aristainetos board + * + * Copyright (C) 2014 Heiko Schocher + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include + +/ { + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_2p5v: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbh1_vbus: regulator@2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + tmp103: tmp103@71 { + compatible = "ti,tmp103"; + reg = <0x71>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + rtc@68 { + compatible = "dallas,m41t00"; + reg = <0x68>; + }; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 20 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + vmmc-supply = <®_3p3v>; + cd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_3p3v>; + cd-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_gpio>; + + imx6qdl-aristainetos { + pinctrl_aristainetos_usbh1_vbus: aristainetos-usbh1-vbus { + fsl,pins = ; + }; + + pinctrl_aristainetos_usbotg_vbus: aristainetos-usbotg-vbus { + fsl,pins = ; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x100b1 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b1 + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 + MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0 + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x10 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu_disp: ipudisp1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x20000 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 + >; + }; + }; +}; -- cgit v1.2.3 From 4014a4f7c0dca2b3bec54fd0176340ba45a46385 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 20 Jun 2014 13:17:29 +0800 Subject: ARM: dts: imx6sx-sdb: add gpio key support This patch adds support for imx6sx-sdb board's gpio keys: SW4(FUNC1): KEY_VOLUMEUP SW5(FUNC2): KEY_VOLUMEDOWN Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-sdb.dts | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index 9906f654e494..da40f1396798 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -8,6 +8,8 @@ /dts-v1/; +#include +#include #include "imx6sx.dtsi" / { @@ -22,6 +24,24 @@ reg = <0x80000000 0x40000000>; }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -114,6 +134,13 @@ >; }; + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 + MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059 + >; + }; + pinctrl_vcc_sd3: vccsd3grp { fsl,pins = < MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 -- cgit v1.2.3 From 8888f6513b5e23ab0d514f9c1da11f04f2d39e7d Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sun, 15 Jun 2014 20:36:50 +0800 Subject: ARM: dts: imx6qdl: use DT macro for clock ID Switch to use DT macro for clock ID, so that device tree source is more readable. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl.dtsi | 17 ++--- arch/arm/boot/dts/imx6q.dtsi | 27 +++++--- arch/arm/boot/dts/imx6qdl.dtsi | 140 ++++++++++++++++++++++++++--------------- 3 files changed, 116 insertions(+), 68 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 0a9c49d69d41..b453e0e28aee 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -35,8 +35,11 @@ 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks 104>, <&clks 6>, <&clks 16>, - <&clks 17>, <&clks 170>; + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; clock-names = "arm", "pll2_pfd2_396m", "step", "pll1_sw", "pll1_sys"; arm-supply = <®_arm>; @@ -56,7 +59,7 @@ ocram: sram@00900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; - clocks = <&clks 142>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; }; aips1: aips-bus@02000000 { @@ -87,7 +90,7 @@ compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; reg = <0x021f8000 0x4000>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 116>; + clocks = <&clks IMX6DL_CLK_I2C4>; status = "disabled"; }; }; @@ -104,9 +107,9 @@ }; &ldb { - clocks = <&clks 33>, <&clks 34>, - <&clks 39>, <&clks 40>, - <&clks 135>, <&clks 136>; + clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; clock-names = "di0_pll", "di1_pll", "di0_sel", "di1_sel", "di0", "di1"; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index fb6185fc9379..e9f3646d1760 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -43,8 +43,11 @@ 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks 104>, <&clks 6>, <&clks 16>, - <&clks 17>, <&clks 170>; + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; clock-names = "arm", "pll2_pfd2_396m", "step", "pll1_sw", "pll1_sys"; arm-supply = <®_arm>; @@ -78,7 +81,7 @@ ocram: sram@00900000 { compatible = "mmio-sram"; reg = <0x00900000 0x40000>; - clocks = <&clks 142>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; }; aips-bus@02000000 { /* AIPS1 */ @@ -89,7 +92,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02018000 0x4000>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 116>, <&clks 116>; + clocks = <&clks IMX6Q_CLK_ECSPI5>, + <&clks IMX6Q_CLK_ECSPI5>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -140,7 +144,9 @@ compatible = "fsl,imx6q-ahci"; reg = <0x02200000 0x4000>; interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 154>, <&clks 187>, <&clks 105>; + clocks = <&clks IMX6QDL_CLK_SATA>, + <&clks IMX6QDL_CLK_SATA_REF_100M>, + <&clks IMX6QDL_CLK_AHB>; clock-names = "sata", "sata_ref", "ahb"; status = "disabled"; }; @@ -152,7 +158,9 @@ reg = <0x02800000 0x400000>; interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 133>, <&clks 134>, <&clks 137>; + clocks = <&clks IMX6QDL_CLK_IPU2>, + <&clks IMX6QDL_CLK_IPU2_DI0>, + <&clks IMX6QDL_CLK_IPU2_DI1>; clock-names = "bus", "di0", "di1"; resets = <&src 4>; @@ -238,9 +246,10 @@ }; &ldb { - clocks = <&clks 33>, <&clks 34>, - <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>, - <&clks 135>, <&clks 136>; + clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; clock-names = "di0_pll", "di1_pll", "di0_sel", "di1_sel", "di2_sel", "di3_sel", "di0", "di1"; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index b71be4b2b7f3..1fd272b52df1 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -10,6 +10,7 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include #include #include "skeleton.dtsi" @@ -94,7 +95,7 @@ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; - clocks = <&clks 106>; + clocks = <&clks IMX6QDL_CLK_APBH_DMA>; }; gpmi: gpmi-nand@00112000 { @@ -105,8 +106,11 @@ reg-names = "gpmi-nand", "bch"; interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "bch"; - clocks = <&clks 152>, <&clks 153>, <&clks 151>, - <&clks 150>, <&clks 149>; + clocks = <&clks IMX6QDL_CLK_GPMI_IO>, + <&clks IMX6QDL_CLK_GPMI_APB>, + <&clks IMX6QDL_CLK_GPMI_BCH>, + <&clks IMX6QDL_CLK_GPMI_BCH_APB>, + <&clks IMX6QDL_CLK_PER1_BCH>; clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_bch_apb", "per1_bch"; dmas = <&dma_apbh 0>; @@ -118,7 +122,7 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>; interrupts = <1 13 0xf01>; - clocks = <&clks 15>; + clocks = <&clks IMX6QDL_CLK_TWD>; }; L2: l2-cache@00a02000 { @@ -149,7 +153,9 @@ <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 144>, <&clks 206>, <&clks 189>; + clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, + <&clks IMX6QDL_CLK_LVDS1_GATE>, + <&clks IMX6QDL_CLK_PCIE_REF_125M>; clock-names = "pcie", "pcie_bus", "pcie_phy"; status = "disabled"; }; @@ -180,11 +186,11 @@ dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; dma-names = "rx", "tx"; - clocks = <&clks 197>, <&clks 3>, - <&clks 197>, <&clks 0>, - <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, - <&clks 0>; + clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>, + <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>, + <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, + <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, + <&clks IMX6QDL_CLK_DUMMY>; clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", @@ -199,7 +205,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02008000 0x4000>; interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 112>, <&clks 112>; + clocks = <&clks IMX6QDL_CLK_ECSPI1>, + <&clks IMX6QDL_CLK_ECSPI1>; clock-names = "ipg", "per"; dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; dma-names = "rx", "tx"; @@ -212,7 +219,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x0200c000 0x4000>; interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 113>, <&clks 113>; + clocks = <&clks IMX6QDL_CLK_ECSPI2>, + <&clks IMX6QDL_CLK_ECSPI2>; clock-names = "ipg", "per"; dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; dma-names = "rx", "tx"; @@ -225,7 +233,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02010000 0x4000>; interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 114>, <&clks 114>; + clocks = <&clks IMX6QDL_CLK_ECSPI3>, + <&clks IMX6QDL_CLK_ECSPI3>; clock-names = "ipg", "per"; dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; dma-names = "rx", "tx"; @@ -238,7 +247,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02014000 0x4000>; interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 115>, <&clks 115>; + clocks = <&clks IMX6QDL_CLK_ECSPI4>, + <&clks IMX6QDL_CLK_ECSPI4>; clock-names = "ipg", "per"; dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; dma-names = "rx", "tx"; @@ -249,7 +259,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 160>, <&clks 161>; + clocks = <&clks IMX6QDL_CLK_UART_IPG>, + <&clks IMX6QDL_CLK_UART_SERIAL>; clock-names = "ipg", "per"; dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; dma-names = "rx", "tx"; @@ -267,7 +278,7 @@ "fsl,imx21-ssi"; reg = <0x02028000 0x4000>; interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 178>; + clocks = <&clks IMX6QDL_CLK_SSI1_IPG>; dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; dma-names = "rx", "tx"; @@ -281,7 +292,7 @@ "fsl,imx21-ssi"; reg = <0x0202c000 0x4000>; interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 179>; + clocks = <&clks IMX6QDL_CLK_SSI2_IPG>; dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; dma-names = "rx", "tx"; @@ -295,7 +306,7 @@ "fsl,imx21-ssi"; reg = <0x02030000 0x4000>; interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 180>; + clocks = <&clks IMX6QDL_CLK_SSI3_IPG>; dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; dma-names = "rx", "tx"; @@ -328,7 +339,8 @@ compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 62>, <&clks 145>; + clocks = <&clks IMX6QDL_CLK_IPG>, + <&clks IMX6QDL_CLK_PWM1>; clock-names = "ipg", "per"; }; @@ -337,7 +349,8 @@ compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 62>, <&clks 146>; + clocks = <&clks IMX6QDL_CLK_IPG>, + <&clks IMX6QDL_CLK_PWM2>; clock-names = "ipg", "per"; }; @@ -346,7 +359,8 @@ compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 62>, <&clks 147>; + clocks = <&clks IMX6QDL_CLK_IPG>, + <&clks IMX6QDL_CLK_PWM3>; clock-names = "ipg", "per"; }; @@ -355,7 +369,8 @@ compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 62>, <&clks 148>; + clocks = <&clks IMX6QDL_CLK_IPG>, + <&clks IMX6QDL_CLK_PWM4>; clock-names = "ipg", "per"; }; @@ -363,7 +378,8 @@ compatible = "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 108>, <&clks 109>; + clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, + <&clks IMX6QDL_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -372,7 +388,8 @@ compatible = "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 110>, <&clks 111>; + clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, + <&clks IMX6QDL_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -381,7 +398,8 @@ compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; reg = <0x02098000 0x4000>; interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 119>, <&clks 120>; + clocks = <&clks IMX6QDL_CLK_GPT_IPG>, + <&clks IMX6QDL_CLK_GPT_IPG_PER>; clock-names = "ipg", "per"; }; @@ -466,21 +484,21 @@ compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 62>; + clocks = <&clks IMX6QDL_CLK_IPG>; }; wdog1: wdog@020bc000 { compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 0>; + clocks = <&clks IMX6QDL_CLK_DUMMY>; }; wdog2: wdog@020c0000 { compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 0>; + clocks = <&clks IMX6QDL_CLK_DUMMY>; status = "disabled"; }; @@ -598,14 +616,14 @@ interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; fsl,tempmon = <&anatop>; fsl,tempmon-data = <&ocotp>; - clocks = <&clks 172>; + clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; }; usbphy1: usbphy@020c9000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 182>; + clocks = <&clks IMX6QDL_CLK_USBPHY1>; fsl,anatop = <&anatop>; }; @@ -613,7 +631,7 @@ compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 183>; + clocks = <&clks IMX6QDL_CLK_USBPHY2>; fsl,anatop = <&anatop>; }; @@ -726,7 +744,8 @@ reg = <0x00120000 0x9000>; interrupts = <0 115 0x04>; gpr = <&gpr>; - clocks = <&clks 123>, <&clks 124>; + clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HDMI_ISFR>; clock-names = "iahb", "isfr"; status = "disabled"; @@ -761,7 +780,8 @@ compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 155>, <&clks 155>; + clocks = <&clks IMX6QDL_CLK_SDMA>, + <&clks IMX6QDL_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; @@ -789,7 +809,7 @@ compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 162>; + clocks = <&clks IMX6QDL_CLK_USBOH3>; fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc 0>; status = "disabled"; @@ -799,7 +819,7 @@ compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 162>; + clocks = <&clks IMX6QDL_CLK_USBOH3>; fsl,usbphy = <&usbphy2>; fsl,usbmisc = <&usbmisc 1>; status = "disabled"; @@ -809,7 +829,7 @@ compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184400 0x200>; interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 162>; + clocks = <&clks IMX6QDL_CLK_USBOH3>; fsl,usbmisc = <&usbmisc 2>; status = "disabled"; }; @@ -818,7 +838,7 @@ compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184600 0x200>; interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 162>; + clocks = <&clks IMX6QDL_CLK_USBOH3>; fsl,usbmisc = <&usbmisc 3>; status = "disabled"; }; @@ -827,7 +847,7 @@ #index-cells = <1>; compatible = "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; - clocks = <&clks 162>; + clocks = <&clks IMX6QDL_CLK_USBOH3>; }; fec: ethernet@02188000 { @@ -836,7 +856,9 @@ interrupts-extended = <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 117>, <&clks 117>, <&clks 190>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET_REF>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; @@ -852,7 +874,9 @@ compatible = "fsl,imx6q-usdhc"; reg = <0x02190000 0x4000>; interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 163>, <&clks 163>, <&clks 163>; + clocks = <&clks IMX6QDL_CLK_USDHC1>, + <&clks IMX6QDL_CLK_USDHC1>, + <&clks IMX6QDL_CLK_USDHC1>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -862,7 +886,9 @@ compatible = "fsl,imx6q-usdhc"; reg = <0x02194000 0x4000>; interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 164>, <&clks 164>, <&clks 164>; + clocks = <&clks IMX6QDL_CLK_USDHC2>, + <&clks IMX6QDL_CLK_USDHC2>, + <&clks IMX6QDL_CLK_USDHC2>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -872,7 +898,9 @@ compatible = "fsl,imx6q-usdhc"; reg = <0x02198000 0x4000>; interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 165>, <&clks 165>, <&clks 165>; + clocks = <&clks IMX6QDL_CLK_USDHC3>, + <&clks IMX6QDL_CLK_USDHC3>, + <&clks IMX6QDL_CLK_USDHC3>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -882,7 +910,9 @@ compatible = "fsl,imx6q-usdhc"; reg = <0x0219c000 0x4000>; interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 166>, <&clks 166>, <&clks 166>; + clocks = <&clks IMX6QDL_CLK_USDHC4>, + <&clks IMX6QDL_CLK_USDHC4>, + <&clks IMX6QDL_CLK_USDHC4>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -894,7 +924,7 @@ compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; reg = <0x021a0000 0x4000>; interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 125>; + clocks = <&clks IMX6QDL_CLK_I2C1>; status = "disabled"; }; @@ -904,7 +934,7 @@ compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; reg = <0x021a4000 0x4000>; interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 126>; + clocks = <&clks IMX6QDL_CLK_I2C2>; status = "disabled"; }; @@ -914,7 +944,7 @@ compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; reg = <0x021a8000 0x4000>; interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 127>; + clocks = <&clks IMX6QDL_CLK_I2C3>; status = "disabled"; }; @@ -935,7 +965,7 @@ compatible = "fsl,imx6q-weim"; reg = <0x021b8000 0x4000>; interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 196>; + clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; }; ocotp: ocotp@021bc000 { @@ -995,7 +1025,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021e8000 0x4000>; interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 160>, <&clks 161>; + clocks = <&clks IMX6QDL_CLK_UART_IPG>, + <&clks IMX6QDL_CLK_UART_SERIAL>; clock-names = "ipg", "per"; dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; dma-names = "rx", "tx"; @@ -1006,7 +1037,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021ec000 0x4000>; interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 160>, <&clks 161>; + clocks = <&clks IMX6QDL_CLK_UART_IPG>, + <&clks IMX6QDL_CLK_UART_SERIAL>; clock-names = "ipg", "per"; dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; dma-names = "rx", "tx"; @@ -1017,7 +1049,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f0000 0x4000>; interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 160>, <&clks 161>; + clocks = <&clks IMX6QDL_CLK_UART_IPG>, + <&clks IMX6QDL_CLK_UART_SERIAL>; clock-names = "ipg", "per"; dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; dma-names = "rx", "tx"; @@ -1028,7 +1061,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f4000 0x4000>; interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 160>, <&clks 161>; + clocks = <&clks IMX6QDL_CLK_UART_IPG>, + <&clks IMX6QDL_CLK_UART_SERIAL>; clock-names = "ipg", "per"; dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; dma-names = "rx", "tx"; @@ -1043,7 +1077,9 @@ reg = <0x02400000 0x400000>; interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, <0 5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 130>, <&clks 131>, <&clks 132>; + clocks = <&clks IMX6QDL_CLK_IPU1>, + <&clks IMX6QDL_CLK_IPU1_DI0>, + <&clks IMX6QDL_CLK_IPU1_DI1>; clock-names = "bus", "di0", "di1"; resets = <&src 2>; -- cgit v1.2.3 From 77e0d1cc772e1256c4c348d73fe7b6967f447532 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 23 Jun 2014 14:04:01 +0800 Subject: ARM: dts: imx6sx: iomux-gpr syscon is compatible to imx6q The imx6sx iomuxc-gpr syscon is compatible to imx6q, so let's add compatible string 'fsl,imx6q-iomuxc-gpr' for imx6sx iomuxc-gpr syscon node. This is necessary to enable SW workaround for ERR007265, please refer to imx6_pm_common_init of arch/arm/mach-imx/pm-imx6.c for detail. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 78ccf6151ab3..7b41194aef9a 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -697,7 +697,8 @@ }; gpr: iomuxc-gpr@020e4000 { - compatible = "fsl,imx6sx-iomuxc-gpr", "syscon"; + compatible = "fsl,imx6sx-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x020e4000 0x4000>; }; -- cgit v1.2.3 From b29f4fa16e33cdd68bc0346999c16a142d02f07d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Jun 2014 11:21:04 -0300 Subject: ARM: dts: imx6sx: Fix usbmisc compatible string Fix usbmisc compatible string so that usbmisc node can be found and USB functionality can be functional. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 7b41194aef9a..a7d74e7324e3 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -754,7 +754,7 @@ usbmisc: usbmisc@02184800 { #index-cells = <1>; - compatible = "fsl,imx6sx-usbmisc"; + compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; clocks = <&clks IMX6SX_CLK_USBOH3>; }; -- cgit v1.2.3 From 960fefff8b07640aa6cd53812ff502f76b220fc8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Jun 2014 11:21:05 -0300 Subject: ARM: dts: imx6sx-sdb: Add USB support Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-sdb.dts | 55 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index da40f1396798..18c228eb7f52 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -58,6 +58,30 @@ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_usb_otg1_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; }; @@ -81,6 +105,19 @@ status = "okay"; }; +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; @@ -163,6 +200,24 @@ >; }; + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg2: usbot2ggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 -- cgit v1.2.3 From b3d8e11fac83cbebc26e80b2e5e9f8929777ae55 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Jun 2014 11:21:06 -0300 Subject: ARM: dts: imx6sx-sdb: Add PMIC support Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-sdb.dts | 115 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index 18c228eb7f52..25712611f6e8 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -92,6 +92,114 @@ status = "okay"; }; +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -178,6 +286,13 @@ >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + pinctrl_vcc_sd3: vccsd3grp { fsl,pins = < MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 -- cgit v1.2.3 From 4c463178a9ef94e71014baf4bce2443f8070ae77 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 24 Jun 2014 11:19:58 +0100 Subject: ARM: dts: cubox-i: add eSATA DT configuration Add the transmit level, boost and attenuation parameters necessary for the eSATA interface on Cubox-i to work. Signed-off-by: Russell King Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-cubox-i.dts | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-cubox-i.dts b/arch/arm/boot/dts/imx6q-cubox-i.dts index bc5f31e3e892..941365d7ee65 100644 --- a/arch/arm/boot/dts/imx6q-cubox-i.dts +++ b/arch/arm/boot/dts/imx6q-cubox-i.dts @@ -13,4 +13,7 @@ &sata { status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; }; -- cgit v1.2.3 From 548220832123658e65f6b711f845d613e3cc02f0 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 24 Jun 2014 11:20:03 +0100 Subject: ARM: dts: cubox-i: disable spread-spectrum for Cubox-i eSATA Spread-spectrum doesn't work with Cubox-i hardware. eSATA devices are detected, but then fail on normal IO. Therefore, disable this feature. Signed-off-by: Russell King Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-cubox-i.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-cubox-i.dts b/arch/arm/boot/dts/imx6q-cubox-i.dts index 941365d7ee65..9efd8b0c8011 100644 --- a/arch/arm/boot/dts/imx6q-cubox-i.dts +++ b/arch/arm/boot/dts/imx6q-cubox-i.dts @@ -16,4 +16,5 @@ fsl,transmit-level-mV = <1104>; fsl,transmit-boost-mdB = <0>; fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; }; -- cgit v1.2.3 From 1b6f23685d46151b7b450ecc17ac1a1242493351 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 24 Jun 2014 21:13:44 -0300 Subject: ARM: dts: mx6: Disable the keypad in the dtsi files When booting a board that does not have a keypad (such as imx6q-sabresd) the following error is seen on boot: imx-keypad 20b8000.kpp: OF: linux,keymap property not defined in /soc/aips-bus@02000000/kpp@020b8000 imx-keypad 20b8000.kpp: failed to build keymap imx-keypad: probe of 20b8000.kpp failed with error -2 Let's disable the keypad functionality in the dtsi files and let each board dts enable it when needed. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-tx6.dtsi | 1 + arch/arm/boot/dts/imx6qdl.dtsi | 1 + arch/arm/boot/dts/imx6sl.dtsi | 1 + 3 files changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index 66a135392342..f02b80b41d4f 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -620,6 +620,7 @@ MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */ MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */ >; + status = "okay"; }; &pwm1 { diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 1fd272b52df1..d7c97d95c525 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -485,6 +485,7 @@ reg = <0x020b8000 0x4000>; interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_IPG>; + status = "disabled"; }; wdog1: wdog@020bc000 { diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 57d4abe03a94..c0ee12f1f171 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -403,6 +403,7 @@ reg = <0x020b8000 0x4000>; interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_DUMMY>; + status = "disabled"; }; wdog1: wdog@020bc000 { -- cgit v1.2.3 From 5363dcabd3c0b3e051fd6c7a9bf44570c0cc9ee1 Mon Sep 17 00:00:00 2001 From: Denis Carikli Date: Wed, 25 Jun 2014 14:41:35 +0200 Subject: ARM: dts: i.MX25: Fix gpt timers clocks. Without that fix, the board freeze during boot. This appeared after the following commit: 496f065 ARM: i.MX: Use of_clk_get_by_name() for timer clocks for DT case. Signed-off-by: Denis Carikli Acked-by: Sascha Hauer Tested-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index bb74d9582b7e..c1740396b2c9 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -312,7 +312,7 @@ gpt4: timer@53f84000 { compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; reg = <0x53f84000 0x4000>; - clocks = <&clks 9>, <&clks 45>; + clocks = <&clks 95>, <&clks 47>; clock-names = "ipg", "per"; interrupts = <1>; }; @@ -320,7 +320,7 @@ gpt3: timer@53f88000 { compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; reg = <0x53f88000 0x4000>; - clocks = <&clks 9>, <&clks 47>; + clocks = <&clks 94>, <&clks 47>; clock-names = "ipg", "per"; interrupts = <29>; }; @@ -328,7 +328,7 @@ gpt2: timer@53f8c000 { compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; reg = <0x53f8c000 0x4000>; - clocks = <&clks 9>, <&clks 47>; + clocks = <&clks 93>, <&clks 47>; clock-names = "ipg", "per"; interrupts = <53>; }; @@ -336,7 +336,7 @@ gpt1: timer@53f90000 { compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; reg = <0x53f90000 0x4000>; - clocks = <&clks 9>, <&clks 47>; + clocks = <&clks 92>, <&clks 47>; clock-names = "ipg", "per"; interrupts = <54>; }; -- cgit v1.2.3 From acb7ea5eba26696f2f4306624bf176c973a07fe8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 25 Jun 2014 20:48:33 +0200 Subject: ARM: dts: mxs: Split M28EVK into SoM and EVK parts This patch splits the M28EVK device tree file into a common SoM part and an EVK part. This is needed to make it easier for users of the SoM to put it into different, non-reference baseboard. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-m28.dtsi | 87 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx28-m28evk.dts | 62 +-------------------------- 2 files changed, 88 insertions(+), 61 deletions(-) create mode 100644 arch/arm/boot/dts/imx28-m28.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi new file mode 100644 index 000000000000..759cc56253dd --- /dev/null +++ b/arch/arm/boot/dts/imx28-m28.dtsi @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2014 Marek Vasut + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx28.dtsi" + +/ { + model = "DENX M28"; + compatible = "denx,m28", "fsl,imx28"; + + memory { + reg = <0x40000000 0x08000000>; + }; + + apb@80000000 { + apbh@80000000 { + gpmi-nand@8000c000 { + #address-cells = <1>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; + + partition@0 { + label = "bootloader"; + reg = <0x00000000 0x00300000>; + read-only; + }; + + partition@1 { + label = "environment"; + reg = <0x00300000 0x00080000>; + }; + + partition@2 { + label = "redundant-environment"; + reg = <0x00380000 0x00080000>; + }; + + partition@3 { + label = "kernel"; + reg = <0x00400000 0x00400000>; + }; + + partition@4 { + label = "filesystem"; + reg = <0x00800000 0x0f800000>; + }; + }; + }; + + apbx@80040000 { + i2c0: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + rtc: rtc@68 { + compatible = "stm,m41t62"; + reg = <0x68>; + }; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index f0ad7b9b9d9a..b3c09ae3b928 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -10,52 +10,14 @@ */ /dts-v1/; -#include "imx28.dtsi" +#include "imx28-m28.dtsi" / { model = "DENX M28EVK"; compatible = "denx,m28evk", "fsl,imx28"; - memory { - reg = <0x40000000 0x08000000>; - }; - apb@80000000 { apbh@80000000 { - gpmi-nand@8000c000 { - #address-cells = <1>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; - - partition@0 { - label = "bootloader"; - reg = <0x00000000 0x00300000>; - read-only; - }; - - partition@1 { - label = "environment"; - reg = <0x00300000 0x00080000>; - }; - - partition@2 { - label = "redundant-environment"; - reg = <0x00380000 0x00080000>; - }; - - partition@3 { - label = "kernel"; - reg = <0x00400000 0x00400000>; - }; - - partition@4 { - label = "filesystem"; - reg = <0x00800000 0x0f800000>; - }; - }; - ssp0: ssp@80010000 { compatible = "fsl,imx28-mmc"; pinctrl-names = "default"; @@ -175,10 +137,6 @@ }; i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - sgtl5000: codec@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; @@ -192,11 +150,6 @@ reg = <0x51>; pagesize = <32>; }; - - rtc: rtc@68 { - compatible = "stm,m41t62"; - reg = <0x68>; - }; }; lradc@80050000 { @@ -284,19 +237,6 @@ }; regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - reg_vddio_sd0: regulator@1 { compatible = "regulator-fixed"; reg = <1>; -- cgit v1.2.3 From ac08281ed63c7f0282a3c6800b68772f69e9459c Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Wed, 25 Jun 2014 13:01:30 +0200 Subject: ARM: dts: i.MX53: add aipstz nodes The AHB to IP bridges (AIPSTZ) allow fine grained access rights management. Add both bridges to the DT. Signed-off-by: Steffen Trumtrar Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index d8d3f979f599..5fe8509cc4b6 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -259,6 +259,11 @@ }; }; + aipstz1: bridge@53f00000 { + compatible = "fsl,imx53-aipstz"; + reg = <0x53f00000 0x60>; + }; + usbphy0: usbphy@0 { compatible = "usb-nop-xceiv"; clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; @@ -571,6 +576,11 @@ reg = <0x60000000 0x10000000>; ranges; + aipstz2: bridge@63f00000 { + compatible = "fsl,imx53-aipstz"; + reg = <0x63f00000 0x60>; + }; + iim: iim@63f98000 { compatible = "fsl,imx53-iim", "fsl,imx27-iim"; reg = <0x63f98000 0x4000>; -- cgit v1.2.3 From e60e9461d4c608ccd553620622388e4d1a63dcf6 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 25 Jun 2014 17:28:52 -0300 Subject: ARM: dts: imx25-pdk: Add USB OTG support Tested by loading the g_ether module and doing a ping between mx25pdk and the host PC via USB. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pdk.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index 8f9a424a80d6..9c21b1583762 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -248,3 +248,10 @@ dr_mode = "host"; status = "okay"; }; + +&usbotg { + phy_type = "utmi"; + dr_mode = "otg"; + external-vbus-divider; + status = "okay"; +}; -- cgit v1.2.3 From fd101c4c566321a57dcafe8e3832d7a93dead3b7 Mon Sep 17 00:00:00 2001 From: Silvio Fricke Date: Tue, 1 Jul 2014 13:08:59 +0200 Subject: ARM: dts: imx6: edmqmx6: Add PCIe support Add support for the PCI express bus available on MX6 Data Modul edm-qmx6 board. Signed-off-by: Silvio Fricke Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index e0302636aff5..f36dab0e711c 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -323,6 +323,12 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1 + >; + }; + pinctrl_pfuze: pfuze100grp1 { fsl,pins = < MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000 @@ -385,6 +391,13 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 8 0>; + status = "okay"; +}; + &sata { status = "okay"; }; -- cgit v1.2.3 From 3c6c86859474d146be58fffcf76fad91d0eedb4c Mon Sep 17 00:00:00 2001 From: Silvio Fricke Date: Tue, 1 Jul 2014 13:09:00 +0200 Subject: ARM: dts: imx6: edmqmx6: Add two other i2c buses Signed-off-by: Silvio Fricke Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index f36dab0e711c..dd9ef1625d92 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -118,6 +118,13 @@ status = "okay"; }; +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + &i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -274,6 +281,13 @@ }; }; +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -316,6 +330,13 @@ >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 @@ -323,6 +344,13 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1 -- cgit v1.2.3 From 37183793f5de7ffd6d5421ff4caa3a972a0a887c Mon Sep 17 00:00:00 2001 From: Silvio Fricke Date: Tue, 1 Jul 2014 13:09:01 +0200 Subject: ARM: dts: imx6: edmqmx6: Add can bus Signed-off-by: Silvio Fricke Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index dd9ef1625d92..8c1cb53464a0 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -95,6 +95,12 @@ }; }; +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + &ecspi5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi5>; @@ -300,6 +306,13 @@ >; }; + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + >; + }; + pinctrl_ecspi5: ecspi5rp-1 { fsl,pins = < MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000 -- cgit v1.2.3 From aeb885387f3d18c6fc9d5cbd6895bcd10c2703f5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 2 Jul 2014 11:58:49 -0300 Subject: ARM: dts: imx6sx: Fix sdma node Use the correct compatible string for sdma and also provide the sdma firmware path. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index a7d74e7324e3..29290780206a 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -703,13 +703,15 @@ }; sdma: sdma@020ec000 { - compatible = "fsl,imx6sx-sdma"; + compatible = "fsl,imx6sx-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_SDMA>, <&clks IMX6SX_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; + /* imx6sx reuses imx6q sdma firmware */ + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; }; }; -- cgit v1.2.3 From 3a462a624b7c77b783a32bc1b9415186370fbf03 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 2 Jul 2014 11:58:50 -0300 Subject: ARM: dts: imx6sx: Pass the fsl,fifo-depth property Like the other mx6 variants, we need to pass fsl,fifo-depth property in dtsi. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 29290780206a..92d48becdb45 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -306,6 +306,7 @@ clock-names = "ipg", "baud"; dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; status = "disabled"; }; @@ -318,6 +319,7 @@ clock-names = "ipg", "baud"; dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; status = "disabled"; }; @@ -330,6 +332,7 @@ clock-names = "ipg", "baud"; dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; status = "disabled"; }; -- cgit v1.2.3 From 9c86ae8c705ccebb80c28034b095a4d7ec3f4ab0 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 2 Jul 2014 11:58:52 -0300 Subject: ARM: dts: imx6sx-sdb: Add audio support Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-sdb.dts | 72 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index 25712611f6e8..a3980d970590 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -82,9 +82,39 @@ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_psu_5v: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "PSU-5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; + + sound { + compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + ssi-controller = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <6>; }; }; +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; @@ -200,6 +230,31 @@ }; }; +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6SX_CLK_AUDIO>; + DCVDD-supply = <&vgen4_reg>; + DBVDD-supply = <&vgen4_reg>; + AVDD-supply = <&vgen4_reg>; + CPVDD-supply = <&vgen4_reg>; + MICVDD-supply = <&vgen3_reg>; + PLLVDD-supply = <&vgen4_reg>; + SPKVDD1-supply = <®_psu_5v>; + SPKVDD2-supply = <®_psu_5v>; + }; +}; + +&ssi2 { + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -260,6 +315,16 @@ &iomuxc { imx6x-sdb { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 + MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0 + MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0 + MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 + >; + }; + pinctrl_enet1: enet1grp { fsl,pins = < MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 @@ -293,6 +358,13 @@ >; }; + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 + >; + }; + pinctrl_vcc_sd3: vccsd3grp { fsl,pins = < MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 -- cgit v1.2.3 From 811e76856ab525bc392e7e4651e8d76f7e047e35 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Fri, 4 Jul 2014 14:30:27 +0800 Subject: ARM: dts: imx: correct sdma compatbile for imx6sl and imx6sx The SDMA on imx6sl and imx6sx is more compatible with imx6q one than imx35. Let's use "fsl,imx6q-sdma" instead of "fsl,imx35-sdma", so that SDMA ROM script on imx6sl and imx6sx can work for audio driver just like the case of imx6q. Reported-by: Fabio Estevam Signed-off-by: Shawn Guo Acked-by: Robin Gong --- arch/arm/boot/dts/imx6sl.dtsi | 2 +- arch/arm/boot/dts/imx6sx.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index c0ee12f1f171..0467ac064e9d 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -608,7 +608,7 @@ }; sdma: sdma@020ec000 { - compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma"; + compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma"; reg = <0x020ec000 0x4000>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_SDMA>, diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 92d48becdb45..0c5094adedfa 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -706,7 +706,7 @@ }; sdma: sdma@020ec000 { - compatible = "fsl,imx6sx-sdma", "fsl,imx35-sdma"; + compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; reg = <0x020ec000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_SDMA>, -- cgit v1.2.3 From ea336fa8eeb4b00f746983e3f24bc99e1547fb58 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 5 Jul 2014 09:36:07 +0400 Subject: ARM: i.MX27 clk: dts: Use clock defines in DTS files Use clock definitions in i.MX27 DTS files. Additional changes included in this patch (imx27.dtsi): - Fix IPG clock for UART6. - Use EMI_AHB_GATE clock for WEIM. - Added GPIO_IPG_GATE clock for GPIO nodes. Currently this clock is not used by the driver, but it can be added in the future. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-pdk.dts | 2 +- arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 2 +- arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 2 +- arch/arm/boot/dts/imx27.dtsi | 115 +++++++++++++++--------- 4 files changed, 77 insertions(+), 44 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts index 4c317716b510..49450dbbcab8 100644 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ b/arch/arm/boot/dts/imx27-pdk.dts @@ -28,7 +28,7 @@ usbphy0: usbphy@0 { compatible = "usb-nop-xceiv"; reg = <0>; - clocks = <&clks 0>; + clocks = <&clks IMX27_CLK_DUMMY>; clock-names = "main_clk"; }; }; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index fe02bc7a24fd..538568b0de26 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -61,7 +61,7 @@ compatible = "usb-nop-xceiv"; reg = <2>; vcc-supply = <®_5v0>; - clocks = <&clks 0>; + clocks = <&clks IMX27_CLK_DUMMY>; clock-names = "main_clk"; }; }; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index 2e376edce972..b4e955e3be8d 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi @@ -51,7 +51,7 @@ compatible = "usb-nop-xceiv"; reg = <0>; vcc-supply = <&sw3_reg>; - clocks = <&clks 0>; + clocks = <&clks IMX27_CLK_DUMMY>; clock-names = "main_clk"; }; }; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index a75555c39533..107d713e1cbe 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -11,9 +11,11 @@ #include "skeleton.dtsi" #include "imx27-pinfunc.h" + +#include +#include #include #include -#include / { aliases { @@ -68,7 +70,7 @@ 399000 1450000 >; clock-latency = <62500>; - clocks = <&clks 18>; + clocks = <&clks IMX27_CLK_CPU_DIV>; voltage-tolerance = <5>; }; }; @@ -91,7 +93,8 @@ compatible = "fsl,imx27-dma"; reg = <0x10001000 0x1000>; interrupts = <32>; - clocks = <&clks 50>, <&clks 70>; + clocks = <&clks IMX27_CLK_DMA_IPG_GATE>, + <&clks IMX27_CLK_DMA_AHB_GATE>; clock-names = "ipg", "ahb"; #dma-cells = <1>; #dma-channels = <16>; @@ -101,14 +104,15 @@ compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; reg = <0x10002000 0x1000>; interrupts = <27>; - clocks = <&clks 74>; + clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>; }; gpt1: timer@10003000 { compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; reg = <0x10003000 0x1000>; interrupts = <26>; - clocks = <&clks 46>, <&clks 61>; + clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; clock-names = "ipg", "per"; }; @@ -116,7 +120,8 @@ compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; reg = <0x10004000 0x1000>; interrupts = <25>; - clocks = <&clks 45>, <&clks 61>; + clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; clock-names = "ipg", "per"; }; @@ -124,7 +129,8 @@ compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; reg = <0x10005000 0x1000>; interrupts = <24>; - clocks = <&clks 44>, <&clks 61>; + clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; clock-names = "ipg", "per"; }; @@ -133,7 +139,8 @@ compatible = "fsl,imx27-pwm"; reg = <0x10006000 0x1000>; interrupts = <23>; - clocks = <&clks 34>, <&clks 61>; + clocks = <&clks IMX27_CLK_PWM_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; clock-names = "ipg", "per"; }; @@ -141,14 +148,14 @@ compatible = "fsl,imx27-kpp", "fsl,imx21-kpp"; reg = <0x10008000 0x1000>; interrupts = <21>; - clocks = <&clks 37>; + clocks = <&clks IMX27_CLK_KPP_IPG_GATE>; status = "disabled"; }; owire: owire@10009000 { compatible = "fsl,imx27-owire", "fsl,imx21-owire"; reg = <0x10009000 0x1000>; - clocks = <&clks 35>; + clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>; status = "disabled"; }; @@ -156,7 +163,8 @@ compatible = "fsl,imx27-uart", "fsl,imx21-uart"; reg = <0x1000a000 0x1000>; interrupts = <20>; - clocks = <&clks 81>, <&clks 61>; + clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -165,7 +173,8 @@ compatible = "fsl,imx27-uart", "fsl,imx21-uart"; reg = <0x1000b000 0x1000>; interrupts = <19>; - clocks = <&clks 80>, <&clks 61>; + clocks = <&clks IMX27_CLK_UART2_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -174,7 +183,8 @@ compatible = "fsl,imx27-uart", "fsl,imx21-uart"; reg = <0x1000c000 0x1000>; interrupts = <18>; - clocks = <&clks 79>, <&clks 61>; + clocks = <&clks IMX27_CLK_UART3_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -183,7 +193,8 @@ compatible = "fsl,imx27-uart", "fsl,imx21-uart"; reg = <0x1000d000 0x1000>; interrupts = <17>; - clocks = <&clks 78>, <&clks 61>; + clocks = <&clks IMX27_CLK_UART4_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -194,7 +205,8 @@ compatible = "fsl,imx27-cspi"; reg = <0x1000e000 0x1000>; interrupts = <16>; - clocks = <&clks 53>, <&clks 60>; + clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>, + <&clks IMX27_CLK_PER2_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -205,7 +217,8 @@ compatible = "fsl,imx27-cspi"; reg = <0x1000f000 0x1000>; interrupts = <15>; - clocks = <&clks 52>, <&clks 60>; + clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>, + <&clks IMX27_CLK_PER2_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -215,7 +228,7 @@ compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; reg = <0x10010000 0x1000>; interrupts = <14>; - clocks = <&clks 26>; + clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>; dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>; dma-names = "rx0", "tx0", "rx1", "tx1"; fsl,fifo-depth = <8>; @@ -227,7 +240,7 @@ compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; reg = <0x10011000 0x1000>; interrupts = <13>; - clocks = <&clks 25>; + clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>; dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>; dma-names = "rx0", "tx0", "rx1", "tx1"; fsl,fifo-depth = <8>; @@ -240,7 +253,7 @@ compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; reg = <0x10012000 0x1000>; interrupts = <12>; - clocks = <&clks 40>; + clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>; status = "disabled"; }; @@ -248,7 +261,8 @@ compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; reg = <0x10013000 0x1000>; interrupts = <11>; - clocks = <&clks 30>, <&clks 60>; + clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>, + <&clks IMX27_CLK_PER2_GATE>; clock-names = "ipg", "per"; dmas = <&dma 7>; dma-names = "rx-tx"; @@ -259,7 +273,8 @@ compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; reg = <0x10014000 0x1000>; interrupts = <10>; - clocks = <&clks 29>, <&clks 60>; + clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>, + <&clks IMX27_CLK_PER2_GATE>; clock-names = "ipg", "per"; dmas = <&dma 6>; dma-names = "rx-tx"; @@ -276,6 +291,7 @@ gpio1: gpio@10015000 { compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; reg = <0x10015000 0x100>; + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; interrupts = <8>; gpio-controller; #gpio-cells = <2>; @@ -286,6 +302,7 @@ gpio2: gpio@10015100 { compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; reg = <0x10015100 0x100>; + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; interrupts = <8>; gpio-controller; #gpio-cells = <2>; @@ -296,6 +313,7 @@ gpio3: gpio@10015200 { compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; reg = <0x10015200 0x100>; + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; interrupts = <8>; gpio-controller; #gpio-cells = <2>; @@ -306,6 +324,7 @@ gpio4: gpio@10015300 { compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; reg = <0x10015300 0x100>; + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; interrupts = <8>; gpio-controller; #gpio-cells = <2>; @@ -316,6 +335,7 @@ gpio5: gpio@10015400 { compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; reg = <0x10015400 0x100>; + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; interrupts = <8>; gpio-controller; #gpio-cells = <2>; @@ -326,6 +346,7 @@ gpio6: gpio@10015500 { compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; reg = <0x10015500 0x100>; + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; interrupts = <8>; gpio-controller; #gpio-cells = <2>; @@ -337,7 +358,7 @@ audmux: audmux@10016000 { compatible = "fsl,imx27-audmux", "fsl,imx21-audmux"; reg = <0x10016000 0x1000>; - clocks = <&clks 0>; + clocks = <&clks IMX27_CLK_DUMMY>; clock-names = "audmux"; status = "disabled"; }; @@ -348,7 +369,8 @@ compatible = "fsl,imx27-cspi"; reg = <0x10017000 0x1000>; interrupts = <6>; - clocks = <&clks 51>, <&clks 60>; + clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>, + <&clks IMX27_CLK_PER2_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -357,7 +379,8 @@ compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; reg = <0x10019000 0x1000>; interrupts = <4>; - clocks = <&clks 43>, <&clks 61>; + clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; clock-names = "ipg", "per"; }; @@ -365,7 +388,8 @@ compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; reg = <0x1001a000 0x1000>; interrupts = <3>; - clocks = <&clks 42>, <&clks 61>; + clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; clock-names = "ipg", "per"; }; @@ -373,7 +397,8 @@ compatible = "fsl,imx27-uart", "fsl,imx21-uart"; reg = <0x1001b000 0x1000>; interrupts = <49>; - clocks = <&clks 77>, <&clks 61>; + clocks = <&clks IMX27_CLK_UART5_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -382,7 +407,8 @@ compatible = "fsl,imx27-uart", "fsl,imx21-uart"; reg = <0x1001c000 0x1000>; interrupts = <48>; - clocks = <&clks 78>, <&clks 61>; + clocks = <&clks IMX27_CLK_UART6_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -393,7 +419,7 @@ compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; reg = <0x1001d000 0x1000>; interrupts = <1>; - clocks = <&clks 39>; + clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>; status = "disabled"; }; @@ -401,7 +427,8 @@ compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; reg = <0x1001e000 0x1000>; interrupts = <9>; - clocks = <&clks 28>, <&clks 60>; + clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>, + <&clks IMX27_CLK_PER2_GATE>; clock-names = "ipg", "per"; dmas = <&dma 36>; dma-names = "rx-tx"; @@ -412,7 +439,8 @@ compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; reg = <0x1001f000 0x1000>; interrupts = <2>; - clocks = <&clks 41>, <&clks 61>; + clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; clock-names = "ipg", "per"; }; }; @@ -428,7 +456,9 @@ compatible = "fsl,imx27-fb", "fsl,imx21-fb"; interrupts = <61>; reg = <0x10021000 0x1000>; - clocks = <&clks 36>, <&clks 65>, <&clks 59>; + clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>, + <&clks IMX27_CLK_LCDC_AHB_GATE>, + <&clks IMX27_CLK_PER3_GATE>; clock-names = "ipg", "ahb", "per"; status = "disabled"; }; @@ -437,7 +467,8 @@ compatible = "fsl,imx27-vpu"; reg = <0x10023000 0x0200>; interrupts = <53>; - clocks = <&clks 57>, <&clks 66>; + clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>, + <&clks IMX27_CLK_VPU_AHB_GATE>; clock-names = "per", "ahb"; iram = <&iram>; }; @@ -446,7 +477,7 @@ compatible = "fsl,imx27-usb"; reg = <0x10024000 0x200>; interrupts = <56>; - clocks = <&clks 75>; + clocks = <&clks IMX27_CLK_USB_IPG_GATE>; fsl,usbmisc = <&usbmisc 0>; status = "disabled"; }; @@ -455,7 +486,7 @@ compatible = "fsl,imx27-usb"; reg = <0x10024200 0x200>; interrupts = <54>; - clocks = <&clks 75>; + clocks = <&clks IMX27_CLK_USB_IPG_GATE>; fsl,usbmisc = <&usbmisc 1>; status = "disabled"; }; @@ -464,7 +495,7 @@ compatible = "fsl,imx27-usb"; reg = <0x10024400 0x200>; interrupts = <55>; - clocks = <&clks 75>; + clocks = <&clks IMX27_CLK_USB_IPG_GATE>; fsl,usbmisc = <&usbmisc 2>; status = "disabled"; }; @@ -473,14 +504,15 @@ #index-cells = <1>; compatible = "fsl,imx27-usbmisc"; reg = <0x10024600 0x200>; - clocks = <&clks 62>; + clocks = <&clks IMX27_CLK_USB_AHB_GATE>; }; sahara2: sahara@10025000 { compatible = "fsl,imx27-sahara"; reg = <0x10025000 0x1000>; interrupts = <59>; - clocks = <&clks 32>, <&clks 64>; + clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>, + <&clks IMX27_CLK_SAHARA_AHB_GATE>; clock-names = "ipg", "ahb"; }; @@ -494,14 +526,15 @@ compatible = "fsl,imx27-iim"; reg = <0x10028000 0x1000>; interrupts = <62>; - clocks = <&clks 38>; + clocks = <&clks IMX27_CLK_IIM_IPG_GATE>; }; fec: ethernet@1002b000 { compatible = "fsl,imx27-fec"; reg = <0x1002b000 0x4000>; interrupts = <50>; - clocks = <&clks 48>, <&clks 67>; + clocks = <&clks IMX27_CLK_FEC_IPG_GATE>, + <&clks IMX27_CLK_FEC_AHB_GATE>; clock-names = "ipg", "ahb"; status = "disabled"; }; @@ -513,7 +546,7 @@ compatible = "fsl,imx27-nand"; reg = <0xd8000000 0x1000>; interrupts = <29>; - clocks = <&clks 54>; + clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>; status = "disabled"; }; @@ -522,7 +555,7 @@ #size-cells = <1>; compatible = "fsl,imx27-weim"; reg = <0xd8002000 0x1000>; - clocks = <&clks 0>; + clocks = <&clks IMX27_CLK_EMI_AHB_GATE>; ranges = < 0 0 0xc0000000 0x08000000 1 0 0xc8000000 0x08000000 -- cgit v1.2.3 From 4c03527eb77ca267e60a2ea2e86497aab3bf7ea9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 7 Jul 2014 10:04:52 -0300 Subject: ARM: imx6: Align ssi nodes between mx6 variants Since commit 98ea6ad2edd2 (ARM: dts: imx6: use imx51-ssi) the mx6 ssi is compatible with imx51, so align all the mx6 variant ssi compatible strings as: compatible = "fsl,-ssi", "fsl,imx51-ssi"; Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 9 +++------ arch/arm/boot/dts/imx6sl.dtsi | 9 +++------ arch/arm/boot/dts/imx6sx.dtsi | 6 +++--- 3 files changed, 9 insertions(+), 15 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index d7c97d95c525..c701af958006 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -274,8 +274,7 @@ ssi1: ssi@02028000 { compatible = "fsl,imx6q-ssi", - "fsl,imx51-ssi", - "fsl,imx21-ssi"; + "fsl,imx51-ssi"; reg = <0x02028000 0x4000>; interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_SSI1_IPG>; @@ -288,8 +287,7 @@ ssi2: ssi@0202c000 { compatible = "fsl,imx6q-ssi", - "fsl,imx51-ssi", - "fsl,imx21-ssi"; + "fsl,imx51-ssi"; reg = <0x0202c000 0x4000>; interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_SSI2_IPG>; @@ -302,8 +300,7 @@ ssi3: ssi@02030000 { compatible = "fsl,imx6q-ssi", - "fsl,imx51-ssi", - "fsl,imx21-ssi"; + "fsl,imx51-ssi"; reg = <0x02030000 0x4000>; interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_SSI3_IPG>; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 0467ac064e9d..c75800ca8b35 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -227,8 +227,7 @@ ssi1: ssi@02028000 { compatible = "fsl,imx6sl-ssi", - "fsl,imx51-ssi", - "fsl,imx21-ssi"; + "fsl,imx51-ssi"; reg = <0x02028000 0x4000>; interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_SSI1>; @@ -241,8 +240,7 @@ ssi2: ssi@0202c000 { compatible = "fsl,imx6sl-ssi", - "fsl,imx51-ssi", - "fsl,imx21-ssi"; + "fsl,imx51-ssi"; reg = <0x0202c000 0x4000>; interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_SSI2>; @@ -255,8 +253,7 @@ ssi3: ssi@02030000 { compatible = "fsl,imx6sl-ssi", - "fsl,imx51-ssi", - "fsl,imx21-ssi"; + "fsl,imx51-ssi"; reg = <0x02030000 0x4000>; interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_SSI3>; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 0c5094adedfa..f4b9da65bc0f 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -298,7 +298,7 @@ }; ssi1: ssi@02028000 { - compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi"; + compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x02028000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_SSI1_IPG>, @@ -311,7 +311,7 @@ }; ssi2: ssi@0202c000 { - compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi"; + compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x0202c000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_SSI2_IPG>, @@ -324,7 +324,7 @@ }; ssi3: ssi@02030000 { - compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi"; + compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x02030000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_SSI3_IPG>, -- cgit v1.2.3 From 025781539a3ccf867c1e0f2fc63f61cc8c7c5415 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 8 Jul 2014 16:14:47 +0800 Subject: ARM: dts: imx53: correct clock-names of SATA node Per the binding doc imx-sata.txt, the first entry of clock-names should be "sata" than anything else. Correct it for imx53 SATA node. It works for now only because SATA driver gets clock by index so far. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 5fe8509cc4b6..64fa27b36be0 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -108,7 +108,7 @@ clocks = <&clks IMX5_CLK_SATA_GATE>, <&clks IMX5_CLK_SATA_REF>, <&clks IMX5_CLK_AHB>; - clock-names = "sata_gate", "sata_ref", "ahb"; + clock-names = "sata", "sata_ref", "ahb"; status = "disabled"; }; -- cgit v1.2.3 From 8536239e371fababdb2b97468a07b3dac1cbfd5e Mon Sep 17 00:00:00 2001 From: George Joseph Date: Tue, 8 Jul 2014 12:48:16 -0600 Subject: ARM: dts: Restructure imx6qdl-wandboard.dtsi for new rev C1 board. The rev C1 Wandboard uses the Broadcom 4330 for WiFi and Bluetooth instead of the 4329. This changes the PADS assigned for the control lines. Another side effect of the change is that on the rev C1 board, usdhc driver can't detect the chip presence correctly so usdhc2 now needs its 'non-removeable' property removed. So that rev B1 and earlier can continue to work, this patch splits the board-specific definitions from imx6qdl-wandboard.dtsi into imx6qdl-wandboard-revb1.dtsi and imx6qdl-wandboard-revc1.dtsi. The new files include the original base imx6qdl-wandboard.dtsi which retains the common definitions. The existing imx6dl-wandboard.dts includes imx6qdl-wandboard-revc1.dtsi and imx6dl-wandboard-revb1.dts (new) includes imx6qdl-wandboard-revb1.dtsi. This makes the rev C1 board the new default. The same pattern is used for imx6q-wandboard.dts. So, from U-Boot on a WB-Quad you use imxq-wandboard-revb1.dtb for the older B1 board and imxq-wandboard.dtb for the current rev C1 board. Signed-off-by: George Joseph Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 ++ arch/arm/boot/dts/imx6dl-wandboard-revb1.dts | 22 ++++++++++++++ arch/arm/boot/dts/imx6dl-wandboard.dts | 2 +- arch/arm/boot/dts/imx6q-wandboard-revb1.dts | 26 ++++++++++++++++ arch/arm/boot/dts/imx6q-wandboard.dts | 2 +- arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi | 42 ++++++++++++++++++++++++++ arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi | 41 +++++++++++++++++++++++++ arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 21 ------------- 8 files changed, 135 insertions(+), 23 deletions(-) create mode 100644 arch/arm/boot/dts/imx6dl-wandboard-revb1.dts create mode 100644 arch/arm/boot/dts/imx6q-wandboard-revb1.dts create mode 100644 arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 644d4c2e58ec..90d5f494cf1d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -205,6 +205,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6dl-tx6u-801x.dtb \ imx6dl-tx6u-811x.dtb \ imx6dl-wandboard.dtb \ + imx6dl-wandboard-revb1.dtb \ imx6q-arm2.dtb \ imx6q-cm-fx6.dtb \ imx6q-cubox-i.dtb \ @@ -224,6 +225,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-sbc6x.dtb \ imx6q-udoo.dtb \ imx6q-wandboard.dtb \ + imx6q-wandboard-revb1.dtb \ imx6q-tx6q-1010.dtb \ imx6q-tx6q-1010-comtft.dtb \ imx6q-tx6q-1020.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts b/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts new file mode 100644 index 000000000000..f607d4f1d244 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts @@ -0,0 +1,22 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-wandboard-revb1.dtsi" + +/ { + model = "Wandboard i.MX6 Dual Lite Board"; + compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/imx6dl-wandboard.dts index e672891c1626..bbb616723097 100644 --- a/arch/arm/boot/dts/imx6dl-wandboard.dts +++ b/arch/arm/boot/dts/imx6dl-wandboard.dts @@ -10,7 +10,7 @@ */ /dts-v1/; #include "imx6dl.dtsi" -#include "imx6qdl-wandboard.dtsi" +#include "imx6qdl-wandboard-revc1.dtsi" / { model = "Wandboard i.MX6 Dual Lite Board"; diff --git a/arch/arm/boot/dts/imx6q-wandboard-revb1.dts b/arch/arm/boot/dts/imx6q-wandboard-revb1.dts new file mode 100644 index 000000000000..20bf3c282623 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-wandboard-revb1.dts @@ -0,0 +1,26 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-wandboard-revb1.dtsi" + +/ { + model = "Wandboard i.MX6 Quad Board"; + compatible = "wand,imx6q-wandboard", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x80000000>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-wandboard.dts b/arch/arm/boot/dts/imx6q-wandboard.dts index 36be17f207b1..4a8a6ee13e9f 100644 --- a/arch/arm/boot/dts/imx6q-wandboard.dts +++ b/arch/arm/boot/dts/imx6q-wandboard.dts @@ -10,7 +10,7 @@ */ /dts-v1/; #include "imx6q.dtsi" -#include "imx6qdl-wandboard.dtsi" +#include "imx6qdl-wandboard-revc1.dtsi" / { model = "Wandboard i.MX6 Quad Board"; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi new file mode 100644 index 000000000000..ef7fa62b9898 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include "imx6qdl-wandboard.dtsi" + +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-wandboard { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* GPIO_0_CLKO */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x0f0b0 /* WL_REF_ON */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x0f0b0 /* WL_RST_N */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */ + >; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi new file mode 100644 index 000000000000..8d893a78cdf0 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include "imx6qdl-wandboard.dtsi" + +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-wandboard { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* GPIO_0_CLKO */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x0f0b0 /* WIFI_ON (reset, active low) */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON (unused) */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE, input */ + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x0f0b0 /* GPIO5_IO31 (Wifi Power Enable) */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE (unused) */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x80000000 /* BT_ON */ + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x80000000 /* BT_WAKE */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000 /* BT_HOST_WAKE */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ + >; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index 13eae9e5bae8..5fb091675582 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -91,22 +91,8 @@ &iomuxc { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; imx6qdl-wandboard { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 /* WL_REF_ON */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* WL_RST_N */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 - >; - }; pinctrl_audmux: audmuxgrp { fsl,pins = < @@ -268,13 +254,6 @@ status = "okay"; }; -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - non-removable; - status = "okay"; -}; - &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; -- cgit v1.2.3 From e7779620d081481cb0a79535f9e8cae47194de7e Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 14 Jul 2014 09:18:46 +0200 Subject: ARM: dts: vf610: fix length of eshdc1 register property Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index 6cc314e7b8fb..6a6190ce2318 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -362,7 +362,7 @@ esdhc1: esdhc@400b2000 { compatible = "fsl,imx53-esdhc"; - reg = <0x400b2000 0x4000>; + reg = <0x400b2000 0x1000>; interrupts = <0 28 0x04>; clocks = <&clks VF610_CLK_IPG_BUS>, <&clks VF610_CLK_PLATFORM_BUS>, -- cgit v1.2.3 From cb9456b53898302b2e1a3eded4e22c7a306b8bd0 Mon Sep 17 00:00:00 2001 From: Iain Paton Date: Sun, 13 Jul 2014 16:56:35 +0100 Subject: ARM: dts: imx6: RIoTboard explicitly define pad settings Instead of relying on defaults or bootloader settings, explicitly define all pad settings. This resolves reported issues of no analogue audio output. Signed-off-by: Iain Paton Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-riotboard.dts | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 80c926894d1e..43cb3fd76be7 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -334,10 +334,10 @@ imx6-riotboard { pinctrl_audmux: audmuxgrp { fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x8000000 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x8000000 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x8000000 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x8000000 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ >; }; @@ -375,7 +375,7 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 @@ -388,9 +388,9 @@ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 /* AR8035 pin strapping: MODE#1: pull up */ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 /* AR8035 pin strapping: MODE#3: pull up */ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 /* GPIO16 -> AR8035 25MHz */ + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* AR8035 interrupt */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; }; @@ -425,8 +425,8 @@ pinctrl_led: ledgrp { fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* user led0 */ - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x80000000 /* user led1 */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */ + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */ >; }; @@ -492,8 +492,8 @@ pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x80000000 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 >; }; @@ -505,8 +505,8 @@ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* SD2 CD */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* SD2 WP */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */ >; }; @@ -518,8 +518,8 @@ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3 CD */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x80000000 /* SD3 WP */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */ >; }; @@ -531,7 +531,7 @@ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 /* SD4 RST (eMMC) */ + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */ >; }; }; -- cgit v1.2.3 From 18e8499b22f5ea21449f2ea8730e06982c24cfc0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 25 Jun 2014 20:48:32 +0200 Subject: ARM: dts: mx5: Split M53EVK into SoM and EVK parts This patch splits the M53EVK device tree file into a common SoM part and an EVK part. This is needed to make it easier for users of the SoM to put it into different, non-reference baseboard. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-m53.dtsi | 140 +++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx53-m53evk.dts | 112 ++--------------------------- 2 files changed, 144 insertions(+), 108 deletions(-) create mode 100644 arch/arm/boot/dts/imx53-m53.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/imx53-m53.dtsi new file mode 100644 index 000000000000..87a7fc709c2d --- /dev/null +++ b/arch/arm/boot/dts/imx53-m53.dtsi @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2014 Marek Vasut + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx53.dtsi" + +/ { + model = "DENX M53"; + compatible = "denx,imx53-m53", "fsl,imx53"; + + memory { + reg = <0x70000000 0x20000000>, + <0xb0000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p2v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + + reg_backlight: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "lcd-supply"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "okay"; + + stmpe610@41 { + compatible = "st,stmpe610"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41>; + id = <0>; + blocks = <0x5>; + interrupts = <6 0x0>; + interrupt-parent = <&gpio7>; + irq-trigger = <0x1>; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + reg = <0>; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <3>; + st,touch-det-delay = <3>; + st,settling = <4>; + st,fraction-z = <7>; + st,i-drive = <1>; + }; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc: rtc@68 { + compatible = "stm,m41t62"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-m53evk { + pinctrl_hog: hoggrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 + MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 + MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 + >; + }; + + pinctrl_nand: nandgrp { + fsl,pins = < + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 + MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 + MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 + MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 + MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 + MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 + MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 + MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 + MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 + >; + }; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts index 0689c1eaa9b1..d0e0f57eb432 100644 --- a/arch/arm/boot/dts/imx53-m53evk.dts +++ b/arch/arm/boot/dts/imx53-m53evk.dts @@ -10,17 +10,12 @@ */ /dts-v1/; -#include "imx53.dtsi" +#include "imx53-m53.dtsi" / { model = "DENX M53EVK"; compatible = "denx,imx53-m53evk", "fsl,imx53"; - memory { - reg = <0x70000000 0x20000000>, - <0xb0000000 0x20000000>; - }; - display1: display@di1 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "bgr666"; @@ -81,25 +76,6 @@ #address-cells = <1>; #size-cells = <0>; - reg_3p2v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; - - - reg_backlight: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "lcd-supply"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; - reg_usbh1_vbus: regulator@3 { compatible = "regulator-fixed"; reg = <3>; @@ -174,50 +150,6 @@ }; }; -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <400000>; - status = "okay"; - - stmpe610@41 { - compatible = "st,stmpe610"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x41>; - id = <0>; - blocks = <0x5>; - interrupts = <6 0x0>; - interrupt-parent = <&gpio7>; - irq-trigger = <0x1>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - reg = <0>; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <3>; - st,touch-det-delay = <3>; - st,settling = <4>; - st,fraction-z = <7>; - st,i-drive = <1>; - }; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - pagesize = <32>; - }; - - rtc: rtc@68 { - compatible = "stm,m41t62"; - reg = <0x68>; - }; -}; - &i2c3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; @@ -229,11 +161,8 @@ pinctrl-0 = <&pinctrl_hog>; imx53-m53evk { - pinctrl_hog: hoggrp { + pinctrl_usb: usbgrp { fsl,pins = < - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 - MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 MX53_PAD_GPIO_2__GPIO1_2 0x80000000 MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000 >; @@ -302,13 +231,6 @@ >; }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 - MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 - >; - }; - pinctrl_i2c3: i2c3grp { fsl,pins = < MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 @@ -353,26 +275,6 @@ >; }; - pinctrl_nand: nandgrp { - fsl,pins = < - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 - MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 - MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 - MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 - MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 - MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 - MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 - MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 - MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 - >; - }; - pinctrl_pwm1: pwm1grp { fsl,pins = < MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 @@ -408,14 +310,6 @@ remote-endpoint = <&display1_in>; }; -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - status = "okay"; -}; - &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; @@ -449,6 +343,8 @@ }; &usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb>; vbus-supply = <®_usbh1_vbus>; phy_type = "utmi"; status = "okay"; -- cgit v1.2.3 From e2047e33f2bd2713f6924c6dc2bf13e15784402e Mon Sep 17 00:00:00 2001 From: Robert Nelson Date: Tue, 8 Jul 2014 09:49:22 -0500 Subject: ARM: dts: add initial Rex Pro board support Add initial Rex Pro i.mx6q board support. Ethernet, UART, USB, I2C, SPI, HDMI, Audio, and SDHC cards are working. Currently no mainline u-boot, so boot with cat zImage imx6q-rex-pro.dtb > zImage.dtb, then using mkimage create uImage Signed-off-by: Robert Nelson Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6q-rex-pro.dts | 34 ++++ arch/arm/boot/dts/imx6qdl-rex.dtsi | 357 ++++++++++++++++++++++++++++++++++++ 3 files changed, 392 insertions(+) create mode 100644 arch/arm/boot/dts/imx6q-rex-pro.dts create mode 100644 arch/arm/boot/dts/imx6qdl-rex.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 90d5f494cf1d..06210421c578 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -219,6 +219,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-gw54xx.dtb \ imx6q-nitrogen6x.dtb \ imx6q-phytec-pbab01.dtb \ + imx6q-rex-pro.dtb \ imx6q-sabreauto.dtb \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ diff --git a/arch/arm/boot/dts/imx6q-rex-pro.dts b/arch/arm/boot/dts/imx6q-rex-pro.dts new file mode 100644 index 000000000000..3c2852b16f78 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-rex-pro.dts @@ -0,0 +1,34 @@ +/* + * Copyright 2014 FEDEVEL, Inc. + * + * Author: Robert Nelson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-rex.dtsi" + +/ { + model = "Rex Pro i.MX6 Quad Board"; + compatible = "rex,imx6q-rex-pro", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x80000000>; + }; +}; + +&ecspi3 { + flash: m25p80@0 { + compatible = "sst,sst25vf032b"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi new file mode 100644 index 000000000000..df7bcf86c156 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi @@ -0,0 +1,357 @@ +/* + * Copyright 2014 FEDEVEL, Inc. + * + * Author: Robert Nelson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbh1_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + led0: usr { + label = "usr"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + }; + + sound { + compatible = "fsl,imx6-rex-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6-rex-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&ecspi3 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@57 { + compatible = "at,24c02"; + reg = <0x57>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-rex { + pinctrl_hog: hoggrp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x000b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + /* user led */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + /* power enable, high active */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x10b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x10b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + /* CD */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + /* WP */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1f0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + /* CD */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + /* WP */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1f0b0 + >; + }; + }; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; -- cgit v1.2.3 From 417d65f65f783e21e8fc6698a748a88105cae1c6 Mon Sep 17 00:00:00 2001 From: Robert Nelson Date: Tue, 8 Jul 2014 09:49:23 -0500 Subject: ARM: dts: add initial Rex Basic board support Add initial Rex Pro i.mx6dl board support. Ethernet, UART, USB, I2C, SPI, HDMI, Audio, and SDHC cards are working. Currently no mainline u-boot, so boot with cat zImage imx6dl-rex-basic.dtb > zImage.dtb, then using mkimage create uImage Signed-off-by: Robert Nelson Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-rex-basic.dts | 30 ++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-rex-basic.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 06210421c578..c853ca22b06a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -197,6 +197,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6dl-hummingboard.dtb \ imx6dl-nitrogen6x.dtb \ imx6dl-phytec-pbab01.dtb \ + imx6dl-rex-basic.dtb \ imx6dl-riotboard.dtb \ imx6dl-sabreauto.dtb \ imx6dl-sabrelite.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-rex-basic.dts b/arch/arm/boot/dts/imx6dl-rex-basic.dts new file mode 100644 index 000000000000..b13845c2823b --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-rex-basic.dts @@ -0,0 +1,30 @@ +/* + * Copyright 2014 FEDEVEL, Inc. + * + * Author: Robert Nelson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-rex.dtsi" + +/ { + model = "Rex Basic i.MX6 Dual Lite Board"; + compatible = "rex,imx6dl-rex-basic", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x20000000>; + }; +}; + +&ecspi3 { + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; -- cgit v1.2.3 From 69603fbbc4798e8d02cb822edf5dce3f8a625427 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 16 Jul 2014 14:08:49 +0800 Subject: ARM: dts: vf610: add FlexCAN node Add FlexCAN node for the two FlexCAN IP instances in Vybrid. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index 6a6190ce2318..583dd363c9dc 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -14,6 +14,8 @@ / { aliases { + can0 = &can0; + can1 = &can1; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -103,6 +105,16 @@ <&clks VF610_CLK_DMAMUX1>; }; + can0: flexcan@40020000 { + compatible = "fsl,vf610-flexcan"; + reg = <0x40020000 0x4000>; + interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_FLEXCAN0>, + <&clks VF610_CLK_FLEXCAN0>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart0: serial@40027000 { compatible = "fsl,vf610-lpuart"; reg = <0x40027000 0x1000>; @@ -405,6 +417,17 @@ clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; + + can1: flexcan@400d4000 { + compatible = "fsl,vf610-flexcan"; + reg = <0x400d4000 0x4000>; + interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_FLEXCAN1>, + <&clks VF610_CLK_FLEXCAN1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; }; }; -- cgit v1.2.3 From 8fe9346b945d76ddb3f08c00e34d701174c62fa0 Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Fri, 4 Apr 2014 17:23:45 -0700 Subject: ARM: zynq: DT: Migrate UART to Cadence binding The Zynq UART is Cadence IP and the driver has been renamed accordingly. Migrate the DT to use the new binding for the UART driver. Signed-off-by: Soren Brinkmann Acked-by: Peter Crosthwaite Acked-by: Rob Herring Tested-by: Michal Simek Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-7000.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 760bbc463c5b..029cbac30454 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -105,19 +105,19 @@ }; uart0: serial@e0000000 { - compatible = "xlnx,xuartps"; + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; - clock-names = "ref_clk", "aper_clk"; + clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { - compatible = "xlnx,xuartps"; + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; - clock-names = "ref_clk", "aper_clk"; + clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; -- cgit v1.2.3 From 6f4b82a3568ea6dc721dc611754053846dca5781 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Sat, 19 Jul 2014 03:11:48 +0900 Subject: ARM: dts: clean up arm-pmu node for exynos4 This patch cleans a arm-pmu node up for exynos4. Only exynos4412 series boards have four pmu interrupts. Rest of exynos4 boards, except 4412, have only two pmu interrupts. Thus, we can define two interrupts in the exynos4.dtsi and extends the interrupts only exynos4412.dtsi. Cc: Chanwoo Choi Cc: Tomasz Figa Signed-off-by: Chanho Park Tested-by: Tushar Behera Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4.dtsi | 6 ++++++ arch/arm/boot/dts/exynos4210.dtsi | 6 ------ arch/arm/boot/dts/exynos4412.dtsi | 4 ++++ arch/arm/boot/dts/exynos4x12.dtsi | 6 ------ 4 files changed, 10 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index c91284441694..ec78bea04620 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -123,6 +123,12 @@ reg = <0x10440000 0x1000>; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&combiner>; + interrupts = <2 2>, <3 2>; + }; + sys_reg: syscon@10010000 { compatible = "samsung,exynos4-sysreg", "syscon"; reg = <0x10010000 0x400>; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index ee3001f38821..a4f28e8a6f87 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -93,12 +93,6 @@ #clock-cells = <1>; }; - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&combiner>; - interrupts = <2 2>, <3 2>; - }; - pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos4210-pinctrl"; reg = <0x11400000 0x1000>; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index c42a3e196cd5..d8bc059e172f 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -26,6 +26,10 @@ samsung,combiner-nr = <20>; }; + pmu { + interrupts = <2 2>, <3 2>, <18 2>, <19 2>; + }; + gic: interrupt-controller@10490000 { cpu-offset = <0x4000>; }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index c5a943df1cd7..95cdfb9e7d59 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -31,12 +31,6 @@ mshc0 = &mshc_0; }; - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&combiner>; - interrupts = <2 2>, <3 2>, <18 2>, <19 2>; - }; - sysram@02020000 { compatible = "mmio-sram"; reg = <0x02020000 0x40000>; -- cgit v1.2.3 From 8060098bbb564d27a287057a93d4fe3bfd266290 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Sat, 19 Jul 2014 04:09:15 +0900 Subject: ARM: dts: Add cros_ec to exynos5420-peach-pit and exynos5800-peach-pi This adds cros_ec to exynos5420-peach-pit and exynos5800-peach-pi, including: * The keyboard * The i2c tunnel * The tps65090 under the i2c tunnel * The battery under the i2c tunnel To add extra motivation, it should be noted that tps65090 is one of the things needed to get display-related FETs turned on for pit and pi. Signed-off-by: Doug Anderson Tested-by: Javier Martinez Canillas Tested-by: Tushar Behera Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420-peach-pit.dts | 145 +++++++++++++++++++++++++++++ arch/arm/boot/dts/exynos5800-peach-pi.dts | 145 +++++++++++++++++++++++++++++ 2 files changed, 290 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index c7b2bbae71a9..228a6b1e0aa1 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -25,6 +25,11 @@ "google,pit", "google,peach","samsung,exynos5420", "samsung,exynos5"; + aliases { + /* Assign 20 so we don't get confused w/ builtin ones */ + i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; + }; + backlight { compatible = "pwm-backlight"; pwms = <&pwm 0 1000000 0>; @@ -88,6 +93,13 @@ pinctrl-0 = <&usb301_vbus_en>; enable-active-high; }; + + vbat: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbat-supply"; + regulator-boot-on; + regulator-always-on; + }; }; &dp { @@ -244,6 +256,20 @@ samsung,pin-drv = <0>; }; + ec_irq: ec-irq { + samsung,pins = "gpx1-5"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + tps65090_irq: tps65090-irq { + samsung,pins = "gpx2-5"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + dp_hpd_gpio: dp_hpd_gpio { samsung,pins = "gpx2-6"; samsung,pin-function = <0>; @@ -260,6 +286,19 @@ }; &pinctrl_3 { + /* Drive SPI lines at x2 for better integrity */ + spi2-bus { + samsung,pin-drv = <2>; + }; + + /* Drive SPI chip select at x2 for better integrity */ + ec_spi_cs: ec-spi-cs { + samsung,pins = "gpb1-2"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + usb300_vbus_en: usb300-vbus-en { samsung,pins = "gph0-0"; samsung,pin-function = <1>; @@ -279,6 +318,111 @@ status = "okay"; }; +&spi_2 { + status = "okay"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + cs-gpios = <&gpb1 2 0>; + + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; + interrupt-parent = <&gpx1>; + interrupts = <5 0>; + pinctrl-names = "default"; + pinctrl-0 = <&ec_spi_cs &ec_irq>; + reg = <0>; + spi-max-frequency = <3125000>; + + controller-data { + samsung,spi-feedback-delay = <1>; + }; + + i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + google,remote-bus = <0>; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,poll-retry-count = <1>; + sbs,i2c-retry-count = <2>; + }; + + power-regulator@48 { + compatible = "ti,tps65090"; + reg = <0x48>; + + /* + * Config irq to disable internal pulls + * even though we run in polling mode. + */ + pinctrl-names = "default"; + pinctrl-0 = <&tps65090_irq>; + + vsys1-supply = <&vbat>; + vsys2-supply = <&vbat>; + vsys3-supply = <&vbat>; + infet1-supply = <&vbat>; + infet2-supply = <&vbat>; + infet3-supply = <&vbat>; + infet4-supply = <&vbat>; + infet5-supply = <&vbat>; + infet6-supply = <&vbat>; + infet7-supply = <&vbat>; + vsys-l1-supply = <&vbat>; + vsys-l2-supply = <&vbat>; + + regulators { + tps65090_dcdc1: dcdc1 { + ti,enable-ext-control; + }; + tps65090_dcdc2: dcdc2 { + ti,enable-ext-control; + }; + tps65090_dcdc3: dcdc3 { + ti,enable-ext-control; + }; + tps65090_fet1: fet1 { + regulator-name = "vcd_led"; + }; + tps65090_fet2: fet2 { + regulator-name = "video_mid"; + regulator-always-on; + }; + tps65090_fet3: fet3 { + regulator-name = "wwan_r"; + regulator-always-on; + }; + tps65090_fet4: fet4 { + regulator-name = "sdcard"; + regulator-always-on; + }; + tps65090_fet5: fet5 { + regulator-name = "camout"; + }; + tps65090_fet6: fet6 { + regulator-name = "lcd_vdd"; + }; + tps65090_fet7: fet7 { + regulator-name = "video_mid_1a"; + regulator-always-on; + }; + tps65090_ldo1: ldo1 { + }; + tps65090_ldo2: ldo2 { + }; + }; + + charger { + compatible = "ti,tps65090-charger"; + }; + }; + }; + }; +}; + &uart_3 { status = "okay"; }; @@ -300,3 +444,4 @@ timeout-sec = <32>; }; +#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 0bc97d94474c..f3ee48bbe05f 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -23,6 +23,11 @@ "google,pi", "google,peach", "samsung,exynos5800", "samsung,exynos5"; + aliases { + /* Assign 20 so we don't get confused w/ builtin ones */ + i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; + }; + backlight { compatible = "pwm-backlight"; pwms = <&pwm 0 1000000 0>; @@ -86,6 +91,13 @@ pinctrl-0 = <&usb301_vbus_en>; enable-active-high; }; + + vbat: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbat-supply"; + regulator-boot-on; + regulator-always-on; + }; }; &dp { @@ -242,6 +254,20 @@ samsung,pin-drv = <0>; }; + ec_irq: ec-irq { + samsung,pins = "gpx1-5"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + tps65090_irq: tps65090-irq { + samsung,pins = "gpx2-5"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + dp_hpd_gpio: dp_hpd_gpio { samsung,pins = "gpx2-6"; samsung,pin-function = <0>; @@ -258,6 +284,19 @@ }; &pinctrl_3 { + /* Drive SPI lines at x2 for better integrity */ + spi2-bus { + samsung,pin-drv = <2>; + }; + + /* Drive SPI chip select at x2 for better integrity */ + ec_spi_cs: ec-spi-cs { + samsung,pins = "gpb1-2"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + usb300_vbus_en: usb300-vbus-en { samsung,pins = "gph0-0"; samsung,pin-function = <1>; @@ -277,6 +316,111 @@ status = "okay"; }; +&spi_2 { + status = "okay"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + cs-gpios = <&gpb1 2 0>; + + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; + interrupt-parent = <&gpx1>; + interrupts = <5 0>; + pinctrl-names = "default"; + pinctrl-0 = <&ec_spi_cs &ec_irq>; + reg = <0>; + spi-max-frequency = <3125000>; + + controller-data { + samsung,spi-feedback-delay = <1>; + }; + + i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + google,remote-bus = <0>; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,poll-retry-count = <1>; + sbs,i2c-retry-count = <2>; + }; + + power-regulator@48 { + compatible = "ti,tps65090"; + reg = <0x48>; + + /* + * Config irq to disable internal pulls + * even though we run in polling mode. + */ + pinctrl-names = "default"; + pinctrl-0 = <&tps65090_irq>; + + vsys1-supply = <&vbat>; + vsys2-supply = <&vbat>; + vsys3-supply = <&vbat>; + infet1-supply = <&vbat>; + infet2-supply = <&vbat>; + infet3-supply = <&vbat>; + infet4-supply = <&vbat>; + infet5-supply = <&vbat>; + infet6-supply = <&vbat>; + infet7-supply = <&vbat>; + vsys-l1-supply = <&vbat>; + vsys-l2-supply = <&vbat>; + + regulators { + tps65090_dcdc1: dcdc1 { + ti,enable-ext-control; + }; + tps65090_dcdc2: dcdc2 { + ti,enable-ext-control; + }; + tps65090_dcdc3: dcdc3 { + ti,enable-ext-control; + }; + tps65090_fet1: fet1 { + regulator-name = "vcd_led"; + }; + tps65090_fet2: fet2 { + regulator-name = "video_mid"; + regulator-always-on; + }; + tps65090_fet3: fet3 { + regulator-name = "wwan_r"; + regulator-always-on; + }; + tps65090_fet4: fet4 { + regulator-name = "sdcard"; + regulator-always-on; + }; + tps65090_fet5: fet5 { + regulator-name = "camout"; + }; + tps65090_fet6: fet6 { + regulator-name = "lcd_vdd"; + }; + tps65090_fet7: fet7 { + regulator-name = "video_mid_1a"; + regulator-always-on; + }; + tps65090_ldo1: ldo1 { + }; + tps65090_ldo2: ldo2 { + }; + }; + + charger { + compatible = "ti,tps65090-charger"; + }; + }; + }; + }; +}; + &uart_3 { status = "okay"; }; @@ -298,3 +442,4 @@ timeout-sec = <32>; }; +#include "cros-ec-keyboard.dtsi" -- cgit v1.2.3 From ccaba4527156da1619a23bafcb944e8e029d0573 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Sat, 19 Jul 2014 04:10:44 +0900 Subject: ARM: dts: Add I2S dt node for exynos3250 This patch add I2S (Inter-IC Sound) dt node which supports 1-port stereo (1 channels) IIS-bus for audio interface with DMA-based operation. Signed-off-by: Tomasz Figa Signed-off-by: Inha Song Tested-by: Inha Song Signed-off-by: Chanwoo Choi Acked-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos3250.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 3e678fa335bf..77a06df6dc72 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -425,6 +425,19 @@ status = "disabled"; }; + i2s2: i2s@13970000 { + compatible = "samsung,s3c6410-i2s"; + reg = <0x13970000 0x100>; + interrupts = <0 126 0>; + clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0"; + dmas = <&pdma0 14>, <&pdma0 13>; + dma-names = "tx", "rx"; + pinctrl-0 = <&i2s2_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + pwm: pwm@139D0000 { compatible = "samsung,exynos4210-pwm"; reg = <0x139D0000 0x1000>; -- cgit v1.2.3 From ee39a3e308a418a3ff8a911335ae56fc321e3dfc Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 16 Jul 2014 01:15:43 +0800 Subject: ARM: dts: sun6i: Add pin muxing options for GMAC The A31 SoC has a GMAC gigabit ethernet controller supporting MII, GMII, RGMII modes. Add pin muxing options for these modes. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index baf8eff57610..47e143aa82fe 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -467,6 +467,48 @@ allwinner,drive = <2>; allwinner,pull = <0>; }; + + gmac_pins_mii_a: gmac_mii@0 { + allwinner,pins = "PA0", "PA1", "PA2", "PA3", + "PA8", "PA9", "PA11", + "PA12", "PA13", "PA14", "PA19", + "PA20", "PA21", "PA22", "PA23", + "PA24", "PA26", "PA27"; + allwinner,function = "gmac"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + gmac_pins_gmii_a: gmac_gmii@0 { + allwinner,pins = "PA0", "PA1", "PA2", "PA3", + "PA4", "PA5", "PA6", "PA7", + "PA8", "PA9", "PA10", "PA11", + "PA12", "PA13", "PA14", "PA15", + "PA16", "PA17", "PA18", "PA19", + "PA20", "PA21", "PA22", "PA23", + "PA24", "PA25", "PA26", "PA27"; + allwinner,function = "gmac"; + /* + * data lines in GMII mode run at 125MHz and + * might need a higher signal drive strength + */ + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + gmac_pins_rgmii_a: gmac_rgmii@0 { + allwinner,pins = "PA0", "PA1", "PA2", "PA3", + "PA9", "PA10", "PA11", + "PA12", "PA13", "PA14", "PA19", + "PA20", "PA25", "PA26", "PA27"; + allwinner,function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + allwinner,drive = <3>; + allwinner,pull = <0>; + }; }; ahb1_rst: reset@01c202c0 { -- cgit v1.2.3 From ed29861ae87953e0d559baaf9d225e8f8a8ff19a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 16 Jul 2014 01:15:44 +0800 Subject: ARM: dts: sun6i: Add GMAC clock node to the A31 dtsi The GMAC uses 1 of 2 sources for its transmit clock, depending on the PHY interface mode. Add both sources as dummy clocks, and as parents to the GMAC clock node. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 47e143aa82fe..b78a5aa4bccc 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -281,6 +281,34 @@ "usb_ohci0", "usb_ohci1", "usb_ohci2"; }; + + /* + * The following two are dummy clocks, placeholders used in the gmac_tx + * clock. The gmac driver will choose one parent depending on the PHY + * interface mode, using clk_set_rate auto-reparenting. + * The actual TX clock rate is not controlled by the gmac_tx clock. + */ + mii_phy_tx_clk: clk@1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "mii_phy_tx"; + }; + + gmac_int_tx_clk: clk@2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_int_tx"; + }; + + gmac_tx_clk: clk@01c200d0 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-gmac-clk"; + reg = <0x01c200d0 0x4>; + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; + clock-output-names = "gmac_tx"; + }; }; soc@01c00000 { -- cgit v1.2.3 From 3dca65f8a67c525cbddfb1fca149435ab4ce37b0 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 16 Jul 2014 01:15:45 +0800 Subject: ARM: dts: sun6i: Add A31 GMAC gigabit ethernet controller node The A31 has the same GMAC found on the A20 SoC, except it has an extra reset control. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index b78a5aa4bccc..578fde202cc1 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -691,6 +691,23 @@ status = "disabled"; }; + gmac: ethernet@01c30000 { + compatible = "allwinner,sun7i-a20-gmac"; + reg = <0x01c30000 0x1054>; + interrupts = <0 82 4>; + interrupt-names = "macirq"; + clocks = <&ahb1_gates 17>, <&gmac_tx_clk>; + clock-names = "stmmaceth", "allwinner_gmac_tx"; + resets = <&ahb1_rst 17>; + reset-names = "stmmaceth"; + snps,pbl = <2>; + snps,fixed-burst; + snps,force_sf_dma_mode; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + timer@01c60000 { compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; reg = <0x01c60000 0x1000>; -- cgit v1.2.3 From e5073fde6b3f6aafec867cfa9f19597f57349a5d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 16 Jul 2014 01:15:46 +0800 Subject: ARM: dts: sun6i: Add ethernet alias for GMAC Alias GMAC as ethernet0 so U-boot can fill in the MAC address. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 578fde202cc1..44b07e512c24 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -23,6 +23,7 @@ serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; + ethernet0 = &gmac; }; -- cgit v1.2.3 From c220aec2bb793bf5a1fb451fd3e4db87654c5ba5 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 16 Jul 2014 01:15:47 +0800 Subject: ARM: dts: sun6i: Add Merrii A31 Hummingbird support This adds support for the A31 Hummingbird: http://www.merrii.com/en/pla_d.asp?id=172 The Merrii A31 Hummingbird is a development board based on the Allwinner A31 SoC with multiple USB ports through a USB hub chip, a uSD slot, a 10/100/1000M ethernet port, an AP6210 WiFi/BT chip, TV-in, HDMI, VGA, audio in/out ports, and LCD/CSI headers. Signed-off-by: Maxime Ripard [wens@csie.org: enable usbphy, ehci0, ohci0 for on-board usb hub; add pcf8563 rtc node; add comments for i2c0 and mmc0 pull-ups; correct ethernet phy address to 0x01; drop uart2 (BT chip has no power) and uart3 (no device); use proper commit message] Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 119 ++++++++++++++++++++++++++++ 2 files changed, 120 insertions(+) create mode 100644 arch/arm/boot/dts/sun6i-a31-hummingbird.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c3ee9fba892b..8be3687120d2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -375,6 +375,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \ dtb-$(CONFIG_MACH_SUN6I) += \ sun6i-a31-app4-evb1.dtb \ sun6i-a31-colombus.dtb \ + sun6i-a31-hummingbird.dtb \ sun6i-a31-m9.dtb dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-cubieboard2.dtb \ diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts new file mode 100644 index 000000000000..f142065b3c1f --- /dev/null +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -0,0 +1,119 @@ +/* + * Copyright 2014 Maxime Ripard + * + * Maxime Ripard + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun6i-a31.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "Merrii A31 Hummingbird"; + compatible = "merrii,a31-hummingbird", "allwinner,sun6i-a31"; + + chosen { + bootargs = "earlyprintk console=ttyS0,115200"; + }; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 0 8 0>; /* PA8 */ + cd-inverted; + status = "okay"; + }; + + usbphy: phy@01c19400 { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; + }; + + ehci0: usb@01c1a000 { + status = "okay"; + }; + + ohci0: usb@01c1a400 { + status = "okay"; + }; + + pio: pinctrl@01c20800 { + mmc0_pins_a: mmc0@0 { + /* external pull-ups missing for some pins */ + allwinner,pull = <1>; + }; + + mmc0_cd_pin_hummingbird: mmc0_cd_pin@0 { + allwinner,pins = "PA8"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + + usb1_vbus_pin_a: usb1_vbus_pin@0 { + allwinner,pins = "PH24"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + /* pull-ups and devices require AXP221 DLDO3 */ + status = "failed"; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + + i2c2: i2c@01c2b400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + gmac: ethernet@01c30000 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + reg_usb1_vbus: usb1-vbus { + pinctrl-0 = <&usb1_vbus_pin_a>; + gpio = <&pio 7 24 0>; /* PH24 */ + status = "okay"; + }; +}; -- cgit v1.2.3 From 6c1062baf6f38b8f496989a47b7b4b1740c2f399 Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Mon, 21 Jul 2014 13:48:15 -0300 Subject: ARM: mvebu: Add ethernet aliases required by U-Boot The vendor bootloader provided for Armada 375 boards expect an alias for the ethernet nodes, which is used to fixup the MAC address. Signed-off-by: Marcin Wojtas Link: https://lkml.kernel.org/r/1405961296-5846-6-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-375.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index d4619ad6e35c..bfcbe5891f2c 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -25,6 +25,8 @@ gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; + ethernet0 = ð0; + ethernet1 = ð1; }; clocks { -- cgit v1.2.3 From 112dc53db1c27594e3b1504189c2004115fb1914 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Mon, 21 Jul 2014 13:48:16 -0300 Subject: ARM: mvebu: Add missing MDIO clock in Armada 375 In Armada 375 SoCs, the MDIO is handled by a separate orion-mdio driver, despite the register is contained within the "LMS" block of the network controller. Therefore we need to add the clock to the MDIO devicetree to prevent the controller from being accesed with its clock gated. This is needed, for instance, to be able to load the MDIO driver before the network driver. Signed-off-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1405961296-5846-7-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-375.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index bfcbe5891f2c..c1e49e7bf0fa 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -158,6 +158,7 @@ #size-cells = <0>; compatible = "marvell,orion-mdio"; reg = <0xc0054 0x4>; + clocks = <&gateclk 19>; }; /* Network controller */ -- cgit v1.2.3 From 215556046da0975acae8741b2f27413008b23bd4 Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Thu, 5 Jun 2014 09:05:23 -0700 Subject: ARM: zynq: DT: Add XADC node Add node for the Xilinx A/D Converter. Cc: Lars-Peter Clausen Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-7000.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 029cbac30454..39365d8a864c 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -65,6 +65,14 @@ interrupt-parent = <&intc>; ranges; + adc@f8007100 { + compatible = "xlnx,zynq-xadc-1.00.a"; + reg = <0xf8007100 0x20>; + interrupts = <0 7 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 12>; + }; + i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; -- cgit v1.2.3 From e0a5c552caf7a4865f3d5aa077003ef2d35217db Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Thu, 10 Jul 2014 11:53:38 -0700 Subject: ARM: zynq: DT: Add GPIO node Add node describing Zynq's GPIO controller. Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-7000.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 39365d8a864c..366ca6434f54 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -71,6 +71,16 @@ interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; + }; + + gpio0: gpio@e000a000 { + compatible = "xlnx,zynq-gpio-1.0"; + #gpio-cells = <2>; + clocks = <&clkc 42>; + gpio-controller; + interrupt-parent = <&intc>; + interrupts = <0 20 4>; + reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { -- cgit v1.2.3 From 087b04701111e07f7abb799801ceed256f49cf6e Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 24 Jul 2014 15:45:00 +0100 Subject: ARM: dts: dove: add DT LCD controllers Add the DT fragment for the Marvell Dove LCD controllers. Signed-off-by: Russell King Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/E1XAKGS-0004WE-8h@rmk-PC.arm.linux.org.uk Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 3b891dd20993..a5441d5482a6 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -630,6 +630,20 @@ reg = <0xe8400 0x0c>; ngpios = <8>; }; + + lcd1: lcd-controller@810000 { + compatible = "marvell,dove-lcd"; + reg = <0x810000 0x1000>; + interrupts = <46>; + status = "disabled"; + }; + + lcd0: lcd-controller@820000 { + compatible = "marvell,dove-lcd"; + reg = <0x820000 0x1000>; + interrupts = <47>; + status = "disabled"; + }; }; }; }; -- cgit v1.2.3 From 6726e3edf88337e30d3cbeaecce75919b4bf8f92 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Fri, 25 Jul 2014 01:00:12 +0200 Subject: ARM: dts: zynq: Add Parallella device tree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows to boot the Adapteva Parallella board to serial console. Cc: Andreas Olofsson Signed-off-by: Andreas Färber Signed-off-by: Michal Simek --- arch/arm/boot/dts/Makefile | 4 ++- arch/arm/boot/dts/zynq-parallella.dts | 64 +++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/zynq-parallella.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index adb5ed9e269e..976720f379e4 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -419,7 +419,9 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ wm8650-mid.dtb \ wm8750-apc8750.dtb \ wm8850-w70v2.dtb -dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ +dtb-$(CONFIG_ARCH_ZYNQ) += \ + zynq-parallella.dtb \ + zynq-zc702.dtb \ zynq-zc706.dtb \ zynq-zed.dtb dtb-$(CONFIG_MACH_ARMADA_370) += \ diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts new file mode 100644 index 000000000000..41afd9da6876 --- /dev/null +++ b/arch/arm/boot/dts/zynq-parallella.dts @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2014 SUSE LINUX Products GmbH + * + * Derived from zynq-zed.dts: + * + * Copyright (C) 2011 Xilinx + * Copyright (C) 2012 National Instruments Corp. + * Copyright (C) 2013 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Adapteva Parallella Board"; + compatible = "adapteva,parallella", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; + + chosen { + bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait"; + linux,stdout-path = "/amba/serial@e0001000"; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet_phy: ethernet-phy@0 { + /* Marvell 88E1318 */ + compatible = "ethernet-phy-id0141.0e90", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + marvell,reg-init = <0x3 0x10 0xff00 0x1e>, + <0x3 0x11 0xfff0 0xa>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; -- cgit v1.2.3 From fbb4add88c7d1240c75129c1442ec8dbed3182ae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Fri, 25 Jul 2014 01:00:15 +0200 Subject: ARM: dts: zynq: Add DMAC for Parallella MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber Acked-by: Soren Brinkmann Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-7000.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/zynq-parallella.dts | 4 ++++ 2 files changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 366ca6434f54..cf0f3e4057cf 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -204,6 +204,22 @@ }; }; + dmac_s: dmac@f8003000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xf8003000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 13 4>, + <0 14 4>, <0 15 4>, + <0 16 4>, <0 17 4>, + <0 40 4>, <0 41 4>, + <0 42 4>, <0 43 4>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <4>; + clocks = <&clkc 27>; + clock-names = "apb_pclk"; + }; + devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; reg = <0xf8007000 0x100>; diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts index 41afd9da6876..1595138ec499 100644 --- a/arch/arm/boot/dts/zynq-parallella.dts +++ b/arch/arm/boot/dts/zynq-parallella.dts @@ -34,6 +34,10 @@ }; }; +&dmac_s { + status = "okay"; +}; + &gem0 { status = "okay"; phy-mode = "rgmii-id"; -- cgit v1.2.3 From aa9c4f740d821b623eb5f313538ac2912ebcb2d0 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 16 Jul 2014 17:08:14 +0200 Subject: ARM: rockchip: clarify usability of DEBUG_RK3X_UART debug_ll options The debug uart settings from the DEBUG_RK3X_UART options are usable on all Rockchip SoCs from the rk30xx and rk31xx series but not on the new rk3288 SoCs. Thus clarify their use to prevent confusion. Signed-off-by: Heiko Stuebner Reviewed-by: Doug Anderson Acked-by: Arnd Bergmann --- arch/arm/Kconfig.debug | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 8f90595069a1..a8dbf5e51d11 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -582,7 +582,7 @@ choice on Rockchip based platforms. config DEBUG_RK3X_UART0 - bool "Kernel low-level debugging messages via Rockchip RK3X UART0" + bool "Kernel low-level debugging messages via Rockchip RK30/RK31 UART0" depends on ARCH_ROCKCHIP select DEBUG_UART_8250 help @@ -590,7 +590,7 @@ choice on Rockchip based platforms. config DEBUG_RK3X_UART1 - bool "Kernel low-level debugging messages via Rockchip RK3X UART1" + bool "Kernel low-level debugging messages via Rockchip RK30/RK31 UART1" depends on ARCH_ROCKCHIP select DEBUG_UART_8250 help @@ -598,7 +598,7 @@ choice on Rockchip based platforms. config DEBUG_RK3X_UART2 - bool "Kernel low-level debugging messages via Rockchip RK3X UART2" + bool "Kernel low-level debugging messages via Rockchip RK30/RK31 UART2" depends on ARCH_ROCKCHIP select DEBUG_UART_8250 help @@ -606,7 +606,7 @@ choice on Rockchip based platforms. config DEBUG_RK3X_UART3 - bool "Kernel low-level debugging messages via Rockchip RK3X UART3" + bool "Kernel low-level debugging messages via Rockchip RK30/RK31 UART3" depends on ARCH_ROCKCHIP select DEBUG_UART_8250 help -- cgit v1.2.3 From efd02ee92b3efae6f4f1056640d407ac45c4051c Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 28 Jun 2014 13:31:17 +0200 Subject: ARM: rockchip: add debug uart used by rk3288 The uarts on rk3288 are still compatible with the dw_8250, but located at a different position and need DEBUG_UART_8250_WORD enabled. Signed-off-by: Heiko Stuebner Reviewed-by: Doug Anderson Tested-by: Doug Anderson Tested-by: Will Deacon Acked-by: Arnd Bergmann --- arch/arm/Kconfig.debug | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index a8dbf5e51d11..8dcc00d44dab 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -613,6 +613,14 @@ choice Say Y here if you want kernel low-level debugging support on Rockchip based platforms. + config DEBUG_RK32_UART2 + bool "Kernel low-level debugging messages via Rockchip RK32 UART2" + depends on ARCH_ROCKCHIP + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on Rockchip RK32xx based platforms. + config DEBUG_S3C_UART0 depends on PLAT_SAMSUNG select DEBUG_EXYNOS_UART if ARCH_EXYNOS @@ -1096,6 +1104,7 @@ config DEBUG_UART_PHYS default 0xf991e000 if DEBUG_QCOM_UARTDM default 0xfcb00000 if DEBUG_HI3620_UART default 0xfe800000 if ARCH_IOP32X + default 0xff690000 if DEBUG_RK32_UART2 default 0xffc02000 if DEBUG_SOCFPGA_UART default 0xffd82340 if ARCH_IOP13XX default 0xfff36000 if DEBUG_HIGHBANK_UART @@ -1152,6 +1161,7 @@ config DEBUG_UART_VIRT default 0xfec02000 if DEBUG_SOCFPGA_UART default 0xfec12000 if DEBUG_MVEBU_UART || DEBUG_MVEBU_UART_ALTERNATE default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0 + default 0xfec90000 if DEBUG_RK32_UART2 default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1 default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 default 0xfed12000 if ARCH_KIRKWOOD @@ -1186,7 +1196,7 @@ config DEBUG_UART_8250_WORD ARCH_KEYSTONE || \ DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \ DEBUG_DAVINCI_DA8XX_UART2 || \ - DEBUG_BCM_KONA_UART + DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 config DEBUG_UART_8250_FLOW_CONTROL bool "Enable flow control for 8250 UART" -- cgit v1.2.3 From 7b5da4c3b9c6ef8d7cd7635b839adfb836edb08a Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 26 May 2014 00:13:51 +0200 Subject: ARM: Kconfig: set default gpio number for rockchip SoCs The new rk3288 needs a bigger gpio space, as it has 9 gpio banks. Signed-off-by: Heiko Stuebner Reviewed-by: Doug Anderson Tested-by: Doug Anderson Tested-by: Will Deacon Acked-by: Arnd Bergmann --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 245058b3b0ef..b3ba139f599a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1558,6 +1558,7 @@ config ARCH_NR_GPIO default 416 if ARCH_SUNXI default 392 if ARCH_U8500 default 352 if ARCH_VT8500 + default 288 if ARCH_ROCKCHIP default 264 if MACH_H4700 default 0 help -- cgit v1.2.3 From 7a1917abdd428a6c9f6bf261306d069320e502b5 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 28 Jun 2014 20:13:42 +0200 Subject: ARM: rockchip: enable support for RK3288 SoCs Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible. Signed-off-by: Heiko Stuebner Tested-by: Will Deacon Reviewed-by: Doug Anderson Tested-by: Doug Anderson Acked-by: Arnd Bergmann --- arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/rockchip.c | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index e4564c259ed1..d1686696ca41 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -6,6 +6,7 @@ config ARCH_ROCKCHIP select ARCH_REQUIRE_GPIOLIB select ARM_GIC select CACHE_L2X0 + select HAVE_ARM_ARCH_TIMER select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select DW_APB_TIMER_OF diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index 968cc348e624..8ab9e0e7ff04 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -29,6 +29,7 @@ static const char * const rockchip_board_dt_compat[] = { "rockchip,rk3066a", "rockchip,rk3066b", "rockchip,rk3188", + "rockchip,rk3288", NULL, }; -- cgit v1.2.3 From 2ab557b72d46cf5ee746b041e86e41e550a4b10c Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 15 Jul 2014 20:16:19 +0200 Subject: ARM: dts: rockchip: add core rk3288 dtsi Node definitions shared by all rk3288 based boards. Signed-off-by: Heiko Stuebner Tested-by: Will Deacon Tested-by: Doug Anderson Reviewed-by: Doug Anderson Acked-by: Arnd Bergmann --- arch/arm/boot/dts/rk3288.dtsi | 575 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 575 insertions(+) create mode 100644 arch/arm/boot/dts/rk3288.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi new file mode 100644 index 000000000000..3ef89512c942 --- /dev/null +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -0,0 +1,575 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include "skeleton.dtsi" + +/ { + compatible = "rockchip,rk3288"; + + interrupt-parent = <&gic>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a12"; + reg = <0x500>; + }; + cpu@501 { + device_type = "cpu"; + compatible = "arm,cortex-a12"; + reg = <0x501>; + }; + cpu@502 { + device_type = "cpu"; + compatible = "arm,cortex-a12"; + reg = <0x502>; + }; + cpu@503 { + device_type = "cpu"; + compatible = "arm,cortex-a12"; + reg = <0x503>; + }; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + }; + + i2c1: i2c@ff140000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff140000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; + + i2c3: i2c@ff150000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff150000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + status = "disabled"; + }; + + i2c4: i2c@ff160000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff160000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; + status = "disabled"; + }; + + i2c5: i2c@ff170000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff170000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C5>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_xfer>; + status = "disabled"; + }; + + uart0: serial@ff180000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; + reg = <0xff180000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "disabled"; + }; + + uart1: serial@ff190000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; + reg = <0xff190000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "disabled"; + }; + + uart2: serial@ff690000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; + reg = <0xff690000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + status = "disabled"; + }; + + uart3: serial@ff1b0000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; + reg = <0xff1b0000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; + status = "disabled"; + }; + + uart4: serial@ff1c0000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; + reg = <0xff1c0000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + status = "disabled"; + }; + + i2c0: i2c@ff650000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff650000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + status = "disabled"; + }; + + i2c2: i2c@ff660000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff660000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + status = "disabled"; + }; + + pmu: power-management@ff730000 { + compatible = "rockchip,rk3288-pmu", "syscon"; + reg = <0xff730000 0x100>; + }; + + sgrf: syscon@ff740000 { + compatible = "rockchip,rk3288-sgrf", "syscon"; + reg = <0xff740000 0x1000>; + }; + + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3288-cru"; + reg = <0xff760000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + grf: syscon@ff770000 { + compatible = "rockchip,rk3288-grf", "syscon"; + reg = <0xff770000 0x1000>; + }; + + wdt: watchdog@ff800000 { + compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; + reg = <0xff800000 0x100>; + interrupts = ; + status = "disabled"; + }; + + gic: interrupt-controller@ffc01000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0xffc01000 0x1000>, + <0xffc02000 0x1000>, + <0xffc04000 0x2000>, + <0xffc06000 0x2000>; + interrupts = ; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3288-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@ff750000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff750000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@ff780000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff780000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@ff790000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff790000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@ff7a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7a0000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio4@ff7b0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7b0000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio5@ff7c0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7c0000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO5>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio6@ff7d0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7d0000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO6>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio7@ff7e0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7e0000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO7>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio8: gpio8@ff7f0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7f0000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO8>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, + <0 16 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, + <8 5 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, + <6 10 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, + <2 17 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, + <7 18 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c5 { + i2c5_xfer: i2c5-xfer { + rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, + <7 20 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_cd: sdmcc-cd { + rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, + <6 17 RK_FUNC_1 &pcfg_pull_up>, + <6 18 RK_FUNC_1 &pcfg_pull_up>, + <6 19 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; + }; + + emmc_pwr: emmc-pwr { + rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; + }; + + emmc_bus1: emmc-bus1 { + rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; + }; + + emmc_bus4: emmc-bus4 { + rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, + <3 1 RK_FUNC_2 &pcfg_pull_up>, + <3 2 RK_FUNC_2 &pcfg_pull_up>, + <3 3 RK_FUNC_2 &pcfg_pull_up>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, + <3 1 RK_FUNC_2 &pcfg_pull_up>, + <3 2 RK_FUNC_2 &pcfg_pull_up>, + <3 3 RK_FUNC_2 &pcfg_pull_up>, + <3 4 RK_FUNC_2 &pcfg_pull_up>, + <3 5 RK_FUNC_2 &pcfg_pull_up>, + <3 6 RK_FUNC_2 &pcfg_pull_up>, + <3 7 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, + <4 17 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, + <5 9 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, + <7 23 RK_FUNC_1 &pcfg_pull_none>; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, + <7 8 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart4 { + uart4_xfer: uart4-xfer { + rockchip,pins = <5 12 3 &pcfg_pull_up>, + <5 13 3 &pcfg_pull_none>; + }; + + uart4_cts: uart4-cts { + rockchip,pins = <5 14 3 &pcfg_pull_none>; + }; + + uart4_rts: uart4-rts { + rockchip,pins = <5 15 3 &pcfg_pull_none>; + }; + }; + }; +}; -- cgit v1.2.3 From 6ce0562a75a9b283afe089cccdf1c111b5f461f1 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 15 Jul 2014 20:09:44 +0200 Subject: ARM: dts: add rk3288 evaluation board There exist 2 variants using either the act8846 or rk808 as pmic, while the rest of the board stays the same. Signed-off-by: Heiko Stuebner Tested-by: Will Deacon Reviewed-by: Doug Anderson Tested-by: Doug Anderson Acked-by: Arnd Bergmann --- arch/arm/boot/dts/rk3288-evb-act8846.dts | 134 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3288-evb-rk808.dts | 18 +++++ arch/arm/boot/dts/rk3288-evb.dtsi | 74 +++++++++++++++++ 3 files changed, 226 insertions(+) create mode 100644 arch/arm/boot/dts/rk3288-evb-act8846.dts create mode 100644 arch/arm/boot/dts/rk3288-evb-rk808.dts create mode 100644 arch/arm/boot/dts/rk3288-evb.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts new file mode 100644 index 000000000000..7d59ff4de408 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts @@ -0,0 +1,134 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include "rk3288-evb.dtsi" + +/ { + compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288"; +}; + +&i2c0 { + hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + + #clock-cells = <0>; + clock-output-names = "xin32k"; + }; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + status = "okay"; + + regulators { + vcc_ddr: REG1 { + regulator-name = "VCC_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_io: REG2 { + regulator-name = "VCC_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_log: REG3 { + regulator-name = "VDD_LOG"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_20: REG4 { + regulator-name = "VCC_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vccio_sd: REG5 { + regulator-name = "VCCIO_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd10_lcd: REG6 { + regulator-name = "VDD10_LCD"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcca_codec: REG7 { + regulator-name = "VCCA_CODEC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcca_tp: REG8 { + regulator-name = "VCCA_TP"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vccio_pmu: REG9 { + regulator-name = "VCCIO_PMU"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_10: REG10 { + regulator-name = "VDD_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "VCC_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc18_lcd: REG12 { + regulator-name = "VCC18_LCD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = ; + }; + }; +}; diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts new file mode 100644 index 000000000000..9a88b6c66396 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts @@ -0,0 +1,18 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include "rk3288-evb.dtsi" + +/ { + compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; +}; diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi new file mode 100644 index 000000000000..749e20db3b37 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -0,0 +1,74 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "rk3288.dtsi" + +/ { + memory { + reg = <0x0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + button@0 { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&pinctrl { + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; -- cgit v1.2.3 From b1db66b818a4cb1a654ae51a5ca32a09d1ccd825 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Thu, 24 Jul 2014 15:17:50 -0700 Subject: ARM: dts: Build dtbs for Rockchip boards This allows the "make dtbs" target to work. Signed-off-by: Doug Anderson Signed-off-by: Heiko Stuebner Acked-by: Arnd Bergmann --- arch/arm/boot/dts/Makefile | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index adb5ed9e269e..637decaa23f6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -318,6 +318,11 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8084-mtp.dtb \ qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += \ + rk3066a-bqcurie2.dtb \ + rk3188-radxarock.dtb \ + rk3288-evb-act8846.dtb \ + rk3288-evb-rk808.dtb dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ s3c6410-smdk6410.dtb -- cgit v1.2.3 From b13d2a7b43654c7f52aba9dc04f93cf7055ebc8b Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 15 Apr 2014 01:16:44 +0200 Subject: ARM: dts: rockchip: add cru nodes and update device clocks to use it This adds a node for the clock and reset unit on rk3188 and rk3066 SoCs and also updates the device nodes retrieve their clocks from there, instead of the previous gate clock nodes. Signed-off-by: Heiko Stuebner Acked-By: Max Schwarz Tested-By: Max Schwarz --- arch/arm/boot/dts/rk3066a.dtsi | 28 +++++++++++++++++++--------- arch/arm/boot/dts/rk3188.dtsi | 18 ++++++++++++++---- arch/arm/boot/dts/rk3xxx.dtsi | 16 ++++++++-------- 3 files changed, 41 insertions(+), 21 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 4387cfd420ba..15c81d2c2d52 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -15,6 +15,7 @@ #include #include +#include #include "rk3xxx.dtsi" #include "rk3066a-clocks.dtsi" @@ -45,7 +46,7 @@ compatible = "snps,dw-apb-timer-osc"; reg = <0x20038000 0x100>; interrupts = ; - clocks = <&clk_gates1 0>, <&clk_gates7 7>; + clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; clock-names = "timer", "pclk"; }; @@ -53,7 +54,7 @@ compatible = "snps,dw-apb-timer-osc"; reg = <0x2003a000 0x100>; interrupts = ; - clocks = <&clk_gates1 1>, <&clk_gates7 8>; + clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; clock-names = "timer", "pclk"; }; @@ -61,7 +62,7 @@ compatible = "snps,dw-apb-timer-osc"; reg = <0x2000e000 0x100>; interrupts = ; - clocks = <&clk_gates1 2>, <&clk_gates7 9>; + clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; clock-names = "timer", "pclk"; }; @@ -78,6 +79,15 @@ }; }; + cru: clock-controller@20000000 { + compatible = "rockchip,rk3066a-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + pinctrl@20008000 { compatible = "rockchip,rk3066a-pinctrl"; rockchip,grf = <&grf>; @@ -89,7 +99,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20034000 0x100>; interrupts = ; - clocks = <&clk_gates8 9>; + clocks = <&cru PCLK_GPIO0>; gpio-controller; #gpio-cells = <2>; @@ -102,7 +112,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003c000 0x100>; interrupts = ; - clocks = <&clk_gates8 10>; + clocks = <&cru PCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; @@ -115,7 +125,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003e000 0x100>; interrupts = ; - clocks = <&clk_gates8 11>; + clocks = <&cru PCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; @@ -128,7 +138,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20080000 0x100>; interrupts = ; - clocks = <&clk_gates8 12>; + clocks = <&cru PCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; @@ -141,7 +151,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20084000 0x100>; interrupts = ; - clocks = <&clk_gates8 13>; + clocks = <&cru PCLK_GPIO4>; gpio-controller; #gpio-cells = <2>; @@ -154,7 +164,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2000a000 0x100>; interrupts = ; - clocks = <&clk_gates8 15>; + clocks = <&cru PCLK_GPIO6>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 238c996d4a7f..bf0741a89b7c 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -15,6 +15,7 @@ #include #include +#include #include "rk3xxx.dtsi" #include "rk3188-clocks.dtsi" @@ -74,6 +75,15 @@ }; }; + cru: clock-controller@20000000 { + compatible = "rockchip,rk3188-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + pinctrl@20008000 { compatible = "rockchip,rk3188-pinctrl"; rockchip,grf = <&grf>; @@ -87,7 +97,7 @@ compatible = "rockchip,rk3188-gpio-bank0"; reg = <0x2000a000 0x100>; interrupts = ; - clocks = <&clk_gates8 9>; + clocks = <&cru PCLK_GPIO0>; gpio-controller; #gpio-cells = <2>; @@ -100,7 +110,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003c000 0x100>; interrupts = ; - clocks = <&clk_gates8 10>; + clocks = <&cru PCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; @@ -113,7 +123,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003e000 0x100>; interrupts = ; - clocks = <&clk_gates8 11>; + clocks = <&cru PCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; @@ -126,7 +136,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20080000 0x100>; interrupts = ; - clocks = <&clk_gates8 12>; + clocks = <&cru PCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 2adf1cc9e85d..b47d5fe81187 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -60,14 +60,14 @@ compatible = "arm,cortex-a9-global-timer"; reg = <0x1013c200 0x20>; interrupts = ; - clocks = <&dummy150m>; + clocks = <&cru CORE_PERI>; }; local-timer@1013c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x1013c600 0x20>; interrupts = ; - clocks = <&dummy150m>; + clocks = <&cru CORE_PERI>; }; uart0: serial@10124000 { @@ -76,7 +76,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&clk_gates1 8>; + clocks = <&cru SCLK_UART0>; status = "disabled"; }; @@ -86,7 +86,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&clk_gates1 10>; + clocks = <&cru SCLK_UART1>; status = "disabled"; }; @@ -96,7 +96,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&clk_gates1 12>; + clocks = <&cru SCLK_UART2>; status = "disabled"; }; @@ -106,7 +106,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&clk_gates1 14>; + clocks = <&cru SCLK_UART3>; status = "disabled"; }; @@ -117,7 +117,7 @@ #address-cells = <1>; #size-cells = <0>; - clocks = <&clk_gates5 10>, <&clk_gates2 11>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; clock-names = "biu", "ciu"; status = "disabled"; @@ -130,7 +130,7 @@ #address-cells = <1>; #size-cells = <0>; - clocks = <&clk_gates5 11>, <&clk_gates2 13>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; clock-names = "biu", "ciu"; status = "disabled"; -- cgit v1.2.3 From 560106c1ca063e7cbbb527c0df2c6929cb36c6ae Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 15 Apr 2014 19:44:59 +0200 Subject: ARM: dts: rockchip: move oscillator input clock into main dtsi The clock definitions get a lot shorter due to the soc clocks being handled by rk3188-cru and only the input clock remains. These can now simply live in the main rk3xxx.dtsi without affecting readability. At the same time, rename the node to oscillator, adding a clock-output-names property to match how the rk3288 handles this. Signed-off-by: Heiko Stuebner Acked-By: Max Schwarz Tested-By: Max Schwarz --- arch/arm/boot/dts/rk3066a-clocks.dtsi | 6 ------ arch/arm/boot/dts/rk3188-clocks.dtsi | 6 ------ arch/arm/boot/dts/rk3xxx.dtsi | 7 +++++++ 3 files changed, 7 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3066a-clocks.dtsi b/arch/arm/boot/dts/rk3066a-clocks.dtsi index 6e307fc4c451..0d4d667b82dc 100644 --- a/arch/arm/boot/dts/rk3066a-clocks.dtsi +++ b/arch/arm/boot/dts/rk3066a-clocks.dtsi @@ -31,12 +31,6 @@ #clock-cells = <0>; }; - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - dummy48m: dummy48m { compatible = "fixed-clock"; clock-frequency = <48000000>; diff --git a/arch/arm/boot/dts/rk3188-clocks.dtsi b/arch/arm/boot/dts/rk3188-clocks.dtsi index b1b92dc245ce..6bc0373a2fb8 100644 --- a/arch/arm/boot/dts/rk3188-clocks.dtsi +++ b/arch/arm/boot/dts/rk3188-clocks.dtsi @@ -31,12 +31,6 @@ #clock-cells = <0>; }; - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - dummy48m: dummy48m { compatible = "fixed-clock"; clock-frequency = <48000000>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index b47d5fe81187..6d163644c7cd 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -20,6 +20,13 @@ / { interrupt-parent = <&gic>; + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + clock-output-names = "xin24m"; + }; + soc { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From d356d96f8558d69d4b0d4c72d95002e9b6533531 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 21 Jun 2014 17:03:40 +0200 Subject: arm: dts: rockchip: remove obsolete clock gate definitions The clock and reset unit is now provided by the rk3188-cru clock driver and thus the old style definitions of the gate clocks can go away. Signed-off-by: Heiko Stuebner Acked-By: Max Schwarz Tested-By: Max Schwarz --- arch/arm/boot/dts/rk3066a-clocks.dtsi | 293 ---------------------------------- arch/arm/boot/dts/rk3066a.dtsi | 1 - arch/arm/boot/dts/rk3188-clocks.dtsi | 283 -------------------------------- arch/arm/boot/dts/rk3188.dtsi | 1 - 4 files changed, 578 deletions(-) delete mode 100644 arch/arm/boot/dts/rk3066a-clocks.dtsi delete mode 100644 arch/arm/boot/dts/rk3188-clocks.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3066a-clocks.dtsi b/arch/arm/boot/dts/rk3066a-clocks.dtsi deleted file mode 100644 index 0d4d667b82dc..000000000000 --- a/arch/arm/boot/dts/rk3066a-clocks.dtsi +++ /dev/null @@ -1,293 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { - compatible = "fixed-clock"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - dummy48m: dummy48m { - compatible = "fixed-clock"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - - dummy150m: dummy150m { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - }; - - clk_gates0: gate-clk@200000d0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d0 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_core_periph", "gate_cpu_gpll", - "gate_ddrphy", "gate_aclk_cpu", - "gate_hclk_cpu", "gate_pclk_cpu", - "gate_atclk_cpu", "gate_i2s0", - "gate_i2s0_frac", "gate_i2s1", - "gate_i2s1_frac", "gate_i2s2", - "gate_i2s2_frac", "gate_spdif", - "gate_spdif_frac", "gate_testclk"; - - #clock-cells = <1>; - }; - - clk_gates1: gate-clk@200000d4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d4 0x4>; - clocks = <&xin24m>, <&xin24m>, - <&xin24m>, <&dummy>, - <&dummy>, <&xin24m>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>; - - clock-output-names = - "gate_timer0", "gate_timer1", - "gate_timer2", "gate_jtag", - "gate_aclk_lcdc1_src", "gate_otgphy0", - "gate_otgphy1", "gate_ddr_gpll", - "gate_uart0", "gate_frac_uart0", - "gate_uart1", "gate_frac_uart1", - "gate_uart2", "gate_frac_uart2", - "gate_uart3", "gate_frac_uart3"; - - #clock-cells = <1>; - }; - - clk_gates2: gate-clk@200000d8 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d8 0x4>; - clocks = <&clk_gates2 1>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&clk_gates2 3>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy48m>, - <&dummy>, <&dummy48m>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_periph_src", "gate_aclk_periph", - "gate_hclk_periph", "gate_pclk_periph", - "gate_smc", "gate_mac", - "gate_hsadc", "gate_hsadc_frac", - "gate_saradc", "gate_spi0", - "gate_spi1", "gate_mmc0", - "gate_mac_lbtest", "gate_mmc1", - "gate_emmc", "gate_tsadc"; - - #clock-cells = <1>; - }; - - clk_gates3: gate-clk@200000dc { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000dc 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_aclk_lcdc0_src", "gate_dclk_lcdc0", - "gate_dclk_lcdc1", "gate_pclkin_cif0", - "gate_pclkin_cif1", "reserved", - "reserved", "gate_cif0_out", - "gate_cif1_out", "gate_aclk_vepu", - "gate_hclk_vepu", "gate_aclk_vdpu", - "gate_hclk_vdpu", "gate_gpu_src", - "reserved", "gate_xin27m"; - - #clock-cells = <1>; - }; - - clk_gates4: gate-clk@200000e0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e0 0x4>; - clocks = <&clk_gates2 2>, <&clk_gates2 3>, - <&clk_gates2 1>, <&clk_gates2 1>, - <&clk_gates2 1>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates2 2>, - <&clk_gates0 4>, <&clk_gates0 4>, - <&clk_gates0 3>, <&clk_gates0 3>, - <&clk_gates0 3>, <&clk_gates2 3>, - <&clk_gates0 4>; - - clock-output-names = - "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix", - "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix", - "gate_aclk_pei_niu", "gate_hclk_usb_peri", - "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri", - "gate_hclk_cpubus", "gate_hclk_ahb2apb", - "gate_aclk_strc_sys", "gate_aclk_l2mem_con", - "gate_aclk_intmem", "gate_pclk_tsadc", - "gate_hclk_hdmi"; - - #clock-cells = <1>; - }; - - clk_gates5: gate-clk@200000e4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e4 0x4>; - clocks = <&clk_gates0 3>, <&clk_gates2 1>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 4>, <&clk_gates0 5>, - <&clk_gates2 1>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates4 5>, - <&clk_gates4 5>, <&dummy>; - - clock-output-names = - "gate_aclk_dmac1", "gate_aclk_dmac2", - "gate_pclk_efuse", "gate_pclk_tzpc", - "gate_pclk_grf", "gate_pclk_pmu", - "gate_hclk_rom", "gate_pclk_ddrupctl", - "gate_aclk_smc", "gate_hclk_nandc", - "gate_hclk_mmc0", "gate_hclk_mmc1", - "gate_hclk_emmc", "gate_hclk_otg0", - "gate_hclk_otg1", "gate_aclk_gpu"; - - #clock-cells = <1>; - }; - - clk_gates6: gate-clk@200000e8 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e8 0x4>; - clocks = <&clk_gates3 0>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates0 4>, <&clk_gates3 0>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates3 0>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates0 4>, <&clk_gates3 0>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_aclk_lcdc0", "gate_hclk_lcdc0", - "gate_hclk_lcdc1", "gate_aclk_lcdc1", - "gate_hclk_cif0", "gate_aclk_cif0", - "gate_hclk_cif1", "gate_aclk_cif1", - "gate_aclk_ipp", "gate_hclk_ipp", - "gate_hclk_rga", "gate_aclk_rga", - "gate_hclk_vio_bus", "gate_aclk_vio0", - "gate_aclk_vcodec", "gate_shclk_vio_h2h"; - - #clock-cells = <1>; - }; - - clk_gates7: gate-clk@200000ec { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000ec 0x4>; - clocks = <&clk_gates2 2>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates2 3>; - - clock-output-names = - "gate_hclk_emac", "gate_hclk_spdif", - "gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch", - "gate_hclk_i2s_8ch", "gate_hclk_hsadc", - "gate_hclk_pidf", "gate_pclk_timer0", - "gate_pclk_timer1", "gate_pclk_timer2", - "gate_pclk_pwm01", "gate_pclk_pwm23", - "gate_pclk_spi0", "gate_pclk_spi1", - "gate_pclk_saradc", "gate_pclk_wdt"; - - #clock-cells = <1>; - }; - - clk_gates8: gate-clk@200000f0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000f0 0x4>; - clocks = <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&dummy>, <&clk_gates0 5>; - - clock-output-names = - "gate_pclk_uart0", "gate_pclk_uart1", - "gate_pclk_uart2", "gate_pclk_uart3", - "gate_pclk_i2c0", "gate_pclk_i2c1", - "gate_pclk_i2c2", "gate_pclk_i2c3", - "gate_pclk_i2c4", "gate_pclk_gpio0", - "gate_pclk_gpio1", "gate_pclk_gpio2", - "gate_pclk_gpio3", "gate_pclk_gpio4", - "reserved", "gate_pclk_gpio6"; - - #clock-cells = <1>; - }; - - clk_gates9: gate-clk@200000f4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000f4 0x4>; - clocks = <&dummy>, <&clk_gates0 5>, - <&dummy>, <&dummy>, - <&dummy>, <&clk_gates1 4>, - <&clk_gates0 5>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>; - - clock-output-names = - "gate_clk_core_dbg", "gate_pclk_dbg", - "gate_clk_trace", "gate_atclk", - "gate_clk_l2c", "gate_aclk_vio1", - "gate_pclk_publ", "gate_aclk_intmem0", - "gate_aclk_intmem1", "gate_aclk_intmem2", - "gate_aclk_intmem3"; - - #clock-cells = <1>; - }; - }; - -}; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 15c81d2c2d52..6476ce7a2987 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -17,7 +17,6 @@ #include #include #include "rk3xxx.dtsi" -#include "rk3066a-clocks.dtsi" / { compatible = "rockchip,rk3066a"; diff --git a/arch/arm/boot/dts/rk3188-clocks.dtsi b/arch/arm/boot/dts/rk3188-clocks.dtsi deleted file mode 100644 index 6bc0373a2fb8..000000000000 --- a/arch/arm/boot/dts/rk3188-clocks.dtsi +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { - compatible = "fixed-clock"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - dummy48m: dummy48m { - compatible = "fixed-clock"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - - dummy150m: dummy150m { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - }; - - clk_gates0: gate-clk@200000d0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d0 0x4>; - clocks = <&dummy150m>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_core_periph", "gate_cpu_gpll", - "gate_ddrphy", "gate_aclk_cpu", - "gate_hclk_cpu", "gate_pclk_cpu", - "gate_atclk_cpu", "gate_aclk_core", - "reserved", "gate_i2s0", - "gate_i2s0_frac", "reserved", - "reserved", "gate_spdif", - "gate_spdif_frac", "gate_testclk"; - - #clock-cells = <1>; - }; - - clk_gates1: gate-clk@200000d4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d4 0x4>; - clocks = <&xin24m>, <&xin24m>, - <&xin24m>, <&dummy>, - <&dummy>, <&xin24m>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>; - - clock-output-names = - "gate_timer0", "gate_timer1", - "gate_timer3", "gate_jtag", - "gate_aclk_lcdc1_src", "gate_otgphy0", - "gate_otgphy1", "gate_ddr_gpll", - "gate_uart0", "gate_frac_uart0", - "gate_uart1", "gate_frac_uart1", - "gate_uart2", "gate_frac_uart2", - "gate_uart3", "gate_frac_uart3"; - - #clock-cells = <1>; - }; - - clk_gates2: gate-clk@200000d8 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d8 0x4>; - clocks = <&clk_gates2 1>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&clk_gates2 3>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy48m>, - <&dummy>, <&dummy48m>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_periph_src", "gate_aclk_periph", - "gate_hclk_periph", "gate_pclk_periph", - "gate_smc", "gate_mac", - "gate_hsadc", "gate_hsadc_frac", - "gate_saradc", "gate_spi0", - "gate_spi1", "gate_mmc0", - "gate_mac_lbtest", "gate_mmc1", - "gate_emmc", "reserved"; - - #clock-cells = <1>; - }; - - clk_gates3: gate-clk@200000dc { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000dc 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&xin24m>, <&xin24m>, - <&dummy>, <&dummy>, - <&xin24m>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&xin24m>, <&dummy>; - - clock-output-names = - "gate_aclk_lcdc0_src", "gate_dclk_lcdc0", - "gate_dclk_lcdc1", "gate_pclkin_cif0", - "gate_timer2", "gate_timer4", - "gate_hsicphy", "gate_cif0_out", - "gate_timer5", "gate_aclk_vepu", - "gate_hclk_vepu", "gate_aclk_vdpu", - "gate_hclk_vdpu", "reserved", - "gate_timer6", "gate_aclk_gpu_src"; - - #clock-cells = <1>; - }; - - clk_gates4: gate-clk@200000e0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e0 0x4>; - clocks = <&clk_gates2 2>, <&clk_gates2 3>, - <&clk_gates2 1>, <&clk_gates2 1>, - <&clk_gates2 1>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates2 2>, - <&clk_gates0 4>, <&clk_gates0 4>, - <&clk_gates0 3>, <&dummy>, - <&clk_gates0 3>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix", - "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix", - "gate_aclk_pei_niu", "gate_hclk_usb_peri", - "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri", - "gate_hclk_cpubus", "gate_hclk_ahb2apb", - "gate_aclk_strc_sys", "reserved", - "gate_aclk_intmem", "reserved", - "gate_hclk_imem1", "gate_hclk_imem0"; - - #clock-cells = <1>; - }; - - clk_gates5: gate-clk@200000e4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e4 0x4>; - clocks = <&clk_gates0 3>, <&clk_gates2 1>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 4>, <&clk_gates0 5>, - <&clk_gates2 1>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates4 5>; - - clock-output-names = - "gate_aclk_dmac1", "gate_aclk_dmac2", - "gate_pclk_efuse", "gate_pclk_tzpc", - "gate_pclk_grf", "gate_pclk_pmu", - "gate_hclk_rom", "gate_pclk_ddrupctl", - "gate_aclk_smc", "gate_hclk_nandc", - "gate_hclk_mmc0", "gate_hclk_mmc1", - "gate_hclk_emmc", "gate_hclk_otg0"; - - #clock-cells = <1>; - }; - - clk_gates6: gate-clk@200000e8 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e8 0x4>; - clocks = <&clk_gates3 0>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates0 4>, <&clk_gates3 0>, - <&dummy>, <&dummy>, - <&clk_gates3 0>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates0 4>, <&clk_gates3 0>; - - clock-output-names = - "gate_aclk_lcdc0", "gate_hclk_lcdc0", - "gate_hclk_lcdc1", "gate_aclk_lcdc1", - "gate_hclk_cif0", "gate_aclk_cif0", - "reserved", "reserved", - "gate_aclk_ipp", "gate_hclk_ipp", - "gate_hclk_rga", "gate_aclk_rga", - "gate_hclk_vio_bus", "gate_aclk_vio0"; - - #clock-cells = <1>; - }; - - clk_gates7: gate-clk@200000ec { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000ec 0x4>; - clocks = <&clk_gates2 2>, <&clk_gates0 4>, - <&clk_gates0 4>, <&dummy>, - <&dummy>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates0 5>, - <&dummy>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates2 3>; - - clock-output-names = - "gate_hclk_emac", "gate_hclk_spdif", - "gate_hclk_i2s0_2ch", "gate_hclk_otg1", - "gate_hclk_hsic", "gate_hclk_hsadc", - "gate_hclk_pidf", "gate_pclk_timer0", - "reserved", "gate_pclk_timer2", - "gate_pclk_pwm01", "gate_pclk_pwm23", - "gate_pclk_spi0", "gate_pclk_spi1", - "gate_pclk_saradc", "gate_pclk_wdt"; - - #clock-cells = <1>; - }; - - clk_gates8: gate-clk@200000f0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000f0 0x4>; - clocks = <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&dummy>; - - clock-output-names = - "gate_pclk_uart0", "gate_pclk_uart1", - "gate_pclk_uart2", "gate_pclk_uart3", - "gate_pclk_i2c0", "gate_pclk_i2c1", - "gate_pclk_i2c2", "gate_pclk_i2c3", - "gate_pclk_i2c4", "gate_pclk_gpio0", - "gate_pclk_gpio1", "gate_pclk_gpio2", - "gate_pclk_gpio3", "gate_aclk_gps"; - - #clock-cells = <1>; - }; - - clk_gates9: gate-clk@200000f4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000f4 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_clk_core_dbg", "gate_pclk_dbg", - "gate_clk_trace", "gate_atclk", - "gate_clk_l2c", "gate_aclk_vio1", - "gate_pclk_publ", "gate_aclk_gpu"; - - #clock-cells = <1>; - }; - }; - -}; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index bf0741a89b7c..0db541c4e7b3 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -17,7 +17,6 @@ #include #include #include "rk3xxx.dtsi" -#include "rk3188-clocks.dtsi" / { compatible = "rockchip,rk3188"; -- cgit v1.2.3 From c3030d30d9c99c057b5ddfa289cffa637a2775f5 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 26 Jul 2014 18:44:35 +0200 Subject: ARM: dts: rockchip: remove soc subnodes Comments received from the rk3288 submission indicated that a generic subnode to group soc components should not be used. So to keep all rockchip devicetree files similar, remove it from rk3066 and rk3188. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 134 ++++++----- arch/arm/boot/dts/rk3066a.dtsi | 390 ++++++++++++++++----------------- arch/arm/boot/dts/rk3188-radxarock.dts | 83 ++++--- arch/arm/boot/dts/rk3188.dtsi | 334 ++++++++++++++-------------- arch/arm/boot/dts/rk3xxx.dtsi | 221 +++++++++---------- 5 files changed, 573 insertions(+), 589 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index afb327322a4a..6131675695eb 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -24,87 +24,85 @@ reg = <0x60000000 0x40000000>; }; - soc { - uart0: serial@10124000 { - status = "okay"; - }; + uart0: serial@10124000 { + status = "okay"; + }; - uart1: serial@10126000 { - status = "okay"; - }; + uart1: serial@10126000 { + status = "okay"; + }; - uart2: serial@20064000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "okay"; - }; + uart2: serial@20064000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + status = "okay"; + }; - uart3: serial@20068000 { - status = "okay"; - }; + uart3: serial@20068000 { + status = "okay"; + }; - vcc_sd0: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "sdmmc-supply"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio3 7 GPIO_ACTIVE_LOW>; - startup-delay-us = <100000>; - }; + vcc_sd0: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "sdmmc-supply"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio3 7 GPIO_ACTIVE_LOW>; + startup-delay-us = <100000>; + }; - dwmmc@10214000 { /* sdmmc */ - num-slots = <1>; - status = "okay"; + dwmmc@10214000 { /* sdmmc */ + num-slots = <1>; + status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; - vmmc-supply = <&vcc_sd0>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; + vmmc-supply = <&vcc_sd0>; - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; + slot@0 { + reg = <0>; + bus-width = <4>; + disable-wp; }; + }; - dwmmc@10218000 { /* wifi */ - num-slots = <1>; - status = "okay"; - non-removable; + dwmmc@10218000 { /* wifi */ + num-slots = <1>; + status = "okay"; + non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; + slot@0 { + reg = <0>; + bus-width = <4>; + disable-wp; }; + }; - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - button@0 { - gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */ - linux,code = <116>; - label = "GPIO Key Power"; - linux,input-type = <1>; - gpio-key,wakeup = <1>; - debounce-interval = <100>; - }; - button@1 { - gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */ - linux,code = <104>; - label = "GPIO Key Vol-"; - linux,input-type = <1>; - gpio-key,wakeup = <0>; - debounce-interval = <100>; - }; - /* VOL+ comes somehow thru the ADC */ + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + button@0 { + gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */ + linux,code = <116>; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + button@1 { + gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */ + linux,code = <104>; + label = "GPIO Key Vol-"; + linux,input-type = <1>; + gpio-key,wakeup = <0>; + debounce-interval = <100>; }; + /* VOL+ comes somehow thru the ADC */ }; }; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 6476ce7a2987..4ad8f59503dd 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -40,255 +40,253 @@ }; }; - soc { - timer@20038000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x20038000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; - clock-names = "timer", "pclk"; - }; + timer@20038000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x20038000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; + clock-names = "timer", "pclk"; + }; + + timer@2003a000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2003a000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; + clock-names = "timer", "pclk"; + }; + + timer@2000e000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2000e000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; + clock-names = "timer", "pclk"; + }; - timer@2003a000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x2003a000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; - clock-names = "timer", "pclk"; + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x10000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x0 0x50>; }; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3066a-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pinctrl@20008000 { + compatible = "rockchip,rk3066a-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; - timer@2000e000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x2000e000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; - clock-names = "timer", "pclk"; + gpio0: gpio0@20034000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20034000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; }; - sram: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x10000>; + gpio1: gpio1@2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x0 0x50>; - }; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; }; - cru: clock-controller@20000000 { - compatible = "rockchip,rk3066a-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; + gpio2: gpio2@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; - #clock-cells = <1>; - #reset-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; }; - pinctrl@20008000 { - compatible = "rockchip,rk3066a-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; + gpio3: gpio3@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; - gpio0: gpio0@20034000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20034000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; - gpio-controller; - #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; - interrupt-controller; - #interrupt-cells = <2>; - }; + gpio4: gpio4@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>; - gpio1: gpio1@2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; - gpio-controller; - #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; - interrupt-controller; - #interrupt-cells = <2>; - }; + gpio6: gpio6@2000a000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2000a000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO6>; - gpio2: gpio2@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; - gpio-controller; - #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; - interrupt-controller; - #interrupt-cells = <2>; - }; + pcfg_pull_default: pcfg_pull_default { + bias-pull-pin-default; + }; - gpio3: gpio3@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; + pcfg_pull_none: pcfg_pull_none { + bias-disable; + }; - gpio-controller; - #gpio-cells = <2>; + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = , + ; + }; - interrupt-controller; - #interrupt-cells = <2>; + uart0_cts: uart0-cts { + rockchip,pins = ; }; - gpio4: gpio4@20084000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20084000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>; + uart0_rts: uart0-rts { + rockchip,pins = ; + }; + }; - gpio-controller; - #gpio-cells = <2>; + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = , + ; + }; - interrupt-controller; - #interrupt-cells = <2>; + uart1_cts: uart1-cts { + rockchip,pins = ; }; - gpio6: gpio6@2000a000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2000a000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO6>; + uart1_rts: uart1-rts { + rockchip,pins = ; + }; + }; - gpio-controller; - #gpio-cells = <2>; + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = , + ; + }; + /* no rts / cts for uart2 */ + }; - interrupt-controller; - #interrupt-cells = <2>; + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = , + ; }; - pcfg_pull_default: pcfg_pull_default { - bias-pull-pin-default; + uart3_cts: uart3-cts { + rockchip,pins = ; }; - pcfg_pull_none: pcfg_pull_none { - bias-disable; + uart3_rts: uart3-rts { + rockchip,pins = ; }; + }; - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = , - ; - }; + sd0 { + sd0_clk: sd0-clk { + rockchip,pins = ; + }; - uart0_cts: uart0-cts { - rockchip,pins = ; - }; + sd0_cmd: sd0-cmd { + rockchip,pins = ; + }; - uart0_rts: uart0-rts { - rockchip,pins = ; - }; + sd0_cd: sd0-cd { + rockchip,pins = ; }; - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = , - ; - }; + sd0_wp: sd0-wp { + rockchip,pins = ; + }; - uart1_cts: uart1-cts { - rockchip,pins = ; - }; + sd0_bus1: sd0-bus-width1 { + rockchip,pins = ; + }; - uart1_rts: uart1-rts { - rockchip,pins = ; - }; + sd0_bus4: sd0-bus-width4 { + rockchip,pins = , + , + , + ; }; + }; - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = , - ; - }; - /* no rts / cts for uart2 */ + sd1 { + sd1_clk: sd1-clk { + rockchip,pins = ; }; - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = , - ; - }; + sd1_cmd: sd1-cmd { + rockchip,pins = ; + }; - uart3_cts: uart3-cts { - rockchip,pins = ; - }; + sd1_cd: sd1-cd { + rockchip,pins = ; + }; - uart3_rts: uart3-rts { - rockchip,pins = ; - }; + sd1_wp: sd1-wp { + rockchip,pins = ; }; - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = ; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = ; - }; - - sd0_cd: sd0-cd { - rockchip,pins = ; - }; - - sd0_wp: sd0-wp { - rockchip,pins = ; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = ; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = , - , - , - ; - }; + sd1_bus1: sd1-bus-width1 { + rockchip,pins = ; }; - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = ; - }; - - sd1_cmd: sd1-cmd { - rockchip,pins = ; - }; - - sd1_cd: sd1-cd { - rockchip,pins = ; - }; - - sd1_wp: sd1-wp { - rockchip,pins = ; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = ; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = , - , - , - ; - }; + sd1_bus4: sd1-bus-width4 { + rockchip,pins = , + , + , + ; }; }; }; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index a5eee55079cb..7a002f523ec4 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -23,59 +23,56 @@ reg = <0x60000000 0x80000000>; }; - soc { - uart0: serial@10124000 { - status = "okay"; - }; + uart0: serial@10124000 { + status = "okay"; + }; - uart1: serial@10126000 { - status = "okay"; - }; + uart1: serial@10126000 { + status = "okay"; + }; - uart2: serial@20064000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "okay"; - }; + uart2: serial@20064000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + status = "okay"; + }; - uart3: serial@20068000 { - status = "okay"; - }; + uart3: serial@20068000 { + status = "okay"; + }; - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; - button@0 { - gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; - linux,code = <116>; - label = "GPIO Key Power"; - linux,input-type = <1>; - gpio-key,wakeup = <1>; - debounce-interval = <100>; - }; + button@0 { + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; }; + }; - gpio-leds { - compatible = "gpio-leds"; - - green { - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; + gpio-leds { + compatible = "gpio-leds"; - yellow { - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; + green { + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; - sleep { - gpios = <&gpio0 15 0>; - default-state = "off"; - }; + yellow { + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + default-state = "off"; }; + sleep { + gpios = <&gpio0 15 0>; + default-state = "off"; + }; }; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 0db541c4e7b3..038d9d45264c 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -52,223 +52,221 @@ }; }; - soc { - global-timer@1013c200 { - interrupts = ; + global-timer@1013c200 { + interrupts = ; + }; + + local-timer@1013c600 { + interrupts = ; + }; + + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x8000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x0 0x50>; }; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3188-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; - local-timer@1013c600 { - interrupts = ; + pinctrl@20008000 { + compatible = "rockchip,rk3188-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@0x2000a000 { + compatible = "rockchip,rk3188-gpio-bank0"; + reg = <0x2000a000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; }; - sram: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x8000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x8000>; + gpio1: gpio1@0x2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x0 0x50>; - }; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; }; - cru: clock-controller@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; + gpio2: gpio2@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; - #clock-cells = <1>; - #reset-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; }; - pinctrl@20008000 { - compatible = "rockchip,rk3188-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; + gpio3: gpio3@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; - #address-cells = <1>; - #size-cells = <1>; - ranges; + gpio-controller; + #gpio-cells = <2>; - gpio0: gpio0@0x2000a000 { - compatible = "rockchip,rk3188-gpio-bank0"; - reg = <0x2000a000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; + interrupt-controller; + #interrupt-cells = <2>; + }; - gpio-controller; - #gpio-cells = <2>; + pcfg_pull_up: pcfg_pull_up { + bias-pull-up; + }; - interrupt-controller; - #interrupt-cells = <2>; - }; + pcfg_pull_down: pcfg_pull_down { + bias-pull-down; + }; - gpio1: gpio1@0x2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; + pcfg_pull_none: pcfg_pull_none { + bias-disable; + }; - gpio-controller; - #gpio-cells = <2>; + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = , + ; + }; - interrupt-controller; - #interrupt-cells = <2>; + uart0_cts: uart0-cts { + rockchip,pins = ; }; - gpio2: gpio2@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; + uart0_rts: uart0-rts { + rockchip,pins = ; + }; + }; - gpio-controller; - #gpio-cells = <2>; + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = , + ; + }; - interrupt-controller; - #interrupt-cells = <2>; + uart1_cts: uart1-cts { + rockchip,pins = ; }; - gpio3: gpio3@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; + uart1_rts: uart1-rts { + rockchip,pins = ; + }; + }; - gpio-controller; - #gpio-cells = <2>; + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = , + ; + }; + /* no rts / cts for uart2 */ + }; - interrupt-controller; - #interrupt-cells = <2>; + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = , + ; }; - pcfg_pull_up: pcfg_pull_up { - bias-pull-up; + uart3_cts: uart3-cts { + rockchip,pins = ; }; - pcfg_pull_down: pcfg_pull_down { - bias-pull-down; + uart3_rts: uart3-rts { + rockchip,pins = ; }; + }; - pcfg_pull_none: pcfg_pull_none { - bias-disable; + sd0 { + sd0_clk: sd0-clk { + rockchip,pins = ; }; - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = , - ; - }; + sd0_cmd: sd0-cmd { + rockchip,pins = ; + }; - uart0_cts: uart0-cts { - rockchip,pins = ; - }; + sd0_cd: sd0-cd { + rockchip,pins = ; + }; - uart0_rts: uart0-rts { - rockchip,pins = ; - }; + sd0_wp: sd0-wp { + rockchip,pins = ; }; - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = , - ; - }; + sd0_pwr: sd0-pwr { + rockchip,pins = ; + }; - uart1_cts: uart1-cts { - rockchip,pins = ; - }; + sd0_bus1: sd0-bus-width1 { + rockchip,pins = ; + }; - uart1_rts: uart1-rts { - rockchip,pins = ; - }; + sd0_bus4: sd0-bus-width4 { + rockchip,pins = , + , + , + ; }; + }; - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = , - ; - }; - /* no rts / cts for uart2 */ + sd1 { + sd1_clk: sd1-clk { + rockchip,pins = ; }; - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = , - ; - }; + sd1_cmd: sd1-cmd { + rockchip,pins = ; + }; - uart3_cts: uart3-cts { - rockchip,pins = ; - }; + sd1_cd: sd1-cd { + rockchip,pins = ; + }; - uart3_rts: uart3-rts { - rockchip,pins = ; - }; + sd1_wp: sd1-wp { + rockchip,pins = ; }; - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = ; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = ; - }; - - sd0_cd: sd0-cd { - rockchip,pins = ; - }; - - sd0_wp: sd0-wp { - rockchip,pins = ; - }; - - sd0_pwr: sd0-pwr { - rockchip,pins = ; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = ; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = , - , - , - ; - }; + sd1_bus1: sd1-bus-width1 { + rockchip,pins = ; }; - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = ; - }; - - sd1_cmd: sd1-cmd { - rockchip,pins = ; - }; - - sd1_cd: sd1-cd { - rockchip,pins = ; - }; - - sd1_wp: sd1-wp { - rockchip,pins = ; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = ; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = , - , - , - ; - }; + sd1_bus4: sd1-bus-width4 { + rockchip,pins = , + , + , + ; }; }; }; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 6d163644c7cd..f70addd793a7 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -27,120 +27,113 @@ clock-output-names = "xin24m"; }; - soc { + scu@1013c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1013c000 0x100>; + }; + + pmu: pmu@20004000 { + compatible = "rockchip,rk3066-pmu", "syscon"; + reg = <0x20004000 0x100>; + }; + + grf: grf@20008000 { + compatible = "syscon"; + reg = <0x20008000 0x200>; + }; + + gic: interrupt-controller@1013d000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1013d000 0x1000>, + <0x1013c100 0x0100>; + }; + + L2: l2-cache-controller@10138000 { + compatible = "arm,pl310-cache"; + reg = <0x10138000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + global-timer@1013c200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x1013c200 0x20>; + interrupts = ; + clocks = <&cru CORE_PERI>; + }; + + local-timer@1013c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1013c600 0x20>; + interrupts = ; + clocks = <&cru CORE_PERI>; + }; + + uart0: serial@10124000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10124000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&cru SCLK_UART0>; + status = "disabled"; + }; + + uart1: serial@10126000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10126000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&cru SCLK_UART1>; + status = "disabled"; + }; + + uart2: serial@20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&cru SCLK_UART2>; + status = "disabled"; + }; + + uart3: serial@20068000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20068000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&cru SCLK_UART3>; + status = "disabled"; + }; + + dwmmc@10214000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10214000 0x1000>; + interrupts = ; #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - scu@1013c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1013c000 0x100>; - }; - - pmu: pmu@20004000 { - compatible = "rockchip,rk3066-pmu", "syscon"; - reg = <0x20004000 0x100>; - }; - - grf: grf@20008000 { - compatible = "syscon"; - reg = <0x20008000 0x200>; - }; - - gic: interrupt-controller@1013d000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x1013d000 0x1000>, - <0x1013c100 0x0100>; - }; - - L2: l2-cache-controller@10138000 { - compatible = "arm,pl310-cache"; - reg = <0x10138000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - global-timer@1013c200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x1013c200 0x20>; - interrupts = ; - clocks = <&cru CORE_PERI>; - }; - - local-timer@1013c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1013c600 0x20>; - interrupts = ; - clocks = <&cru CORE_PERI>; - }; - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - status = "disabled"; - }; - - uart1: serial@10126000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10126000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART1>; - status = "disabled"; - }; - - uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART2>; - status = "disabled"; - }; - - uart3: serial@20068000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20068000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART3>; - status = "disabled"; - }; - - dwmmc@10214000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10214000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; - - status = "disabled"; - }; - - dwmmc@10218000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10218000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; - clock-names = "biu", "ciu"; - - status = "disabled"; - }; + #size-cells = <0>; + + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; + clock-names = "biu", "ciu"; + + status = "disabled"; + }; + + dwmmc@10218000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10218000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; + clock-names = "biu", "ciu"; + + status = "disabled"; }; }; -- cgit v1.2.3 From e40b43d6ea0c5c30ba3655b304d2d526539fc7ed Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 26 Jul 2014 18:53:07 +0200 Subject: ARM: dts: rockchip: add handles for shared nodes that don't have one yet Some nodes that are changed in the dtsi hierarchy do not have handles yet. As it was suggested in the rk3288 submission to do subsequent nodes changes through such handle-references, add the missing ones. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 2 +- arch/arm/boot/dts/rk3188.dtsi | 2 +- arch/arm/boot/dts/rk3xxx.dtsi | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 4ad8f59503dd..ecf722ea5982 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -86,7 +86,7 @@ #reset-cells = <1>; }; - pinctrl@20008000 { + pinctrl: pinctrl@20008000 { compatible = "rockchip,rk3066a-pinctrl"; rockchip,grf = <&grf>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 038d9d45264c..7b631ec3102c 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -82,7 +82,7 @@ #reset-cells = <1>; }; - pinctrl@20008000 { + pinctrl: pinctrl@20008000 { compatible = "rockchip,rk3188-pinctrl"; rockchip,grf = <&grf>; rockchip,pmu = <&pmu>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index f70addd793a7..10e7586c1dc2 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -57,14 +57,14 @@ cache-level = <2>; }; - global-timer@1013c200 { + global_timer: global-timer@1013c200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x1013c200 0x20>; interrupts = ; clocks = <&cru CORE_PERI>; }; - local-timer@1013c600 { + local_timer: local-timer@1013c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x1013c600 0x20>; interrupts = ; @@ -111,7 +111,7 @@ status = "disabled"; }; - dwmmc@10214000 { + mmc0: dwmmc@10214000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10214000 0x1000>; interrupts = ; @@ -124,7 +124,7 @@ status = "disabled"; }; - dwmmc@10218000 { + mmc1: dwmmc@10218000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10218000 0x1000>; interrupts = ; -- cgit v1.2.3 From fcbbf965254ff1693c26a5646e4e62adc3a6118d Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 26 Jul 2014 23:08:06 +0200 Subject: ARM: dts: uses handles to reference nodes for changes Use the handles for subsequent changes to nodes, similar to like the rk3288 submission does it. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 91 ++++++++++++++++------------------ arch/arm/boot/dts/rk3066a.dtsi | 30 +++++++++++ arch/arm/boot/dts/rk3188-radxarock.dts | 36 +++++++------- arch/arm/boot/dts/rk3188.dtsi | 36 +++++++++++--- 4 files changed, 119 insertions(+), 74 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 6131675695eb..38910f6992bf 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -24,24 +24,6 @@ reg = <0x60000000 0x40000000>; }; - uart0: serial@10124000 { - status = "okay"; - }; - - uart1: serial@10126000 { - status = "okay"; - }; - - uart2: serial@20064000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "okay"; - }; - - uart3: serial@20068000 { - status = "okay"; - }; - vcc_sd0: fixed-regulator { compatible = "regulator-fixed"; regulator-name = "sdmmc-supply"; @@ -51,36 +33,6 @@ startup-delay-us = <100000>; }; - dwmmc@10214000 { /* sdmmc */ - num-slots = <1>; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; - vmmc-supply = <&vcc_sd0>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; - }; - - dwmmc@10218000 { /* wifi */ - num-slots = <1>; - status = "okay"; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; - }; - gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; @@ -106,3 +58,46 @@ /* VOL+ comes somehow thru the ADC */ }; }; + +&mmc0 { /* sdmmc */ + num-slots = <1>; + status = "okay"; + vmmc-supply = <&vcc_sd0>; + + slot@0 { + reg = <0>; + bus-width = <4>; + disable-wp; + }; +}; + +&mmc1 { /* wifi */ + num-slots = <1>; + status = "okay"; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + disable-wp; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index ecf722ea5982..460932b2baa8 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -291,3 +291,33 @@ }; }; }; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; +}; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 7a002f523ec4..241e2a4d4b99 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -23,24 +23,6 @@ reg = <0x60000000 0x80000000>; }; - uart0: serial@10124000 { - status = "okay"; - }; - - uart1: serial@10126000 { - status = "okay"; - }; - - uart2: serial@20064000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "okay"; - }; - - uart3: serial@20068000 { - status = "okay"; - }; - gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; @@ -76,3 +58,21 @@ }; }; }; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 7b631ec3102c..4a9f7020c562 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -52,14 +52,6 @@ }; }; - global-timer@1013c200 { - interrupts = ; - }; - - local-timer@1013c600 { - interrupts = ; - }; - sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x8000>; @@ -271,3 +263,31 @@ }; }; }; + +&global_timer { + interrupts = ; +}; + +&local_timer { + interrupts = ; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; +}; -- cgit v1.2.3 From 6e4b3b4b66dd6e7f4980a6626d54a532deb47517 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 22 Jul 2014 22:56:16 +0200 Subject: ARM: dts: rockchip: remove address from pinctrl nodes The pincontroller uses the GRF and PMU syscons nowadays, so should not contain an address in its device node. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 2 +- arch/arm/boot/dts/rk3188.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 460932b2baa8..3198394429c2 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -86,7 +86,7 @@ #reset-cells = <1>; }; - pinctrl: pinctrl@20008000 { + pinctrl: pinctrl { compatible = "rockchip,rk3066a-pinctrl"; rockchip,grf = <&grf>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 4a9f7020c562..dd7f61fe98d4 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -74,7 +74,7 @@ #reset-cells = <1>; }; - pinctrl: pinctrl@20008000 { + pinctrl: pinctrl { compatible = "rockchip,rk3188-pinctrl"; rockchip,grf = <&grf>; rockchip,pmu = <&pmu>; -- cgit v1.2.3 From ff84b90ecd1cfd00af3d1832fd8bf3c18e555d4e Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 26 Jul 2014 23:28:03 +0200 Subject: ARM: dts: rockchip: oder nodes by register address To create some sort of ordering of nodes, they are suggested to be ordered by their register address. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 48 +++++++++++------------ arch/arm/boot/dts/rk3xxx.dtsi | 86 +++++++++++++++++++++--------------------- 2 files changed, 67 insertions(+), 67 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 3198394429c2..21b87dece38c 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -40,30 +40,6 @@ }; }; - timer@20038000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x20038000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; - clock-names = "timer", "pclk"; - }; - - timer@2003a000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x2003a000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; - clock-names = "timer", "pclk"; - }; - - timer@2000e000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x2000e000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; - clock-names = "timer", "pclk"; - }; - sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x10000>; @@ -86,6 +62,30 @@ #reset-cells = <1>; }; + timer@2000e000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2000e000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; + clock-names = "timer", "pclk"; + }; + + timer@20038000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x20038000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; + clock-names = "timer", "pclk"; + }; + + timer@2003a000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2003a000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; + clock-names = "timer", "pclk"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3066a-pinctrl"; rockchip,grf = <&grf>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 10e7586c1dc2..ad204da6c60f 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -27,29 +27,6 @@ clock-output-names = "xin24m"; }; - scu@1013c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1013c000 0x100>; - }; - - pmu: pmu@20004000 { - compatible = "rockchip,rk3066-pmu", "syscon"; - reg = <0x20004000 0x100>; - }; - - grf: grf@20008000 { - compatible = "syscon"; - reg = <0x20008000 0x200>; - }; - - gic: interrupt-controller@1013d000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x1013d000 0x1000>, - <0x1013c100 0x0100>; - }; - L2: l2-cache-controller@10138000 { compatible = "arm,pl310-cache"; reg = <0x10138000 0x1000>; @@ -57,6 +34,11 @@ cache-level = <2>; }; + scu@1013c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1013c000 0x100>; + }; + global_timer: global-timer@1013c200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x1013c200 0x20>; @@ -71,6 +53,14 @@ clocks = <&cru CORE_PERI>; }; + gic: interrupt-controller@1013d000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1013d000 0x1000>, + <0x1013c100 0x0100>; + }; + uart0: serial@10124000 { compatible = "snps,dw-apb-uart"; reg = <0x10124000 0x400>; @@ -91,26 +81,6 @@ status = "disabled"; }; - uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART2>; - status = "disabled"; - }; - - uart3: serial@20068000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20068000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART3>; - status = "disabled"; - }; - mmc0: dwmmc@10214000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10214000 0x1000>; @@ -136,4 +106,34 @@ status = "disabled"; }; + + pmu: pmu@20004000 { + compatible = "rockchip,rk3066-pmu", "syscon"; + reg = <0x20004000 0x100>; + }; + + grf: grf@20008000 { + compatible = "syscon"; + reg = <0x20008000 0x200>; + }; + + uart2: serial@20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&cru SCLK_UART2>; + status = "disabled"; + }; + + uart3: serial@20068000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20068000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&cru SCLK_UART3>; + status = "disabled"; + }; }; -- cgit v1.2.3 From 9cdffd8cb9b5f30495a9c284ab05d5b803f3b457 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 24 Jun 2014 20:12:06 +0200 Subject: ARM: dts: add rk3066 and rk3188 i2c device nodes and pinctrl settings The core controller settings themself are identical, only the compatible and pinctrl settings differ. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 60 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3188.dtsi | 65 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3xxx.dtsi | 84 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 209 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 21b87dece38c..18e802c08a91 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -179,6 +179,41 @@ bias-disable; }; + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = , + ; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = , + ; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = , + ; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = , + ; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = , + ; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = , @@ -292,6 +327,31 @@ }; }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index dd7f61fe98d4..ba1193ca00a7 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -147,6 +147,41 @@ bias-disable; }; + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = , + ; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = , + ; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = , + ; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = , + ; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = , + ; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = , @@ -272,6 +307,36 @@ interrupts = ; }; +&i2c0 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; +}; + +&i2c1 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; +}; + +&i2c2 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; +}; + +&i2c3 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; +}; + +&i2c4 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index ad204da6c60f..d3fa4d1a2f8a 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -20,6 +20,14 @@ / { interrupt-parent = <&gic>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -117,6 +125,82 @@ reg = <0x20008000 0x200>; }; + i2c0: i2c@2002d000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2002d000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + rockchip,bus-index = <0>; + + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + + status = "disabled"; + }; + + i2c1: i2c@2002f000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2002f000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C1>; + clock-names = "i2c"; + + status = "disabled"; + }; + + i2c2: i2c@20056000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x20056000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C2>; + clock-names = "i2c"; + + status = "disabled"; + }; + + i2c3: i2c@2005a000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2005a000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C3>; + clock-names = "i2c"; + + status = "disabled"; + }; + + i2c4: i2c@2005e000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2005e000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C4>; + clock-names = "i2c"; + + status = "disabled"; + }; + uart2: serial@20064000 { compatible = "snps,dw-apb-uart"; reg = <0x20064000 0x400>; -- cgit v1.2.3 From a953a6c77da2b8c2beb6db500b870e0b8c48fe64 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 26 Jun 2014 01:33:58 +0200 Subject: ARM: dts: rockchip: add tps65910 regulator for bqcurie2 The Curie2 uses a tps659102 as its main pmic, so add the i2c1 and tps65910 node as well as define the used voltages and regulator-names according to the schematics. Also fix the supply of the sd0 regulator, as it is supplied by the vio reg. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 87 ++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 38910f6992bf..8b479f767561 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -31,6 +31,7 @@ regulator-max-microvolt = <3000000>; gpio = <&gpio3 7 GPIO_ACTIVE_LOW>; startup-delay-us = <100000>; + vin-supply = <&vcc_io>; }; gpio-keys { @@ -59,6 +60,92 @@ }; }; +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + + interrupt-parent = <&gpio6>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; + + regulators { + vcc_rtc: regulator@0 { + regulator-name = "vcc_rtc"; + regulator-always-on; + }; + + vcc_io: regulator@1 { + regulator-name = "vcc_io"; + regulator-always-on; + }; + + vdd_arm: regulator@2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_ddr: regulator@3 { + regulator-name = "vcc_ddr"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc18_cif: regulator@5 { + regulator-name = "vcc18_cif"; + regulator-always-on; + }; + + vdd_11: regulator@6 { + regulator-name = "vdd_11"; + regulator-always-on; + }; + + vcc_25: regulator@7 { + regulator-name = "vcc_25"; + regulator-always-on; + }; + + vcc_18: regulator@8 { + regulator-name = "vcc_18"; + regulator-always-on; + }; + + vcc25_hdmi: regulator@9 { + regulator-name = "vcc25_hdmi"; + regulator-always-on; + }; + + vcca_33: regulator@10 { + regulator-name = "vcca_33"; + regulator-always-on; + }; + + vcc_tp: regulator@11 { + regulator-name = "vcc_tp"; + regulator-always-on; + }; + + vcc28_cif: regulator@12 { + regulator-name = "vcc28_cif"; + regulator-always-on; + }; + }; + }; +}; + +/* must be included after &tps gets defined */ +#include "tps65910.dtsi" + &mmc0 { /* sdmmc */ num-slots = <1>; status = "okay"; -- cgit v1.2.3 From fe2c89afa7797a7b5b949be298775d908d51f612 Mon Sep 17 00:00:00 2001 From: Beniamino Galvani Date: Sun, 22 Jun 2014 16:41:09 +0200 Subject: ARM: dts: add i2c and regulator nodes to rk3188-radxarock This enables the 2nd i2c bus and adds the act8846 pmic as device. Signed-off-by: Beniamino Galvani Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188-radxarock.dts | 112 +++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 241e2a4d4b99..a2812932cc5e 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -59,6 +59,118 @@ }; }; +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&act8846_dvs0_ctl>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "VCC_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd_log: REG2 { + regulator-name = "VDD_LOG"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vdd_arm: REG3 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + vcc_io: REG4 { + regulator-name = "VCC_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_10: REG5 { + regulator-name = "VDD_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vdd_hdmi: REG6 { + regulator-name = "VDD_HDMI"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vcc18: REG7 { + regulator-name = "VCC_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcca_33: REG8 { + regulator-name = "VCCA_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_rmii: REG9 { + regulator-name = "VCC_RMII"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vccio_wl: REG10 { + regulator-name = "VCCIO_WL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "VCC18_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc28: REG12 { + regulator-name = "VCC_28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + }; + }; +}; + +&pinctrl { + pcfg_output_low: pcfg-output-low { + output-low; + }; + + act8846 { + act8846_dvs0_ctl: act8846-dvs0-ctl { + rockchip,pins = ; + }; + }; +}; + &uart0 { status = "okay"; }; -- cgit v1.2.3 From b09e35a388ad23eb90497a352b8e5e5cb4b97bf2 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 26 Jun 2014 16:18:44 +0200 Subject: ARM: dts: rk3188-radxarock: enable sd-card slot The Radxa Rock contains one sd-card slot. Add the supplying regulator and enable its dw_mmc node. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188-radxarock.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index a2812932cc5e..7628b4868d2a 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -57,6 +57,16 @@ default-state = "off"; }; }; + + vcc_sd0: sdmmc-regulator { + compatible = "regulator-fixed"; + regulator-name = "sdmmc-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 1 GPIO_ACTIVE_LOW>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; }; &i2c1 { @@ -159,6 +169,18 @@ }; }; +&mmc0 { + num-slots = <1>; + status = "okay"; + vmmc-supply = <&vcc_sd0>; + + slot@0 { + reg = <0>; + bus-width = <4>; + disable-wp; + }; +}; + &pinctrl { pcfg_output_low: pcfg-output-low { output-low; -- cgit v1.2.3 From 69667ca2c4ad5bd346fb694a68e676fa46b2fba0 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 26 Jun 2014 16:06:12 +0200 Subject: ARM: dts: rockchip: add both clocks to uart nodes Use the newly ammended dw_8250 clock binding to define both the baudclk as well as the pclk supplying the ip. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3xxx.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index d3fa4d1a2f8a..989c33785ec4 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -75,7 +75,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; status = "disabled"; }; @@ -85,7 +86,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&cru SCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; status = "disabled"; }; @@ -207,7 +209,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&cru SCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; status = "disabled"; }; @@ -217,7 +220,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&cru SCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; status = "disabled"; }; }; -- cgit v1.2.3 From 550c7f4e6377cf5093b1b8d6b99cde2506bfea23 Mon Sep 17 00:00:00 2001 From: Beniamino Galvani Date: Thu, 26 Jun 2014 20:03:41 +0200 Subject: ARM: dts: rockchip: add pwm nodes This adds the necessary nodex and pinctrl settings for the Rockchip PWM-driver. Signed-off-by: Beniamino Galvani Modified to use the new clock defines and added rk3066 pins. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3188.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3xxx.dtsi | 32 ++++++++++++++++++++++++++++++ 3 files changed, 120 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 18e802c08a91..9c34da4d8aad 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -214,6 +214,30 @@ }; }; + pwm0 { + pwm0_out: pwm0-out { + rockchip,pins = ; + }; + }; + + pwm1 { + pwm1_out: pwm1-out { + rockchip,pins = ; + }; + }; + + pwm2 { + pwm2_out: pwm2-out { + rockchip,pins = ; + }; + }; + + pwm3 { + pwm3_out: pwm3-out { + rockchip,pins = ; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = , @@ -362,6 +386,26 @@ pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; }; +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_out>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_out>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_out>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_out>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index ba1193ca00a7..27215e0b5c3b 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -182,6 +182,30 @@ }; }; + pwm0 { + pwm0_out: pwm0-out { + rockchip,pins = ; + }; + }; + + pwm1 { + pwm1_out: pwm1-out { + rockchip,pins = ; + }; + }; + + pwm2 { + pwm2_out: pwm2-out { + rockchip,pins = ; + }; + }; + + pwm3 { + pwm3_out: pwm3-out { + rockchip,pins = ; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = , @@ -337,6 +361,26 @@ pinctrl-0 = <&i2c4_xfer>; }; +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_out>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_out>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_out>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_out>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 989c33785ec4..c6f05610ed2d 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -158,6 +158,38 @@ status = "disabled"; }; + pwm0: pwm@20030000 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20030000 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM01>; + status = "disabled"; + }; + + pwm1: pwm@20030010 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20030010 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM01>; + status = "disabled"; + }; + + pwm2: pwm@20050020 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050020 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM23>; + status = "disabled"; + }; + + pwm3: pwm@20050030 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050030 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM23>; + status = "disabled"; + }; + i2c2: i2c@20056000 { compatible = "rockchip,rk3066-i2c"; reg = <0x20056000 0x1000>; -- cgit v1.2.3 From 08567053f5cc4255ab53b75277b6102a3202bd75 Mon Sep 17 00:00:00 2001 From: Beniamino Galvani Date: Sun, 13 Jul 2014 14:10:01 +0200 Subject: ARM: dts: rk3188-radxarock: add GPIO IR receiver node This adds a device tree node for the infrared receiver connected to a GPIO pin on the Radxa Rock. Signed-off-by: Beniamino Galvani Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188-radxarock.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 7628b4868d2a..b7f34232e3d2 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -58,6 +58,13 @@ }; }; + ir_recv: gpio-ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 10 1>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_recv_pin>; + }; + vcc_sd0: sdmmc-regulator { compatible = "regulator-fixed"; regulator-name = "sdmmc-supply"; @@ -191,6 +198,12 @@ rockchip,pins = ; }; }; + + ir-receiver { + ir_recv_pin: ir-recv-pin { + rockchip,pins = ; + }; + }; }; &uart0 { -- cgit v1.2.3 From f07ab7a0f36a3cfcd675bf120156e36cf66d9583 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Fri, 25 Jul 2014 13:12:31 +0200 Subject: ARM: dts: zynq: Add SPI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber Reviewed-by: Soren Brinkmann Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-7000.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index cf0f3e4057cf..ef11dab30446 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -140,6 +140,30 @@ interrupts = <0 50 4>; }; + spi0: spi@e0006000 { + compatible = "xlnx,zynq-spi-r1p6"; + reg = <0xe0006000 0x1000>; + status = "disabled"; + interrupt-parent = <&intc>; + interrupts = <0 26 4>; + clocks = <&clkc 25>, <&clkc 34>; + clock-names = "ref_clk", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@e0007000 { + compatible = "xlnx,zynq-spi-r1p6"; + reg = <0xe0007000 0x1000>; + status = "disabled"; + interrupt-parent = <&intc>; + interrupts = <0 49 4>; + clocks = <&clkc 26>, <&clkc 35>; + clock-names = "ref_clk", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + gem0: ethernet@e000b000 { compatible = "cdns,gem"; reg = <0xe000b000 0x4000>; -- cgit v1.2.3 From a62451c3f91af33e47a17f17ae65de76774b2854 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 30 Jun 2014 17:15:39 -0500 Subject: ARM: dts: enable SMP support for bcm28155 Define nodes representing the two Cortex A9 CPUs in a bcm28155 SoC. Signed-off-by: Ray Jui Signed-off-by: Alex Elder Signed-off-by: Matt Porter --- arch/arm/boot/dts/bcm11351.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 6b05ae6d476f..2ddaa5136611 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -27,6 +27,25 @@ bootargs = "console=ttyS0,115200n8"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "brcm,bcm11351-cpu-method"; + secondary-boot-reg = <0x3500417c>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + gic: interrupt-controller@3ff00100 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; -- cgit v1.2.3 From 1d3138b75e3af493261c7a1e085b66b34c74dfbb Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 30 Jun 2014 17:15:40 -0500 Subject: ARM: dts: enable SMP support for bcm21664 Define nodes representing the two Cortex A9 CPUs in a bcm21644 SoC. Signed-off-by: Alex Elder Signed-off-by: Matt Porter --- arch/arm/boot/dts/bcm21664.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index 8b366822bb43..2016b72a8fb7 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi @@ -27,6 +27,25 @@ bootargs = "console=ttyS0,115200n8"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "brcm,bcm11351-cpu-method"; + secondary-boot-reg = <0x35004178>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + gic: interrupt-controller@3ff00100 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; -- cgit v1.2.3 From 40c2da45366171bdc9ad1968489aaae190248383 Mon Sep 17 00:00:00 2001 From: Benoit Masson Date: Sun, 27 Jul 2014 16:30:39 -0700 Subject: ARM: mvebu: Add dts definition for Lenovo Iomega ix4-300d NAS The Lenovo Iomega ix4-300d is a 4-Bay sata NAS with dual Gb, USB2.0 & 3.0, powered by a Marvell Armada XP MV78230 dual core CPU. http://shop.lenovo.com/us/en/servers/network-storage/lenovoemc/ix4-300d/ Signed-off-by: Benoit Masson Link: https://lkml.kernel.org/r/1406503839-4662-1-git-send-email-yahoo@perenite.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts | 284 ++++++++++++++++++++++++ 2 files changed, 286 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index abf47db584ac..d4adeee7a81e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -440,8 +440,9 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-axpwifiap.dtb \ armada-xp-db.dtb \ armada-xp-gp.dtb \ - armada-xp-netgear-rn2120.dtb \ + armada-xp-lenovo-ix4-300d.dtb \ armada-xp-matrix.dtb \ + armada-xp-netgear-rn2120.dtb \ armada-xp-openblocks-ax3-4.dtb dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \ dove-cubox.dtb \ diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts new file mode 100644 index 000000000000..469cf7137595 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts @@ -0,0 +1,284 @@ +/* + * Device Tree file for Lenovo Iomega ix4-300d + * + * Copyright (C) 2014, Benoit Masson + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include +#include +#include "armada-xp-mv78230.dtsi" + +/ { + model = "Lenovo Iomega ix4-300d"; + compatible = "lenovo,ix4-300d", "marvell,armadaxp-mv78230", + "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "/soc/internal-regs/serial@12000"; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x20000000>; /* 512MB */ + }; + + soc { + ranges = ; + + pcie-controller { + status = "okay"; + + /* Quad port sata: Marvell 88SX7042 */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* USB 3.0 xHCI controller: NEC D720200F1 */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + + internal-regs { + pinctrl { + poweroff_pin: poweroff-pin { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + power_button_pin: power-button-pin { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + reset_button_pin: reset-button-pin { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + select_button_pin: select-button-pin { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + scroll_button_pin: scroll-button-pin { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + hdd_led_pin: hdd-led-pin { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1318 */ + reg = <1>; + }; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + usb@50000 { + status = "okay"; + }; + + usb@51000 { + status = "okay"; + }; + + i2c@11000 { + clock-frequency = <400000>; + status = "okay"; + + adt7473@2e { + compatible = "adi,adt7473"; + reg = <0x2e>; + }; + + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0xe0000>; + read-only; + }; + + partition@e0000 { + label = "u-boot-env"; + reg = <0xe0000 0x20000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env2"; + reg = <0x100000 0x20000>; + read-only; + }; + + partition@120000 { + label = "zImage"; + reg = <0x120000 0x400000>; + }; + + partition@520000 { + label = "initrd"; + reg = <0x520000 0x400000>; + }; + + partition@xE00000 { + label = "boot"; + reg = <0xE00000 0x3F200000>; + }; + + partition@flash { + label = "flash"; + reg = <0x0 0x40000000>; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&power_button_pin &reset_button_pin + &select_button_pin &scroll_button_pin>; + pinctrl-names = "default"; + + power-button { + label = "Power Button"; + linux,code = ; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + reset-button { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + + select-button { + label = "Select Button"; + linux,code = ; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + + scroll-button { + label = "Scroll Button"; + linux,code = ; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + }; + + spi3 { + compatible = "spi-gpio"; + status = "okay"; + gpio-sck = <&gpio0 25 GPIO_ACTIVE_LOW>; + gpio-mosi = <&gpio1 15 GPIO_ACTIVE_LOW>; /*gpio 47*/ + cs-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <2>; + spi-max-frequency = <100000>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&hdd_led_pin>; + pinctrl-names = "default"; + + hdd-led { + label = "ix4-300d:hdd:blue"; + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + power-led { + label = "ix4-300d:power:white"; + gpios = <&gpio_spi 1 GPIO_ACTIVE_LOW>; + /* init blinking while booting */ + linux,default-trigger = "timer"; + default-state = "on"; + }; + + sysfail-led { + label = "ix4-300d:sysfail:red"; + gpios = <&gpio_spi 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + sys-led { + label = "ix4-300d:sys:blue"; + gpios = <&gpio_spi 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + hddfail-led { + label = "ix4-300d:hddfail:red"; + gpios = <&gpio_spi 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + }; + + /* + * Warning: you need both eth1 & 0 PHY initialized (i.e having + * them up does the tweak) for poweroff to shutdown otherwise it + * reboots + */ + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&poweroff_pin>; + pinctrl-names = "default"; + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + }; +}; -- cgit v1.2.3 From 79187a8e242046a0525a296509e80c5ee24fbaf1 Mon Sep 17 00:00:00 2001 From: Marc Carino Date: Wed, 26 Feb 2014 01:27:21 -0800 Subject: ARM: brcmstb: dts: add a reference DTS for Broadcom 7445 Add a sample DTS which will allow bootup of a board populated with the BCM7445 chip. Signed-off-by: Marc Carino Acked-by: Arnd Bergmann Signed-off-by: Brian Norris Cc: Matt Porter Signed-off-by: Matt Porter --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/bcm7445-bcm97445svmb.dts | 14 ++++ arch/arm/boot/dts/bcm7445.dtsi | 111 +++++++++++++++++++++++++++++ 3 files changed, 127 insertions(+) create mode 100644 arch/arm/boot/dts/bcm7445-bcm97445svmb.dts create mode 100644 arch/arm/boot/dts/bcm7445.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index adb5ed9e269e..38439ca9b361 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -59,6 +59,8 @@ dtb-$(CONFIG_ARCH_BERLIN) += \ berlin2-sony-nsz-gs7.dtb \ berlin2cd-google-chromecast.dtb \ berlin2q-marvell-dmp.dtb +dtb-$(CONFIG_ARCH_BRCMSTB) += \ + bcm7445-bcm97445svmb.dtb dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ da850-evm.dtb dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb diff --git a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts new file mode 100644 index 000000000000..9eec2ac1112f --- /dev/null +++ b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts @@ -0,0 +1,14 @@ +/dts-v1/; +#include "bcm7445.dtsi" + +/ { + model = "Broadcom STB (bcm7445), SVMB reference board"; + compatible = "brcm,bcm7445", "brcm,brcmstb"; + + memory { + device_type = "memory"; + reg = <0x00 0x00000000 0x00 0x40000000>, + <0x00 0x40000000 0x00 0x40000000>, + <0x00 0x80000000 0x00 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi new file mode 100644 index 000000000000..0ca0f4e523d0 --- /dev/null +++ b/arch/arm/boot/dts/bcm7445.dtsi @@ -0,0 +1,111 @@ +#include + +#include "skeleton.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Broadcom STB (bcm7445)"; + compatible = "brcm,bcm7445", "brcm,brcmstb"; + interrupt-parent = <&gic>; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "brcm,brahma-b15"; + device_type = "cpu"; + enable-method = "brcm,brahma-b15"; + reg = <0>; + }; + + cpu@1 { + compatible = "brcm,brahma-b15"; + device_type = "cpu"; + enable-method = "brcm,brahma-b15"; + reg = <1>; + }; + + cpu@2 { + compatible = "brcm,brahma-b15"; + device_type = "cpu"; + enable-method = "brcm,brahma-b15"; + reg = <2>; + }; + + cpu@3 { + compatible = "brcm,brahma-b15"; + device_type = "cpu"; + enable-method = "brcm,brahma-b15"; + reg = <3>; + }; + }; + + gic: interrupt-controller@ffd00000 { + compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic"; + reg = <0x00 0xffd01000 0x00 0x1000>, + <0x00 0xffd02000 0x00 0x2000>, + <0x00 0xffd04000 0x00 0x2000>, + <0x00 0xffd06000 0x00 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + rdb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x00 0xf0000000 0x1000000>; + + serial@40ab00 { + compatible = "ns16550a"; + reg = <0x40ab00 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <0x4d3f640>; + }; + + sun_top_ctrl: syscon@404000 { + compatible = "brcm,bcm7445-sun-top-ctrl", + "syscon"; + reg = <0x404000 0x51c>; + }; + + hif_cpubiuctrl: syscon@3e2400 { + compatible = "brcm,bcm7445-hif-cpubiuctrl", + "syscon"; + reg = <0x3e2400 0x5b4>; + }; + + hif_continuation: syscon@452000 { + compatible = "brcm,bcm7445-hif-continuation", + "syscon"; + reg = <0x452000 0x100>; + }; + }; + + smpboot { + compatible = "brcm,brcmstb-smpboot"; + syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>; + syscon-cont = <&hif_continuation>; + }; + + reboot { + compatible = "brcm,brcmstb-reboot"; + syscon = <&sun_top_ctrl 0x304 0x308>; + }; +}; -- cgit v1.2.3 From 0a8f59411772c890ed1263d1fa585a9ea7eecf33 Mon Sep 17 00:00:00 2001 From: Andreas Faerber Date: Tue, 29 Jul 2014 06:09:56 +0900 Subject: ARM: dts: Add PMU to exynos5410 Exynos initialization code now relies on obtaining the PMU address, so prepare a PMU node for Exynos5410. Fixes: fce9e5bb2526 ("ARM: EXYNOS: Add support for mapping PMU base address via DT") Signed-off-by: Andreas Faerber Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5410.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 9d0b8cc1409c..790d4886d7b5 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -91,6 +91,11 @@ reg = <0x10000000 0x100>; }; + pmu_system_controller: system-controller@10040000 { + compatible = "samsung,exynos5410-pmu", "syscon"; + reg = <0x10040000 0x5000>; + }; + mct: mct@101C0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0xB00>; -- cgit v1.2.3 From 98504def7cd7fdda94de8a9a90887d1dc787c609 Mon Sep 17 00:00:00 2001 From: Andreas Faerber Date: Tue, 29 Jul 2014 06:10:40 +0900 Subject: ARM: EXYNOS: Add support for Exynos5410 PMU Exynos initialization code now relies on obtaining the PMU address, so add the new 5410 value to the list of compatible string matches. This unbreaks booting on 5410 based boards. Fixes: fce9e5bb2526 ("ARM: EXYNOS: Add support for mapping PMU base address via DT") Signed-off-by: Andreas Faerber Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/exynos.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index df41bd190dfb..a83a312299a3 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -252,6 +252,7 @@ static const struct of_device_id exynos_dt_pmu_match[] = { { .compatible = "samsung,exynos4212-pmu" }, { .compatible = "samsung,exynos4412-pmu" }, { .compatible = "samsung,exynos5250-pmu" }, + { .compatible = "samsung,exynos5410-pmu" }, { .compatible = "samsung,exynos5420-pmu" }, { /*sentinel*/ }, }; -- cgit v1.2.3 From fbe4e9f55b276f515f15e869ce039fe78fc43c6c Mon Sep 17 00:00:00 2001 From: Vikas Sajjan Date: Tue, 29 Jul 2014 06:17:39 +0900 Subject: ARM: dts: Add PMU DT node for exynos5260 SoC Adds PMU DT node for exynos5260 SoC. Signed-off-by: Vikas Sajjan Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5260.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 5398a60207ca..4f2fabeecb0e 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -227,6 +227,11 @@ interrupts = <0 243 0>; }; + pmu_system_controller: system-controller@10D50000 { + compatible = "samsung,exynos5260-pmu", "syscon"; + reg = <0x10D50000 0x10000>; + }; + uart0: serial@12C00000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C00000 0x100>; -- cgit v1.2.3 From 22ead0d7024c7aa477118c83d865e773a05ef25d Mon Sep 17 00:00:00 2001 From: Vikas Sajjan Date: Tue, 29 Jul 2014 06:17:39 +0900 Subject: ARM: EXYNOS: Add exynos5260 PMU compatible string to DT match table Exynos initialisation code now relies on obtaining the PMU address via DT, so add the exynos5260 PMU compatible string to DT match table. Signed-off-by: Vikas Sajjan Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/exynos.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index a83a312299a3..493dbc23936f 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -252,6 +252,7 @@ static const struct of_device_id exynos_dt_pmu_match[] = { { .compatible = "samsung,exynos4212-pmu" }, { .compatible = "samsung,exynos4412-pmu" }, { .compatible = "samsung,exynos5250-pmu" }, + { .compatible = "samsung,exynos5260-pmu" }, { .compatible = "samsung,exynos5410-pmu" }, { .compatible = "samsung,exynos5420-pmu" }, { /*sentinel*/ }, -- cgit v1.2.3 From fdf26183781bf4c2e80b6a84146d95b875aa1b2d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 23 Jul 2014 15:03:03 +0200 Subject: ARM: zynq: DT: Add CAN node Add node describing Zynq's CAN controller. Signed-off-by: Michal Simek Reviewed-by: Soren Brinkmann --- arch/arm/boot/dts/zynq-7000.dtsi | 26 +++++++++++++++++++++++++- arch/arm/boot/dts/zynq-zc702.dts | 4 ++++ 2 files changed, 29 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index ef11dab30446..6cc83d4c6c76 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -71,7 +71,31 @@ interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; - }; + }; + + can0: can@e0008000 { + compatible = "xlnx,zynq-can-1.0"; + status = "disabled"; + clocks = <&clkc 19>, <&clkc 36>; + clock-names = "can_clk", "pclk"; + reg = <0xe0008000 0x1000>; + interrupts = <0 28 4>; + interrupt-parent = <&intc>; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + }; + + can1: can@e0009000 { + compatible = "xlnx,zynq-can-1.0"; + status = "disabled"; + clocks = <&clkc 20>, <&clkc 37>; + clock-names = "can_clk", "pclk"; + reg = <0xe0009000 0x1000>; + interrupts = <0 51 4>; + interrupt-parent = <&intc>; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 5e09cee33d42..835c3089c61c 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -29,6 +29,10 @@ }; +&can0 { + status = "okay"; +}; + &gem0 { status = "okay"; phy-mode = "rgmii"; -- cgit v1.2.3 From d1a28b686048c756940526e9c5bd0520a6017ca8 Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Mon, 28 Jul 2014 09:24:03 -0700 Subject: ARM: zynq: DT: Remove DMA from board DTs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The DMA engine is enabled for all DTs that derive from zynq-7000.dtsi. There is no need to override the 'status' property in board DTs. Signed-off-by: Soren Brinkmann Reviewed-by: Andreas Färber Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-parallella.dts | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts index 1595138ec499..41afd9da6876 100644 --- a/arch/arm/boot/dts/zynq-parallella.dts +++ b/arch/arm/boot/dts/zynq-parallella.dts @@ -34,10 +34,6 @@ }; }; -&dmac_s { - status = "okay"; -}; - &gem0 { status = "okay"; phy-mode = "rgmii-id"; -- cgit v1.2.3 From 10bc0450f09116d47e0374104868286de1066d6e Mon Sep 17 00:00:00 2001 From: Andreas Faerber Date: Wed, 30 Jul 2014 07:51:51 +0900 Subject: ARM: dts: max77686 is exynos5250-snow only Move it from exynos5250-cros-common.dtsi to exynos5250-snow.dts. Spring does not need it, it uses an s5m8767 instead. Signed-off-by: Andreas Faerber Reviewed-by: Doug Anderson Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250-cros-common.dtsi | 151 ------------------------- arch/arm/boot/dts/exynos5250-snow.dts | 154 ++++++++++++++++++++++++++ 2 files changed, 154 insertions(+), 151 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi index 89ac90f59e2e..61128d10b83c 100644 --- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi @@ -27,163 +27,12 @@ i2c2_bus: i2c2-bus { samsung,pin-pud = <0>; }; - - max77686_irq: max77686-irq { - samsung,pins = "gpx3-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; }; i2c@12C60000 { status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; - - max77686@09 { - compatible = "maxim,max77686"; - interrupt-parent = <&gpx3>; - interrupts = <2 0>; - pinctrl-names = "default"; - pinctrl-0 = <&max77686_irq>; - wakeup-source; - reg = <0x09>; - #clock-cells = <1>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "P1.0V_LDO_OUT1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "P1.8V_LDO_OUT2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "P1.8V_LDO_OUT3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "P1.1V_LDO_OUT7"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "P1.0V_LDO_OUT8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "P1.8V_LDO_OUT10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "P3.0V_LDO_OUT12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "P1.8V_LDO_OUT14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "P1.0V_LDO_OUT15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "P1.8V_LDO_OUT16"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "P1.8V_BUCK_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "P1.35V_BUCK_OUT6"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "P2.0V_BUCK_OUT7"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "P2.85V_BUCK_OUT8"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - }; - }; }; i2c@12C70000 { diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 6c36d412fd30..36212974ffed 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -432,3 +432,157 @@ }; }; }; +&i2c_0 { + max77686@09 { + compatible = "maxim,max77686"; + interrupt-parent = <&gpx3>; + interrupts = <2 0>; + pinctrl-names = "default"; + pinctrl-0 = <&max77686_irq>; + wakeup-source; + reg = <0x09>; + #clock-cells = <1>; + + voltage-regulators { + ldo1_reg: LDO1 { + regulator-name = "P1.0V_LDO_OUT1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "P1.8V_LDO_OUT2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "P1.8V_LDO_OUT3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "P1.1V_LDO_OUT7"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "P1.0V_LDO_OUT8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "P1.8V_LDO_OUT10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "P3.0V_LDO_OUT12"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo14_reg: LDO14 { + regulator-name = "P1.8V_LDO_OUT14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "P1.0V_LDO_OUT15"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "P1.8V_LDO_OUT16"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "P1.8V_BUCK_OUT5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "P1.35V_BUCK_OUT6"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "P2.0V_BUCK_OUT7"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "P2.85V_BUCK_OUT8"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + }; + }; +}; + +&pinctrl_0 { + max77686_irq: max77686-irq { + samsung,pins = "gpx3-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; -- cgit v1.2.3 From 3428f20b65ec0d24be0adbc819e2bfb2eacb0bc2 Mon Sep 17 00:00:00 2001 From: Andreas Faerber Date: Wed, 30 Jul 2014 07:51:56 +0900 Subject: ARM: dts: cypress,cyapa trackpad is exynos5250-Snow only Move it from exynos5250-cros-common.dtsi to exynos5250-snow.dts. Spring does not need it, it uses an Atmel maXTouch instead. Signed-off-by: Andreas Faerber Reviewed-by: Doug Anderson Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250-cros-common.dtsi | 8 -------- arch/arm/boot/dts/exynos5250-snow.dts | 11 +++++++++++ 2 files changed, 11 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi index 61128d10b83c..e603e9c70142 100644 --- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi @@ -39,14 +39,6 @@ status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; - - trackpad { - reg = <0x67>; - compatible = "cypress,cyapa"; - interrupts = <2 0>; - interrupt-parent = <&gpx1>; - wakeup-source; - }; }; i2c@12C80000 { diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 36212974ffed..7c4bdaaf4879 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -432,6 +432,7 @@ }; }; }; + &i2c_0 { max77686@09 { compatible = "maxim,max77686"; @@ -578,6 +579,16 @@ }; }; +&i2c_1 { + trackpad { + reg = <0x67>; + compatible = "cypress,cyapa"; + interrupts = <2 0>; + interrupt-parent = <&gpx1>; + wakeup-source; + }; +}; + &pinctrl_0 { max77686_irq: max77686-irq { samsung,pins = "gpx3-2"; -- cgit v1.2.3 From 47580e8d94c2a3baac6713533ae765c2087b34d9 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Wed, 30 Jul 2014 07:54:46 +0900 Subject: ARM: dts: Specify MAX77686 pmic interrupt for exynos5250-smdk5250 The IRQB interrupt pin of MAX77686 PMIC is connected to GPX3[2] pin of Exynos5250 on the Exynos5250 SMDK board. Specify this connection using interrupts property for the max77686 pmic node. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250-smdk5250.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index a794a705d404..aaa055ac0fe3 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -44,6 +44,8 @@ max77686@09 { compatible = "maxim,max77686"; reg = <0x09>; + interrupt-parent = <&gpx3>; + interrupts = <2 0>; voltage-regulators { ldo1_reg: LDO1 { -- cgit v1.2.3 From 9dfb33477d141737e496f6a472d87f177ed38bd1 Mon Sep 17 00:00:00 2001 From: Chanwoo Choi Date: Wed, 30 Jul 2014 07:57:24 +0900 Subject: ARM: dts: Add TMU dt node to monitor the temperature for exynos3250 This patch add TMU (Thermal Management Unit) dt node to monitor the high temperature for Exynos3250. Signed-off-by: Chanwoo Choi Acked-by: Kyungmin Park Acked-by: Eduardo Valentin Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos3250.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 77a06df6dc72..41a260a7db2a 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -168,6 +168,15 @@ status = "disabled"; }; + tmu: tmu@100C0000 { + compatible = "samsung,exynos3250-tmu"; + reg = <0x100C0000 0x100>; + interrupts = <0 216 0>; + clocks = <&cmu CLK_TMU_APBIF>; + clock-names = "tmu_apbif"; + status = "disabled"; + }; + gic: interrupt-controller@10481000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; -- cgit v1.2.3 From 81632461f3dad24d9896ec8bc1fbdd6850cc1909 Mon Sep 17 00:00:00 2001 From: Chanwoo Choi Date: Wed, 30 Jul 2014 07:57:28 +0900 Subject: ARM: dts: Remove duplicate 'interrput-parent' property for exynos3250 This patch removes duplicat 'interrupt-parent' property for Exynos3250 because exynos3250.dtsi already defined 'interrupt-parent' property as following: In arch/arm/boot/dts/exynos3250.dtsi: compatible = "samsung,exynos3250"; interrupt-parent = <&gic>; Signed-off-by: Chanwoo Choi Acked-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos3250.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 41a260a7db2a..5043178af395 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -204,7 +204,6 @@ wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; interrupts = <0 48 0>; }; }; @@ -243,7 +242,6 @@ compatible = "arm,amba-bus"; #address-cells = <1>; #size-cells = <1>; - interrupt-parent = <&gic>; ranges; pdma0: pdma@12680000 { -- cgit v1.2.3 From a9408a6bba0de106d702fe5fa36fdc545116e9ab Mon Sep 17 00:00:00 2001 From: Chanwoo Choi Date: Wed, 30 Jul 2014 07:57:32 +0900 Subject: ARM: dts: Add missing pinctrl for uart0/1 for exynos3250 This patch add missing pinctrl for uart0/1 for Exynos3250. The gpio pin ( uart0_data, uart0_fctl, uart1_data) is only used for UART IP. Signed-off-by: Chanwoo Choi Acked-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos3250.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 5043178af395..abd6eb31b2c2 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -284,6 +284,8 @@ interrupts = <0 109 0>; clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_data &uart0_fctl>; status = "disabled"; }; @@ -293,6 +295,8 @@ interrupts = <0 110 0>; clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_data>; status = "disabled"; }; -- cgit v1.2.3 From 23c93bc92ca13094254277816e6b672d4bb4f24c Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 30 Jul 2014 12:05:55 +0200 Subject: ARM: dts: rockchip: remove pinctrl setting from radxarock uart2 We set default pinctrl settings for the uarts in rk3188.dtsi already, so remove forgotten duplicate. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188-radxarock.dts | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index b7f34232e3d2..4195f5a99e63 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -215,8 +215,6 @@ }; &uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; status = "okay"; }; -- cgit v1.2.3 From eb2b9d47dd907eba5d766d942723811393454346 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 30 Jul 2014 10:16:17 +0200 Subject: ARM: dts: rockchip: add watchdog node This adds the Designware compatible watchdog found on RK3xxx Cortex-A9 SoCs. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 4 ++++ arch/arm/boot/dts/rk3066a.dtsi | 4 ++++ arch/arm/boot/dts/rk3188-radxarock.dts | 4 ++++ arch/arm/boot/dts/rk3188.dtsi | 4 ++++ arch/arm/boot/dts/rk3xxx.dtsi | 8 ++++++++ 5 files changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 8b479f767561..042f821d9e4d 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -188,3 +188,7 @@ &uart3 { status = "okay"; }; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 9c34da4d8aad..879a818fba51 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -425,3 +425,7 @@ pinctrl-names = "default"; pinctrl-0 = <&uart3_xfer>; }; + +&wdt { + compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; +}; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 4195f5a99e63..171b610db709 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -221,3 +221,7 @@ &uart3 { status = "okay"; }; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 27215e0b5c3b..ee801a9c6b74 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -400,3 +400,7 @@ pinctrl-names = "default"; pinctrl-0 = <&uart3_xfer>; }; + +&wdt { + compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; +}; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index c6f05610ed2d..8caf85d83901 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -174,6 +174,14 @@ status = "disabled"; }; + wdt: watchdog@2004c000 { + compatible = "snps,dw-wdt"; + reg = <0x2004c000 0x100>; + clocks = <&cru PCLK_WDT>; + interrupts = ; + status = "disabled"; + }; + pwm2: pwm@20050020 { compatible = "rockchip,rk2928-pwm"; reg = <0x20050020 0x10>; -- cgit v1.2.3 From 067cc28670c53f919ebf821bc123f1097ae4283b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 25 Jul 2014 12:40:02 -0600 Subject: ARM: tegra: paz00: Fix some indentation inconsistencies Indentation of the clock property used a hodgepodge of tabs and spaces. Make them more consistent (tabs for indentation followed by spaces for alignment). Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/boot/dts/tegra20-paz00.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 9a39a8001f78..d4438e30de45 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -296,7 +296,7 @@ request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; slave-addr = <138>; clocks = <&tegra_car TEGRA20_CLK_I2C3>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; resets = <&tegra_car 67>; reset-names = "i2c"; @@ -589,8 +589,8 @@ GPIO_ACTIVE_HIGH>; clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; -- cgit v1.2.3 From ae171be4e08b86bb24b3591be49d6e29940abff8 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 25 Jul 2014 12:40:03 -0600 Subject: ARM: tegra: apalis t30: fix device tree compatible node Working on sound support I noticed the Apalis T30 Evaluation board device tree missing the more generic Apalis T30 compatible string. Signed-off-by: Marcel Ziswiler Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 992143372af0..45d40f024585 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -5,7 +5,7 @@ / { model = "Toradex Apalis T30 on Apalis Evaluation Board"; - compatible = "toradex,apalis_t30-eval", "nvidia,tegra30"; + compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30", "nvidia,tegra30"; aliases { rtc0 = "/i2c@7000c000/rtc@68"; -- cgit v1.2.3 From 83a742b431501c1cf971983fa1911ae5d4b0440c Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Wed, 30 Jul 2014 13:00:10 -0700 Subject: ARM: dts: Turn on USB host vbus on rk3288-evb There is no phy driver that works on the Rockchip board for either USB host port yet. For now just hardcode the vbus signal to be on all the time which makes both the dwc2 host and the EHCI port work. Signed-off-by: Doug Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-evb.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 749e20db3b37..e6c5b03de3c0 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -35,6 +35,18 @@ debounce-interval = <100>; }; }; + + /* This turns on USB vbus for both host0 (ehci) and host1 (dwc2) */ + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + }; }; &i2c0 { @@ -71,4 +83,10 @@ rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; -- cgit v1.2.3 From beb4b3f56e342a6ac9b6920bb9b08473c2e37485 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Wed, 30 Jul 2014 13:00:11 -0700 Subject: ARM: dts: add rk3288 ehci usb devices rk3288 has two kind of usb controller; this adds the ehci variant for host0 and hsic. At the moment we don't add any phys for these controllers, but the default settings seem to work OK. There is a hardware problem in ohci controller which make it unavailable and host0 controller can only support high-speed devices. Signed-off-by: Kever Yang Signed-off-by: Doug Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 3ef89512c942..e7cb00873dd4 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -251,6 +251,26 @@ status = "disabled"; }; + usb_host0_ehci: usb@ff500000 { + compatible = "generic-ehci"; + reg = <0xff500000 0x100>; + interrupts = ; + clocks = <&cru HCLK_USBHOST0>; + clock-names = "usbhost"; + status = "disabled"; + }; + + /* NOTE: ohci@ff520000 doesn't actually work on hardware */ + + usb_hsic: usb@ff5c0000 { + compatible = "generic-ehci"; + reg = <0xff5c0000 0x100>; + interrupts = ; + clocks = <&cru HCLK_HSIC>; + clock-names = "usbhost"; + status = "disabled"; + }; + gic: interrupt-controller@ffc01000 { compatible = "arm,gic-400"; interrupt-controller; -- cgit v1.2.3 From 163cb917b836184c42f185b8fbd9185e20c5f499 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Wed, 30 Jul 2014 13:00:12 -0700 Subject: ARM: dts: Enable USB host0 (EHCI) on rk3288-evb This is the top USB port on the evb (the one closest to the Ethernet connector). Signed-off-by: Doug Anderson Signed-off-by: Kever Yang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-evb.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index e6c5b03de3c0..4f572093c8b4 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -90,3 +90,7 @@ }; }; }; + +&usb_host0_ehci { + status = "okay"; +}; -- cgit v1.2.3