From 1b362e3e350f72c6cb4b3346f6ba92a529082a09 Mon Sep 17 00:00:00 2001 From: David Daney Date: Fri, 22 Jan 2010 14:41:15 -0800 Subject: MIPS: Decode c0_config4 for large TLBs. For processors that have more than 64 TLBs, we need to decode both config1 and config4 to determine the total number TLBs. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/866/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/mips/kernel/cpu-probe.c') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 758ad426c57f..323395081b2a 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -700,6 +700,19 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) return config3 & MIPS_CONF_M; } +static inline unsigned int decode_config4(struct cpuinfo_mips *c) +{ + unsigned int config4; + + config4 = read_c0_config4(); + + if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT + && cpu_has_tlb) + c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; + + return config4 & MIPS_CONF_M; +} + static void __cpuinit decode_configs(struct cpuinfo_mips *c) { int ok; @@ -718,6 +731,8 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c) ok = decode_config2(c); if (ok) ok = decode_config3(c); + if (ok) + ok = decode_config4(c); mips_probe_watch_registers(c); } -- cgit v1.2.3 From 2fe062608086f9b74a80f16272c5a59a3e05722f Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Wed, 20 Jan 2010 00:59:27 +0100 Subject: MIPS: Cleanup switches with cases that can be merged Signed-off-by: Roel Kluin To: linux-mips@linux-mips.org To: Andrew Morton To: LKML Patchwork: http://patchwork.linux-mips.org/patch/860/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/mips/kernel/cpu-probe.c') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 323395081b2a..1773544e3dbb 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -746,9 +746,6 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "MIPS 4Kc"; break; case PRID_IMP_4KEC: - c->cputype = CPU_4KEC; - __cpu_name[cpu] = "MIPS 4KEc"; - break; case PRID_IMP_4KECR2: c->cputype = CPU_4KEC; __cpu_name[cpu] = "MIPS 4KEc"; -- cgit v1.2.3 From 874fd3b5acc20f2a464409045aef3b2288069787 Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 28 Jan 2010 16:52:12 -0800 Subject: MIPS: Allow the auxv's elf_platform entry to be set. The userspace runtime linker uses the elf_platform to find the libraries optimized for the current CPU archecture variant. First we need to allow it to be set to something other than NULL. Follow-on patches will set some values for specific CPUs. GLIBC already does the right thing. The kernel just needs to supply good data. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/891/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/mips/kernel/cpu-probe.c') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 1773544e3dbb..494e8ab48d63 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -926,6 +926,7 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) } const char *__cpu_name[NR_CPUS]; +const char *__elf_platform; __cpuinit void cpu_probe(void) { -- cgit v1.2.3 From 368bf8ef304f426be0a8a0be5b0e437747598c10 Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 28 Jan 2010 16:52:13 -0800 Subject: MIPS: Set __elf_platform for Octeon. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/892/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/mips/kernel/cpu-probe.c') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 494e8ab48d63..9ea5ca89e85f 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -917,6 +917,8 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) case PRID_IMP_CAVIUM_CN52XX: c->cputype = CPU_CAVIUM_OCTEON; __cpu_name[cpu] = "Cavium Octeon"; + if (cpu == 0) + __elf_platform = "octeon"; break; default: printk(KERN_INFO "Unknown Octeon chip!\n"); -- cgit v1.2.3 From 6f329468f3086e9d8f3832930fdb09ab3769176b Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 10 Feb 2010 15:12:48 -0800 Subject: MIPS: Give Octeon+ CPUs their own cputype. This allows us to treat them differently at runtime. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/951/ Patchwork: http://patchwork.linux-mips.org/patch/987/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'arch/mips/kernel/cpu-probe.c') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 9ea5ca89e85f..be5bb16be4e0 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -162,6 +162,7 @@ void __init check_wait(void) case CPU_BCM6348: case CPU_BCM6358: case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: cpu_wait = r4k_wait; break; @@ -911,12 +912,16 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) case PRID_IMP_CAVIUM_CN38XX: case PRID_IMP_CAVIUM_CN31XX: case PRID_IMP_CAVIUM_CN30XX: + c->cputype = CPU_CAVIUM_OCTEON; + __cpu_name[cpu] = "Cavium Octeon"; + goto platform; case PRID_IMP_CAVIUM_CN58XX: case PRID_IMP_CAVIUM_CN56XX: case PRID_IMP_CAVIUM_CN50XX: case PRID_IMP_CAVIUM_CN52XX: - c->cputype = CPU_CAVIUM_OCTEON; - __cpu_name[cpu] = "Cavium Octeon"; + c->cputype = CPU_CAVIUM_OCTEON_PLUS; + __cpu_name[cpu] = "Cavium Octeon+"; +platform: if (cpu == 0) __elf_platform = "octeon"; break; -- cgit v1.2.3