From 641e97f318870921d048154af6807e46e43c307a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:05 +0100 Subject: [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle --- arch/mips/mm/cache.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'arch/mips/mm/cache.c') diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 81f925a9a731..43dde874f414 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -3,13 +3,14 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994 - 2003, 07 by Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 1994 - 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 2007 MIPS Technologies, Inc. */ #include #include #include #include +#include #include #include #include @@ -157,12 +158,6 @@ void __init cpu_cache_init(void) tx39_cache_init(); return; } - if (cpu_has_sb1_cache) { - extern void __weak sb1_cache_init(void); - - sb1_cache_init(); - return; - } panic(cache_panic); } -- cgit v1.2.3