From 55c44991e2910519bab274c857d95a08100ff5f7 Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Tue, 10 Jul 2007 18:44:34 +0800 Subject: [POWERPC] Create common fsl pci/e files based on 86xx platforms Move arch/powerpc/platforms/86xx/pci.c -> arch/powerpc/sysdev/fsl_pci.c arch/powerpc/sysdev/fsl_pcie.h -> arch/powerpc/sysdev/fsl_pci.h as the base to unify 83xx/85xx/86xx pci and pcie. Add CONFIG_FSL_PCI to build fsl_pci.c for Freescale pci and pcie option. The code still works for 86xx platforms. Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 238 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 238 insertions(+) create mode 100644 arch/powerpc/sysdev/fsl_pci.c (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c new file mode 100644 index 000000000000..24ba1b6b31fb --- /dev/null +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -0,0 +1,238 @@ +/* + * MPC86XX pci setup code + * + * Recode: ZHANG WEI + * Initial author: Xianghua Xiao + * + * Copyright 2006 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "../platforms/86xx/mpc86xx.h" + +#undef DEBUG + +#ifdef DEBUG +#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) +#else +#define DBG(fmt, args...) +#endif + +struct pcie_outbound_window_regs { + uint pexotar; /* 0x.0 - PCI Express outbound translation address register */ + uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */ + uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */ + char res1[4]; + uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */ + char res2[12]; +}; + +struct pcie_inbound_window_regs { + uint pexitar; /* 0x.0 - PCI Express inbound translation address register */ + char res1[4]; + uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */ + uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */ + uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */ + char res2[12]; +}; + +static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc) +{ + volatile struct ccsr_pex *pcie; + volatile struct pcie_outbound_window_regs *pcieow; + volatile struct pcie_inbound_window_regs *pcieiw; + int i = 0; + + DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start, + rsrc->end - rsrc->start + 1); + pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); + + /* Disable all windows (except pexowar0 since its ignored) */ + pcie->pexowar1 = 0; + pcie->pexowar2 = 0; + pcie->pexowar3 = 0; + pcie->pexowar4 = 0; + pcie->pexiwar1 = 0; + pcie->pexiwar2 = 0; + pcie->pexiwar3 = 0; + + pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1; + pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1; + + /* Setup outbound MEM window */ + for(i = 0; i < 3; i++) + if (hose->mem_resources[i].flags & IORESOURCE_MEM){ + DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n", + hose->mem_resources[i].start, + hose->mem_resources[i].end + - hose->mem_resources[i].start + 1); + pcieow->pexotar = (hose->mem_resources[i].start) >> 12 + & 0x000fffff; + pcieow->pexotear = 0; + pcieow->pexowbar = (hose->mem_resources[i].start) >> 12 + & 0x000fffff; + /* Enable, Mem R/W */ + pcieow->pexowar = 0x80044000 | + (__ilog2(hose->mem_resources[i].end + - hose->mem_resources[i].start + 1) + - 1); + pcieow++; + } + + /* Setup outbound IO window */ + if (hose->io_resource.flags & IORESOURCE_IO){ + DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n", + hose->io_resource.start, + hose->io_resource.end - hose->io_resource.start + 1, + hose->io_base_phys); + pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff; + pcieow->pexotear = 0; + pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff; + /* Enable, IO R/W */ + pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end + - hose->io_resource.start + 1) - 1); + } + + /* Setup 2G inbound Memory Window @ 0 */ + pcieiw->pexitar = 0x00000000; + pcieiw->pexiwbar = 0x00000000; + /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */ + pcieiw->pexiwar = 0xa0f5501e; +} + +static void __init +mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size) +{ + u16 cmd; + + DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n", + pcie_offset, pcie_size); + + early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY + | PCI_COMMAND_IO; + early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); + + early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); +} + +static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) +{ + struct resource *res; + int i, res_idx = PCI_BRIDGE_RESOURCES; + struct pci_controller *hose; + + /* + * Make the bridge be transparent. + */ + dev->transparent = 1; + + hose = pci_bus_to_host(dev->bus); + if (!hose) { + printk(KERN_ERR "Can't find hose for bus %d\n", + dev->bus->number); + return; + } + + if (hose->io_resource.flags) { + res = &dev->resource[res_idx++]; + res->start = hose->io_resource.start; + res->end = hose->io_resource.end; + res->flags = hose->io_resource.flags; + } + + for (i = 0; i < 3; i++) { + res = &dev->resource[res_idx + i]; + res->start = hose->mem_resources[i].start; + res->end = hose->mem_resources[i].end; + res->flags = hose->mem_resources[i].flags; + } +} + + +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); + +#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */ +#define PCIE_LTSSM_L0 0x16 /* L0 state */ + +int __init mpc86xx_add_bridge(struct device_node *dev) +{ + int len; + struct pci_controller *hose; + struct resource rsrc; + const int *bus_range; + int has_address = 0; + int primary = 0; + u16 val; + + DBG("Adding PCIE host bridge %s\n", dev->full_name); + + /* Fetch host bridge registers address */ + has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); + + /* Get bus range if any */ + bus_range = of_get_property(dev, "bus-range", &len); + if (bus_range == NULL || len < 2 * sizeof(int)) + printk(KERN_WARNING "Can't get bus-range for %s, assume" + " bus 0\n", dev->full_name); + + pci_assign_all_buses = 1; + hose = pcibios_alloc_controller(dev); + if (!hose) + return -ENOMEM; + + hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG | + PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; + + hose->first_busno = bus_range ? bus_range[0] : 0x0; + hose->last_busno = bus_range ? bus_range[1] : 0xff; + + setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); + + /* Probe the hose link training status */ + early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val); + if (val < PCIE_LTSSM_L0) + return -ENXIO; + + /* Setup the PCIE host controller. */ + mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1); + + if ((rsrc.start & 0xfffff) == 0x8000) + primary = 1; + + printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. " + "Firmware bus number: %d->%d\n", + (unsigned long) rsrc.start, + hose->first_busno, hose->last_busno); + + DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", + hose, hose->cfg_addr, hose->cfg_data); + + /* Interpret the "ranges" property */ + /* This also maps the I/O region and sets isa_io/mem_base */ + pci_process_bridge_OF_ranges(hose, dev, primary); + + /* Setup PEX window registers */ + setup_pcie_atmu(hose, &rsrc); + + return 0; +} -- cgit v1.2.3 From 9ac4dd301eebb3cd8de801e02bfc91f296e56f63 Mon Sep 17 00:00:00 2001 From: Zang Roy-r61911 Date: Tue, 10 Jul 2007 18:46:35 +0800 Subject: [POWERPC] Rewrite Freescale PCI/PCIe support for 8{3,5,6}xx Rewrite the Freescale PCI code to support PCI on 83xx/85xx/86xx and PCIe on 85xx/86xx. Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 244 ++++++++++++++++++------------------------ 1 file changed, 105 insertions(+), 139 deletions(-) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 24ba1b6b31fb..10c47b56702e 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -1,136 +1,98 @@ /* - * MPC86XX pci setup code + * MPC85xx/86xx PCI/PCIE support routing. * - * Recode: ZHANG WEI - * Initial author: Xianghua Xiao + * Copyright 2007 Freescale Semiconductor, Inc * - * Copyright 2006 Freescale Semiconductor Inc. + * Initial author: Xianghua Xiao + * Recode: ZHANG WEI + * Rewrite the routing for Frescale PCI and PCI Express + * Roy Zang * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ - -#include -#include -#include +#include #include -#include +#include +#include +#include +#include -#include -#include #include #include #include +#include #include #include -#include "../platforms/86xx/mpc86xx.h" - -#undef DEBUG - -#ifdef DEBUG -#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) -#else -#define DBG(fmt, args...) -#endif - -struct pcie_outbound_window_regs { - uint pexotar; /* 0x.0 - PCI Express outbound translation address register */ - uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */ - uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */ - char res1[4]; - uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */ - char res2[12]; -}; - -struct pcie_inbound_window_regs { - uint pexitar; /* 0x.0 - PCI Express inbound translation address register */ - char res1[4]; - uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */ - uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */ - uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */ - char res2[12]; -}; - -static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc) +/* atmu setup for fsl pci/pcie controller */ +void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc) { - volatile struct ccsr_pex *pcie; - volatile struct pcie_outbound_window_regs *pcieow; - volatile struct pcie_inbound_window_regs *pcieiw; - int i = 0; + struct ccsr_pci __iomem *pci; + int i; - DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start, + pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start, rsrc->end - rsrc->start + 1); - pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); - - /* Disable all windows (except pexowar0 since its ignored) */ - pcie->pexowar1 = 0; - pcie->pexowar2 = 0; - pcie->pexowar3 = 0; - pcie->pexowar4 = 0; - pcie->pexiwar1 = 0; - pcie->pexiwar2 = 0; - pcie->pexiwar3 = 0; - - pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1; - pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1; - - /* Setup outbound MEM window */ - for(i = 0; i < 3; i++) - if (hose->mem_resources[i].flags & IORESOURCE_MEM){ - DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n", - hose->mem_resources[i].start, - hose->mem_resources[i].end - - hose->mem_resources[i].start + 1); - pcieow->pexotar = (hose->mem_resources[i].start) >> 12 - & 0x000fffff; - pcieow->pexotear = 0; - pcieow->pexowbar = (hose->mem_resources[i].start) >> 12 - & 0x000fffff; - /* Enable, Mem R/W */ - pcieow->pexowar = 0x80044000 | - (__ilog2(hose->mem_resources[i].end - - hose->mem_resources[i].start + 1) - - 1); - pcieow++; - } - - /* Setup outbound IO window */ - if (hose->io_resource.flags & IORESOURCE_IO){ - DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n", - hose->io_resource.start, - hose->io_resource.end - hose->io_resource.start + 1, - hose->io_base_phys); - pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff; - pcieow->pexotear = 0; - pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff; - /* Enable, IO R/W */ - pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end - - hose->io_resource.start + 1) - 1); - } - - /* Setup 2G inbound Memory Window @ 0 */ - pcieiw->pexitar = 0x00000000; - pcieiw->pexiwbar = 0x00000000; - /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */ - pcieiw->pexiwar = 0xa0f5501e; + pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); + + /* Disable all windows (except powar0 since its ignored) */ + for(i = 1; i < 5; i++) + out_be32(&pci->pow[i].powar, 0); + for(i = 0; i < 3; i++) + out_be32(&pci->piw[i].piwar, 0); + + /* Setup outbound MEM window */ + for(i = 0; i < 3; i++) + if (hose->mem_resources[i].flags & IORESOURCE_MEM){ + pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n", + hose->mem_resources[i].start, + hose->mem_resources[i].end + - hose->mem_resources[i].start + 1); + out_be32(&pci->pow[i+1].potar, + (hose->mem_resources[i].start >> 12) + & 0x000fffff); + out_be32(&pci->pow[i+1].potear, 0); + out_be32(&pci->pow[i+1].powbar, + (hose->mem_resources[i].start >> 12) + & 0x000fffff); + /* Enable, Mem R/W */ + out_be32(&pci->pow[i+1].powar, 0x80044000 + | (__ilog2(hose->mem_resources[i].end + - hose->mem_resources[i].start + 1) - 1)); + } + + /* Setup outbound IO window */ + if (hose->io_resource.flags & IORESOURCE_IO){ + pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n", + hose->io_resource.start, + hose->io_resource.end - hose->io_resource.start + 1, + hose->io_base_phys); + out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12) + & 0x000fffff); + out_be32(&pci->pow[i+1].potear, 0); + out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12) + & 0x000fffff); + /* Enable, IO R/W */ + out_be32(&pci->pow[i+1].powar, 0x80088000 + | (__ilog2(hose->io_resource.end + - hose->io_resource.start + 1) - 1)); + } + + /* Setup 2G inbound Memory Window @ 1 */ + out_be32(&pci->piw[2].pitar, 0x00000000); + out_be32(&pci->piw[2].piwbar,0x00000000); + out_be32(&pci->piw[2].piwar, PIWAR_2G); } -static void __init -mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size) +void __init setup_pci_cmd(struct pci_controller *hose) { u16 cmd; - - DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n", - pcie_offset, pcie_size); - early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY - | PCI_COMMAND_IO; + | PCI_COMMAND_IO; early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); - early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); } @@ -167,72 +129,76 @@ static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) } } +int __init fsl_pcie_check_link(struct pci_controller *hose) +{ + u16 val; + early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val); + if (val < PCIE_LTSSM_L0) + return 1; + return 0; +} -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); - -#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */ -#define PCIE_LTSSM_L0 0x16 /* L0 state */ - -int __init mpc86xx_add_bridge(struct device_node *dev) +int __init fsl_add_bridge(struct device_node *dev, int is_primary) { int len; struct pci_controller *hose; struct resource rsrc; const int *bus_range; - int has_address = 0; - int primary = 0; - u16 val; - DBG("Adding PCIE host bridge %s\n", dev->full_name); + pr_debug("Adding PCI host bridge %s\n", dev->full_name); /* Fetch host bridge registers address */ - has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); + if (of_address_to_resource(dev, 0, &rsrc)) { + printk(KERN_WARNING "Can't get pci register base!"); + return -ENOMEM; + } /* Get bus range if any */ bus_range = of_get_property(dev, "bus-range", &len); if (bus_range == NULL || len < 2 * sizeof(int)) printk(KERN_WARNING "Can't get bus-range for %s, assume" - " bus 0\n", dev->full_name); + " bus 0\n", dev->full_name); pci_assign_all_buses = 1; hose = pcibios_alloc_controller(dev); if (!hose) return -ENOMEM; - hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG | - PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; - hose->first_busno = bus_range ? bus_range[0] : 0x0; hose->last_busno = bus_range ? bus_range[1] : 0xff; - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); - - /* Probe the hose link training status */ - early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val); - if (val < PCIE_LTSSM_L0) - return -ENXIO; + /* check PCI express bridge */ + if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") || + of_device_is_compatible(dev, "fsl,mpc8641-pcie")) + hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG | + PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; - /* Setup the PCIE host controller. */ - mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1); + setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); + setup_pci_cmd(hose); - if ((rsrc.start & 0xfffff) == 0x8000) - primary = 1; + /* check PCI express link status */ + if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") || + of_device_is_compatible(dev, "fsl,mpc8641-pcie")) + if (fsl_pcie_check_link(hose)) + return -ENXIO; - printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. " - "Firmware bus number: %d->%d\n", - (unsigned long) rsrc.start, - hose->first_busno, hose->last_busno); + printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx." + "Firmware bus number: %d->%d\n", + (unsigned long long)rsrc.start, hose->first_busno, + hose->last_busno); - DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", + pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", hose, hose->cfg_addr, hose->cfg_data); /* Interpret the "ranges" property */ /* This also maps the I/O region and sets isa_io/mem_base */ - pci_process_bridge_OF_ranges(hose, dev, primary); + pci_process_bridge_OF_ranges(hose, dev, is_primary); /* Setup PEX window registers */ - setup_pcie_atmu(hose, &rsrc); + setup_pci_atmu(hose, &rsrc); return 0; } + +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); -- cgit v1.2.3 From 957ecffc2527ebd414c6e35b65f0f744739b012d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 11 Jul 2007 13:31:58 -0500 Subject: [POWERPC] FSL: Cleanup how we detect if we are a PCIe controller Use the PCI capabilities to determine if we are PCIe PHB. Also use PPC_INDIRECT_TYPE_NO_PCIE_LINK since the Freescale PCIe controllers will lock the system if they don't have link and you try to do a config access to anything but the PHB. Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 10c47b56702e..69d3c6eee83d 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -102,6 +102,10 @@ static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) int i, res_idx = PCI_BRIDGE_RESOURCES; struct pci_controller *hose; + /* if we aren't a PCIe don't bother */ + if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) + return ; + /* * Make the bridge be transparent. */ @@ -167,20 +171,16 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) hose->first_busno = bus_range ? bus_range[0] : 0x0; hose->last_busno = bus_range ? bus_range[1] : 0xff; - /* check PCI express bridge */ - if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") || - of_device_is_compatible(dev, "fsl,mpc8641-pcie")) - hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG | - PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); setup_pci_cmd(hose); /* check PCI express link status */ - if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") || - of_device_is_compatible(dev, "fsl,mpc8641-pcie")) + if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { + hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG | + PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; if (fsl_pcie_check_link(hose)) - return -ENXIO; + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; + } printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx." "Firmware bus number: %d->%d\n", -- cgit v1.2.3 From 3f6c5dae277d43b4fe2dd77a5984b0ef9aee52c6 Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Tue, 10 Jul 2007 18:47:06 +0800 Subject: [POWERPC] Use Freescale pci/pcie common code for 85xx boards Switch the 85xx platform over to using the FSL generic PCI code. This gets ups PCIe support in addition to base PCI support. Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 69d3c6eee83d..2eefcde5b0da 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -200,5 +200,12 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) return 0; } +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0012, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0013, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0014, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0015, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0018, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0019, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x001a, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); -- cgit v1.2.3 From 6c0a11c118471f79795202348fbd0e6580341794 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Jul 2007 15:29:53 -0500 Subject: [POWERPC] Fixup resources on pci_bus for PCIe PHB when no device is connected On the 85xx/86xx PCIe controllers if there is no device connected to the PHB we will still allocate a pci_bus for downstream bus of the virtual P2P bridge. However the resources allocated to the downstream bus are not correct and so we just mimic the resources from the upstream pci_bus. Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 2eefcde5b0da..faafae601a72 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -142,6 +142,20 @@ int __init fsl_pcie_check_link(struct pci_controller *hose) return 0; } +void fsl_pcibios_fixup_bus(struct pci_bus *bus) +{ + struct pci_controller *hose = (struct pci_controller *) bus->sysdata; + int i; + + /* deal with bogus pci_bus when we don't have anything connected on PCIe */ + if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) { + if (bus->parent) { + for (i = 0; i < 4; ++i) + bus->resource[i] = bus->parent->resource[i]; + } + } +} + int __init fsl_add_bridge(struct device_node *dev, int is_primary) { int len; -- cgit v1.2.3 From aa3c112146e387dcd68bea2a8354514fe725da0d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 16 Jul 2007 10:45:07 -0500 Subject: [POWERPC] 85xx: Added 8568 PCIe support Added the PCIe device node to the 8568 dts and the needed quirk entries. Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index faafae601a72..c6a30f9c2073 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -221,5 +221,9 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0015, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0018, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0019, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x001a, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0020, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0021, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0024, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0025, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); -- cgit v1.2.3 From 2e56ff206b7c6c28b847ccdbe46ad69b3263ac32 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Jul 2007 16:07:35 -0500 Subject: [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime Make it so we do a runtime check to know if we need to write cfg_addr as big or little endian. This is needed if we want to allow 86xx support to co-exist in the same kernel as other 6xx PPCs. Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index c6a30f9c2073..d7747e05d1da 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -185,7 +185,8 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) hose->first_busno = bus_range ? bus_range[0] : 0x0; hose->last_busno = bus_range ? bus_range[1] : 0xff; - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); + setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, + PPC_INDIRECT_TYPE_BIG_ENDIAN); setup_pci_cmd(hose); /* check PCI express link status */ -- cgit v1.2.3 From f16dab981aa9d423bdfe096e3422acd33d905c1e Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Fri, 13 Jul 2007 18:05:08 +0800 Subject: [POWERPC] Add basic PCI/PCI Express support for 8544DS board Add basic support for the PCIe PHB and enable the ULI bridge. Signed-off-by: York Sun Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index d7747e05d1da..dcd0ca86bdf6 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -226,5 +226,7 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0020, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0021, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0024, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0025, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0030, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0031, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); -- cgit v1.2.3 From 7391ff35b241dbcba471e05059b5c05fdc8196db Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 20 Jul 2007 13:49:29 -0500 Subject: [POWERPC] Make sure virtual P2P bridge registers are setup on PCIe PHB For the Freescale PCIe PHBs Not all firmwares setup the virtual P2P bridge registers properly. Make sure they get setup based on what the struct pci_controller got from the device tree. Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index dcd0ca86bdf6..f88a9aecdf16 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -118,11 +118,24 @@ static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) return; } + /* Clear out any of the virtual P2P bridge registers */ + pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0); + pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, 0); + pci_write_config_byte(dev, PCI_IO_BASE, 0x10); + pci_write_config_byte(dev, PCI_IO_LIMIT, 0); + pci_write_config_word(dev, PCI_MEMORY_BASE, 0x10); + pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0); + pci_write_config_word(dev, PCI_PREF_BASE_UPPER32, 0x0); + pci_write_config_word(dev, PCI_PREF_LIMIT_UPPER32, 0x0); + pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10); + pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0); + if (hose->io_resource.flags) { res = &dev->resource[res_idx++]; res->start = hose->io_resource.start; res->end = hose->io_resource.end; res->flags = hose->io_resource.flags; + update_bridge_resource(dev, res); } for (i = 0; i < 3; i++) { @@ -130,6 +143,7 @@ static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) res->start = hose->mem_resources[i].start; res->end = hose->mem_resources[i].end; res->flags = hose->mem_resources[i].flags; + update_bridge_resource(dev, res); } } -- cgit v1.2.3 From eb12af43333dd9d54158f35147a79628c41152db Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 20 Jul 2007 16:29:09 -0500 Subject: [POWERPC] FSL: Add support for PCI-X controllers Some set of 85xx platforms have PCI-X controllers. The old arch/ppc code setup these controllers and we haven't moved it over to arch/powerpc. We use the PCI-X Capabilties to know if we are in PCI-X mode instead of the Global Utilities PORDEVSR. Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index f88a9aecdf16..13aaefc1af5b 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -89,11 +89,22 @@ void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc) void __init setup_pci_cmd(struct pci_controller *hose) { u16 cmd; + int cap_x; + early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); - early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); + + cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); + if (cap_x) { + int pci_x_cmd = cap_x + PCI_X_CMD; + cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ + | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; + early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); + } else { + early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); + } } static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) -- cgit v1.2.3 From c26c372cdbe7de1b9d0c88adce2ae21ef9249e9a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 4 Jun 2007 12:27:14 -0500 Subject: [POWERPC] Add Freescale PCI VENDOR ID and 8641 device IDs Also add 8641/8641D device IDs as well. All of which already exist or have been submitted to The Linux PCI ID Repository at: http://pci-ids.ucw.cz/ CC-to: pci-ids@ucw.cz Signed-off-by: Jon Loeliger Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 13aaefc1af5b..946d72b2ad70 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -253,5 +253,5 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0024, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0025, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0030, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0031, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_transparent); -- cgit v1.2.3 From e58712111fe6eb7573fd6dd12d80de3bec13f277 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 23 Jul 2007 15:47:26 -0500 Subject: [POWERPC] 85xx: Added needed MPC85xx PCI device IDs Added the MPC85xx PCI device IDs that we need for the quirks we have. Also, fixed the MPC8567E, MPC8567 device IDs which had the wrong value. Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 946d72b2ad70..51c223385feb 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -240,18 +240,18 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) return 0; } -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0012, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0013, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0014, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0015, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0018, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0019, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x001a, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0020, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0021, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0024, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0025, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0030, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0031, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_transparent); -- cgit v1.2.3 From 7659c038d3d0a635b5aeff04aed523d7b6c1dde8 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 25 Jul 2007 00:29:53 -0500 Subject: [POWERPC] Fix PCI indirect for big-endian cfg_addr We didn't actually propogate the flag we pass into setup_indirect_pci() to set indirect_type and thus were getting the wrong endianness if PPC_INDIRECT_TYPE_BIG_ENDIAN was set. Also, we need to or in additional flags rather than just doing a direct assignment. Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 51c223385feb..87122275c9b4 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -216,7 +216,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) /* check PCI express link status */ if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { - hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG | + hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; if (fsl_pcie_check_link(hose)) hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; -- cgit v1.2.3 From 282045b45060d5a8be0ebd13c1506551c6a0a0b8 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 26 Jul 2007 00:16:05 -0500 Subject: [POWREPC] Fixup a number of modpost warnings on ppc32 Fixed the following warnings: WARNING: vmlinux.o(.text+0x2934): Section mismatch: reference to .init.text:__alloc_bootmem (between 'irq_alloc_host' and 'irq_set_default_host') WARNING: vmlinux.o(.text+0xb2aa): Section mismatch: reference to .init.data:boot_command_line (between 'register_early_udbg_console' and 'udbg_printf') WARNING: vmlinux.o(.text+0xb2b2): Section mismatch: reference to .init.data:boot_command_line (between 'register_early_udbg_console' and 'udbg_printf') WARNING: vmlinux.o(.text+0xe354): Section mismatch: reference to .init.text:__alloc_bootmem (between 'pcibios_alloc_controller' and 'pci_domain_nr') WARNING: vmlinux.o(.text+0x12768): Section mismatch: reference to .init.text:update_bridge_resource (between 'quirk_fsl_pcie_transparent' and 'indirect_read_config') WARNING: vmlinux.o(.text+0x127a8): Section mismatch: reference to .init.text:update_bridge_resource (between 'quirk_fsl_pcie_transparent' and 'indirect_read_config') WARNING: vmlinux.o(.text+0x17566c): Section mismatch: reference to .init.text:pcibios_fixup_bus (between 'pci_scan_child_bus' and 'pci_scan_bus_parented') Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 87122275c9b4..9fb0ce5c7176 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -107,7 +107,7 @@ void __init setup_pci_cmd(struct pci_controller *hose) } } -static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) +static void __init quirk_fsl_pcie_transparent(struct pci_dev *dev) { struct resource *res; int i, res_idx = PCI_BRIDGE_RESOURCES; -- cgit v1.2.3 From 15f6ddc7d9cf96f2ee88897c7164198ed6e45a77 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 21 Aug 2007 19:15:31 -0500 Subject: [POWERPC] Fix PCI Device ID for MPC8544/8533 processors The initial user manuals for MPC8544/8533 had some issues with properly documenting the device IDs for MPC8544/8533. These processors are almost identical and both show up on the reference boards. Fix up the quirks for PCIe support to handle MPC8533/E. Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 9fb0ce5c7176..114c90f8f560 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -251,6 +251,8 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_transpare DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_transparent); -- cgit v1.2.3 From 5d54ddcbcf931bf07cd1ce262bda4674ebd1427f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 11 Sep 2007 01:25:43 -0500 Subject: [POWERPC] 85xx: Add basic Uniprocessor MPC8572 DS port Added basic board port for MPC8572 DS reference platform that is similiar to the MPC8544/33 DS reference platform in uniprocessor mode. Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 114c90f8f560..34cad96e0de9 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -255,5 +255,7 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_transpare DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_transparent) +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_transparent); -- cgit v1.2.3 From 61c5d3cde10689867b86c8352aa0295637e941cb Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Wed, 3 Oct 2007 15:09:50 -0500 Subject: [POWERPC] Treat 8610 PCIe host bridge as transparent Signed-off-by: Jason Jin Signed-off-by: Jon Loeliger Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 34cad96e0de9..98290f4ef3df 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -259,3 +259,4 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_transpare DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_transparent); -- cgit v1.2.3 From 2fce1225af6f2d3bb9ffb4e6253400db61278594 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 3 Oct 2007 23:37:33 -0500 Subject: [POWERPC] FSL: Access PCIe LTSSM register with correct size The LTSSM register is actual 32-bits wide so we should be doing a dword access. Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 98290f4ef3df..af090c93be10 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -160,8 +160,8 @@ static void __init quirk_fsl_pcie_transparent(struct pci_dev *dev) int __init fsl_pcie_check_link(struct pci_controller *hose) { - u16 val; - early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val); + u32 val; + early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); if (val < PCIE_LTSSM_L0) return 1; return 0; -- cgit v1.2.3