From 85b59f5bb24aeca1a987cbb206e228bf630c8327 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 1 Feb 2010 13:01:42 +0900 Subject: sh: Enable PCI66 support for SH7780 host controller. This adds some helper glue for scanning the bus and determining if all of the devices are 66MHz capable or not before flipping on 66MHz mode. This isn't quite to spec, but it's fairly consistent with what other embedded controllers end up having to do. Scanning code cribbed from the MIPS txx9 PCI code. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/common.c | 64 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 arch/sh/drivers/pci/common.c (limited to 'arch/sh/drivers/pci/common.c') diff --git a/arch/sh/drivers/pci/common.c b/arch/sh/drivers/pci/common.c new file mode 100644 index 000000000000..f67c946a8612 --- /dev/null +++ b/arch/sh/drivers/pci/common.c @@ -0,0 +1,64 @@ +#include +#include + +static int __init +early_read_config_word(struct pci_channel *hose, + int top_bus, int bus, int devfn, int offset, u16 *value) +{ + struct pci_dev fake_dev; + struct pci_bus fake_bus; + + fake_dev.bus = &fake_bus; + fake_dev.sysdata = hose; + fake_dev.devfn = devfn; + fake_bus.number = bus; + fake_bus.sysdata = hose; + fake_bus.ops = hose->pci_ops; + + if (bus != top_bus) + /* Fake a parent bus structure. */ + fake_bus.parent = &fake_bus; + else + fake_bus.parent = NULL; + + return pci_read_config_word(&fake_dev, offset, value); +} + +int __init pci_is_66mhz_capable(struct pci_channel *hose, + int top_bus, int current_bus) +{ + u32 pci_devfn; + unsigned short vid; + int cap66 = -1; + u16 stat; + + printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n"); + + for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) { + if (PCI_FUNC(pci_devfn)) + continue; + if (early_read_config_word(hose, top_bus, current_bus, + pci_devfn, PCI_VENDOR_ID, &vid) != + PCIBIOS_SUCCESSFUL) + continue; + if (vid == 0xffff) + continue; + + /* check 66MHz capability */ + if (cap66 < 0) + cap66 = 1; + if (cap66) { + early_read_config_word(hose, top_bus, current_bus, + pci_devfn, PCI_STATUS, &stat); + if (!(stat & PCI_STATUS_66MHZ)) { + printk(KERN_DEBUG + "PCI: %02x:%02x not 66MHz capable.\n", + current_bus, pci_devfn); + cap66 = 0; + break; + } + } + } + + return cap66 > 0; +} -- cgit v1.2.3 From ef407beefbd9928792ccc93857e408e0057bc17b Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 1 Feb 2010 16:39:46 +0900 Subject: sh: Hook up ERR/PERR/SERR detection for SH7780 PCI host controllers. These were never handled before, so implement some common infrastructure to support them, then make use of that in the SH7780-specific code. In practice there is little here that can not be generalized for SH4 parts, which will be an incremental change as the 7780/7751 code is gradually unified. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/common.c | 79 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) (limited to 'arch/sh/drivers/pci/common.c') diff --git a/arch/sh/drivers/pci/common.c b/arch/sh/drivers/pci/common.c index f67c946a8612..25aec005da18 100644 --- a/arch/sh/drivers/pci/common.c +++ b/arch/sh/drivers/pci/common.c @@ -1,4 +1,6 @@ #include +#include +#include #include static int __init @@ -62,3 +64,80 @@ int __init pci_is_66mhz_capable(struct pci_channel *hose, return cap66 > 0; } + +static void pcibios_enable_err(unsigned long __data) +{ + struct pci_channel *hose = (struct pci_channel *)__data; + + del_timer(&hose->err_timer); + printk(KERN_DEBUG "PCI: re-enabling error IRQ.\n"); + enable_irq(hose->err_irq); +} + +static void pcibios_enable_serr(unsigned long __data) +{ + struct pci_channel *hose = (struct pci_channel *)__data; + + del_timer(&hose->serr_timer); + printk(KERN_DEBUG "PCI: re-enabling system error IRQ.\n"); + enable_irq(hose->serr_irq); +} + +void pcibios_enable_timers(struct pci_channel *hose) +{ + if (hose->err_irq) { + init_timer(&hose->err_timer); + hose->err_timer.data = (unsigned long)hose; + hose->err_timer.function = pcibios_enable_err; + } + + if (hose->serr_irq) { + init_timer(&hose->serr_timer); + hose->serr_timer.data = (unsigned long)hose; + hose->serr_timer.function = pcibios_enable_serr; + } +} + +/* + * A simple handler for the regular PCI status errors, called from IRQ + * context. + */ +unsigned int pcibios_handle_status_errors(unsigned long addr, + unsigned int status, + struct pci_channel *hose) +{ + unsigned int cmd = 0; + + if (status & PCI_STATUS_REC_MASTER_ABORT) { + printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n", addr); + cmd |= PCI_STATUS_REC_MASTER_ABORT; + } + + if (status & PCI_STATUS_REC_TARGET_ABORT) { + printk(KERN_DEBUG "PCI: target abort: "); + pcibios_report_status(PCI_STATUS_REC_TARGET_ABORT | + PCI_STATUS_SIG_TARGET_ABORT | + PCI_STATUS_REC_MASTER_ABORT, 1); + printk("\n"); + + cmd |= PCI_STATUS_REC_TARGET_ABORT; + } + + if (status & (PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY)) { + printk(KERN_DEBUG "PCI: parity error detected: "); + pcibios_report_status(PCI_STATUS_PARITY | + PCI_STATUS_DETECTED_PARITY, 1); + printk("\n"); + + cmd |= PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY; + + /* Now back off of the IRQ for awhile */ + if (hose->err_irq) { + disable_irq(hose->err_irq); + hose->err_timer.expires = jiffies + HZ; + add_timer(&hose->err_timer); + } + } + + return cmd; +} -- cgit v1.2.3 From 9ad62ec4f752c82b39aa5927f23d894b46ae10b9 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 3 Feb 2010 16:46:20 +0900 Subject: sh: Fix up early PCI PERR/SERR IRQ handling. This adds support for handling early PERR/SERR triggering in between controller registration and the initial bus scan. Buggy cards end up asserting these as soon as the M66EN scan is undertaken, resulting in an early crash. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/common.c | 51 ++++++++++++++++++++++++++++++-------------- 1 file changed, 35 insertions(+), 16 deletions(-) (limited to 'arch/sh/drivers/pci/common.c') diff --git a/arch/sh/drivers/pci/common.c b/arch/sh/drivers/pci/common.c index 25aec005da18..dbf138199871 100644 --- a/arch/sh/drivers/pci/common.c +++ b/arch/sh/drivers/pci/common.c @@ -3,29 +3,48 @@ #include #include -static int __init -early_read_config_word(struct pci_channel *hose, - int top_bus, int bus, int devfn, int offset, u16 *value) +/* + * These functions are used early on before PCI scanning is done + * and all of the pci_dev and pci_bus structures have been created. + */ +static struct pci_dev *fake_pci_dev(struct pci_channel *hose, + int top_bus, int busnr, int devfn) { - struct pci_dev fake_dev; - struct pci_bus fake_bus; + static struct pci_dev dev; + static struct pci_bus bus; - fake_dev.bus = &fake_bus; - fake_dev.sysdata = hose; - fake_dev.devfn = devfn; - fake_bus.number = bus; - fake_bus.sysdata = hose; - fake_bus.ops = hose->pci_ops; + dev.bus = &bus; + dev.sysdata = hose; + dev.devfn = devfn; + bus.number = busnr; + bus.sysdata = hose; + bus.ops = hose->pci_ops; - if (bus != top_bus) + if(busnr != top_bus) /* Fake a parent bus structure. */ - fake_bus.parent = &fake_bus; + bus.parent = &bus; else - fake_bus.parent = NULL; + bus.parent = NULL; - return pci_read_config_word(&fake_dev, offset, value); + return &dev; } +#define EARLY_PCI_OP(rw, size, type) \ +int __init early_##rw##_config_##size(struct pci_channel *hose, \ + int top_bus, int bus, int devfn, int offset, type value) \ +{ \ + return pci_##rw##_config_##size( \ + fake_pci_dev(hose, top_bus, bus, devfn), \ + offset, value); \ +} + +EARLY_PCI_OP(read, byte, u8 *) +EARLY_PCI_OP(read, word, u16 *) +EARLY_PCI_OP(read, dword, u32 *) +EARLY_PCI_OP(write, byte, u8) +EARLY_PCI_OP(write, word, u16) +EARLY_PCI_OP(write, dword, u32) + int __init pci_is_66mhz_capable(struct pci_channel *hose, int top_bus, int current_bus) { @@ -133,7 +152,7 @@ unsigned int pcibios_handle_status_errors(unsigned long addr, /* Now back off of the IRQ for awhile */ if (hose->err_irq) { - disable_irq(hose->err_irq); + disable_irq_nosync(hose->err_irq); hose->err_timer.expires = jiffies + HZ; add_timer(&hose->err_timer); } -- cgit v1.2.3