From 31c3af503eb75488aafb7a3d292b9e00962f2cee Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 19 Jan 2010 11:14:31 +0000 Subject: sh: support SIU sourcing from external clock on sh7722 Implement .set_rate() for all SH "div4 clocks," .enable(), .disable(), and .set_parent() for those, that support them. This allows, among other uses, reparenting of SIU clocks to the external source, and enabling and disabling of the IrDA clock on sh7722. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/clock-cpg.c | 94 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 91 insertions(+), 3 deletions(-) (limited to 'arch/sh/kernel/cpu/clock-cpg.c') diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c index 6dfe2cced3fc..2827abb5d2ab 100644 --- a/arch/sh/kernel/cpu/clock-cpg.c +++ b/arch/sh/kernel/cpu/clock-cpg.c @@ -160,13 +160,81 @@ static unsigned long sh_clk_div4_recalc(struct clk *clk) return clk->freq_table[idx].frequency; } +static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent) +{ + struct clk_div_mult_table *table = clk->priv; + u32 value; + int ret; + + if (!strcmp("pll_clk", parent->name)) + value = __raw_readl(clk->enable_reg) & ~(1 << 7); + else + value = __raw_readl(clk->enable_reg) | (1 << 7); + + ret = clk_reparent(clk, parent); + if (ret < 0) + return ret; + + __raw_writel(value, clk->enable_reg); + + /* Rebiuld the frequency table */ + clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, + table, &clk->arch_flags); + + return 0; +} + +static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id) +{ + unsigned long value; + int idx = clk_rate_table_find(clk, clk->freq_table, rate); + if (idx < 0) + return idx; + + value = __raw_readl(clk->enable_reg); + value &= ~0xf; + value |= idx; + __raw_writel(value, clk->enable_reg); + + return 0; +} + +static int sh_clk_div4_enable(struct clk *clk) +{ + __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg); + return 0; +} + +static void sh_clk_div4_disable(struct clk *clk) +{ + __raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg); +} + static struct clk_ops sh_clk_div4_clk_ops = { .recalc = sh_clk_div4_recalc, + .set_rate = sh_clk_div4_set_rate, .round_rate = sh_clk_div_round_rate, }; -int __init sh_clk_div4_register(struct clk *clks, int nr, - struct clk_div_mult_table *table) +static struct clk_ops sh_clk_div4_enable_clk_ops = { + .recalc = sh_clk_div4_recalc, + .set_rate = sh_clk_div4_set_rate, + .round_rate = sh_clk_div_round_rate, + .enable = sh_clk_div4_enable, + .disable = sh_clk_div4_disable, +}; + +static struct clk_ops sh_clk_div4_reparent_clk_ops = { + .recalc = sh_clk_div4_recalc, + .set_rate = sh_clk_div4_set_rate, + .round_rate = sh_clk_div_round_rate, + .enable = sh_clk_div4_enable, + .disable = sh_clk_div4_disable, + .set_parent = sh_clk_div4_set_parent, +}; + +static int __init sh_clk_div4_register_ops(struct clk *clks, int nr, + struct clk_div_mult_table *table, struct clk_ops *ops) { struct clk *clkp; void *freq_table; @@ -185,7 +253,7 @@ int __init sh_clk_div4_register(struct clk *clks, int nr, for (k = 0; !ret && (k < nr); k++) { clkp = clks + k; - clkp->ops = &sh_clk_div4_clk_ops; + clkp->ops = ops; clkp->id = -1; clkp->priv = table; @@ -198,6 +266,26 @@ int __init sh_clk_div4_register(struct clk *clks, int nr, return ret; } +int __init sh_clk_div4_register(struct clk *clks, int nr, + struct clk_div_mult_table *table) +{ + return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops); +} + +int __init sh_clk_div4_enable_register(struct clk *clks, int nr, + struct clk_div_mult_table *table) +{ + return sh_clk_div4_register_ops(clks, nr, table, + &sh_clk_div4_enable_clk_ops); +} + +int __init sh_clk_div4_reparent_register(struct clk *clks, int nr, + struct clk_div_mult_table *table) +{ + return sh_clk_div4_register_ops(clks, nr, table, + &sh_clk_div4_reparent_clk_ops); +} + #ifdef CONFIG_SH_CLK_CPG_LEGACY static struct clk master_clk = { .name = "master_clk", -- cgit v1.2.3 From de7ca2144c36291a491bd39afad172f56432a4bb Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 19 Feb 2010 09:12:00 +0000 Subject: sh: clock-cpg div4 set_rate() shift fix Make sure the div4 bitfield is shifted according to the enable_bit value in sh_clk_div4_set_rate(). Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/clock-cpg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/sh/kernel/cpu/clock-cpg.c') diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c index 2827abb5d2ab..72a5e621a9bb 100644 --- a/arch/sh/kernel/cpu/clock-cpg.c +++ b/arch/sh/kernel/cpu/clock-cpg.c @@ -192,8 +192,8 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id return idx; value = __raw_readl(clk->enable_reg); - value &= ~0xf; - value |= idx; + value &= ~(0xf << clk->enable_bit); + value |= (idx << clk->enable_bit); __raw_writel(value, clk->enable_reg); return 0; -- cgit v1.2.3 From 0a5f337ecd20e70e84a5cfc0f2c24d0366087026 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 19 Feb 2010 09:22:25 +0000 Subject: sh: introduce struct clk_div4_table This patch introduces struct clk_div4_table. The structure will be used to keep div4 specific data, and is with this patch replacing the struct clk_div_mult_table pointer arg used by the sh_clk_div4_register() functions. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/clock-cpg.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'arch/sh/kernel/cpu/clock-cpg.c') diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c index 72a5e621a9bb..1fc8a0e50603 100644 --- a/arch/sh/kernel/cpu/clock-cpg.c +++ b/arch/sh/kernel/cpu/clock-cpg.c @@ -149,7 +149,8 @@ int __init sh_clk_div6_register(struct clk *clks, int nr) static unsigned long sh_clk_div4_recalc(struct clk *clk) { - struct clk_div_mult_table *table = clk->priv; + struct clk_div4_table *d4t = clk->priv; + struct clk_div_mult_table *table = d4t->div_mult_table; unsigned int idx; clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, @@ -162,7 +163,8 @@ static unsigned long sh_clk_div4_recalc(struct clk *clk) static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent) { - struct clk_div_mult_table *table = clk->priv; + struct clk_div4_table *d4t = clk->priv; + struct clk_div_mult_table *table = d4t->div_mult_table; u32 value; int ret; @@ -234,11 +236,11 @@ static struct clk_ops sh_clk_div4_reparent_clk_ops = { }; static int __init sh_clk_div4_register_ops(struct clk *clks, int nr, - struct clk_div_mult_table *table, struct clk_ops *ops) + struct clk_div4_table *table, struct clk_ops *ops) { struct clk *clkp; void *freq_table; - int nr_divs = table->nr_divisors; + int nr_divs = table->div_mult_table->nr_divisors; int freq_table_size = sizeof(struct cpufreq_frequency_table); int ret = 0; int k; @@ -267,20 +269,20 @@ static int __init sh_clk_div4_register_ops(struct clk *clks, int nr, } int __init sh_clk_div4_register(struct clk *clks, int nr, - struct clk_div_mult_table *table) + struct clk_div4_table *table) { return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops); } int __init sh_clk_div4_enable_register(struct clk *clks, int nr, - struct clk_div_mult_table *table) + struct clk_div4_table *table) { return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_enable_clk_ops); } int __init sh_clk_div4_reparent_register(struct clk *clks, int nr, - struct clk_div_mult_table *table) + struct clk_div4_table *table) { return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_reparent_clk_ops); -- cgit v1.2.3 From 7be85c6eb4462cd973e680d9dcf897a7b5b26165 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 19 Feb 2010 09:26:56 +0000 Subject: sh: add sh7724 kick callback to clk_div4_table This patch adds a ->kick() callback to clk_div4_table and ties it into sh_clk_div4_set_rate(). A sh7724 specific kick function is also added that updates the KICK bit whenever div4 clocks in FRQCRA and FRQCRB have been set. Allows us to set the VPU clock. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/clock-cpg.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/sh/kernel/cpu/clock-cpg.c') diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c index 1fc8a0e50603..eed5eaff96ba 100644 --- a/arch/sh/kernel/cpu/clock-cpg.c +++ b/arch/sh/kernel/cpu/clock-cpg.c @@ -188,6 +188,7 @@ static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent) static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id) { + struct clk_div4_table *d4t = clk->priv; unsigned long value; int idx = clk_rate_table_find(clk, clk->freq_table, rate); if (idx < 0) @@ -198,6 +199,9 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id value |= (idx << clk->enable_bit); __raw_writel(value, clk->enable_reg); + if (d4t->kick) + d4t->kick(clk); + return 0; } -- cgit v1.2.3