From 3718b8f35c4e99b53ee0f695a8daa52fccfacbb1 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 24 Aug 2015 13:56:17 +0200 Subject: clk-imx6q.c: set eth phy clock dependent on RMII/RGMII Evaluate the device tree to find out about the used phy mode rather than using a hardcoded value of 125MHz valid for RGMII only. --- arch/arm/mach-imx/clk-imx6q.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index f0d80007677c..8669c9224c43 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include #include #include "clk.h" @@ -129,7 +131,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; - int i; + int i, phy_mode; clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); @@ -568,8 +570,16 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); } - /*Set enet_ref clock to 125M to supply for RGMII tx_clk */ - clk_set_rate(clk[IMX6QDL_CLK_ENET_REF], 125000000); + /*Set enet_ref clock to 125M to supply for RGMII tx_clk or to 50M for RMII */ + phy_mode = PHY_INTERFACE_MODE_RGMII; + np = of_find_node_by_name(NULL, "ethernet"); + if (of_device_is_available(np)) + phy_mode = of_get_phy_mode(np); + else { + phy_mode = PHY_INTERFACE_MODE_RGMII; + } + of_node_put(np); + clk_set_rate(clk[IMX6QDL_CLK_ENET_REF], phy_mode != PHY_INTERFACE_MODE_RMII ? 125000000 : 50000000); #ifdef CONFIG_MX6_VPU_352M /* -- cgit v1.2.3