From c5246863929e52eca234722e229e3607e41e055c Mon Sep 17 00:00:00 2001 From: Venu Byravarasu Date: Fri, 29 Jun 2012 11:58:51 +0530 Subject: arm: tegra: usb_phy: utmip remote wakeup issue Do not clear sleep walk pointer for utmip port after remote wakeup is detected. This should be cleared after control is given to USB master from PMC. Bug 999208 Change-Id: I9f498521989c6421f0043dc1b4364591d4907423 Signed-off-by: Venu Byravarasu (cherry picked from commit e4dbecfe031cbacd4f22bbbcdf971ab11ad81ee8) Reviewed-on: http://git-master/r/112938 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/tegra3_usb_phy.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index 6a8dc3d252e6..874bb1325a22 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -721,10 +721,6 @@ static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy) val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE); writel(val, pmc_base + PMC_SLEEP_CFG); - val = readl(pmc_base + PMC_TRIGGERS); - val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst); - writel(val, pmc_base + PMC_TRIGGERS); - val = readl(base + UTMIP_PMC_WAKEUP0); val &= ~EVENT_INT_ENB; writel(val, base + UTMIP_PMC_WAKEUP0); @@ -744,6 +740,10 @@ static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy) val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst)); writel(val, pmc_base + PMC_USB_AO); + val = readl(pmc_base + PMC_TRIGGERS); + val |= UTMIP_CLR_WALK_PTR(inst); + writel(val, pmc_base + PMC_TRIGGERS); + phy->remote_wakeup = false; PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst); } @@ -766,8 +766,7 @@ bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy) writel(val, pmc_base + PMC_SLEEP_CFG); val = readl(pmc_base + PMC_TRIGGERS); - val |= UTMIP_CLR_WAKE_ALARM(inst) | - UTMIP_CLR_WALK_PTR(inst); + val |= UTMIP_CLR_WAKE_ALARM(inst); writel(val, pmc_base + PMC_TRIGGERS); val = readl(base + UTMIP_PMC_WAKEUP0); -- cgit v1.2.3 From f4cd0d4448d65a42b65c338f85a3ab8064923c61 Mon Sep 17 00:00:00 2001 From: Bitan Biswas Date: Tue, 24 Jan 2012 13:22:23 +0530 Subject: Revert "arm: tegra: power: disable all sd dpd" This reverts commit 8924926cdb77c6ab270867d4caef7a8cdacd11f2. Bug 924452 Bug 929628 Signed-off-by: Bitan Biswas (cherry picked from commit 142b34993404c853579864f7b7b4f320fb92a715) Change-Id: I9d49703799e32d410beba18938e94e4b641eea6f (cherry picked from commit 8de60b7a832bfbbf09e75def756379dbb2d14c3e) Reviewed-on: http://git-master/r/113387 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Wen Yi Tested-by: Wen Yi Reviewed-by: Bharat Nihalani --- arch/arm/mach-tegra/pm-t3.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/pm-t3.c b/arch/arm/mach-tegra/pm-t3.c index a83174224498..89041c41c389 100644 --- a/arch/arm/mach-tegra/pm-t3.c +++ b/arch/arm/mach-tegra/pm-t3.c @@ -3,7 +3,7 @@ * * Tegra3 SOC-specific power and cluster management * - * Copyright (c) 2009-2012, NVIDIA Corporation. + * Copyright (c) 2009-2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -450,7 +450,10 @@ void tegra_lp0_cpu_mode(bool enter) #define PMC_DPD_SAMPLE 0x20 struct tegra_io_dpd tegra_list_io_dpd[] = { -/* Empty DPD list - sd dpd entries removed */ + /* sd dpd bits in dpd2 register */ + IO_DPD_INFO("sdhci-tegra.0", 1, 1), /* SDMMC1 */ + IO_DPD_INFO("sdhci-tegra.2", 1, 2), /* SDMMC3 */ + IO_DPD_INFO("sdhci-tegra.3", 1, 3), /* SDMMC4 */ }; struct tegra_io_dpd *tegra_io_dpd_get(struct device *dev) @@ -481,8 +484,10 @@ void tegra_io_dpd_enable(struct tegra_io_dpd *hnd) unsigned int dpd_status; unsigned int dpd_enable_lsb; - if ((!hnd)) + if ((!hnd)) { + pr_warn("SD IO DPD handle NULL in %s\n", __func__); return; + } spin_lock(&tegra_io_dpd_lock); dpd_enable_lsb = (hnd->io_dpd_reg_index) ? APBDEV_DPD2_ENABLE_LSB : APBDEV_DPD_ENABLE_LSB; @@ -510,8 +515,10 @@ void tegra_io_dpd_disable(struct tegra_io_dpd *hnd) unsigned int dpd_status; unsigned int dpd_enable_lsb; - if ((!hnd)) + if ((!hnd)) { + pr_warn("SD IO DPD handle NULL in %s\n", __func__); return; + } spin_lock(&tegra_io_dpd_lock); dpd_enable_lsb = (hnd->io_dpd_reg_index) ? APBDEV_DPD2_ENABLE_LSB : APBDEV_DPD_ENABLE_LSB; -- cgit v1.2.3 From 5e07056dc8b922b8b43a01b60a949c1dda75d9a9 Mon Sep 17 00:00:00 2001 From: Wen Yi Date: Wed, 20 Jun 2012 21:42:13 -0700 Subject: arm: tegra: sd: enable sd dpd This is a WAR solution that allows for the turning on SD DPD feature. The original issue is that enabling SD DPD immediately after device comes out of LP0 causes ULPI disconnect. The root cause of that is not known. The WAR is to delay the enabling of SD DPD for 100ms after device comes out of LP0. Bug 929628 Change-Id: I3c5e35ace422e5441535c2c0fe18545b53bbddc4 Signed-off-by: Wen Yi (cherry picked from commit bffb7b917d52a3523af80db21322ec7ba5fd33f9) Reviewed-on: http://git-master/r/113392 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-cardhu.c | 2 ++ arch/arm/mach-tegra/board-enterprise.c | 2 ++ arch/arm/mach-tegra/board-kai.c | 2 ++ arch/arm/mach-tegra/board-p1852.c | 2 ++ arch/arm/mach-tegra/include/mach/io_dpd.h | 30 +++++++++--------- arch/arm/mach-tegra/pm-t2.c | 12 ++++++- arch/arm/mach-tegra/pm-t3.c | 52 +++++++++++++++++++++++++++++-- arch/arm/mach-tegra/pm.h | 9 +----- 8 files changed, 84 insertions(+), 27 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c index 1fa3f4f82ef2..f8fb5c528cbd 100644 --- a/arch/arm/mach-tegra/board-cardhu.c +++ b/arch/arm/mach-tegra/board-cardhu.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include #include @@ -1386,6 +1387,7 @@ static void __init tegra_cardhu_init(void) cardhu_uart_init(); platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices)); tegra_ram_console_debug_init(); + tegra_io_dpd_init(); cardhu_sdhci_init(); cardhu_regulator_init(); cardhu_dtv_init(); diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c index 9c8890ed96cf..e703b56fd939 100644 --- a/arch/arm/mach-tegra/board-enterprise.c +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -48,6 +48,7 @@ #include #include #include +#include #include #include #include @@ -969,6 +970,7 @@ static void __init tegra_enterprise_init(void) platform_add_devices(enterprise_devices, ARRAY_SIZE(enterprise_devices)); tegra_ram_console_debug_init(); enterprise_regulator_init(); + tegra_io_dpd_init(); enterprise_sdhci_init(); #ifdef CONFIG_TEGRA_EDP_LIMITS enterprise_edp_init(); diff --git a/arch/arm/mach-tegra/board-kai.c b/arch/arm/mach-tegra/board-kai.c index bf4ae415072d..07fbccfd8138 100644 --- a/arch/arm/mach-tegra/board-kai.c +++ b/arch/arm/mach-tegra/board-kai.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include #include @@ -870,6 +871,7 @@ static void __init tegra_kai_init(void) kai_audio_init(); platform_add_devices(kai_devices, ARRAY_SIZE(kai_devices)); tegra_ram_console_debug_init(); + tegra_io_dpd_init(); kai_sdhci_init(); kai_regulator_init(); kai_suspend_init(); diff --git a/arch/arm/mach-tegra/board-p1852.c b/arch/arm/mach-tegra/board-p1852.c index ce7768e19594..5e7aea1c486d 100644 --- a/arch/arm/mach-tegra/board-p1852.c +++ b/arch/arm/mach-tegra/board-p1852.c @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include @@ -592,6 +593,7 @@ static void __init tegra_p1852_init(void) p1852_gpio_init(); p1852_uart_init(); p1852_usb_init(); + tegra_io_dpd_init(); p1852_sdhci_init(); p1852_spi_init(); platform_add_devices(p1852_devices, ARRAY_SIZE(p1852_devices)); diff --git a/arch/arm/mach-tegra/include/mach/io_dpd.h b/arch/arm/mach-tegra/include/mach/io_dpd.h index 8d153792b798..6eb05c3f1b93 100644 --- a/arch/arm/mach-tegra/include/mach/io_dpd.h +++ b/arch/arm/mach-tegra/include/mach/io_dpd.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/include/mach/io_dpd.h * - * Copyright (C) 2012 NVIDIA Corporation. + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -16,25 +16,23 @@ #ifndef __MACH_TEGRA_IO_DPD_H #define __MACH_TEGRA_IO_DPD_H +#include + +/* Tegra io dpd entry - for each supported driver */ +struct tegra_io_dpd { + const char *name; /* driver name */ + u8 io_dpd_reg_index; /* io dpd register index */ + u8 io_dpd_bit; /* bit position for driver in dpd register */ + u8 need_delay_dpd; /* work around to delay dpd after lp0*/ + struct delayed_work delay_dpd; + struct mutex delay_lock; +}; + /* Tegra io dpd APIs */ -#ifdef CONFIG_PM_SLEEP struct tegra_io_dpd *tegra_io_dpd_get(struct device *dev); /* get handle */ void tegra_io_dpd_enable(struct tegra_io_dpd *hnd); /* enable dpd */ void tegra_io_dpd_disable(struct tegra_io_dpd *hnd); /* disable dpd */ -#else -static inline struct tegra_io_dpd *tegra_io_dpd_get(struct device *dev) -{ - return NULL; -} -static inline void tegra_io_dpd_enable(struct tegra_io_dpd *hnd) -{ - /* Do nothing */ -} -static inline void tegra_io_dpd_disable(struct tegra_io_dpd *hnd) -{ - /* Do nothing */ -} -#endif +int tegra_io_dpd_init(void); #endif /* end __MACH_TEGRA_IO_DPD_H */ diff --git a/arch/arm/mach-tegra/pm-t2.c b/arch/arm/mach-tegra/pm-t2.c index 7ddbb2125595..3ecd27167883 100644 --- a/arch/arm/mach-tegra/pm-t2.c +++ b/arch/arm/mach-tegra/pm-t2.c @@ -3,7 +3,7 @@ * * Tegra 2 LP0 scratch register preservation * - * Copyright (c) 2009-2011, NVIDIA Corporation. + * Copyright (c) 2009-2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -357,6 +357,8 @@ void __init tegra2_lp0_suspend_init(void) wmb(); } +#ifdef CONFIG_PM_SLEEP + struct tegra_io_dpd *tegra_io_dpd_get(struct device *dev) { return NULL; @@ -374,3 +376,11 @@ void tegra_io_dpd_disable(struct tegra_io_dpd *hnd) return; } EXPORT_SYMBOL(tegra_io_dpd_disable); + +#endif + +int tegra_io_dpd_init(void) +{ + return 0; +} +EXPORT_SYMBOL(tegra_io_dpd_init); diff --git a/arch/arm/mach-tegra/pm-t3.c b/arch/arm/mach-tegra/pm-t3.c index 89041c41c389..32a260e2dd43 100644 --- a/arch/arm/mach-tegra/pm-t3.c +++ b/arch/arm/mach-tegra/pm-t3.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -456,6 +457,7 @@ struct tegra_io_dpd tegra_list_io_dpd[] = { IO_DPD_INFO("sdhci-tegra.3", 1, 3), /* SDMMC4 */ }; +#ifdef CONFIG_PM_SLEEP struct tegra_io_dpd *tegra_io_dpd_get(struct device *dev) { int i; @@ -473,7 +475,6 @@ struct tegra_io_dpd *tegra_io_dpd_get(struct device *dev) ((name) ? name : "NULL")); return NULL; } -EXPORT_SYMBOL(tegra_io_dpd_get); static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); static DEFINE_SPINLOCK(tegra_io_dpd_lock); @@ -507,7 +508,6 @@ void tegra_io_dpd_enable(struct tegra_io_dpd *hnd) spin_unlock(&tegra_io_dpd_lock); return; } -EXPORT_SYMBOL(tegra_io_dpd_enable); void tegra_io_dpd_disable(struct tegra_io_dpd *hnd) { @@ -533,4 +533,52 @@ void tegra_io_dpd_disable(struct tegra_io_dpd *hnd) spin_unlock(&tegra_io_dpd_lock); return; } + +static void tegra_io_dpd_delayed_disable(struct work_struct *work) +{ + struct tegra_io_dpd *hnd = container_of( + to_delayed_work(work), struct tegra_io_dpd, delay_dpd); + tegra_io_dpd_disable(hnd); + hnd->need_delay_dpd = 0; +} + +int tegra_io_dpd_init(void) +{ + int i; + for (i = 0; + i < (sizeof(tegra_list_io_dpd) / sizeof(struct tegra_io_dpd)); + i++) { + INIT_DELAYED_WORK(&(tegra_list_io_dpd[i].delay_dpd), + tegra_io_dpd_delayed_disable); + mutex_init(&(tegra_list_io_dpd[i].delay_lock)); + tegra_list_io_dpd[i].need_delay_dpd = 0; + } + return 0; +} + +#else + +int tegra_io_dpd_init(void) +{ + return 0; +} + +void tegra_io_dpd_enable(struct tegra_io_dpd *hnd) +{ +} + +void tegra_io_dpd_disable(struct tegra_io_dpd *hnd) +{ +} + +struct tegra_io_dpd *tegra_io_dpd_get(struct device *dev) +{ + return NULL; +} + +#endif + +EXPORT_SYMBOL(tegra_io_dpd_get); +EXPORT_SYMBOL(tegra_io_dpd_enable); EXPORT_SYMBOL(tegra_io_dpd_disable); +EXPORT_SYMBOL(tegra_io_dpd_init); diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 421b21ac9342..65e816c7abc0 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -2,7 +2,7 @@ * arch/arm/mach-tegra/include/mach/pm.h * * Copyright (C) 2010 Google, Inc. - * Copyright (C) 2010-2012 NVIDIA Corporation + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * * Author: * Colin Cross @@ -67,13 +67,6 @@ struct tegra_suspend_platform_data { unsigned int cpu_resume_boost; /* CPU frequency resume boost in kHz */ }; -/* Tegra io dpd entry - for each supported driver */ -struct tegra_io_dpd { - const char *name; /* driver name */ - u8 io_dpd_reg_index; /* io dpd register index */ - u8 io_dpd_bit; /* bit position for driver in dpd register */ -}; - unsigned long tegra_cpu_power_good_time(void); unsigned long tegra_cpu_power_off_time(void); unsigned long tegra_cpu_lp2_min_residency(void); -- cgit v1.2.3 From 60cd13b6f1bfa4fb808add87d225d8373f4cf3f8 Mon Sep 17 00:00:00 2001 From: Vinayak Pane Date: Mon, 11 Jun 2012 18:08:14 -0700 Subject: arm: tegra: usb_phy: fix hsic suspend issue on xmm XMM modem fails at auto-suspend on hsic. Fixing this issue by enabling PMC sleepwalk code conditionally and only at phy-on and phy-off routines. Bug 991709 Signed-off-by: Vinayak Pane Reviewed-on: http://git-master/r/109324 (cherry picked from commit 100f818a16ce97411a98ddb0e2c5c9e73a9e654a) Change-Id: If6f92b8b36f856fa633cb411ac20dbe6e862890c Reviewed-on: http://git-master/r/115612 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/tegra3_usb_phy.c | 19 ++++++++++++++----- arch/arm/mach-tegra/tegra_usb_phy.h | 1 + 2 files changed, 15 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index 874bb1325a22..57c270caba73 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -1997,6 +1997,7 @@ static void uhsic_phy_restore_start(struct tegra_usb_phy *phy) /* check whether we wake up from the remote resume */ if (UHSIC_WALK_PTR_VAL & val) { phy->remote_wakeup = true; + pr_info("%s: uhsic remote wakeup detected\n", __func__); } else { if (!((UHSIC_STROBE_VAL_P0 | UHSIC_DATA_VAL_P0) & val)) { uhsic_phy_disable_pmc_bus_ctrl(phy); @@ -2198,6 +2199,15 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) phy->phy_clk_on = true; phy->hw_accessible = true; + if (phy->pmc_sleepwalk) { + DBG("%s(%d) inst:[%d] restore phy\n", __func__, __LINE__, + phy->inst); + uhsic_phy_restore_start(phy); + usb_phy_bringup_host_controller(phy); + uhsic_phy_restore_end(phy); + phy->pmc_sleepwalk = false; + } + return 0; } @@ -2219,7 +2229,10 @@ static int uhsic_phy_power_off(struct tegra_usb_phy *phy) /* Disable interrupts */ writel(0, base + USB_USBINTR); - uhsic_setup_pmc_wake_detect(phy); + if (phy->pmc_sleepwalk == false) { + uhsic_setup_pmc_wake_detect(phy); + phy->pmc_sleepwalk = true; + } val = readl(base + HOSTPC1_DEVLC); val |= HOSTPC1_DEVLC_PHCD; @@ -2368,10 +2381,6 @@ int uhsic_phy_resume(struct tegra_usb_phy *phy) { DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); - uhsic_phy_restore_start(phy); - usb_phy_bringup_host_controller(phy); - uhsic_phy_restore_end(phy); - return 0; } diff --git a/arch/arm/mach-tegra/tegra_usb_phy.h b/arch/arm/mach-tegra/tegra_usb_phy.h index 0dc4cd73c5e7..731632d23679 100644 --- a/arch/arm/mach-tegra/tegra_usb_phy.h +++ b/arch/arm/mach-tegra/tegra_usb_phy.h @@ -95,6 +95,7 @@ struct tegra_usb_phy { bool remote_wakeup; bool hw_accessible; bool ulpi_clk_padout_ena; + bool pmc_sleepwalk; }; int usb_phy_reg_status_wait(void __iomem *reg, u32 mask, -- cgit v1.2.3 From 9aed57c5b382154e89bb08ca160a413162e0e17d Mon Sep 17 00:00:00 2001 From: Dongfang Shi Date: Thu, 3 May 2012 16:40:49 -0700 Subject: ARM: tegra: p1852: Dual-display support for all SKUs Ported Peter's original change 86413 to main. board-p1852-panel.c: Add support for primary and secondary LVDS displays, and secondary HDMI display. board-p1852-pinmux.c: Add configuration for HDMI and LVDS board-p1852.c: board-p1852.h: Support for determining which p1852 sku is in use hdmi.c:If no edid retrieved, but there's a hardwired mode, enable it (used to support HDMI->LVDS output on p1852 sku 2) devices.c:added secondary display data. Bug 977859 Bug 994011 Change-Id: Ide8fb6bf7dd873b1d50269fb98d7c1687e4d9073 Signed-off-by: Dongfang Shi Reviewed-on: http://git-master/r/100438 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-p1852-panel.c | 390 +++++++++++++++++++++++++++++++- arch/arm/mach-tegra/board-p1852.c | 21 +- arch/arm/mach-tegra/board-p1852.h | 11 + arch/arm/mach-tegra/devices.c | 37 +++ arch/arm/mach-tegra/devices.h | 1 + 5 files changed, 451 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-p1852-panel.c b/arch/arm/mach-tegra/board-p1852-panel.c index 4e86476cdd2c..970133d8a78e 100644 --- a/arch/arm/mach-tegra/board-p1852-panel.c +++ b/arch/arm/mach-tegra/board-p1852-panel.c @@ -29,7 +29,18 @@ #include "board.h" #include "devices.h" #include "tegra3_host1x_devices.h" +#include "board-p1852.h" +#include "gpio-names.h" +#define P1852_LVDS_ENA1 TEGRA_GPIO_PV0 +#define P1852_LVDS_ENA2 TEGRA_GPIO_PV1 +#define P1852_HDMI_HPD TEGRA_GPIO_PN7 +#define P1852_HDMI_RGB TEGRA_GPIO_PW1 +#define P1852_LVDS_SER1_ADDR 0xd +#define P1852_LVDS_SER2_ADDR 0xc + + +/* RGB panel requires no special enable/disable */ static int p1852_panel_enable(void) { return 0; @@ -40,6 +51,186 @@ static int p1852_panel_disable(void) return 0; } +/* enable primary LVDS */ +static int p1852_lvds_enable(void) +{ + struct i2c_adapter *adapter; + struct i2c_board_info info = {{0}}; + static struct i2c_client *client; + struct i2c_msg msg[2]; + u8 cmd_buf[] = {0x4, 0}; + int status=-1; + + /* Turn on serializer chip */ + gpio_set_value(P1852_LVDS_ENA1, 1); + + /* Program the serializer */ + adapter = i2c_get_adapter(3); + if (!adapter) + pr_warning("%s: adapter is null\n", __func__); + else { + info.addr = P1852_LVDS_SER1_ADDR; + if (!client) + client = i2c_new_device(adapter, &info); + i2c_put_adapter(adapter); + if (!client) + pr_warning("%s: client is null\n", __func__); + else { + msg[0].addr = P1852_LVDS_SER1_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = &cmd_buf[0]; + + status = i2c_transfer(client->adapter, msg, 1); + /* ignore first write status */ + + msg[0].addr = P1852_LVDS_SER1_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = &cmd_buf[0]; + + msg[1].addr = P1852_LVDS_SER1_ADDR; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = &cmd_buf[1]; + + status = i2c_transfer(client->adapter, msg, 2); + if (status < 0) { + pr_warning("%s: i2c failed, addr=0x%x, reg=%d, ret=%d\n", + __func__, P1852_LVDS_SER1_ADDR, cmd_buf[0], status); + } + else { + cmd_buf[1] |= (1 << 2); + cmd_buf[1] |= (1 << 3); + + msg[0].addr = P1852_LVDS_SER1_ADDR; + msg[0].flags = 0; + msg[0].len = 2; + msg[0].buf = &cmd_buf[0]; + + status = i2c_transfer(client->adapter, msg, 1); + if (status < 0) { + pr_warning("%s: i2c err, addr=0x%x, reg=%d, ret=%d\n", + __func__, P1852_LVDS_SER1_ADDR, cmd_buf[0], status); + } + } + } + } + return (status<0 ? status : 0); +} + +/* Disable primary LVDS */ +static int p1852_lvds_disable(void) +{ + /* Turn off serializer chip */ + gpio_set_value(P1852_LVDS_ENA1, 0); + + return 0; +} + +/* Enable secondary LVDS */ +static int p1852_lvds2_enable(void) +{ + struct i2c_adapter *adapter; + struct i2c_board_info info = {{0}}; + static struct i2c_client *client; + struct i2c_msg msg[2]; + u8 cmd_buf[] = {0x4, 0}; + int status=-1; + + /* Enable HDMI HPD */ + /* need nothing here */ + + /* Turn on HDMI-RGB converter */ + gpio_set_value(P1852_HDMI_RGB, 1); + + /* Turn on serializer chip */ + gpio_set_value(P1852_LVDS_ENA2, 1); + + /* Program the serializer */ + adapter = i2c_get_adapter(3); + if (!adapter) + pr_warning("%s: adapter is null\n", __func__); + else { + info.addr = P1852_LVDS_SER2_ADDR; + if (!client) + client = i2c_new_device(adapter, &info); + i2c_put_adapter(adapter); + if (!client) + pr_warning("%s: client is null\n", __func__); + else { + msg[0].addr = P1852_LVDS_SER2_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = &cmd_buf[0]; + + status = i2c_transfer(client->adapter, msg, 1); + /* ignore first write status */ + + msg[0].addr = P1852_LVDS_SER2_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = &cmd_buf[0]; + + msg[1].addr = P1852_LVDS_SER2_ADDR; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = &cmd_buf[1]; + + status = i2c_transfer(client->adapter, msg, 2); + if (status < 0) { + pr_warning("%s: i2c failed, addr=0x%x, reg=%d, ret=%d\n", + __func__, P1852_LVDS_SER2_ADDR, cmd_buf[0], status); + } + else { + cmd_buf[1] |= (1 << 2); + cmd_buf[1] |= (1 << 3); + + msg[0].addr = P1852_LVDS_SER2_ADDR; + msg[0].flags = 0; + msg[0].len = 2; + msg[0].buf = &cmd_buf[0]; + + status = i2c_transfer(client->adapter, msg, 1); + if (status < 0) { + pr_warning("%s: i2c err, addr=0x%x, reg=%d, ret=%d\n", + __func__, P1852_LVDS_SER2_ADDR, cmd_buf[0], status); + } + } + } + } + return (status<0 ? status : 0); +} + +/* Disable secondary LVDS */ +static int p1852_lvds2_disable(void) +{ + /* Turn off serializer chip */ + gpio_set_value(P1852_LVDS_ENA2, 0); + + /* Turn off HDMI-RGB converter */ + gpio_set_value(P1852_HDMI_RGB, 0); + + /* Turn off HDMI */ + /* need nothing here */ + + return 0; +} + +/* Enable secondary HDMI */ +static int p1852_hdmi_enable(void) +{ + /* need nothing here */ + return 0; +} + +/* Disable secondary HDMI */ +static int p1852_hdmi_disable(void) +{ + /* need nothing here */ + return 0; +} + #ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT static struct tegra_dc_mode p1852_panel_modes[] = { @@ -123,9 +314,42 @@ static struct tegra_fb_data p1852_fb_data = { #endif +/* Mode data for secondary LVDS out */ +static struct tegra_dc_mode p1852_hdmi_lvds_modes[] = { + { + /* 800x480@60 */ + .pclk = 33260000, + .h_ref_to_sync = 1, + .v_ref_to_sync = 1, + .h_sync_width = 64, + .v_sync_width = 3, + .h_back_porch = 128, + .v_back_porch = 38, + .h_front_porch = 64, + .v_front_porch = 4, + .h_active = 800, + .v_active = 480, + }, +}; + +static struct tegra_fb_data p1852_hdmi_fb_data = { + .win = 0, + .xres = 800, + .yres = 480, + .bits_per_pixel = 32, + .flags = TEGRA_FB_FLIP_ON_PROBE, +}; + +/* Start of DC_OUT data + * disp1 = Primary RGB out + * ser1 = Primary LVDS out + * ser2 = Secondary LVDS out + * hdmi = Secondary HDMI out + */ static struct tegra_dc_out p1852_disp1_out = { .align = TEGRA_DC_ALIGN_MSB, .order = TEGRA_DC_ORDER_RED_BLUE, + .parent_clk = "pll_d_out0", .type = TEGRA_DC_OUT_RGB, .modes = p1852_panel_modes, .n_modes = ARRAY_SIZE(p1852_panel_modes), @@ -133,6 +357,51 @@ static struct tegra_dc_out p1852_disp1_out = { .disable = p1852_panel_disable, }; +static struct tegra_dc_out p1852_ser1_out = { + .align = TEGRA_DC_ALIGN_MSB, + .order = TEGRA_DC_ORDER_RED_BLUE, + .parent_clk = "pll_d_out0", + .type = TEGRA_DC_OUT_RGB, + .modes = p1852_panel_modes, + .n_modes = ARRAY_SIZE(p1852_panel_modes), + .enable = p1852_lvds_enable, + .disable = p1852_lvds_disable, +}; + +static struct tegra_dc_out p1852_ser2_out = { + .align = TEGRA_DC_ALIGN_MSB, + .order = TEGRA_DC_ORDER_RED_BLUE, + .parent_clk = "pll_d2_out0", + .type = TEGRA_DC_OUT_HDMI, + .flags = TEGRA_DC_OUT_HOTPLUG_LOW | + TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND, + .max_pixclock = KHZ2PICOS(148500), + .hotplug_gpio = P1852_HDMI_HPD, + .modes = p1852_hdmi_lvds_modes, + .n_modes = ARRAY_SIZE(p1852_hdmi_lvds_modes), + .enable = p1852_lvds2_enable, + .disable = p1852_lvds2_disable, + .dcc_bus = 3, +}; + +static struct tegra_dc_out p1852_hdmi_out = { + .align = TEGRA_DC_ALIGN_MSB, + .order = TEGRA_DC_ORDER_RED_BLUE, + .parent_clk = "pll_d2_out0", + .type = TEGRA_DC_OUT_HDMI, + .flags = TEGRA_DC_OUT_HOTPLUG_LOW | + TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND, + .max_pixclock = KHZ2PICOS(148500), + .hotplug_gpio = P1852_HDMI_HPD, + .enable = p1852_hdmi_enable, + .disable = p1852_hdmi_disable, + + .dcc_bus = 1, +}; + +/* End of DC_OUT data */ + +/* Start of platform data */ static struct tegra_dc_platform_data p1852_disp1_pdata = { .flags = TEGRA_DC_FLAG_ENABLED, .default_out = &p1852_disp1_out, @@ -140,6 +409,29 @@ static struct tegra_dc_platform_data p1852_disp1_pdata = { .fb = &p1852_fb_data, }; +static struct tegra_dc_platform_data p1852_ser1_pdata = { + .flags = TEGRA_DC_FLAG_ENABLED, + .default_out = &p1852_ser1_out, + .emc_clk_rate = 300000000, + .fb = &p1852_fb_data, +}; + +static struct tegra_dc_platform_data p1852_ser2_pdata = { + .flags = TEGRA_DC_FLAG_ENABLED, + .default_out = &p1852_ser2_out, + .emc_clk_rate = 300000000, + .fb = &p1852_hdmi_fb_data, +}; + +static struct tegra_dc_platform_data p1852_hdmi_pdata = { + .flags = TEGRA_DC_FLAG_ENABLED, + .default_out = &p1852_hdmi_out, + .emc_clk_rate = 300000000, + .fb = &p1852_hdmi_fb_data, +}; + +/* End of platform data */ + static struct nvmap_platform_carveout p1852_carveouts[] = { [0] = { .name = "iram", @@ -166,7 +458,7 @@ static struct platform_device *p1852_gfx_devices[] __initdata = { &tegra_nvmap_device, }; -int __init p1852_panel_init(void) +static int __init p1852_sku2_panel_init(void) { int err; struct resource *res; @@ -174,16 +466,62 @@ int __init p1852_panel_init(void) p1852_carveouts[1].base = tegra_carveout_start; p1852_carveouts[1].size = tegra_carveout_size; tegra_nvmap_device.dev.platform_data = &p1852_nvmap_data; - tegra_disp1_device.dev.platform_data = &p1852_disp1_pdata; + /* + * sku2 has primary LVDS out and secondary LVDS out + * (via HDMI->RGB->Serializer) + */ + tegra_disp1_device.dev.platform_data = &p1852_ser1_pdata; + tegra_disp2_device.dev.platform_data = &p1852_ser2_pdata; +#ifdef CONFIG_TEGRA_GRHOST + err = tegra3_register_host1x_devices(); + if (err) + return err; +#endif + + err = platform_add_devices(p1852_gfx_devices, + ARRAY_SIZE(p1852_gfx_devices)); + +#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC) res = nvhost_get_resource_byname(&tegra_disp1_device, IORESOURCE_MEM, "fbmem"); - if (!res) { - pr_err("No memory resources\n"); - return -ENODEV; + if (res) { + res->start = tegra_fb_start; + res->end = tegra_fb_start + tegra_fb_size - 1; + } + + if (!err) + err = nvhost_device_register(&tegra_disp1_device); + + res = nvhost_get_resource_byname(&tegra_disp2_device, + IORESOURCE_MEM, "fbmem"); + if (res) { + res->start = tegra_fb2_start; + res->end = tegra_fb2_start + tegra_fb2_size - 1; } - res->start = tegra_fb_start; - res->end = tegra_fb_start + tegra_fb_size - 1; + + if (!err) + err = nvhost_device_register(&tegra_disp2_device); +#endif + +#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_NVAVP) + if (!err) + err = nvhost_device_register(&nvavp_device); +#endif + return err; +} + +static int __init p1852_sku8_panel_init(void) +{ + int err; + struct resource *res; + + p1852_carveouts[1].base = tegra_carveout_start; + p1852_carveouts[1].size = tegra_carveout_size; + tegra_nvmap_device.dev.platform_data = &p1852_nvmap_data; + /* sku 8 has primary RGB out and secondary HDMI out */ + tegra_disp1_device.dev.platform_data = &p1852_disp1_pdata; + tegra_disp2_device.dev.platform_data = &p1852_hdmi_pdata; #ifdef CONFIG_TEGRA_GRHOST err = tegra3_register_host1x_devices(); @@ -193,12 +531,50 @@ int __init p1852_panel_init(void) err = platform_add_devices(p1852_gfx_devices, ARRAY_SIZE(p1852_gfx_devices)); + +#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC) + res = nvhost_get_resource_byname(&tegra_disp1_device, + IORESOURCE_MEM, "fbmem"); + if (res) { + res->start = tegra_fb_start; + res->end = tegra_fb_start + tegra_fb_size - 1; + } + if (!err) err = nvhost_device_register(&tegra_disp1_device); + res = nvhost_get_resource_byname(&tegra_disp2_device, + IORESOURCE_MEM, "fbmem"); + if (res) { + res->start = tegra_fb2_start; + res->end = tegra_fb2_start + tegra_fb2_size - 1; + } + + if (!err) + err = nvhost_device_register(&tegra_disp2_device); +#endif + #if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_NVAVP) if (!err) err = nvhost_device_register(&nvavp_device); #endif return err; } + +int __init p1852_panel_init(void) +{ + int skuid; + + skuid = p1852_get_skuid(); + + switch (skuid) { + case 2: + return p1852_sku2_panel_init(); + case 5: /* Sku 5 display is same as 8 */ + case 8: + return p1852_sku8_panel_init(); + default: + pr_warning("%s: unknown skuid %d\n", __func__, skuid); + return 1; + } +} diff --git a/arch/arm/mach-tegra/board-p1852.c b/arch/arm/mach-tegra/board-p1852.c index 5e7aea1c486d..c195f0f4ca5a 100644 --- a/arch/arm/mach-tegra/board-p1852.c +++ b/arch/arm/mach-tegra/board-p1852.c @@ -609,12 +609,29 @@ static void __init tegra_p1852_init(void) static void __init tegra_p1852_reserve(void) { #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) - tegra_reserve(0, SZ_8M, 0); + tegra_reserve(0, SZ_8M, SZ_8M); #else - tegra_reserve(SZ_128M, SZ_8M, 0); + tegra_reserve(SZ_128M, SZ_8M, SZ_8M); #endif } +int p1852_get_skuid() +{ + switch (system_rev) { + case TEGRA_P1852_SKU2_A00: + case TEGRA_P1852_SKU2_B00: + return 2; + case TEGRA_P1852_SKU5_A00: + case TEGRA_P1852_SKU5_B00: + return 5; + case TEGRA_P1852_SKU8_A00: + case TEGRA_P1852_SKU8_B00: + return 8; + default: + return -1; + } +} + MACHINE_START(P1852, "p1852") .boot_params = 0x80000100, .init_irq = tegra_init_irq, diff --git a/arch/arm/mach-tegra/board-p1852.h b/arch/arm/mach-tegra/board-p1852.h index 1ac0968f9518..529bd3840e63 100644 --- a/arch/arm/mach-tegra/board-p1852.h +++ b/arch/arm/mach-tegra/board-p1852.h @@ -90,16 +90,27 @@ #define AC_PRESENT_INT (TPS6591X_INT_GPIO4 + TPS6591X_IRQ_BASE) +/* List of P1852 skus - replicated from core/include/nvmachtypes.h */ +#define TEGRA_P1852_SKU2_A00 0x020000UL +#define TEGRA_P1852_SKU2_B00 0x020200UL +#define TEGRA_P1852_SKU5_A00 0x050000UL +#define TEGRA_P1852_SKU5_B00 0x050200UL +#define TEGRA_P1852_SKU8_A00 0x080000UL +#define TEGRA_P1852_SKU8_B00 0x080200UL + int p1852_sdhci_init(void); int p1852_pinmux_init(void); int p1852_panel_init(void); int p1852_gpio_init(void); int p1852_pins_state_init(void); +int p1852_get_skuid(void); + #ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT #define TOUCH_GPIO_IRQ_ATMEL_T9 TEGRA_GPIO_PEE1 #define TOUCH_GPIO_RST_ATMEL_T9 TEGRA_GPIO_PW2 #define TOUCH_BUS_ATMEL_T9 0 #endif + #endif diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c index fb97f94b939f..508320582560 100644 --- a/arch/arm/mach-tegra/devices.c +++ b/arch/arm/mach-tegra/devices.c @@ -1698,6 +1698,43 @@ struct nvhost_device tegra_disp1_device = { .num_resources = ARRAY_SIZE(tegra_disp1_resources), }; +static struct resource tegra_disp2_resources[] = { + { + .name = "irq", + .start = INT_DISPLAY_B_GENERAL, + .end = INT_DISPLAY_B_GENERAL, + .flags = IORESOURCE_IRQ, + }, + { + .name = "regs", + .start = TEGRA_DISPLAY2_BASE, + .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "fbmem", + .flags = IORESOURCE_MEM, + .start = 0, + .end = 0, + }, + { + .name = "hdmi_regs", + .start = TEGRA_HDMI_BASE, + .end = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct nvhost_device tegra_disp2_device = { + .name = "tegradc", + .id = 1, + .resource = tegra_disp2_resources, + .num_resources = ARRAY_SIZE(tegra_disp2_resources), + .dev = { + .platform_data = 0, + }, +}; + struct platform_device tegra_nvmap_device = { .name = "tegra-nvmap", .id = -1, diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h index 830f2cf7accc..ca492cdd11db 100644 --- a/arch/arm/mach-tegra/devices.h +++ b/arch/arm/mach-tegra/devices.h @@ -131,6 +131,7 @@ extern struct platform_device debug_uarte_device; #endif extern struct nvhost_device tegra_disp1_device; +extern struct nvhost_device tegra_disp2_device; extern struct platform_device tegra_nvmap_device; #ifndef CONFIG_ARCH_TEGRA_2x_SOC extern struct platform_device tegra_cec_device; -- cgit v1.2.3 From 0f64d5820ea1caa2b879aea7f68614d45edf6d32 Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Fri, 8 Jun 2012 14:43:35 -0700 Subject: ARM: tegra: dvfs: Update Tegra3 sdmmc dvfs tables Added Tegra3 sdmmc4 dvfs table and downgraded sdmmc 2/4 maximum clock limits based on recent characterization results. Bug 817679 Bug 841336 Change-Id: I88ddeaabf0739efc0f9c18c41cace331792d4d43 Signed-off-by: Alex Frid Reviewed-on: http://git-master/r/107780 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Pavan Kunapuli Tested-by: Pavan Kunapuli Reviewed-by: Yu-Huan Hsu --- arch/arm/mach-tegra/tegra3_clocks.c | 4 ++-- arch/arm/mach-tegra/tegra3_dvfs.c | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 1161f1ca64f9..122d9d51580c 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -4322,9 +4322,9 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ - PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ + PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 50000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ - PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ + PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 102000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0), PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0), PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0), diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c index 5af1b44cd99c..10ba0715c33e 100644 --- a/arch/arm/mach-tegra/tegra3_dvfs.c +++ b/arch/arm/mach-tegra/tegra3_dvfs.c @@ -305,6 +305,7 @@ static struct dvfs core_dvfs_table[] = { CORE_DVFS("fuse_burn", -1, 1, KHZ, 1, 1, 1, 1, 26000, 26000, 26000, 26000, 26000), CORE_DVFS("sdmmc1", -1, 1, KHZ, 104000, 104000, 104000, 104000, 104000, 208000, 208000, 208000, 208000), CORE_DVFS("sdmmc3", -1, 1, KHZ, 104000, 104000, 104000, 104000, 104000, 208000, 208000, 208000, 208000), + CORE_DVFS("sdmmc4", -1, 1, KHZ, 51000, 102000, 102000, 102000, 102000, 102000, 102000, 102000, 102000), CORE_DVFS("ndflash", -1, 1, KHZ, 120000, 120000, 120000, 120000, 200000, 200000, 200000, 200000, 200000), CORE_DVFS("nor", 0, 1, KHZ, 1, 115000, 130000, 130000, 133000, 133000, 133000, 133000, 133000), -- cgit v1.2.3 From e6e9afa497611669b26b805302ec5642a18a57a6 Mon Sep 17 00:00:00 2001 From: Jay Agarwal Date: Fri, 6 Jul 2012 14:42:03 +0530 Subject: arm: config: tegra3 Enable XHCI driver for USB3 1. Enable USB3 for both android and L4T 2. Enable R8169 for android, already enabled for L4T Bug 956573 Change-Id: If8d7cf653a5cd2b02352ad07fee3a56c3f568d3a Signed-off-by: Jay Agarwal Reviewed-on: http://git-master/r/113856 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Thota Reviewed-by: Bharat Nihalani --- arch/arm/configs/tegra3_android_defconfig | 9 ++++----- arch/arm/configs/tegra3_defconfig | 6 +++--- 2 files changed, 7 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/configs/tegra3_android_defconfig b/arch/arm/configs/tegra3_android_defconfig index 0ab4493d3205..deb90a6a24e6 100644 --- a/arch/arm/configs/tegra3_android_defconfig +++ b/arch/arm/configs/tegra3_android_defconfig @@ -26,9 +26,6 @@ CONFIG_ARCH_TEGRA=y CONFIG_GPIO_PCA953X=y CONFIG_ARCH_TEGRA_3x_SOC=y CONFIG_TEGRA_PCI=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_POWERSAVE=y CONFIG_MACH_CARDHU=y CONFIG_MACH_TEGRA_ENTERPRISE=y CONFIG_MACH_KAI=y @@ -46,6 +43,8 @@ CONFIG_ARM_ERRATA_742230=y CONFIG_ARM_ERRATA_743622=y CONFIG_ARM_ERRATA_751472=y CONFIG_ARM_ERRATA_752520=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIEASPM_POWERSAVE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_SMP=y @@ -194,7 +193,6 @@ CONFIG_AD525X_DPOT_I2C=y CONFIG_APDS9802ALS=y CONFIG_SENSORS_NCT1008=y CONFIG_UID_STAT=y -# CONFIG_BCM4329_RFKILL is not set CONFIG_TEGRA_CRYPTO_DEV=y CONFIG_MAX1749_VIBRATOR=y CONFIG_EEPROM_AT24=y @@ -223,6 +221,7 @@ CONFIG_DM_UEVENT=y CONFIG_NETDEVICES=y CONFIG_DUMMY=y CONFIG_TUN=y +CONFIG_R8169=y # CONFIG_NETDEV_10000 is not set CONFIG_BCM4329=m CONFIG_BCM4329_FIRST_SCAN=y @@ -385,6 +384,7 @@ CONFIG_USB_DEVICEFS=y CONFIG_USB_SUSPEND=y CONFIG_USB_OTG=y # CONFIG_USB_OTG_WHITELIST is not set +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ACM=y CONFIG_USB_WDM=y @@ -452,7 +452,6 @@ CONFIG_NLS_ISO8859_1=y CONFIG_PRINTK_TIME=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_SECTION_MISMATCH=y -CONFIG_DEBUG_FS=y CONFIG_LOCKUP_DETECTOR=y # CONFIG_DETECT_HUNG_TASK is not set CONFIG_SCHEDSTATS=y diff --git a/arch/arm/configs/tegra3_defconfig b/arch/arm/configs/tegra3_defconfig index 86d74c113a23..0739438d704a 100644 --- a/arch/arm/configs/tegra3_defconfig +++ b/arch/arm/configs/tegra3_defconfig @@ -27,9 +27,6 @@ CONFIG_ARCH_TEGRA=y CONFIG_GPIO_PCA953X=y CONFIG_ARCH_TEGRA_3x_SOC=y CONFIG_TEGRA_PCI=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_POWERSAVE=y CONFIG_MACH_CARDHU=y CONFIG_MACH_TEGRA_ENTERPRISE=y CONFIG_TEGRA_PWM=y @@ -47,6 +44,8 @@ CONFIG_ARM_ERRATA_742230=y CONFIG_ARM_ERRATA_743622=y CONFIG_ARM_ERRATA_751472=y CONFIG_ARM_ERRATA_752520=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIEASPM_POWERSAVE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_SMP=y @@ -357,6 +356,7 @@ CONFIG_USB_DEVICEFS=y CONFIG_USB_SUSPEND=y CONFIG_USB_OTG=y # CONFIG_USB_OTG_WHITELIST is not set +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ACM=y CONFIG_USB_WDM=y -- cgit v1.2.3 From 9238fb22cd84919e2c75b600071cda48eb86c1ca Mon Sep 17 00:00:00 2001 From: Prem Sasidharan Date: Mon, 9 Jul 2012 18:30:58 -0700 Subject: arm: tegra: cpu: changing cpu min. freq to 51MHz Changing the CPU min. frequency to 51MHz. This helps in bringing down the core power to 46mW. Bug 1005275 Change-Id: I61daa59866be7baf8ebb741000904422cb095e85 Signed-off-by: Prem Sasidharan (cherry picked from commit afbb34d5871b69df328d5aae37f69f25a8946514) Reviewed-on: http://git-master/r/115452 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Wen Yi Tested-by: Wen Yi Reviewed-by: Bharat Nihalani --- arch/arm/mach-tegra/pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 7a08bc1aef24..85a6cf19234a 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -178,7 +178,7 @@ struct suspend_context tegra_sctx; #define MC_SECURITY_SIZE 0x70 #define MC_SECURITY_CFG2 0x7c -#define AWAKE_CPU_FREQ_MIN 100000 +#define AWAKE_CPU_FREQ_MIN 51000 static struct pm_qos_request_list awake_cpu_freq_req; struct dvfs_rail *tegra_cpu_rail; -- cgit v1.2.3 From 969361b41f95efb349da4ed7a0e8834cc9c2ab89 Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Sat, 14 Jul 2012 17:08:01 -0700 Subject: ARM: tegra: clock: Add missed Tegra3 PERIPH_ON_APB attributes Change-Id: I12be16dbc2614224ba852216a645d0f84c795334 Signed-off-by: Alex Frid Reviewed-on: http://git-master/r/115929 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Peterson --- arch/arm/mach-tegra/tegra3_clocks.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 122d9d51580c..d9ebb1140a9e 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -4290,7 +4290,7 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB), PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB), PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0), - PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0), + PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, PERIPH_ON_APB), PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB), PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB), PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, PERIPH_ON_APB), @@ -4303,9 +4303,9 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 408000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), - PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), - PERIPH_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), + PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, PERIPH_ON_APB), @@ -4315,11 +4315,11 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("sbc4", "spi_tegra.3", "spi", 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("sbc5", "spi_tegra.4", "spi", 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("sbc6", "spi_tegra.5", "spi", 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0), - PERIPH_CLK_EX("ndflash","tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71, &tegra_nand_clk_ops), - PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, PERIPH_ON_APB), + PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB, &tegra_nand_clk_ops), + PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 50000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ @@ -4328,10 +4328,10 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0), PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0), PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0), - PERIPH_CLK("cec", "tegra_cec", NULL, 136, 0, 26000000, mux_clk_m, PERIPH_ON_APB), + PERIPH_CLK("cec", "tegra_cec", NULL, 136, 0, 26000000, mux_clk_m, PERIPH_ON_APB), PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 600000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT), - PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */ - PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* max rate ??? */ + PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */ @@ -4365,7 +4365,7 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT), PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ - PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0, &tegra_dtv_clk_ops), + PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, PERIPH_ON_APB, &tegra_dtv_clk_ops), PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71), PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8), @@ -4381,7 +4381,7 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */ PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET), - PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71), + PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71), PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71), PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71), @@ -4389,7 +4389,7 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0), PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0), - PERIPH_CLK("se", "se", NULL, 127, 0x42c, 625000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT), + PERIPH_CLK("se", "se", NULL, 127, 0x42c, 625000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB), PERIPH_CLK("mselect", "mselect", NULL, 99, 0x3b4, 108000000, mux_pllp_clkm, MUX | DIV_U71), SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), -- cgit v1.2.3 From 21aba41cb87afea59e1ee9aa9e1ef5ce7fd66ee8 Mon Sep 17 00:00:00 2001 From: Vinayak Pane Date: Fri, 29 Jun 2012 13:08:36 -0700 Subject: arm: tegra: xmm: flashed modem start with hsic_active low Flashed modem should start with hsic_active signal as low. The hsic register is done at falling edge of ap_wake. Bug 1006183 Signed-off-by: Vinayak Pane Reviewed-on: http://git-master/r/112781 (cherry picked from commit 6437d1453d2a7694c2efa183cff135297f9f45e3) Change-Id: I7bf355088096788b030fd861ef257a9f635c66e7 Reviewed-on: http://git-master/r/115610 Tested-by: Vinayak Pane Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Steve Lin --- arch/arm/mach-tegra/baseband-xmm-power.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/baseband-xmm-power.c b/arch/arm/mach-tegra/baseband-xmm-power.c index 36f5fc6611f9..9482bbecc77d 100644 --- a/arch/arm/mach-tegra/baseband-xmm-power.c +++ b/arch/arm/mach-tegra/baseband-xmm-power.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/baseband-xmm-power.c * - * Copyright (C) 2011 NVIDIA Corporation + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -78,7 +78,7 @@ static struct gpio tegra_baseband_gpios[] = { { -1, GPIOF_OUT_INIT_LOW, "BB_ON" }, { -1, GPIOF_OUT_INIT_LOW, "IPC_BB_WAKE" }, { -1, GPIOF_IN, "IPC_AP_WAKE" }, - { -1, GPIOF_OUT_INIT_HIGH, "IPC_HSIC_ACTIVE" }, + { -1, GPIOF_OUT_INIT_LOW, "IPC_HSIC_ACTIVE" }, { -1, GPIOF_IN, "IPC_HSIC_SUS_REQ" }, }; @@ -559,15 +559,14 @@ irqreturn_t xmm_power_ipc_ap_wake_irq(int irq, void *dev_id) return IRQ_HANDLED; } else if (ipc_ap_wake_state == IPC_AP_WAKE_INIT1) { if (!value) { - pr_debug("%s - IPC_AP_WAKE_INIT2" - " - wait for rising edge\n", __func__); - } else { - pr_debug("%s - IPC_AP_WAKE_INIT2" - " - got rising edge\n", __func__); + pr_debug("%s - got falling edge at INIT1\n", __func__); /* go to IPC_AP_WAKE_INIT2 state */ ipc_ap_wake_state = IPC_AP_WAKE_INIT2; queue_work(workqueue, &init2_work); - } + + } else + pr_debug("%s - IPC_AP_WAKE_INIT1" + " - got rising edge\n", __func__); return IRQ_HANDLED; } @@ -774,12 +773,11 @@ static void xmm_power_work_func(struct work_struct *work) case BBXMM_WORK_INIT_FLASH_PM_STEP1: pr_debug("BBXMM_WORK_INIT_FLASH_PM_STEP1\n"); pr_debug("%s: ipc_hsic_active -> 0\n", __func__); - gpio_set_value(pdata->modem.xmm.ipc_hsic_active, 1); + gpio_set_value(pdata->modem.xmm.ipc_hsic_active, 0); /* reset / power on sequence */ xmm_power_reset_on(pdata); /* set power status as on */ power_onoff = 1; - gpio_set_value(pdata->modem.xmm.ipc_hsic_active, 0); /* expecting init2 performs register hsic to enumerate modem * software directly. -- cgit v1.2.3 From 944f3f892662eba946d4ff18bf0d575754b3e2b5 Mon Sep 17 00:00:00 2001 From: Jay Agarwal Date: Fri, 13 Jul 2012 18:20:18 +0530 Subject: arm: tegra: pcie: Enable cardhu a02+ Dock detect GPIO Set E_INPUT and PUPD bit of GPIO_PU4 used for dock detect event for cardhu a02+ board versions and hence enable pcie hotplug for them. Bug 955043 Bug 1009086 Bug 1016722 Change-Id: Ibb66e5bc6fd9cf5333a81988b975b611fe9c5312 Signed-off-by: Jay Agarwal Reviewed-on: http://git-master/r/115692 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Thota GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan --- arch/arm/mach-tegra/board-cardhu-pinmux.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-pinmux.c b/arch/arm/mach-tegra/board-cardhu-pinmux.c index 7b98af0f167c..9ecb2f2d80e5 100644 --- a/arch/arm/mach-tegra/board-cardhu-pinmux.c +++ b/arch/arm/mach-tegra/board-cardhu-pinmux.c @@ -482,6 +482,9 @@ static __initdata struct tegra_pingroup_config cardhu_pinmux_cardhu_a03[] = { DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(PEX_L1_CLKREQ_N, RSVD3, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(PEX_L1_PRSNT_N, RSVD3, PULL_UP, NORMAL, INPUT), + + /*PCIE dock detect*/ + DEFAULT_PINMUX(GPIO_PU4, RSVD1, PULL_UP, NORMAL, INPUT), }; static __initdata struct tegra_pingroup_config cardhu_pinmux_e1291_a04[] = { @@ -489,6 +492,9 @@ static __initdata struct tegra_pingroup_config cardhu_pinmux_e1291_a04[] = { DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(SPI2_MOSI, SPI6, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(DAP3_SCLK, RSVD1, NORMAL, NORMAL, OUTPUT), + + /*PCIE dock detect*/ + DEFAULT_PINMUX(GPIO_PU4, RSVD1, PULL_UP, NORMAL, INPUT), }; static __initdata struct tegra_pingroup_config cardhu_pinmux_e1198[] = { -- cgit v1.2.3 From d56e0d7285cd01e28af9d65e6ca456da96eaefda Mon Sep 17 00:00:00 2001 From: Joshua Primero Date: Mon, 16 Jul 2012 17:09:42 -0700 Subject: ARM: tegra: thermal: Call pm register only once Fixed bug where pm register was being called multiple times. Change-Id: I32f7b10547275e0a9bdad1073f9842589180c0f8 Signed-off-by: Joshua Primero Reviewed-on: http://git-master/r/116203 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bitan Biswas --- arch/arm/mach-tegra/tegra3_thermal.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_thermal.c b/arch/arm/mach-tegra/tegra3_thermal.c index f36f84ccddf4..e8b5e5df4afc 100644 --- a/arch/arm/mach-tegra/tegra3_thermal.c +++ b/arch/arm/mach-tegra/tegra3_thermal.c @@ -441,7 +441,6 @@ int tegra_thermal_device_register(struct tegra_thermal_device *device) tegra_skin_device_register(device); #endif - register_pm_notifier(&tegra_thermal_nb); return 0; } @@ -477,6 +476,8 @@ int __init tegra_thermal_init(struct tegra_thermal_data *data, throttle_list = tlist; throttle_list_size = tlist_size; + register_pm_notifier(&tegra_thermal_nb); + return 0; } -- cgit v1.2.3 From 6b33cd0cf0d4aea214382797c43a0e4077e4c4a7 Mon Sep 17 00:00:00 2001 From: Mohit Kataria Date: Wed, 20 Jun 2012 10:59:37 +0530 Subject: ARM: Tegra3: clocks: optional se.cbus Made se.cbus optional so that se clock can be derived from other clocks and not just from the clocks which drive cbus. Added config option for the same. Bug 978870 Change-Id: I7b5bf405efb58bbb53143f52d2bfe0ebcf6b8322 Signed-off-by: Mohit Kataria Reviewed-on: http://git-master/r/110827 (cherry picked from commit 35e9017b79a3a4b4e0b4098cd2e63ad24018d3de) Reviewed-on: http://git-master/r/106397 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/Kconfig | 20 ++++++++++++++++++++ arch/arm/mach-tegra/tegra3_clocks.c | 2 ++ 2 files changed, 22 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index e94c2f03187b..ed35a91c575c 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -1,3 +1,17 @@ +# Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + if ARCH_TEGRA comment "NVIDIA Tegra options" @@ -410,6 +424,12 @@ config TEGRA_EMC_TO_DDR_CLOCK default "2" if ARCH_TEGRA_2x_SOC default "1" +config TEGRA_SE_ON_CBUS + bool "To Drive SE clock from cbus" + default y + help + This option enables SE clock to be derived from cbus + config TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND bool "Use conservative cpu frequency governor when device enters early suspend" depends on HAS_EARLYSUSPEND && CPU_FREQ diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index d9ebb1140a9e..40030cb00e3a 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -4434,7 +4434,9 @@ struct clk tegra_list_clks[] = { SHARED_CLK("epp.cbus", "tegra_gr2d", "epp", &tegra_clk_cbus, "epp", 0, 0), SHARED_CLK("mpe.cbus", "tegra_mpe", "mpe", &tegra_clk_cbus, "mpe", 0, 0), SHARED_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_cbus, "vde", 0, 0), +#ifdef CONFIG_TEGRA_SE_ON_CBUS SHARED_CLK("se.cbus", "tegra-se", NULL, &tegra_clk_cbus, "se", 0, 0), +#endif SHARED_CLK("cap.cbus", "cap.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING), SHARED_CLK("floor.cbus", "floor.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0), }; -- cgit v1.2.3 From 2286178d7039ab929e44df62b3f7e558893d84fd Mon Sep 17 00:00:00 2001 From: Bitan Biswas Date: Fri, 13 Jul 2012 16:03:17 +0530 Subject: ARM: tegra: wake source interrupts enabled Tegra wake source interrupts are only enabled before suspend bug 904746 Change-Id: Ie9722199b4541f2bac77e47d0c8c7e65d5d8b54d Signed-off-by: Bitan Biswas Reviewed-on: http://git-master/r/115655 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan --- arch/arm/mach-tegra/irq.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 278912486f40..4f34b87d8f36 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -196,6 +196,12 @@ static int tegra_legacy_irq_suspend(void) /* disable COP interrupts */ writel(~0, ictlr + ICTLR_COP_IER_CLR); + + /* disable CPU interrupts */ + writel(~0, ictlr + ICTLR_CPU_IER_CLR); + + /* enable lp1 wake sources */ + writel(ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET); } local_irq_restore(flags); -- cgit v1.2.3 From 79cb5050b1bfbc5a55a53a33d41f6a392befddf5 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Fri, 22 Jun 2012 12:23:36 +0530 Subject: ARM: tegra: enterprise: allow 3mv tolerance for cpu voltage Allow 3mv tolerance on minimum voltage side for cpu voltage. This saves power when system require 900/975mV. bug 997415 Change-Id: I273cdeda6980f5ddf50be7980bced443b386dae8 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/110524 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-enterprise-power.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index bbe39ec4ad3e..ca39bae3d08d 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -741,6 +741,9 @@ int __init enterprise_regulator_init(void) pmc_dpd_pads = readl(pmc + PMC_DPD_PADS_ORIDE); writel(pmc_dpd_pads & ~PMC_DPD_PADS_ORIDE_BLINK , pmc + PMC_DPD_PADS_ORIDE); + /* Setting CPU voltage tolerance in lower side for 3000uV */ + pdata_smps1_common.tolerance_uv = 3000; + /* Disable battery charging if power adapter is connected. */ if (get_power_supply_type() == POWER_SUPPLY_TYPE_MAINS) { bcharger_pdata.num_consumer_supplies = 0; -- cgit v1.2.3 From 871f9eb32a6717f595340d95a56c6530f7b1798a Mon Sep 17 00:00:00 2001 From: Venu Byravarasu Date: Fri, 13 Jul 2012 11:38:04 +0530 Subject: arm: tegra: usb: phy code clean up Code clean up of usb phy driver Change-Id: If951ed461b096be76938504d9e1073a70f59860a Signed-off-by: Venu Byravarasu Reviewed-on: http://git-master/r/115339 (cherry picked from commit 6d4046a6f2170dadaf5647f0bf47aa546dd705b0) Reviewed-on: http://git-master/r/104055 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bitan Biswas --- arch/arm/mach-tegra/usb_phy.c | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c index a83f04a7656c..62884df14269 100644 --- a/arch/arm/mach-tegra/usb_phy.c +++ b/arch/arm/mach-tegra/usb_phy.c @@ -173,8 +173,7 @@ static int tegra_usb_phy_get_clocks(struct tegra_usb_phy *phy) phy->pllu_clk = clk_get_sys(NULL, "pll_u"); if (IS_ERR(phy->pllu_clk)) { ERR("inst:[%d] Can't get pllu_clk clock\n", phy->inst); - err = PTR_ERR(phy->pllu_clk); - goto fail_pll; + return PTR_ERR(phy->pllu_clk); } clk_enable(phy->pllu_clk); @@ -222,8 +221,6 @@ fail_ctrlr_clk: clk_disable(phy->pllu_clk); clk_put(phy->pllu_clk); -fail_pll: - return err; } @@ -233,6 +230,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct platform_device *pdev) struct tegra_usb_platform_data *pdata; struct resource *res; int err; + int plat_data_size = sizeof(struct tegra_usb_platform_data); DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, pdev->id); pdata = dev_get_platdata(&pdev->dev); @@ -242,20 +240,21 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct platform_device *pdev) return ERR_PTR(-EINVAL); } - phy = kzalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL); + phy = devm_kzalloc(&pdev->dev, sizeof(struct tegra_usb_phy), GFP_KERNEL); if (!phy) { ERR("inst:[%d] malloc usb phy failed\n", pdev->id); return ERR_PTR(-ENOMEM); } - phy->pdata = kzalloc(sizeof(struct tegra_usb_platform_data), GFP_KERNEL); + phy->pdata = devm_kzalloc(&pdev->dev, plat_data_size, GFP_KERNEL); if (!phy->pdata) { ERR("inst:[%d] malloc usb phy pdata failed\n", pdev->id); kfree(phy); return ERR_PTR(-ENOMEM); } - memcpy(phy->pdata, pdata, sizeof(struct tegra_usb_platform_data)); + memcpy(phy->pdata, pdata, plat_data_size); + phy->pdev = pdev; phy->inst = pdev->id; @@ -264,15 +263,13 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { ERR("inst:[%d] failed to get I/O memory\n", phy->inst); - err = -ENXIO; - goto fail_io; + return ERR_PTR(-ENXIO); } phy->regs = ioremap(res->start, resource_size(res)); if (!phy->regs) { ERR("inst:[%d] Failed to remap I/O memory\n", phy->inst); - err = -ENOMEM; - goto fail_io; + return ERR_PTR(-ENOMEM); } phy->vdd_reg = regulator_get(NULL, "avdd_usb"); @@ -375,14 +372,9 @@ fail_init: fail_clk: regulator_put(phy->vdd_reg); iounmap(phy->regs); -fail_io: - kfree(phy); - return ERR_PTR(err); } - - void tegra_usb_phy_close(struct tegra_usb_phy *phy) { DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); @@ -418,9 +410,6 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy) tegra_usb_phy_release_clocks(phy); - - kfree(phy->pdata); - kfree(phy); } irqreturn_t tegra_usb_phy_irq(struct tegra_usb_phy *phy) @@ -432,6 +421,7 @@ irqreturn_t tegra_usb_phy_irq(struct tegra_usb_phy *phy) return status; } + int tegra_usb_phy_init(struct tegra_usb_phy *phy) { int status = 0; @@ -551,6 +541,7 @@ int tegra_usb_phy_reset(struct tegra_usb_phy *phy) return status; } + int tegra_usb_phy_pre_suspend(struct tegra_usb_phy *phy) { int status = 0; @@ -565,6 +556,7 @@ int tegra_usb_phy_pre_suspend(struct tegra_usb_phy *phy) return status; } + int tegra_usb_phy_suspend(struct tegra_usb_phy *phy) { int err = 0; @@ -580,6 +572,7 @@ int tegra_usb_phy_suspend(struct tegra_usb_phy *phy) return err; } + int tegra_usb_phy_post_suspend(struct tegra_usb_phy *phy) { int status = 0; @@ -594,6 +587,7 @@ int tegra_usb_phy_post_suspend(struct tegra_usb_phy *phy) return status; } + int tegra_usb_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup) { int status = 0; @@ -608,6 +602,7 @@ int tegra_usb_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup) return status; } + int tegra_usb_phy_resume(struct tegra_usb_phy *phy) { int err = 0; @@ -624,6 +619,7 @@ int tegra_usb_phy_resume(struct tegra_usb_phy *phy) return err; } + int tegra_usb_phy_post_resume(struct tegra_usb_phy *phy) { int status = 0; @@ -638,6 +634,7 @@ int tegra_usb_phy_post_resume(struct tegra_usb_phy *phy) return status; } + int tegra_usb_phy_port_power(struct tegra_usb_phy *phy) { int status = 0; @@ -649,6 +646,7 @@ int tegra_usb_phy_port_power(struct tegra_usb_phy *phy) return status; } + int tegra_usb_phy_bus_reset(struct tegra_usb_phy *phy) { int status = 0; -- cgit v1.2.3 From 989cd8dbb21d7d7916d7460b291961b3d5312bf3 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Mon, 9 Jul 2012 17:23:50 -0700 Subject: ARM: tegra: Fix build issue for no-SMP Fix issues causing the kernel build to fail with CONFIG_SMP not set. Change-Id: I8c7a49970e55354e38ce41d2d1e0dab00ba78f24 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/114317 Reviewed-by: Rohan Somvanshi Tested-by: Rohan Somvanshi --- arch/arm/mach-tegra/board-enterprise-power.c | 2 +- arch/arm/mach-tegra/timer-t3.c | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index ca39bae3d08d..eb9f1d53dea4 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -846,9 +846,9 @@ static struct platform_device enterprise_bpc_mgmt_device = { void __init enterprise_bpc_mgmt_init(void) { +#ifdef CONFIG_SMP int int_gpio = TEGRA_GPIO_TO_IRQ(TEGRA_BPC_TRIGGER); -#ifdef CONFIG_SMP cpumask_setall(&(bpc_mgmt_platform_data.affinity_mask)); irq_set_affinity_hint(int_gpio, &(bpc_mgmt_platform_data.affinity_mask)); diff --git a/arch/arm/mach-tegra/timer-t3.c b/arch/arm/mach-tegra/timer-t3.c index f23873b214b2..b58fc9bbc4c0 100644 --- a/arch/arm/mach-tegra/timer-t3.c +++ b/arch/arm/mach-tegra/timer-t3.c @@ -72,10 +72,8 @@ static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE); #if defined(CONFIG_PM_SLEEP) static cpumask_t wake_timer_canceled; -#if defined(CONFIG_HOTPLUG_CPU) static cpumask_t wake_timer_ready; #endif -#endif #define timer_writel(value, reg) \ __raw_writel(value, (u32)timer_reg_base + (reg)) -- cgit v1.2.3 From 76f95d32ab167e70601904c50d2595de0e955f1d Mon Sep 17 00:00:00 2001 From: Rohan Somvanshi Date: Tue, 3 Jul 2012 12:28:01 +0000 Subject: ARM: tegra: dvfs: Handle Tegra3 alternative dvfs errors Propagate error to the caller when switching between alternative cpu dvfs tables. Change dvfs table during cpu hotplug operation only after the new edp limit is set, and abort bringing cpu core on-line in case of failure in applying new (less conservative) table. When cpu core is removed change dvfs table before setting new edp limit, and ignore error (it is safe to continue with more conservative table). Signed-off-by: Alex Frid (cherry picked from commit 951710ec179fd620a2251d0815ca7bff15da014b) Change-Id: Ib1ad8e41093fb9bee75d3d6bd18d0ac406da8271 Reviewed-on: http://git-master/r/114779 Reviewed-by: Rohan Somvanshi Tested-by: Rohan Somvanshi --- arch/arm/mach-tegra/cpu-tegra.c | 26 +++++++++++++------------- arch/arm/mach-tegra/dvfs.h | 10 +++++----- arch/arm/mach-tegra/tegra3_dvfs.c | 16 ++++++++++------ 3 files changed, 28 insertions(+), 24 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c index 9bed9270b412..ea5bbcf237c0 100644 --- a/arch/arm/mach-tegra/cpu-tegra.c +++ b/arch/arm/mach-tegra/cpu-tegra.c @@ -7,7 +7,7 @@ * Colin Cross * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation * - * Copyright (C) 2010-2012 NVIDIA Corporation + * Copyright (C) 2010-2012 NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -242,12 +242,12 @@ int tegra_edp_update_thermal_zone(int temperature) /* Update cpu rate if cpufreq (at least on cpu0) is already started; alter cpu dvfs table for this thermal zone if necessary */ - tegra_cpu_dvfs_alter(edp_thermal_index, &edp_cpumask, true); + tegra_cpu_dvfs_alter(edp_thermal_index, &edp_cpumask, true, 0); if (target_cpu_speed[0]) { edp_update_limit(); tegra_cpu_set_speed_cap(NULL); } - tegra_cpu_dvfs_alter(edp_thermal_index, &edp_cpumask, false); + tegra_cpu_dvfs_alter(edp_thermal_index, &edp_cpumask, false, 0); mutex_unlock(&tegra_cpu_lock); return ret; @@ -321,31 +321,31 @@ static int tegra_cpu_edp_notify( case CPU_UP_PREPARE: mutex_lock(&tegra_cpu_lock); cpu_set(cpu, edp_cpumask); - tegra_cpu_dvfs_alter(edp_thermal_index, &edp_cpumask, true); edp_update_limit(); cpu_speed = tegra_getspeed(0); new_speed = edp_governor_speed(cpu_speed); if (new_speed < cpu_speed) { ret = tegra_cpu_set_speed_cap(NULL); - if (ret) { - cpu_clear(cpu, edp_cpumask); - edp_update_limit(); - } - - printk(KERN_DEBUG "tegra CPU:%sforce EDP limit %u kHz" + printk(KERN_DEBUG "cpu-tegra:%sforce EDP limit %u kHz" "\n", ret ? " failed to " : " ", new_speed); } - tegra_cpu_dvfs_alter(edp_thermal_index, &edp_cpumask, false); + if (!ret) + ret = tegra_cpu_dvfs_alter( + edp_thermal_index, &edp_cpumask, false, event); + if (ret) { + cpu_clear(cpu, edp_cpumask); + edp_update_limit(); + } mutex_unlock(&tegra_cpu_lock); break; case CPU_DEAD: mutex_lock(&tegra_cpu_lock); cpu_clear(cpu, edp_cpumask); - tegra_cpu_dvfs_alter(edp_thermal_index, &edp_cpumask, true); + tegra_cpu_dvfs_alter( + edp_thermal_index, &edp_cpumask, true, event); edp_update_limit(); tegra_cpu_set_speed_cap(NULL); - tegra_cpu_dvfs_alter(edp_thermal_index, &edp_cpumask, false); mutex_unlock(&tegra_cpu_lock); break; } diff --git a/arch/arm/mach-tegra/dvfs.h b/arch/arm/mach-tegra/dvfs.h index 3bdb13690278..d18a0382f4da 100644 --- a/arch/arm/mach-tegra/dvfs.h +++ b/arch/arm/mach-tegra/dvfs.h @@ -5,7 +5,7 @@ * Author: * Colin Cross * - * Copyright (C) 2010-2011 NVIDIA Corporation. + * Copyright (C) 2010-2012 NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -118,8 +118,8 @@ int tegra_dvfs_predict_millivolts(struct clk *c, unsigned long rate); void tegra_dvfs_core_cap_enable(bool enable); void tegra_dvfs_core_cap_level_set(int level); int tegra_dvfs_alt_freqs_set(struct dvfs *d, unsigned long *alt_freqs); -void tegra_cpu_dvfs_alter( - int edp_thermal_index, const cpumask_t *cpus, bool before_clk_update); +int tegra_cpu_dvfs_alter(int edp_thermal_index, const cpumask_t *cpus, + bool before_clk_update, int cpu_event); #else static inline void tegra_soc_init_dvfs(void) {} @@ -157,8 +157,8 @@ static inline void tegra_dvfs_core_cap_level_set(int level) static inline int tegra_dvfs_alt_freqs_set(struct dvfs *d, unsigned long *alt_freqs) { return 0; } -static inline void tegra_cpu_dvfs_alter( - int edp_thermal_index, const cpumask_t *cpus, bool before_clk_update) +static inline int tegra_cpu_dvfs_alter(int edp_thermal_index, + const cpumask_t *cpus, bool before_clk_update, int cpu_event) {} #endif diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c index 10ba0715c33e..7d8359290a22 100644 --- a/arch/arm/mach-tegra/tegra3_dvfs.c +++ b/arch/arm/mach-tegra/tegra3_dvfs.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/tegra3_dvfs.c * - * Copyright (C) 2010-2012, NVIDIA Corporation. + * Copyright (C) 2010-2012 NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -693,19 +693,23 @@ void __init tegra_soc_init_dvfs(void) tegra_dvfs_core_disabled ? "disabled" : "enabled"); } -void tegra_cpu_dvfs_alter(int edp_thermal_index, const cpumask_t *cpus, - bool before_clk_update) +int tegra_cpu_dvfs_alter(int edp_thermal_index, const cpumask_t *cpus, + bool before_clk_update, int cpu_event) { bool cpu_warm = !!edp_thermal_index; unsigned int n = cpumask_weight(cpus); unsigned long *alt_freqs = cpu_warm ? (n > 1 ? NULL : cpu_0_freqs) : cpu_cold_freqs; - if (cpu_warm == before_clk_update) { + if (cpu_event || (cpu_warm == before_clk_update)) { int ret = tegra_dvfs_alt_freqs_set(cpu_dvfs, alt_freqs); - WARN_ONCE(ret, "tegra dvfs: failed to update CPU alternative" - " frequency limits\n"); + if (ret) { + pr_err("tegra dvfs: failed to set alternative dvfs on " + "%u %s CPUs\n", n, cpu_warm ? "warm" : "cold"); + return ret; + } } + return 0; } int tegra_dvfs_rail_disable_prepare(struct dvfs_rail *rail) -- cgit v1.2.3 From 0245741903a5b16a27cb30ad09bb9fada84f1eca Mon Sep 17 00:00:00 2001 From: Nitin Pai Date: Thu, 28 Jun 2012 14:20:50 +0530 Subject: arm: tegra: p1852: Make TDM1 as 16 channels Made TDM1 as 16 channels so that both devices work in the same configuration. Bug 1008391 Signed-off-by: Nitin Pai Reviewed-on: http://git-master/r/112090 (cherry picked from commit 4d042a0e613ba1c2d715d6ed47daddd61be14a28) Change-Id: I622b046b3b36147b82d47f612febb7ae7ba0767c Reviewed-on: http://git-master/r/116059 Reviewed-by: Rohan Somvanshi Tested-by: Rohan Somvanshi --- arch/arm/mach-tegra/board-p1852.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-p1852.c b/arch/arm/mach-tegra/board-p1852.c index c195f0f4ca5a..008b8ad0aac5 100644 --- a/arch/arm/mach-tegra/board-p1852.c +++ b/arch/arm/mach-tegra/board-p1852.c @@ -209,11 +209,15 @@ static struct tegra_p1852_platform_data p1852_audio_tdm_pdata = { .name = "tegra-i2s-1", .pcm_driver = "tegra-tdm-pcm-audio", .i2s_format = format_tdm, + /* Defines whether the Codec Chip is Master or Slave */ .master = 1, - .num_slots = 4, + /* Defines the number of TDM slots */ + .num_slots = 8, + /* Defines the width of each slot */ .slot_width = 32, - .tx_mask = 0x0f, - .rx_mask = 0x0f, + /* Defines which slots are enabled */ + .tx_mask = 0xff, + .rx_mask = 0xff, }, .codec_info[1] = { .codec_dai_name = "dit-hifi", -- cgit v1.2.3 From 94e947b829c7922cbc2c413db708232dfc7cc4e9 Mon Sep 17 00:00:00 2001 From: Prem Sasidharan Date: Thu, 5 Jul 2012 11:56:14 -0700 Subject: arm: tegra: PLLX LP/G ports switching ON/OFF Enable target PLLX port(LP/G) before cluster switch and disable the previous PLLX port(LP/G) after cluster switch is finished. Seeing a power improvement of ~10mW when core operates at max. voltage and max. frequency. Bug 997358 Signed-off-by: Prem Sasidharan Change-Id: I9d05245977f9f63a8f4c53b1c6797118d2d8b903 Reviewed-on: http://git-master/r/113399 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/pm-t3.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/pm-t3.c b/arch/arm/mach-tegra/pm-t3.c index 32a260e2dd43..89f2bb5f0731 100644 --- a/arch/arm/mach-tegra/pm-t3.c +++ b/arch/arm/mach-tegra/pm-t3.c @@ -102,6 +102,12 @@ #define CPU_CLOCK(cpu) (0x1<<(8+cpu)) #define CPU_RESET(cpu) (0x1111ul<<(cpu)) +#define PLLX_FO_G (1<<28) +#define PLLX_FO_LP (1<<29) + +#define CLK_RST_CONTROLLER_PLLX_MISC_0 \ + (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0xE4) + static int cluster_switch_prolog_clock(unsigned int flags) { u32 reg; @@ -189,6 +195,20 @@ static int cluster_switch_prolog_clock(unsigned int flags) return 0; } +static inline void enable_pllx_cluster_port(void) +{ + u32 val = readl(CLK_RST_CONTROLLER_PLLX_MISC_0); + val &= (is_lp_cluster()?(~PLLX_FO_G):(~PLLX_FO_LP)); + writel(val, CLK_RST_CONTROLLER_PLLX_MISC_0); +} + +static inline void disable_pllx_cluster_port(void) +{ + u32 val = readl(CLK_RST_CONTROLLER_PLLX_MISC_0); + val |= (is_lp_cluster()?PLLX_FO_G:PLLX_FO_LP); + writel(val, CLK_RST_CONTROLLER_PLLX_MISC_0); +} + void tegra_cluster_switch_prolog(unsigned int flags) { unsigned int target_cluster = flags & TEGRA_POWER_CLUSTER_MASK; @@ -223,6 +243,9 @@ void tegra_cluster_switch_prolog(unsigned int flags) /* Set up the flow controller to switch CPUs. */ reg |= FLOW_CTRL_CPU_CSR_SWITCH_CLUSTER; + + /* Enable target port of PLL_X */ + enable_pllx_cluster_port(); } } @@ -305,6 +328,9 @@ void tegra_cluster_switch_epilog(unsigned int flags) cluster_switch_epilog_gic(); } + /* Disable unused port of PLL_X */ + disable_pllx_cluster_port(); + #if DEBUG_CLUSTER_SWITCH { /* FIXME: clock functions below are taking mutex */ -- cgit v1.2.3 From de14d57fdfbbd1de9a6c99cb52455d5bd6afb11f Mon Sep 17 00:00:00 2001 From: Kirill Artamonov Date: Mon, 16 Jul 2012 17:24:00 +0300 Subject: ARM: mm: cache-l2x0: Implement outer_clean_all() There is already implemented full outer clean routine in arch/arm/mm/cache-l2x0.c. Make it possible to use it through outer_cache interface, like other outer maintenance functions. bug 983964 Change-Id: I47f1fad536c151c255e6a42d6517114c334ddfef Reviewed-on: http://git-master/r/116074 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kirill Artamonov Tested-by: Kirill Artamonov Reviewed-by: Krishna Reddy Reviewed-by: Justin Paver Reviewed-by: Bharat Nihalani --- arch/arm/include/asm/outercache.h | 8 ++++++++ arch/arm/mm/cache-l2x0.c | 1 + 2 files changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h index d8387437ec5a..49c5e2d2972d 100644 --- a/arch/arm/include/asm/outercache.h +++ b/arch/arm/include/asm/outercache.h @@ -28,6 +28,7 @@ struct outer_cache_fns { void (*clean_range)(unsigned long, unsigned long); void (*flush_range)(unsigned long, unsigned long); void (*flush_all)(void); + void (*clean_all)(void); void (*inv_all)(void); void (*disable)(void); #ifdef CONFIG_OUTER_CACHE_SYNC @@ -62,6 +63,12 @@ static inline void outer_flush_all(void) outer_cache.flush_all(); } +static inline void outer_clean_all(void) +{ + if (outer_cache.clean_all) + outer_cache.clean_all(); +} + static inline void outer_inv_all(void) { if (outer_cache.inv_all) @@ -83,6 +90,7 @@ static inline void outer_clean_range(phys_addr_t start, phys_addr_t end) static inline void outer_flush_range(phys_addr_t start, phys_addr_t end) { } static inline void outer_flush_all(void) { } +static inline void outer_clean_all(void) { } static inline void outer_inv_all(void) { } static inline void outer_disable(void) { } diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index e6871a3e4d1c..0336d47c5dd4 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -418,6 +418,7 @@ void l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) outer_cache.flush_range = l2x0_flush_range; outer_cache.sync = l2x0_cache_sync; outer_cache.flush_all = l2x0_flush_all; + outer_cache.clean_all = l2x0_clean_all; outer_cache.inv_all = l2x0_inv_all; outer_cache.disable = l2x0_disable; outer_cache.set_debug = l2x0_set_debug; -- cgit v1.2.3 From a741c18a8da46dc51470953a7d931457d589cafb Mon Sep 17 00:00:00 2001 From: Ravindra Lokhande Date: Thu, 19 Jul 2012 19:52:54 +0530 Subject: arm: config: tegra3: enable alsa usb audio Change-Id: I6b6348ec3b604bbf9b8e40fe551023cf94b0b153 Reviewed-on: http://git-master/r/117083 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/configs/tegra3_android_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/tegra3_android_defconfig b/arch/arm/configs/tegra3_android_defconfig index deb90a6a24e6..24a24706ca48 100644 --- a/arch/arm/configs/tegra3_android_defconfig +++ b/arch/arm/configs/tegra3_android_defconfig @@ -371,6 +371,7 @@ CONFIG_SND_HDA_PLATFORM_DRIVER=y CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA=y CONFIG_SND_HDA_POWER_SAVE=y CONFIG_SND_HDA_POWER_SAVE_DEFAULT=10 +CONFIG_SND_USB_AUDIO=y CONFIG_SND_SOC=y CONFIG_SND_SOC_TEGRA=y CONFIG_SND_SOC_TEGRA_WM8903=y -- cgit v1.2.3 From 5ddd56678b30c53ba76ddafddffdbfdb02c5e9db Mon Sep 17 00:00:00 2001 From: Bitan Biswas Date: Thu, 28 Jun 2012 12:58:41 +0530 Subject: ARM: tegra: tegra2 wakeups header cleanup Removed the unnecessary function prototypes in Tegra2 wakeups header Change-Id: Ia41ce72947902cbc483cc85eaefb3a81d091a9b8 Signed-off-by: Bitan Biswas Reviewed-on: http://git-master/r/111817 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan --- arch/arm/mach-tegra/wakeups-t2.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/wakeups-t2.h b/arch/arm/mach-tegra/wakeups-t2.h index 955b351a71fa..142d4c76558b 100644 --- a/arch/arm/mach-tegra/wakeups-t2.h +++ b/arch/arm/mach-tegra/wakeups-t2.h @@ -27,9 +27,6 @@ #error "Tegra 2 wakeup sources valid only for CONFIG_ARCH_TEGRA_2x_SOC" #endif -int tegra_irq_to_wake(int irq); -int tegra_wake_to_irq(int wake); - #define TEGRA_WAKE_GPIO_PO5 0 #define TEGRA_WAKE_GPIO_PV3 1 #define TEGRA_WAKE_GPIO_PL1 2 -- cgit v1.2.3 From 20f4cdc91d6babfe87a2b196aac524a7855c4d55 Mon Sep 17 00:00:00 2001 From: srinivas Date: Mon, 16 Jul 2012 16:09:12 +0530 Subject: arm: tegra3: usb_phy: HSIC rail consumes 4mA in suspend In auto-suspend, removed power downs for HSIC from PADS_CFG1 register. Bug 1011912 Change-Id: I646c196ef9b822ae8d9e12a0f918507fcdd16f0b Signed-off-by: srinivas Reviewed-on: http://git-master/r/116044 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/tegra3_usb_phy.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index 57c270caba73..3a3293eba06a 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -2238,6 +2238,11 @@ static int uhsic_phy_power_off(struct tegra_usb_phy *phy) val |= HOSTPC1_DEVLC_PHCD; writel(val, base + HOSTPC1_DEVLC); + /* Remove power downs for HSIC from PADS CFG1 register */ + val = readl(base + UHSIC_PADS_CFG1); + val |= (UHSIC_PD_BG |UHSIC_PD_TRK | UHSIC_PD_RX | + UHSIC_PD_ZI | UHSIC_PD_TX); + writel(val, base + UHSIC_PADS_CFG1); phy->phy_clk_on = false; phy->hw_accessible = false; -- cgit v1.2.3 From f9288476cff96063d0c8aa2fd6397d143e85f433 Mon Sep 17 00:00:00 2001 From: Bitan Biswas Date: Thu, 12 Jul 2012 18:33:37 +0530 Subject: ARM: tegra: reset io dpd mode Bootloader io dpd settings are cleared during kernel initialization bug 758856 Change-Id: Ic6d5250a5ae127bb45ab37b9200ca06c8d1f11a2 Signed-off-by: Bitan Biswas Reviewed-on: http://git-master/r/115395 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/pm-t2.c | 6 ++++++ arch/arm/mach-tegra/pm-t3.c | 43 ++++++++++++++++++++++++++++++++++++++++--- arch/arm/mach-tegra/pm.c | 4 ++++ arch/arm/mach-tegra/pm.h | 3 +++ 4 files changed, 53 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/pm-t2.c b/arch/arm/mach-tegra/pm-t2.c index 3ecd27167883..6b8515ab2e3e 100644 --- a/arch/arm/mach-tegra/pm-t2.c +++ b/arch/arm/mach-tegra/pm-t2.c @@ -384,3 +384,9 @@ int tegra_io_dpd_init(void) return 0; } EXPORT_SYMBOL(tegra_io_dpd_init); + +void tegra_bl_io_dpd_cleanup() +{ +} +EXPORT_SYMBOL(tegra_bl_io_dpd_cleanup); + diff --git a/arch/arm/mach-tegra/pm-t3.c b/arch/arm/mach-tegra/pm-t3.c index 89f2bb5f0731..939a9b8ad404 100644 --- a/arch/arm/mach-tegra/pm-t3.c +++ b/arch/arm/mach-tegra/pm-t3.c @@ -483,14 +483,16 @@ struct tegra_io_dpd tegra_list_io_dpd[] = { IO_DPD_INFO("sdhci-tegra.3", 1, 3), /* SDMMC4 */ }; +/* we want to cleanup bootloader io dpd setting in kernel */ +static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); + #ifdef CONFIG_PM_SLEEP struct tegra_io_dpd *tegra_io_dpd_get(struct device *dev) { int i; const char *name = dev ? dev_name(dev) : NULL; if (name) { - for (i = 0; i < (sizeof(tegra_list_io_dpd) / - sizeof(struct tegra_io_dpd)); i++) { + for (i = 0; i < ARRAY_SIZE(tegra_list_io_dpd); i++) { if (!(strncmp(tegra_list_io_dpd[i].name, name, strlen(name)))) { return &tegra_list_io_dpd[i]; @@ -502,7 +504,6 @@ struct tegra_io_dpd *tegra_io_dpd_get(struct device *dev) return NULL; } -static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); static DEFINE_SPINLOCK(tegra_io_dpd_lock); void tegra_io_dpd_enable(struct tegra_io_dpd *hnd) @@ -608,3 +609,39 @@ EXPORT_SYMBOL(tegra_io_dpd_get); EXPORT_SYMBOL(tegra_io_dpd_enable); EXPORT_SYMBOL(tegra_io_dpd_disable); EXPORT_SYMBOL(tegra_io_dpd_init); + +struct io_dpd_reg_info { + u32 req_reg_off; + u8 dpd_code_lsb; +}; + +static struct io_dpd_reg_info t3_io_dpd_req_regs[] = { + {0x1b8, 30}, + {0x1c0, 5}, +}; + +/* io dpd off request code */ +#define IO_DPD_CODE_OFF 1 + +/* cleans io dpd settings from bootloader during kernel init */ +void tegra_bl_io_dpd_cleanup() +{ + int i; + unsigned int dpd_mask; + unsigned int dpd_status; + + pr_info("Clear bootloader IO dpd settings\n"); + /* clear all dpd requests from bootloader */ + for (i = 0; i < ARRAY_SIZE(t3_io_dpd_req_regs); i++) { + dpd_mask = ((1 << t3_io_dpd_req_regs[i].dpd_code_lsb) - 1); + dpd_mask |= (IO_DPD_CODE_OFF << + t3_io_dpd_req_regs[i].dpd_code_lsb); + writel(dpd_mask, pmc + t3_io_dpd_req_regs[i].req_reg_off); + /* dpd status register is next to req reg in tegra3 */ + dpd_status = readl(pmc + + (t3_io_dpd_req_regs[i].req_reg_off + 4)); + } + return; +} +EXPORT_SYMBOL(tegra_bl_io_dpd_cleanup); + diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 85a6cf19234a..9049e37ca05a 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -1231,6 +1231,10 @@ out: iram_cpu_lp2_mask = tegra_cpu_lp2_mask; iram_cpu_lp1_mask = tegra_cpu_lp1_mask; + + /* clear io dpd settings before kernel */ + tegra_bl_io_dpd_cleanup(); + fail: #endif if (plat->suspend_mode == TEGRA_SUSPEND_NONE) diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 65e816c7abc0..498170648819 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -67,6 +67,9 @@ struct tegra_suspend_platform_data { unsigned int cpu_resume_boost; /* CPU frequency resume boost in kHz */ }; +/* clears io dpd settings before kernel code */ +void tegra_bl_io_dpd_cleanup(void); + unsigned long tegra_cpu_power_good_time(void); unsigned long tegra_cpu_power_off_time(void); unsigned long tegra_cpu_lp2_min_residency(void); -- cgit v1.2.3 From b2a81ef243fbf4c317554ce5cd149fa2386216b6 Mon Sep 17 00:00:00 2001 From: Jay Agarwal Date: Mon, 16 Jul 2012 16:44:15 +0530 Subject: arm: tegra: pci: unmap/map memory while pwroff/on Rearranged the code to release all memory and res- ources whenever poweroff is called and re-allocate them whenever power on is called. Bug 963969 Change-Id: I31d9cd1e8603e638714bba765aadfdd4eed78d93 Signed-off-by: Jay Agarwal Reviewed-on: http://git-master/r/116048 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani --- arch/arm/mach-tegra/pcie.c | 133 +++++++++++++++++++++++++++++---------------- 1 file changed, 85 insertions(+), 48 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index ec386a51721c..24ca4900daa5 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -300,7 +300,7 @@ struct tegra_pcie_info { void __iomem *reg_clk_base; void __iomem *regs; - struct resource res_mmio; + struct resource *res_mmio; int power_rails_enabled; int pcie_power_enabled; struct work_struct hotplug_detect; @@ -311,20 +311,18 @@ struct tegra_pcie_info { struct clk *pcie_xclk; struct clk *pll_e; struct tegra_pci_platform_data *plat_data; -}; +}tegra_pcie; #define pmc_writel(value, reg) \ __raw_writel(value, (u32)reg_pmc_base + (reg)) #define pmc_readl(reg) \ __raw_readl((u32)reg_pmc_base + (reg)) -static struct tegra_pcie_info tegra_pcie = { - .res_mmio = { - .name = "PCI IO", - .start = MMIO_BASE, - .end = MMIO_BASE + MMIO_SIZE - 1, - .flags = IORESOURCE_MEM, - }, +struct resource tegra_pcie_res_mmio = { + .name = "PCI IO", + .start = MMIO_BASE, + .end = MMIO_BASE + MMIO_SIZE - 1, + .flags = IORESOURCE_MEM, }; static struct resource pcie_io_space; @@ -902,8 +900,10 @@ static void tegra_pcie_enable_controller(void) static int tegra_pcie_enable_regulators(void) { - if (tegra_pcie.power_rails_enabled) + if (tegra_pcie.power_rails_enabled) { + pr_debug("PCIE: Already power rails enabled"); return 0; + } if (tegra_pcie.regulator_hvdd == NULL) { printk(KERN_INFO "PCIE.C: %s : regulator hvdd_pex\n", __func__); @@ -956,8 +956,11 @@ static int tegra_pcie_enable_regulators(void) static int tegra_pcie_disable_regulators(void) { int err = 0; - if (tegra_pcie.power_rails_enabled == 0) + + if (tegra_pcie.power_rails_enabled == 0) { + pr_debug("PCIE: Already power rails disabled"); goto err_exit; + } if (tegra_pcie.regulator_hvdd) err = regulator_disable(tegra_pcie.regulator_hvdd); if (err) @@ -985,16 +988,74 @@ static int tegra_pcie_power_regate(void) return clk_enable(tegra_pcie.pll_e); } +static int tegra_pcie_power_off(void); + +static int tegra_pcie_map_resources(void) +{ + int err; + + /* Allocate config space virtual memory */ + tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ); + if (tegra_pcie.regs == NULL) { + pr_err("PCIE: Failed to map PCI/AFI registers\n"); + err = -ENOMEM; + goto err_exit; + } + + err = request_resource(&iomem_resource, &tegra_pcie_res_mmio); + if (err) { + pr_err("PCIE: Failed to request resources: %d\n", err); + goto err_exit; + } + tegra_pcie.res_mmio = &tegra_pcie_res_mmio; + + /* Allocate downstream IO virtual memory */ + tegra_pcie_io_base = ioremap_nocache(tegra_pcie_res_mmio.start, + resource_size(&tegra_pcie_res_mmio)); + if (tegra_pcie_io_base == NULL) { + pr_err("PCIE: Failed to map IO\n"); + err = -ENOMEM; + goto err_exit; + } + return 0; + +err_exit: + tegra_pcie_power_off(); + return err; +} + +void tegra_pcie_unmap_resources(void) +{ + if (tegra_pcie_io_base) { + iounmap(tegra_pcie_io_base); + tegra_pcie_io_base = 0; + } + if (tegra_pcie.res_mmio) { + release_resource(tegra_pcie.res_mmio); + tegra_pcie.res_mmio = 0; + } + if (tegra_pcie.regs) { + iounmap(tegra_pcie.regs); + tegra_pcie.regs = 0; + } +} + #ifdef CONFIG_PM static int tegra_pcie_power_on(void) { int err = 0; - if (tegra_pcie.pcie_power_enabled) - return 0; + + if (tegra_pcie.pcie_power_enabled) { + pr_debug("PCIE: Already powered on"); + goto err_exit; + } err = tegra_pcie_enable_regulators(); if (err) goto err_exit; err = tegra_pcie_power_regate(); + if (err) + goto err_exit; + err = tegra_pcie_map_resources(); if (err) goto err_exit; @@ -1007,8 +1068,12 @@ err_exit: static int tegra_pcie_power_off(void) { int err = 0; - if (tegra_pcie.pcie_power_enabled == 0) - return 0; + + if (tegra_pcie.pcie_power_enabled == 0) { + pr_debug("PCIE: Already powered off"); + goto err_exit; + } + tegra_pcie_unmap_resources(); if (tegra_pcie.pll_e) clk_disable(tegra_pcie.pll_e); @@ -1053,7 +1118,6 @@ static void tegra_pcie_clocks_put(void) static int tegra_pcie_get_resources(void) { - struct resource *res_mmio = 0; int err; tegra_pcie.power_rails_enabled = 0; @@ -1076,48 +1140,21 @@ static int tegra_pcie_get_resources(void) goto err_pwr_on; } - /* Allocate config space virtual memory */ - tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ); - if (tegra_pcie.regs == NULL) { - pr_err("PCIE: Failed to map PCI/AFI registers\n"); - err = -ENOMEM; - goto err_map_reg; - } - res_mmio = &tegra_pcie.res_mmio; - - err = request_resource(&iomem_resource, res_mmio); + err = tegra_pcie_map_resources(); if (err) { - pr_err("PCIE: Failed to request resources: %d\n", err); - goto err_req_io; - } - - /* Allocate downstream IO virtual memory */ - tegra_pcie_io_base = ioremap_nocache(res_mmio->start, - resource_size(res_mmio)); - if (tegra_pcie_io_base == NULL) { - pr_err("PCIE: Failed to map IO\n"); - err = -ENOMEM; - goto err_map_io; + pr_err("PCIE: failed to map resources: %d\n", err); + goto err_pwr_on; } err = request_irq(INT_PCIE_INTR, tegra_pcie_isr, - IRQF_SHARED, "PCIE", &tegra_pcie); + IRQF_SHARED, "PCIE", &tegra_pcie); if (err) { pr_err("PCIE: Failed to register IRQ: %d\n", err); - goto err_irq; + goto err_pwr_on; } set_irq_flags(INT_PCIE_INTR, IRQF_VALID); - return 0; -err_irq: - iounmap(tegra_pcie_io_base); -err_map_io: - release_resource(&tegra_pcie.res_mmio); -err_req_io: - iounmap(tegra_pcie.regs); -err_map_reg: - tegra_pcie_power_off(); err_pwr_on: tegra_pcie_clocks_put(); err_pwr_on_rail: -- cgit v1.2.3 From 07db1c1698a10950409a5dbbe1f273a107581eb9 Mon Sep 17 00:00:00 2001 From: Peter Zu Date: Fri, 22 Jun 2012 11:11:49 -0700 Subject: ARM: tegra: dvfs: update Tegra3 single-core dvfs table Bug 841336 Signed-off-by: Peter Zu Reviewed-on: http://git-master/r/110587 (cherry picked from commit c0e7904245168cafc426219948ab132a4d832376) Change-Id: I370f4af1d4ce888ebc71351519c1018b82d91913 Reviewed-on: http://git-master/r/116132 Tested-by: Matt Wagner Reviewed-by: Bharat Nihalani --- arch/arm/mach-tegra/dvfs.h | 2 +- arch/arm/mach-tegra/tegra3_dvfs.c | 125 +++++++++++++++++++++----------------- 2 files changed, 70 insertions(+), 57 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/dvfs.h b/arch/arm/mach-tegra/dvfs.h index d18a0382f4da..00f50751d3c4 100644 --- a/arch/arm/mach-tegra/dvfs.h +++ b/arch/arm/mach-tegra/dvfs.h @@ -21,7 +21,7 @@ #ifndef _TEGRA_DVFS_H_ #define _TEGRA_DVFS_H_ -#define MAX_DVFS_FREQS 20 +#define MAX_DVFS_FREQS 38 #define DVFS_RAIL_STATS_TOP_BIN 40 struct clk; diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c index 7d8359290a22..bc1af97e4c53 100644 --- a/arch/arm/mach-tegra/tegra3_dvfs.c +++ b/arch/arm/mach-tegra/tegra3_dvfs.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/tegra3_dvfs.c * - * Copyright (C) 2010-2012 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2010-2012, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -33,7 +33,7 @@ static bool tegra_dvfs_core_disabled; static struct dvfs *cpu_dvfs; static const int cpu_millivolts[MAX_DVFS_FREQS] = { - 800, 825, 850, 875, 900, 916, 950, 975, 1000, 1007, 1025, 1050, 1075, 1100, 1125, 1150, 1175, 1200, 1212, 1237}; + 750, 762, 775, 787, 800, 825, 837, 850, 862, 875, 887, 900, 912, 925, 937, 950, 962, 975, 987, 1000, 1012, 1025, 1037, 1050, 1062, 1075, 1087, 1100, 1112, 1125, 1137, 1150, 1162, 1175, 1187, 1200, 1212, 1237}; static const unsigned int cpu_cold_offs_mhz[MAX_DVFS_FREQS] = { 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50}; @@ -141,59 +141,59 @@ static struct dvfs_relationship tegra3_dvfs_relationships[] = { } static struct dvfs cpu_dvfs_table[] = { - /* Cpu voltages (mV): 800, 825, 850, 875, 900, 916, 950, 975, 1000, 1007, 1025, 1050, 1075, 1100, 1125, 1150, 1175, 1200, 1212, 1237 */ - CPU_DVFS("cpu_g", 0, 0, MHZ, 1, 1, 684, 684, 817, 817, 817, 1026, 1102, 1102, 1149, 1187, 1225, 1282, 1300), - CPU_DVFS("cpu_g", 0, 1, MHZ, 1, 1, 807, 807, 948, 948, 948, 1117, 1171, 1171, 1206, 1300), - CPU_DVFS("cpu_g", 0, 2, MHZ, 1, 1, 883, 883, 1039, 1039, 1039, 1178, 1206, 1206, 1300), - CPU_DVFS("cpu_g", 0, 3, MHZ, 1, 1, 931, 931, 1102, 1102, 1102, 1216, 1300, 1300), - - CPU_DVFS("cpu_g", 1, 0, MHZ, 460, 460, 550, 550, 680, 680, 680, 820, 970, 970, 1040, 1080, 1150, 1200, 1280, 1300), - CPU_DVFS("cpu_g", 1, 1, MHZ, 480, 480, 650, 650, 780, 780, 780, 990, 1040, 1040, 1100, 1200, 1300), - CPU_DVFS("cpu_g", 1, 2, MHZ, 520, 520, 700, 700, 860, 860, 860, 1050, 1150, 1150, 1200, 1300), - CPU_DVFS("cpu_g", 1, 3, MHZ, 550, 550, 770, 770, 910, 910, 910, 1150, 1230, 1230, 1300), - - CPU_DVFS("cpu_g", 2, 1, MHZ, 480, 480, 650, 650, 780, 780, 780, 990, 1040, 1040, 1100, 1200, 1250, 1300, 1330, 1400), - CPU_DVFS("cpu_g", 2, 2, MHZ, 520, 520, 700, 700, 860, 860, 860, 1050, 1150, 1150, 1200, 1280, 1300, 1350, 1400), - CPU_DVFS("cpu_g", 2, 3, MHZ, 550, 550, 770, 770, 910, 910, 910, 1150, 1230, 1230, 1280, 1300, 1350, 1400), - - CPU_DVFS("cpu_g", 3, 1, MHZ, 480, 480, 650, 650, 780, 780, 780, 990, 1040, 1040, 1100, 1200, 1250, 1300, 1330, 1400), - CPU_DVFS("cpu_g", 3, 2, MHZ, 520, 520, 700, 700, 860, 860, 860, 1050, 1150, 1150, 1200, 1280, 1300, 1350, 1400), - CPU_DVFS("cpu_g", 3, 3, MHZ, 550, 550, 770, 770, 910, 910, 910, 1150, 1230, 1230, 1280, 1300, 1350, 1400), - - CPU_DVFS("cpu_g", 4, 0, MHZ, 460, 460, 550, 550, 680, 680, 680, 820, 970, 970, 1040, 1080, 1150, 1200, 1240, 1280, 1320, 1360, 1360, 1500), - CPU_DVFS("cpu_g", 4, 1, MHZ, 480, 480, 650, 650, 780, 780, 780, 990, 1040, 1040, 1100, 1200, 1250, 1300, 1330, 1360, 1400, 1500), - CPU_DVFS("cpu_g", 4, 2, MHZ, 520, 520, 700, 700, 860, 860, 860, 1050, 1150, 1150, 1200, 1280, 1300, 1340, 1380, 1500), - CPU_DVFS("cpu_g", 4, 3, MHZ, 550, 550, 770, 770, 910, 910, 910, 1150, 1230, 1230, 1280, 1330, 1370, 1400, 1500), - - CPU_DVFS("cpu_g", 5, 3, MHZ, 550, 550, 770, 770, 910, 910, 910, 1150, 1230, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1540, 1540, 1700), - CPU_DVFS("cpu_g", 5, 4, MHZ, 550, 550, 770, 770, 940, 940, 940, 1160, 1240, 1240, 1280, 1360, 1390, 1470, 1500, 1520, 1520, 1590, 1700), - - CPU_DVFS("cpu_g", 6, 3, MHZ, 550, 550, 770, 770, 910, 910, 910, 1150, 1230, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1540, 1540, 1700), - CPU_DVFS("cpu_g", 6, 4, MHZ, 550, 550, 770, 770, 940, 940, 940, 1160, 1240, 1240, 1280, 1360, 1390, 1470, 1500, 1520, 1520, 1590, 1700), - - CPU_DVFS("cpu_g", 7, 0, MHZ, 460, 460, 550, 550, 680, 680, 680, 820, 970, 970, 1040, 1080, 1150, 1200, 1280, 1300), - CPU_DVFS("cpu_g", 7, 1, MHZ, 480, 480, 650, 650, 780, 780, 780, 990, 1040, 1040, 1100, 1200, 1300), - CPU_DVFS("cpu_g", 7, 2, MHZ, 520, 520, 700, 700, 860, 860, 860, 1050, 1150, 1150, 1200, 1300), - CPU_DVFS("cpu_g", 7, 3, MHZ, 550, 550, 770, 770, 910, 910, 910, 1150, 1230, 1230, 1300), - CPU_DVFS("cpu_g", 7, 4, MHZ, 550, 550, 770, 770, 940, 940, 940, 1160, 1300, 1300), - - CPU_DVFS("cpu_g", 8, 0, MHZ, 460, 460, 550, 550, 680, 680, 680, 820, 970, 970, 1040, 1080, 1150, 1200, 1280, 1300), - CPU_DVFS("cpu_g", 8, 1, MHZ, 480, 480, 650, 650, 780, 780, 780, 990, 1040, 1040, 1100, 1200, 1300), - CPU_DVFS("cpu_g", 8, 2, MHZ, 520, 520, 700, 700, 860, 860, 860, 1050, 1150, 1150, 1200, 1300), - CPU_DVFS("cpu_g", 8, 3, MHZ, 550, 550, 770, 770, 910, 910, 910, 1150, 1230, 1230, 1300), - CPU_DVFS("cpu_g", 8, 4, MHZ, 550, 550, 770, 770, 940, 940, 940, 1160, 1300, 1300), - - CPU_DVFS("cpu_g", 9, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900), - CPU_DVFS("cpu_g", 10, -1, MHZ, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), - CPU_DVFS("cpu_g", 11, -1, MHZ, 1, 1, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600), - CPU_DVFS("cpu_g", 14, -1, MHZ, 1, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), - CPU_DVFS("cpu_g", 15, -1, MHZ, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), - - CPU_DVFS("cpu_g", 12, 3, MHZ, 550, 550, 770, 770, 910, 910, 910, 1150, 1230, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1540, 1540, 1700), - CPU_DVFS("cpu_g", 12, 4, MHZ, 550, 550, 770, 770, 940, 940, 940, 1160, 1240, 1240, 1280, 1360, 1390, 1470, 1500, 1520, 1520, 1590, 1700), - - CPU_DVFS("cpu_g", 13, 3, MHZ, 550, 550, 770, 770, 910, 910, 910, 1150, 1230, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1540, 1540, 1700), - CPU_DVFS("cpu_g", 13, 4, MHZ, 550, 550, 770, 770, 940, 940, 940, 1160, 1240, 1240, 1280, 1360, 1390, 1470, 1500, 1520, 1520, 1590, 1700), + /* Cpu voltages (mV): 750, 762, 775, 787, 800, 825, 837, 850, 862, 875, 887, 900, 912, 925, 937, 950, 962, 975, 987, 1000, 1012, 1025, 1037, 1050, 1062, 1075, 1087, 1100, 1112, 1125, 1137, 1150, 1162, 1175, 1187, 1200, 1212, 1237 */ + CPU_DVFS("cpu_g", 0, 0, MHZ, 1, 1, 1, 1, 1, 1, 1, 684, 684, 684, 684, 817, 817, 817, 817, 817, 817, 1026, 1026, 1102, 1102, 1149, 1149, 1187, 1187, 1225, 1225, 1282, 1282, 1300), + CPU_DVFS("cpu_g", 0, 1, MHZ, 1, 1, 1, 1, 1, 1, 1, 807, 807, 807, 807, 948, 948, 948, 948, 948, 948, 1117, 1117, 1171, 1171, 1206, 1206, 1300), + CPU_DVFS("cpu_g", 0, 2, MHZ, 1, 1, 1, 1, 1, 1, 1, 883, 883, 883, 883, 1039, 1039, 1039, 1039, 1039, 1039, 1178, 1178, 1206, 1206, 1300), + CPU_DVFS("cpu_g", 0, 3, MHZ, 1, 1, 1, 1, 1, 1, 1, 931, 931, 931, 931, 1102, 1102, 1102, 1102, 1102, 1102, 1216, 1216, 1300, 1300), + + CPU_DVFS("cpu_g", 1, 0, MHZ, 1, 1, 1, 1, 460, 460, 460, 550, 550, 550, 550, 680, 680, 680, 680, 680, 680, 820, 820, 970, 970, 1040, 1040, 1080, 1080, 1150, 1150, 1200, 1200, 1280, 1280, 1300), + CPU_DVFS("cpu_g", 1, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1100, 1100, 1200, 1200, 1300), + CPU_DVFS("cpu_g", 1, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1200, 1200, 1300), + CPU_DVFS("cpu_g", 1, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1300), + + CPU_DVFS("cpu_g", 2, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1100, 1100, 1200, 1200, 1250, 1250, 1300, 1300, 1330, 1330, 1400), + CPU_DVFS("cpu_g", 2, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1200, 1200, 1280, 1280, 1300, 1300, 1350, 1350, 1400), + CPU_DVFS("cpu_g", 2, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1280, 1280, 1300, 1300, 1350, 1350, 1400), + + CPU_DVFS("cpu_g", 3, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1100, 1100, 1200, 1200, 1250, 1250, 1300, 1300, 1330, 1330, 1400), + CPU_DVFS("cpu_g", 3, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1200, 1200, 1280, 1280, 1300, 1300, 1350, 1350, 1400), + CPU_DVFS("cpu_g", 3, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1280, 1280, 1300, 1300, 1350, 1350, 1400), + + CPU_DVFS("cpu_g", 4, 0, MHZ, 1, 1, 1, 1, 460, 460, 460, 550, 550, 550, 550, 680, 680, 680, 680, 680, 680, 820, 820, 970, 970, 1040, 1040, 1080, 1080, 1150, 1150, 1200, 1200, 1240, 1240, 1280, 1280, 1320, 1320, 1360, 1360, 1500), + CPU_DVFS("cpu_g", 4, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1100, 1100, 1200, 1200, 1250, 1250, 1300, 1300, 1330, 1330, 1360, 1360, 1400, 1400, 1500), + CPU_DVFS("cpu_g", 4, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1200, 1200, 1280, 1280, 1300, 1300, 1340, 1340, 1380, 1380, 1500), + CPU_DVFS("cpu_g", 4, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1500), + + CPU_DVFS("cpu_g", 5, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1470, 1470, 1500, 1500, 1500, 1500, 1540, 1540, 1700), + CPU_DVFS("cpu_g", 5, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 1160, 1160, 1240, 1240, 1280, 1280, 1360, 1360, 1390, 1390, 1470, 1470, 1500, 1500, 1520, 1520, 1520, 1520, 1590, 1700), + + CPU_DVFS("cpu_g", 6, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1470, 1470, 1500, 1500, 1500, 1500, 1540, 1540, 1700), + CPU_DVFS("cpu_g", 6, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 1160, 1160, 1240, 1240, 1280, 1280, 1360, 1360, 1390, 1390, 1470, 1470, 1500, 1500, 1520, 1520, 1520, 1520, 1590, 1700), + + CPU_DVFS("cpu_g", 7, 0, MHZ, 1, 1, 1, 1, 460, 460, 460, 550, 550, 550, 550, 680, 680, 680, 680, 680, 680, 820, 820, 970, 970, 1040, 1040, 1080, 1080, 1150, 1150, 1200, 1200, 1280, 1280, 1300), + CPU_DVFS("cpu_g", 7, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1100, 1100, 1200, 1200, 1300), + CPU_DVFS("cpu_g", 7, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1200, 1200, 1300), + CPU_DVFS("cpu_g", 7, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1300), + CPU_DVFS("cpu_g", 7, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 1160, 1160, 1300, 1300), + + CPU_DVFS("cpu_g", 8, 0, MHZ, 1, 1, 1, 1, 460, 460, 460, 550, 550, 550, 550, 680, 680, 680, 680, 680, 680, 820, 820, 970, 970, 1040, 1040, 1080, 1080, 1150, 1150, 1200, 1200, 1280, 1280, 1300), + CPU_DVFS("cpu_g", 8, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1100, 1100, 1200, 1200, 1300), + CPU_DVFS("cpu_g", 8, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1200, 1200, 1300), + CPU_DVFS("cpu_g", 8, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1300), + CPU_DVFS("cpu_g", 8, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 1160, 1160, 1300, 1300), + + CPU_DVFS("cpu_g", 9, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), + CPU_DVFS("cpu_g", 10, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), + CPU_DVFS("cpu_g", 11, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600), + CPU_DVFS("cpu_g", 14, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), + CPU_DVFS("cpu_g", 15, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), + + CPU_DVFS("cpu_g", 12, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1470, 1470, 1500, 1500, 1500, 1500, 1540, 1540, 1700), + CPU_DVFS("cpu_g", 12, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 1160, 1160, 1240, 1240, 1280, 1280, 1360, 1360, 1390, 1390, 1470, 1470, 1500, 1500, 1520, 1520, 1520, 1520, 1590, 1700), + + CPU_DVFS("cpu_g", 13, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1470, 1470, 1500, 1500, 1500, 1500, 1540, 1540, 1700), + CPU_DVFS("cpu_g", 13, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 1160, 1160, 1240, 1240, 1280, 1280, 1360, 1360, 1390, 1390, 1470, 1470, 1500, 1500, 1520, 1520, 1520, 1520, 1590, 1700), /* * "Safe entry" to be used when no match for chip speedo, process @@ -203,7 +203,20 @@ static struct dvfs cpu_dvfs_table[] = { }; static struct dvfs cpu_0_dvfs_table[] = { - /* Cpu voltages (mV): 800, 825, 850, 875, 900, 916, 950, 975, 1000, 1007, 1025, 1050, 1075, 1100, 1125, 1150, 1175, 1200, 1212, 1237 */ + /* Cpu voltages (mV): 750, 762, 775, 787, 800, 825, 837, 850, 862, 875, 887, 900, 912, 925, 937, 950, 962, 975, 987, 1000, 1012, 1025, 1037, 1050, 1062, 1075, 1087, 1100, 1112, 1125, 1137, 1150, 1162, 1175, 1187, 1200, 1212, 1237*/ + CPU_DVFS("cpu_0", 4, 0, MHZ, 1, 1, 1, 475, 475, 475, 475, 640, 640, 640, 760, 760, 760, 860, 860, 860, 860, 860, 1000, 1000, 1000, 1100, 1100, 1100, 1100, 1200, 1200, 1200, 1200, 1200, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1500), + CPU_DVFS("cpu_0", 4, 1, MHZ, 1, 475, 475, 475, 475, 640, 640, 640, 760, 760, 760, 860, 860, 860, 860, 1000, 1000, 1000, 1100, 1100, 1100, 1100, 1200, 1200, 1200, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1400, 1400, 1500), + CPU_DVFS("cpu_0", 4, 2, MHZ, 475, 475, 475, 640, 640, 640, 760, 760, 760, 860, 860, 860, 1000, 1000, 1000, 1000, 1100, 1100, 1200, 1200, 1200, 1200, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1400, 1500), + CPU_DVFS("cpu_0", 4, 3, MHZ, 475, 475, 640, 640, 640, 760, 760, 860, 860, 860, 860, 1000, 1000, 1100, 1100, 1100, 1100, 1200, 1200, 1200, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1400, 1500), + + CPU_DVFS("cpu_0", 5, 3, MHZ, 475, 475, 620, 620, 620, 760, 760, 760, 910, 910, 910, 1000, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1700), + CPU_DVFS("cpu_0", 5, 4, MHZ, 475, 620, 620, 620, 760, 760, 760, 910, 910, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1700), + + CPU_DVFS("cpu_0", 6, 3, MHZ, 475, 475, 620, 620, 620, 760, 760, 760, 910, 910, 910, 1000, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1700), + CPU_DVFS("cpu_0", 6, 4, MHZ, 475, 620, 620, 620, 760, 760, 760, 910, 910, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1700), + + CPU_DVFS("cpu_0", 12, 3, MHZ, 475, 475, 620, 620, 620, 760, 760, 760, 910, 910, 910, 1000, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1700), + CPU_DVFS("cpu_0", 12, 4, MHZ, 475, 620, 620, 620, 760, 760, 760, 910, 910, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1700), }; #define CORE_DVFS(_clk_name, _speedo_id, _auto, _mult, _freqs...) \ -- cgit v1.2.3 From 7427955efd983959109cbfb95ae9d6564329947c Mon Sep 17 00:00:00 2001 From: Peter Zu Date: Thu, 5 Jul 2012 17:01:12 -0700 Subject: ARM: tegra: dvfs: add back 916mV & 1007mV entries Bug 841336 Signed-off-by: Peter Zu Signed-off-by: Manoj Chourasia Reviewed-on: http://git-master/r/113751 (cherry picked from commit 833f9d47a350358000e9201f77a3c9fd655d2900) Change-Id: I679093d9d2577625bff3e02e25ffe90d396ea5a6 Reviewed-on: http://git-master/r/116134 Tested-by: Matt Wagner Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani --- arch/arm/mach-tegra/dvfs.h | 2 +- arch/arm/mach-tegra/tegra3_dvfs.c | 134 +++++++++++++++++++------------------- 2 files changed, 68 insertions(+), 68 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/dvfs.h b/arch/arm/mach-tegra/dvfs.h index 00f50751d3c4..91901b361724 100644 --- a/arch/arm/mach-tegra/dvfs.h +++ b/arch/arm/mach-tegra/dvfs.h @@ -21,7 +21,7 @@ #ifndef _TEGRA_DVFS_H_ #define _TEGRA_DVFS_H_ -#define MAX_DVFS_FREQS 38 +#define MAX_DVFS_FREQS 40 #define DVFS_RAIL_STATS_TOP_BIN 40 struct clk; diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c index bc1af97e4c53..96b7fb54d8c7 100644 --- a/arch/arm/mach-tegra/tegra3_dvfs.c +++ b/arch/arm/mach-tegra/tegra3_dvfs.c @@ -33,10 +33,10 @@ static bool tegra_dvfs_core_disabled; static struct dvfs *cpu_dvfs; static const int cpu_millivolts[MAX_DVFS_FREQS] = { - 750, 762, 775, 787, 800, 825, 837, 850, 862, 875, 887, 900, 912, 925, 937, 950, 962, 975, 987, 1000, 1012, 1025, 1037, 1050, 1062, 1075, 1087, 1100, 1112, 1125, 1137, 1150, 1162, 1175, 1187, 1200, 1212, 1237}; + 750, 762, 775, 787, 800, 825, 837, 850, 862, 875, 887, 900, 912, 916, 925, 937, 950, 962, 975, 987, 1000, 1007, 1012, 1025, 1037, 1050, 1062, 1075, 1087, 1100, 1112, 1125, 1137, 1150, 1162, 1175, 1187, 1200, 1212, 1237}; static const unsigned int cpu_cold_offs_mhz[MAX_DVFS_FREQS] = { - 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50}; + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50}; static const int core_millivolts[MAX_DVFS_FREQS] = { 950, 1000, 1050, 1100, 1150, 1200, 1250, 1300, 1350}; @@ -54,7 +54,7 @@ static int cpu_below_core = VDD_CPU_BELOW_VDD_CORE; static struct dvfs_rail tegra3_dvfs_rail_vdd_cpu = { .reg_id = "vdd_cpu", .max_millivolts = 1250, - .min_millivolts = 800, + .min_millivolts = 750, .step = VDD_SAFE_STEP, .jmp_to_zero = true, }; @@ -141,59 +141,59 @@ static struct dvfs_relationship tegra3_dvfs_relationships[] = { } static struct dvfs cpu_dvfs_table[] = { - /* Cpu voltages (mV): 750, 762, 775, 787, 800, 825, 837, 850, 862, 875, 887, 900, 912, 925, 937, 950, 962, 975, 987, 1000, 1012, 1025, 1037, 1050, 1062, 1075, 1087, 1100, 1112, 1125, 1137, 1150, 1162, 1175, 1187, 1200, 1212, 1237 */ - CPU_DVFS("cpu_g", 0, 0, MHZ, 1, 1, 1, 1, 1, 1, 1, 684, 684, 684, 684, 817, 817, 817, 817, 817, 817, 1026, 1026, 1102, 1102, 1149, 1149, 1187, 1187, 1225, 1225, 1282, 1282, 1300), - CPU_DVFS("cpu_g", 0, 1, MHZ, 1, 1, 1, 1, 1, 1, 1, 807, 807, 807, 807, 948, 948, 948, 948, 948, 948, 1117, 1117, 1171, 1171, 1206, 1206, 1300), - CPU_DVFS("cpu_g", 0, 2, MHZ, 1, 1, 1, 1, 1, 1, 1, 883, 883, 883, 883, 1039, 1039, 1039, 1039, 1039, 1039, 1178, 1178, 1206, 1206, 1300), - CPU_DVFS("cpu_g", 0, 3, MHZ, 1, 1, 1, 1, 1, 1, 1, 931, 931, 931, 931, 1102, 1102, 1102, 1102, 1102, 1102, 1216, 1216, 1300, 1300), - - CPU_DVFS("cpu_g", 1, 0, MHZ, 1, 1, 1, 1, 460, 460, 460, 550, 550, 550, 550, 680, 680, 680, 680, 680, 680, 820, 820, 970, 970, 1040, 1040, 1080, 1080, 1150, 1150, 1200, 1200, 1280, 1280, 1300), - CPU_DVFS("cpu_g", 1, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1100, 1100, 1200, 1200, 1300), - CPU_DVFS("cpu_g", 1, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1200, 1200, 1300), - CPU_DVFS("cpu_g", 1, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1300), - - CPU_DVFS("cpu_g", 2, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1100, 1100, 1200, 1200, 1250, 1250, 1300, 1300, 1330, 1330, 1400), - CPU_DVFS("cpu_g", 2, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1200, 1200, 1280, 1280, 1300, 1300, 1350, 1350, 1400), - CPU_DVFS("cpu_g", 2, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1280, 1280, 1300, 1300, 1350, 1350, 1400), - - CPU_DVFS("cpu_g", 3, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1100, 1100, 1200, 1200, 1250, 1250, 1300, 1300, 1330, 1330, 1400), - CPU_DVFS("cpu_g", 3, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1200, 1200, 1280, 1280, 1300, 1300, 1350, 1350, 1400), - CPU_DVFS("cpu_g", 3, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1280, 1280, 1300, 1300, 1350, 1350, 1400), - - CPU_DVFS("cpu_g", 4, 0, MHZ, 1, 1, 1, 1, 460, 460, 460, 550, 550, 550, 550, 680, 680, 680, 680, 680, 680, 820, 820, 970, 970, 1040, 1040, 1080, 1080, 1150, 1150, 1200, 1200, 1240, 1240, 1280, 1280, 1320, 1320, 1360, 1360, 1500), - CPU_DVFS("cpu_g", 4, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1100, 1100, 1200, 1200, 1250, 1250, 1300, 1300, 1330, 1330, 1360, 1360, 1400, 1400, 1500), - CPU_DVFS("cpu_g", 4, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1200, 1200, 1280, 1280, 1300, 1300, 1340, 1340, 1380, 1380, 1500), - CPU_DVFS("cpu_g", 4, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1500), - - CPU_DVFS("cpu_g", 5, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1470, 1470, 1500, 1500, 1500, 1500, 1540, 1540, 1700), - CPU_DVFS("cpu_g", 5, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 1160, 1160, 1240, 1240, 1280, 1280, 1360, 1360, 1390, 1390, 1470, 1470, 1500, 1500, 1520, 1520, 1520, 1520, 1590, 1700), - - CPU_DVFS("cpu_g", 6, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1470, 1470, 1500, 1500, 1500, 1500, 1540, 1540, 1700), - CPU_DVFS("cpu_g", 6, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 1160, 1160, 1240, 1240, 1280, 1280, 1360, 1360, 1390, 1390, 1470, 1470, 1500, 1500, 1520, 1520, 1520, 1520, 1590, 1700), - - CPU_DVFS("cpu_g", 7, 0, MHZ, 1, 1, 1, 1, 460, 460, 460, 550, 550, 550, 550, 680, 680, 680, 680, 680, 680, 820, 820, 970, 970, 1040, 1040, 1080, 1080, 1150, 1150, 1200, 1200, 1280, 1280, 1300), - CPU_DVFS("cpu_g", 7, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1100, 1100, 1200, 1200, 1300), - CPU_DVFS("cpu_g", 7, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1200, 1200, 1300), - CPU_DVFS("cpu_g", 7, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1300), - CPU_DVFS("cpu_g", 7, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 1160, 1160, 1300, 1300), - - CPU_DVFS("cpu_g", 8, 0, MHZ, 1, 1, 1, 1, 460, 460, 460, 550, 550, 550, 550, 680, 680, 680, 680, 680, 680, 820, 820, 970, 970, 1040, 1040, 1080, 1080, 1150, 1150, 1200, 1200, 1280, 1280, 1300), - CPU_DVFS("cpu_g", 8, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1100, 1100, 1200, 1200, 1300), - CPU_DVFS("cpu_g", 8, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1200, 1200, 1300), - CPU_DVFS("cpu_g", 8, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1300), - CPU_DVFS("cpu_g", 8, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 1160, 1160, 1300, 1300), - - CPU_DVFS("cpu_g", 9, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), - CPU_DVFS("cpu_g", 10, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), - CPU_DVFS("cpu_g", 11, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600), - CPU_DVFS("cpu_g", 14, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), - CPU_DVFS("cpu_g", 15, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), - - CPU_DVFS("cpu_g", 12, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1470, 1470, 1500, 1500, 1500, 1500, 1540, 1540, 1700), - CPU_DVFS("cpu_g", 12, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 1160, 1160, 1240, 1240, 1280, 1280, 1360, 1360, 1390, 1390, 1470, 1470, 1500, 1500, 1520, 1520, 1520, 1520, 1590, 1700), - - CPU_DVFS("cpu_g", 13, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1470, 1470, 1500, 1500, 1500, 1500, 1540, 1540, 1700), - CPU_DVFS("cpu_g", 13, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 1160, 1160, 1240, 1240, 1280, 1280, 1360, 1360, 1390, 1390, 1470, 1470, 1500, 1500, 1520, 1520, 1520, 1520, 1590, 1700), + /* Cpu voltages (mV): 750, 762, 775, 787, 800, 825, 837, 850, 862, 875, 887, 900, 912, 916, 925, 937, 950, 962, 975, 987, 1000, 1007, 1012, 1025, 1037, 1050, 1062, 1075, 1087, 1100, 1112, 1125, 1137, 1150, 1162, 1175, 1187, 1200, 1212, 1237 */ + CPU_DVFS("cpu_g", 0, 0, MHZ, 1, 1, 1, 1, 1, 1, 1, 684, 684, 684, 684, 817, 817, 817, 817, 817, 817, 817, 1026, 1026, 1102, 1102, 1102, 1149, 1149, 1187, 1187, 1225, 1225, 1282, 1282, 1300), + CPU_DVFS("cpu_g", 0, 1, MHZ, 1, 1, 1, 1, 1, 1, 1, 807, 807, 807, 807, 948, 948, 948, 948, 948, 948, 948, 1117, 1117, 1171, 1171, 1171, 1206, 1206, 1300), + CPU_DVFS("cpu_g", 0, 2, MHZ, 1, 1, 1, 1, 1, 1, 1, 883, 883, 883, 883, 1039, 1039, 1039, 1039, 1039, 1039, 1039, 1178, 1178, 1206, 1206, 1206, 1300), + CPU_DVFS("cpu_g", 0, 3, MHZ, 1, 1, 1, 1, 1, 1, 1, 931, 931, 931, 931, 1102, 1102, 1102, 1102, 1102, 1102, 1102, 1216, 1216, 1300, 1300, 1300), + + CPU_DVFS("cpu_g", 1, 0, MHZ, 1, 1, 1, 1, 460, 460, 460, 550, 550, 550, 550, 680, 680, 680, 680, 680, 680, 680, 820, 820, 970, 970, 970, 1040, 1040, 1080, 1080, 1150, 1150, 1200, 1200, 1280, 1280, 1300), + CPU_DVFS("cpu_g", 1, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1040, 1100, 1100, 1200, 1200, 1300), + CPU_DVFS("cpu_g", 1, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1150, 1200, 1200, 1300), + CPU_DVFS("cpu_g", 1, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1300), + + CPU_DVFS("cpu_g", 2, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1040, 1100, 1100, 1200, 1200, 1250, 1250, 1300, 1300, 1330, 1330, 1400), + CPU_DVFS("cpu_g", 2, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1150, 1200, 1200, 1280, 1280, 1300, 1300, 1350, 1350, 1400), + CPU_DVFS("cpu_g", 2, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1280, 1280, 1300, 1300, 1350, 1350, 1400), + + CPU_DVFS("cpu_g", 3, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1040, 1100, 1100, 1200, 1200, 1250, 1250, 1300, 1300, 1330, 1330, 1400), + CPU_DVFS("cpu_g", 3, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1150, 1200, 1200, 1280, 1280, 1300, 1300, 1350, 1350, 1400), + CPU_DVFS("cpu_g", 3, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1280, 1280, 1300, 1300, 1350, 1350, 1400), + + CPU_DVFS("cpu_g", 4, 0, MHZ, 1, 1, 1, 1, 460, 460, 460, 550, 550, 550, 550, 680, 680, 680, 680, 680, 680, 680, 820, 820, 970, 970, 970, 1040, 1040, 1080, 1080, 1150, 1150, 1200, 1200, 1240, 1240, 1280, 1280, 1320, 1320, 1360, 1360, 1500), + CPU_DVFS("cpu_g", 4, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1040, 1100, 1100, 1200, 1200, 1250, 1250, 1300, 1300, 1330, 1330, 1360, 1360, 1400, 1400, 1500), + CPU_DVFS("cpu_g", 4, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1150, 1200, 1200, 1280, 1280, 1300, 1300, 1340, 1340, 1380, 1380, 1500), + CPU_DVFS("cpu_g", 4, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1500), + + CPU_DVFS("cpu_g", 5, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1470, 1470, 1500, 1500, 1500, 1500, 1540, 1540, 1700), + CPU_DVFS("cpu_g", 5, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 940, 1160, 1160, 1240, 1240, 1240, 1280, 1280, 1360, 1360, 1390, 1390, 1470, 1470, 1500, 1500, 1520, 1520, 1520, 1520, 1590, 1700), + + CPU_DVFS("cpu_g", 6, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1470, 1470, 1500, 1500, 1500, 1500, 1540, 1540, 1700), + CPU_DVFS("cpu_g", 6, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 940, 1160, 1160, 1240, 1240, 1240, 1280, 1280, 1360, 1360, 1390, 1390, 1470, 1470, 1500, 1500, 1520, 1520, 1520, 1520, 1590, 1700), + + CPU_DVFS("cpu_g", 7, 0, MHZ, 1, 1, 1, 1, 460, 460, 460, 550, 550, 550, 550, 680, 680, 680, 680, 680, 680, 680, 820, 820, 970, 970, 970, 1040, 1040, 1080, 1080, 1150, 1150, 1200, 1200, 1280, 1280, 1300), + CPU_DVFS("cpu_g", 7, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1040, 1100, 1100, 1200, 1200, 1300), + CPU_DVFS("cpu_g", 7, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1150, 1200, 1200, 1300), + CPU_DVFS("cpu_g", 7, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1300), + CPU_DVFS("cpu_g", 7, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 940, 1160, 1160, 1300, 1300, 1300), + + CPU_DVFS("cpu_g", 8, 0, MHZ, 1, 1, 1, 1, 460, 460, 460, 550, 550, 550, 550, 680, 680, 680, 680, 680, 680, 680, 820, 820, 970, 970, 970, 1040, 1040, 1080, 1080, 1150, 1150, 1200, 1200, 1280, 1280, 1300), + CPU_DVFS("cpu_g", 8, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1040, 1100, 1100, 1200, 1200, 1300), + CPU_DVFS("cpu_g", 8, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1150, 1200, 1200, 1300), + CPU_DVFS("cpu_g", 8, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1300), + CPU_DVFS("cpu_g", 8, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 940, 1160, 1160, 1300, 1300, 1300), + + CPU_DVFS("cpu_g", 9, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), + CPU_DVFS("cpu_g", 10, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), + CPU_DVFS("cpu_g", 11, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600), + CPU_DVFS("cpu_g", 14, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), + CPU_DVFS("cpu_g", 15, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), + + CPU_DVFS("cpu_g", 12, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1470, 1470, 1500, 1500, 1500, 1500, 1540, 1540, 1700), + CPU_DVFS("cpu_g", 12, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 940, 1160, 1160, 1240, 1240, 1240, 1280, 1280, 1360, 1360, 1390, 1390, 1470, 1470, 1500, 1500, 1520, 1520, 1520, 1520, 1590, 1700), + + CPU_DVFS("cpu_g", 13, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1470, 1470, 1500, 1500, 1500, 1500, 1540, 1540, 1700), + CPU_DVFS("cpu_g", 13, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 940, 1160, 1160, 1240, 1240, 1240, 1280, 1280, 1360, 1360, 1390, 1390, 1470, 1470, 1500, 1500, 1520, 1520, 1520, 1520, 1590, 1700), /* * "Safe entry" to be used when no match for chip speedo, process @@ -203,20 +203,20 @@ static struct dvfs cpu_dvfs_table[] = { }; static struct dvfs cpu_0_dvfs_table[] = { - /* Cpu voltages (mV): 750, 762, 775, 787, 800, 825, 837, 850, 862, 875, 887, 900, 912, 925, 937, 950, 962, 975, 987, 1000, 1012, 1025, 1037, 1050, 1062, 1075, 1087, 1100, 1112, 1125, 1137, 1150, 1162, 1175, 1187, 1200, 1212, 1237*/ - CPU_DVFS("cpu_0", 4, 0, MHZ, 1, 1, 1, 475, 475, 475, 475, 640, 640, 640, 760, 760, 760, 860, 860, 860, 860, 860, 1000, 1000, 1000, 1100, 1100, 1100, 1100, 1200, 1200, 1200, 1200, 1200, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1500), - CPU_DVFS("cpu_0", 4, 1, MHZ, 1, 475, 475, 475, 475, 640, 640, 640, 760, 760, 760, 860, 860, 860, 860, 1000, 1000, 1000, 1100, 1100, 1100, 1100, 1200, 1200, 1200, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1400, 1400, 1500), - CPU_DVFS("cpu_0", 4, 2, MHZ, 475, 475, 475, 640, 640, 640, 760, 760, 760, 860, 860, 860, 1000, 1000, 1000, 1000, 1100, 1100, 1200, 1200, 1200, 1200, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1400, 1500), - CPU_DVFS("cpu_0", 4, 3, MHZ, 475, 475, 640, 640, 640, 760, 760, 860, 860, 860, 860, 1000, 1000, 1100, 1100, 1100, 1100, 1200, 1200, 1200, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1400, 1500), + /* Cpu voltages (mV): 750, 762, 775, 787, 800, 825, 837, 850, 862, 875, 887, 900, 912, 916, 925, 937, 950, 962, 975, 987, 1000, 1007, 1012, 1025, 1037, 1050, 1062, 1075, 1087, 1100, 1112, 1125, 1137, 1150, 1162, 1175, 1187, 1200, 1212, 1237*/ + CPU_DVFS("cpu_0", 4, 0, MHZ, 1, 1, 1, 475, 475, 475, 475, 640, 640, 640, 760, 760, 760, 760, 860, 860, 860, 860, 860, 1000, 1000, 1000, 1000, 1100, 1100, 1100, 1100, 1200, 1200, 1200, 1200, 1200, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1500), + CPU_DVFS("cpu_0", 4, 1, MHZ, 1, 475, 475, 475, 475, 640, 640, 640, 760, 760, 760, 860, 860, 860, 860, 860, 1000, 1000, 1000, 1100, 1100, 1100, 1100, 1100, 1200, 1200, 1200, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1400, 1400, 1500), + CPU_DVFS("cpu_0", 4, 2, MHZ, 475, 475, 475, 640, 640, 640, 760, 760, 760, 860, 860, 860, 1000, 1000, 1000, 1000, 1000, 1100, 1100, 1200, 1200, 1200, 1200, 1200, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1400, 1500), + CPU_DVFS("cpu_0", 4, 3, MHZ, 475, 475, 640, 640, 640, 760, 760, 860, 860, 860, 860, 1000, 1000, 1000, 1100, 1100, 1100, 1100, 1200, 1200, 1200, 1200, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1400, 1500), - CPU_DVFS("cpu_0", 5, 3, MHZ, 475, 475, 620, 620, 620, 760, 760, 760, 910, 910, 910, 1000, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1700), - CPU_DVFS("cpu_0", 5, 4, MHZ, 475, 620, 620, 620, 760, 760, 760, 910, 910, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1700), + CPU_DVFS("cpu_0", 5, 3, MHZ, 475, 475, 620, 620, 620, 760, 760, 760, 910, 910, 910, 1000, 1000, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1700), + CPU_DVFS("cpu_0", 5, 4, MHZ, 475, 620, 620, 620, 760, 760, 760, 910, 910, 1000, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1700), - CPU_DVFS("cpu_0", 6, 3, MHZ, 475, 475, 620, 620, 620, 760, 760, 760, 910, 910, 910, 1000, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1700), - CPU_DVFS("cpu_0", 6, 4, MHZ, 475, 620, 620, 620, 760, 760, 760, 910, 910, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1700), + CPU_DVFS("cpu_0", 6, 3, MHZ, 475, 475, 620, 620, 620, 760, 760, 760, 910, 910, 910, 1000, 1000, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1700), + CPU_DVFS("cpu_0", 6, 4, MHZ, 475, 620, 620, 620, 760, 760, 760, 910, 910, 1000, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1700), - CPU_DVFS("cpu_0", 12, 3, MHZ, 475, 475, 620, 620, 620, 760, 760, 760, 910, 910, 910, 1000, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1700), - CPU_DVFS("cpu_0", 12, 4, MHZ, 475, 620, 620, 620, 760, 760, 760, 910, 910, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1700), + CPU_DVFS("cpu_0", 12, 3, MHZ, 475, 475, 620, 620, 620, 760, 760, 760, 910, 910, 910, 1000, 1000, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1700), + CPU_DVFS("cpu_0", 12, 4, MHZ, 475, 620, 620, 620, 760, 760, 760, 910, 910, 1000, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1700), }; #define CORE_DVFS(_clk_name, _speedo_id, _auto, _mult, _freqs...) \ -- cgit v1.2.3 From 147bf262ca48438ec8dca6dcbeff3f1cc456a82c Mon Sep 17 00:00:00 2001 From: Peter Zu Date: Wed, 4 Jul 2012 18:56:48 -0700 Subject: ARM: tegra: clock: relax memory efficiency if 3d clock is off Bug 1003509 Change-Id: I8fb2c0cff7106671f8470b836ea26c09350d6206 Signed-off-by: Peter Zu (cherry picked from commit df2dda0438c2aed3a961d197dce7319fefdf5b30) Reviewed-on: http://git-master/r/115468 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/tegra3_clocks.c | 8 ++++++-- arch/arm/mach-tegra/tegra3_emc.c | 21 +++++++++++++++++++++ arch/arm/mach-tegra/tegra3_emc.h | 3 ++- 3 files changed, 29 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 40030cb00e3a..6b510f612526 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -3073,6 +3073,7 @@ static int tegra3_clk_shared_bus_update(struct clk *bus) unsigned long rate = bus->min_rate; unsigned long bw = 0; unsigned long ceiling = bus->max_rate; + u8 emc_bw_efficiency = tegra_emc_bw_efficiency_boost; if (detach_shared_bus) return 0; @@ -3086,6 +3087,9 @@ static int tegra3_clk_shared_bus_update(struct clk *bus) */ if (c->u.shared_bus_user.enabled || (c->u.shared_bus_user.mode == SHARED_CEILING)) { + if (!strcmp(c->name, "3d.emc")) + emc_bw_efficiency = tegra_emc_bw_efficiency; + switch (c->u.shared_bus_user.mode) { case SHARED_BW: if (bw < bus->max_rate) @@ -3105,8 +3109,8 @@ static int tegra3_clk_shared_bus_update(struct clk *bus) if (bw) { if (bus->flags & PERIPH_EMC_ENB) { - bw = tegra_emc_bw_efficiency ? - (bw / tegra_emc_bw_efficiency) : bus->max_rate; + bw = emc_bw_efficiency ? + (bw / emc_bw_efficiency) : bus->max_rate; bw = (bw < bus->max_rate / 100) ? (bw * 100) : bus->max_rate; } diff --git a/arch/arm/mach-tegra/tegra3_emc.c b/arch/arm/mach-tegra/tegra3_emc.c index a138091d9197..57a673b4df8d 100644 --- a/arch/arm/mach-tegra/tegra3_emc.c +++ b/arch/arm/mach-tegra/tegra3_emc.c @@ -46,6 +46,7 @@ static bool emc_enable; module_param(emc_enable, bool, 0644); u8 tegra_emc_bw_efficiency = 35; +u8 tegra_emc_bw_efficiency_boost = 45; #define EMC_MIN_RATE_DDR3 25500000 #define EMC_STATUS_UPDATE_TIMEOUT 100 @@ -1379,6 +1380,22 @@ static int efficiency_set(void *data, u64 val) DEFINE_SIMPLE_ATTRIBUTE(efficiency_fops, efficiency_get, efficiency_set, "%llu\n"); +static int efficiency_boost_get(void *data, u64 *val) +{ + *val = tegra_emc_bw_efficiency_boost; + return 0; +} +static int efficiency_boost_set(void *data, u64 val) +{ + tegra_emc_bw_efficiency_boost = (val > 100) ? 100 : val; + if (emc) + tegra_clk_shared_bus_update(emc); + + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(efficiency_boost_fops, efficiency_boost_get, + efficiency_boost_set, "%llu\n"); + static int __init tegra_emc_debug_init(void) { if (!tegra_emc_table) @@ -1408,6 +1425,10 @@ static int __init tegra_emc_debug_init(void) emc_debugfs_root, NULL, &efficiency_fops)) goto err_out; + if (!debugfs_create_file("efficiency_boost", S_IRUGO | S_IWUSR, + emc_debugfs_root, NULL, &efficiency_boost_fops)) + goto err_out; + return 0; err_out: diff --git a/arch/arm/mach-tegra/tegra3_emc.h b/arch/arm/mach-tegra/tegra3_emc.h index f59654295ba4..29b4556d749d 100644 --- a/arch/arm/mach-tegra/tegra3_emc.h +++ b/arch/arm/mach-tegra/tegra3_emc.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/tegra3_emc.h * - * Copyright (C) 2012 NVIDIA Corporation + * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,6 +28,7 @@ #define TEGRA_EMC_BRIDGE_MVOLTS_MIN 1200 extern u8 tegra_emc_bw_efficiency; +extern u8 tegra_emc_bw_efficiency_boost; struct tegra_emc_table { u8 rev; -- cgit v1.2.3 From e67927dd092fec85d4026f1e19b42b47266b4208 Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Thu, 17 May 2012 22:11:55 -0700 Subject: ARM: tegra: power: Enforce CPU rate range in secondary boot On Tegra3 make sure cpu rate is within G-mode range before LP to G mode switch triggered by secondary cpu boot directly from LP mode. Bug 988544 Change-Id: I0d86fbf0727a6bbf6069159e7c532947a9d0af73 Signed-off-by: Alex Frid Reviewed-on: http://git-master/r/115930 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Peter Boonstoppel Reviewed-by: Greg Lo Reviewed-by: Yu-Huan Hsu --- arch/arm/mach-tegra/platsmp.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index d1178a820f39..d36b18934acd 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -32,6 +32,7 @@ #include "clock.h" #include "reset.h" #include "sleep.h" +#include "cpu-tegra.h" bool tegra_all_cpus_booted; @@ -209,8 +210,16 @@ int boot_secondary(unsigned int cpu, struct task_struct *idle) /* Early boot, clock infrastructure is not initialized - CPU mode switch is not allowed */ status = -EINVAL; - } else + } else { +#ifdef CONFIG_CPU_FREQ + /* set cpu rate is within g-mode range before switch */ + unsigned int speed = max( + (unsigned long)tegra_getspeed(0), + clk_get_min_rate(cpu_g_clk) / 1000); + tegra_update_cpu_speed(speed); +#endif status = clk_set_parent(cpu_clk, cpu_g_clk); + } if (status) goto done; -- cgit v1.2.3 From 8ecf3112449b1b34d16de9545a6af50c766d30f4 Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Sat, 14 Jul 2012 20:11:04 -0700 Subject: ARM: tegra: clock: Reduce Tegra3 pll post-lock delay Reduced pll post-lock delay from 50us to 2us. Rearranged wait for lock loop to delay first check of lock bit by 2us after pll is enabled. Added read fence for PLLM lock via PMC (in this case enable bit is in APB bus register, but lock detect bit is in PPSB bus register). Bug 1017271 Change-Id: Ibc963533854383e884d87be61e1b98e9d54d3ea0 Signed-off-by: Alex Frid Reviewed-on: http://git-master/r/115933 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/clock.h | 2 +- arch/arm/mach-tegra/tegra3_clocks.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index c27176b1cc0d..888808461bb9 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -27,7 +27,7 @@ #else #define USE_PLL_LOCK_BITS 1 /* Use lock bits for PLL stabiliation */ #define USE_PLLE_SS 1 /* Use spread spectrum coefficients for PLLE */ -#define PLL_POST_LOCK_DELAY 50 /* Safety delay after lock is detected */ +#define PLL_POST_LOCK_DELAY 2 /* Safety delay after lock is detected */ #endif #define DIV_BUS (1 << 0) diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 6b510f612526..bf7fde0154db 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -1395,11 +1395,11 @@ static int tegra3_pll_clk_wait_for_lock(struct clk *c, u32 lock_reg, u32 lock_bi #if USE_PLL_LOCK_BITS int i; for (i = 0; i < c->u.pll.lock_delay; i++) { + udelay(2); /* timeout = 2 * lock time */ if (clk_readl(lock_reg) & lock_bit) { udelay(PLL_POST_LOCK_DELAY); return 0; } - udelay(2); /* timeout = 2 * lock time */ } pr_err("Timed out waiting for lock bit on pll %s", c->name); return -1; @@ -1556,6 +1556,7 @@ static int tegra3_pll_clk_enable(struct clk *c) val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; pmc_writel(val, PMC_PLLP_WB0_OVERRIDE); + pmc_readl(PMC_PLLP_WB0_OVERRIDE); } tegra3_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK); -- cgit v1.2.3 From d7acce488a847262cb783b9caa77d37794f6daf1 Mon Sep 17 00:00:00 2001 From: Mohit Kataria Date: Wed, 20 Jun 2012 11:05:39 +0530 Subject: ARM: Tegra3: clocks: Configurable cbus divider Added config option to set cbus divider. Bug 978870 Change-Id: I49c57064ce695dd703ad97a50b8c0d373f5a05d0 Signed-off-by: Mohit Kataria Reviewed-on: http://git-master/r/114197 (cherry picked from commit 3f2b0e2b973a106d62e1f4bfb75bb40bd1a96b9b) Reviewed-on: http://git-master/r/109962 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/Kconfig | 4 ++++ arch/arm/mach-tegra/tegra3_clocks.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index ed35a91c575c..b84d32add5f8 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -430,6 +430,10 @@ config TEGRA_SE_ON_CBUS help This option enables SE clock to be derived from cbus +config TEGRA_CBUS_CLOCK_DIVIDER + int "CBUS clock divider" + default "2" + config TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND bool "Use conservative cpu frequency governor when device enters early suspend" depends on HAS_EARLYSUSPEND && CPU_FREQ diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index bf7fde0154db..87592e2ee3c5 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -4232,7 +4232,7 @@ static struct clk tegra_clk_cbus = { .ops = &tegra_clk_cbus_ops, .max_rate = 700000000, .mul = 1, - .div = 2, + .div = CONFIG_TEGRA_CBUS_CLOCK_DIVIDER, .flags = PERIPH_ON_CBUS, .shared_bus_backup = { .input = &tegra_pll_p, -- cgit v1.2.3 From 8928dee2d0ddef01bff38c0cbb7931487f66de39 Mon Sep 17 00:00:00 2001 From: Ramalingam C Date: Wed, 11 Jul 2012 14:47:48 +0530 Subject: arm: tegra: cardhu: IrDA support on UARTB Adds the IrDA support functions to the platform_data of UARTB on Verbier boards(E1198 and E1186). And also adds a config variable CONFIG_TEGRA_IRDA to control the IrDA support on Tegra. Bug 999895 Change-Id: Iab77c419004292190421d55fd02e249ff98c728e Signed-off-by: Ramalingam C Reviewed-on: http://git-master/r/114930 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/Kconfig | 8 ++ arch/arm/mach-tegra/Makefile | 1 + arch/arm/mach-tegra/board-cardhu-irda.c | 178 ++++++++++++++++++++++++++++++++ arch/arm/mach-tegra/board-cardhu.c | 25 +++++ arch/arm/mach-tegra/board-cardhu.h | 2 + 5 files changed, 214 insertions(+) create mode 100644 arch/arm/mach-tegra/board-cardhu-irda.c (limited to 'arch') diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index b84d32add5f8..b69f0dc6e24d 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -90,6 +90,14 @@ config TEGRA_PCI help Adds PCIe Host controller driver for tegra based systems +config TEGRA_IRDA + bool "IRDA on UARTB Port of Verbier" + select IRDA_CPLD + depends on ARCH_TEGRA_3x_SOC && MACH_CARDHU + help + Adds support for Vishay IrDA transceiver at UARTB port + of Verbier Boards(E1186 and E1198) with no ULPI rework done. + comment "Tegra board type" config MACH_HARMONY diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 6a563be1495a..cf51359c32e7 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -163,6 +163,7 @@ obj-${CONFIG_MACH_WHISTLER} += board-whistler-memory.o obj-${CONFIG_MACH_CARDHU} += board-cardhu.o obj-${CONFIG_MACH_CARDHU} += board-cardhu-kbc.o +obj-${CONFIG_MACH_CARDHU} += board-cardhu-irda.o obj-${CONFIG_MACH_CARDHU} += board-cardhu-panel.o obj-${CONFIG_MACH_CARDHU} += board-cardhu-pinmux.o obj-${CONFIG_MACH_CARDHU} += board-cardhu-power.o diff --git a/arch/arm/mach-tegra/board-cardhu-irda.c b/arch/arm/mach-tegra/board-cardhu-irda.c new file mode 100644 index 000000000000..489d473fc08f --- /dev/null +++ b/arch/arm/mach-tegra/board-cardhu-irda.c @@ -0,0 +1,178 @@ +/* + * arch/arm/mach-tegra/board-cardhu-irda.c + * + * Copyright (c) 2012, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +/* This driver tested with tfdu6103 irda transceiver */ + +#include +#include +#include +#include + +#include "gpio-names.h" +#include "board-cardhu.h" +#include "board.h" +#include "devices.h" + +/* Uncomment the next line to get the function entry logs */ +/*#define DRV_FUNC 1*/ + +#undef FPRINT +#ifdef DRV_FUNC +#define FPRINT(fmt, args...) printk(KERN_INFO "IRDA: " fmt, ## args) +#else +#define FPRINT(fmt, args...) +#endif + +#define CARDHU_IRDA_SD TEGRA_GPIO_PJ6 +#define CARDHU_IRDA_TX TEGRA_GPIO_PC2 +#define CARDHU_IRDA_RX TEGRA_GPIO_PC3 + +#define IRDA_DELAY 1 + +#define SIR 1 +#define FIR 2 +#define VFIR 3 /* tfdu6108 doesn't support */ + + +static int irda_mode; + +/* If mode = SIR mode switch will be FIR -> SIR + If mode = FIR mode switch will be SIR ->FIR */ + +static int cardhu_irda_mode_switch(int mode) +{ + int ret = -1; + + FPRINT("Start of Func %s\n", __func__); + + if ((mode != SIR) && (mode != FIR)) { + pr_err("Unsupported irda mode\n"); + return ret; + } + + gpio_set_value(CARDHU_IRDA_SD, 1); + + udelay(IRDA_DELAY); + + ret = gpio_request(CARDHU_IRDA_TX, "irda_tx"); + if (ret < 0) { + pr_err("%s: cardhu_irda_tx gpio request failed %d\n", + __func__, ret); + gpio_set_value(CARDHU_IRDA_SD, 0); + return ret; + } + + if (mode == SIR) + ret = gpio_direction_output(CARDHU_IRDA_TX, 0); + else if (mode == FIR) + ret = gpio_direction_output(CARDHU_IRDA_TX, 1); + + if (ret) { + pr_err("%s: cardhu_irda_tx Direction configuration failed %d\n", + __func__, ret); + gpio_set_value(CARDHU_IRDA_SD, 0); + goto closure; + } + + udelay(IRDA_DELAY); + + gpio_set_value(CARDHU_IRDA_SD, 0); + + udelay(IRDA_DELAY); + + if (mode == FIR) { + gpio_set_value(CARDHU_IRDA_TX, 0); + irda_mode = FIR; + pr_info("IrDA Transceiver is switched to FIR mode\n"); + } else { + pr_info("IrDA Transceiver is switched to SIR mode\n"); + irda_mode = SIR; + } + + udelay(IRDA_DELAY); + +closure: + gpio_free(CARDHU_IRDA_TX); + return ret; +} + +static int SD_config(void) +{ + int ret = -1; + + FPRINT("Start of the Func %s\n", __func__); + /* Gpio enable for SD */ + ret = gpio_request(CARDHU_IRDA_SD, "irda_sd"); + if (ret < 0) { + pr_err("%s: cardhu_irda_sd gpio request failed %d\n", + __func__, ret); + return ret; + } + + ret = gpio_direction_output(CARDHU_IRDA_SD, 1); + if (ret) + pr_err("%s: cardhu_irda_sd Direction configuration failed %d\n", + __func__, ret); + return ret; +} + +static void cardhu_irda_start(void) +{ + FPRINT("Start of the Func %s\n", __func__); + pr_info("IrDA transceiver is enabled\n"); + gpio_set_value(CARDHU_IRDA_SD, 0); + irda_mode = SIR; +} + +static void cardhu_irda_shutdown(void) +{ + FPRINT("Start of the Func %s\n", __func__); + pr_info("IrDA transceiver is disabled\n"); + /* Setting the IrDA transceiver into shutdown mode*/ + gpio_set_value(CARDHU_IRDA_SD, 1); +} + +static int cardhu_irda_init(void) +{ + int ret = 0; + + FPRINT("Start of the Func %s\n", __func__); + if (SD_config() < 0) { + pr_err("%s: Error in IRDA_SD signal configuration\n", __func__); + ret = -1; + } + return ret; +} + +static void cardhu_irda_remove(void) +{ + FPRINT("Start of the Func %s\n", __func__); + gpio_free(CARDHU_IRDA_SD); +} + + +struct tegra_uart_platform_data cardhu_irda_pdata = { + .is_irda = true, + .irda_init = cardhu_irda_init, + .irda_start = cardhu_irda_start, + .irda_mode_switch = cardhu_irda_mode_switch, + .irda_shutdown = cardhu_irda_shutdown, + .irda_remove = cardhu_irda_remove, +}; diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c index f8fb5c528cbd..80cab77df587 100644 --- a/arch/arm/mach-tegra/board-cardhu.c +++ b/arch/arm/mach-tegra/board-cardhu.c @@ -492,6 +492,16 @@ static void __init uart_debug_init(void) debug_port_id = 1; } +#ifdef CONFIG_TEGRA_IRDA + if ((board_info.board_id == BOARD_E1186) || + (board_info.board_id == BOARD_E1198)) { + if (debug_port_id == 1) { + cardhu_irda_pdata.is_irda = false; + pr_err("UARTB is not available for IrDA\n"); + } + } +#endif + switch (debug_port_id) { case 0: /* UARTA is the debug port. */ @@ -553,6 +563,9 @@ static void __init cardhu_uart_init(void) { struct clk *c; int i; + struct board_info board_info; + + tegra_get_board_info(&board_info); for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) { c = tegra_get_clock_by_name(uart_parent_clk[i].name); @@ -598,6 +611,18 @@ static void __init cardhu_uart_init(void) } } +#ifdef CONFIG_TEGRA_IRDA + if (((board_info.board_id == BOARD_E1186) || + (board_info.board_id == BOARD_E1198)) && + cardhu_irda_pdata.is_irda) { + cardhu_irda_pdata.parent_clk_list = uart_parent_clk; + cardhu_irda_pdata.parent_clk_count = + ARRAY_SIZE(uart_parent_clk); + + tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata; + } +#endif + platform_add_devices(cardhu_uart_devices, ARRAY_SIZE(cardhu_uart_devices)); } diff --git a/arch/arm/mach-tegra/board-cardhu.h b/arch/arm/mach-tegra/board-cardhu.h index a8be32ec9cdd..7c6a132421f0 100644 --- a/arch/arm/mach-tegra/board-cardhu.h +++ b/arch/arm/mach-tegra/board-cardhu.h @@ -221,6 +221,8 @@ int cardhu_pm298_regulator_init(void); int cardhu_pm299_gpio_switch_regulator_init(void); int cardhu_pm299_regulator_init(void); +extern struct tegra_uart_platform_data cardhu_irda_pdata; + #define MPU_TYPE_MPU3050 1 #define MPU_TYPE_MPU6050 2 #define MPU_GYRO_TYPE MPU_TYPE_MPU3050 -- cgit v1.2.3 From f8f3f9dd17aeef2c1fd2119a3f3cc8b0791c548c Mon Sep 17 00:00:00 2001 From: Ramalingam C Date: Thu, 19 Jul 2012 14:54:30 +0530 Subject: arm: config: tegra3: Enable IrDA support Enables the IrDA support on E1198 and E1186 platforms. This will enable the access to the IrDA transceiver through (/dev/ttyHS1) UARTB of verbier (E1240). Bug 999895 Change-Id: Ib2b8391facddf12b3b48d319e11f548d9f963712 Signed-off-by: Ramalingam C Reviewed-on: http://git-master/r/114952 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan --- arch/arm/configs/tegra3_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/tegra3_defconfig b/arch/arm/configs/tegra3_defconfig index 0739438d704a..95ca04c1832a 100644 --- a/arch/arm/configs/tegra3_defconfig +++ b/arch/arm/configs/tegra3_defconfig @@ -27,6 +27,7 @@ CONFIG_ARCH_TEGRA=y CONFIG_GPIO_PCA953X=y CONFIG_ARCH_TEGRA_3x_SOC=y CONFIG_TEGRA_PCI=y +CONFIG_TEGRA_IRDA=y CONFIG_MACH_CARDHU=y CONFIG_MACH_TEGRA_ENTERPRISE=y CONFIG_TEGRA_PWM=y -- cgit v1.2.3 From 33a657014d3cabea3de90b47ddc9325d0e5af4fa Mon Sep 17 00:00:00 2001 From: Rakesh Bodla Date: Fri, 20 Jul 2012 11:41:09 +0530 Subject: ARM: tegra: phy: avoid illegal access to registers Adding the conditions to prevent illegal register access. Bug 993380 Bug 1006579 Reviewed-on: http://git-master/r/113138 (cherry picked from commit a3c026a229bbce614d7f40319bada1d7bf42942d) Change-Id: I0d8e6c20aab04aa43ae484dc8ceb6fcb2c27d151 Reviewed-on: http://git-master/r/117256 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Rakesh Bodla Tested-by: Rakesh Bodla GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty --- arch/arm/mach-tegra/tegra2_usb_phy.c | 2 ++ arch/arm/mach-tegra/tegra3_usb_phy.c | 10 +++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra2_usb_phy.c b/arch/arm/mach-tegra/tegra2_usb_phy.c index a3440f41bf3c..c7f4a771b1d8 100644 --- a/arch/arm/mach-tegra/tegra2_usb_phy.c +++ b/arch/arm/mach-tegra/tegra2_usb_phy.c @@ -612,6 +612,8 @@ static int utmi_phy_irq(struct tegra_usb_phy *phy) val = readl(base + USB_PORTSC); val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS); writel(val , (base + USB_PORTSC)); + } else if (!phy->phy_clk_on) { + return IRQ_NONE; } } diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index 3a3293eba06a..3152bdf9e107 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -1222,11 +1222,13 @@ static int utmi_phy_irq(struct tegra_usb_phy *phy) void __iomem *base = phy->regs; unsigned long val = 0; - DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); - DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n", + if (phy->phy_clk_on) { + DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); + DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n", readl(base + USB_USBSTS), readl(base + USB_PORTSC)); - DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n", + DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n", readl(base + USB_USBMODE), readl(base + USB_USBCMD)); + } usb_phy_fence_read(phy); /* check if there is any remote wake event */ @@ -1246,6 +1248,8 @@ static int utmi_phy_irq(struct tegra_usb_phy *phy) val = readl(base + USB_PORTSC); val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS); writel(val , (base + USB_PORTSC)); + } else if (!phy->phy_clk_on) { + return IRQ_NONE; } } -- cgit v1.2.3 From f2db920843ba82c5041213d36c4e2a96c9e86b54 Mon Sep 17 00:00:00 2001 From: Prem Sasidharan Date: Tue, 26 Jun 2012 16:27:42 -0700 Subject: arm: tegra: E1506 Tristate and pull down LCD pins Tristating and pulling down LCD_PCLK,LCD_WR_N,LCD_HSYNC,LCD_VSYNC LCD_SCK,LCD_SDOUT and LCD_SCIN for E1506 DSI panel. Bug 999702 Signed-off-by: Prem Sasidharan Reviewed-on: http://git-master/r/111390 (cherry picked from commit 822a1c8ce2a50ff7b53cdd811c3ae1e47568d69d) Change-Id: Icba97ddcbc4e7bd0b8c4744703e85bf8bc94ba69 Reviewed-on: http://git-master/r/117308 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Bharat Nihalani Reviewed-by: Bharat Nihalani --- arch/arm/mach-tegra/board-cardhu-pinmux.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-pinmux.c b/arch/arm/mach-tegra/board-cardhu-pinmux.c index 9ecb2f2d80e5..09d7c8911f22 100644 --- a/arch/arm/mach-tegra/board-cardhu-pinmux.c +++ b/arch/arm/mach-tegra/board-cardhu-pinmux.c @@ -542,6 +542,16 @@ static __initdata struct tegra_pingroup_config unused_pins_lowpower[] = { DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT), }; +static __initdata struct tegra_pingroup_config unused_pins_lowpower_e1506[] = { + DEFAULT_PINMUX(LCD_PCLK, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_WR_N, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_HSYNC, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_VSYNC, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_SCK, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_SDOUT, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_SDIN, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), +}; + static __initdata struct tegra_pingroup_config gmi_pins_269[] = { /* Continuation of table unused_pins_lowpower only for PM269 */ DEFAULT_PINMUX(GMI_CS0_N, NAND, PULL_UP, NORMAL, OUTPUT), @@ -692,6 +702,8 @@ int __init cardhu_pinmux_init(void) if (display_board_info.board_id == BOARD_DISPLAY_E1506) { tegra_pinmux_config_table(cardhu_pinmux_pm269_e1506, ARRAY_SIZE(cardhu_pinmux_pm269_e1506)); + tegra_pinmux_config_table(unused_pins_lowpower_e1506, + ARRAY_SIZE(unused_pins_lowpower_e1506)); } tegra_pinmux_config_table(unused_pins_lowpower, -- cgit v1.2.3 From 2f156d6e7e0bbd3e76d25fe5191f232de316c3c3 Mon Sep 17 00:00:00 2001 From: Rakesh Goyal Date: Fri, 20 Jul 2012 14:49:57 +0530 Subject: arm: tegra: enterprise: increase drive strength for sdmmc1 Bug 987713 Change-Id: I4e6fb47007e337ec992d5ee58510c664957b448d Signed-off-by: Rakesh Goyal Reviewed-on: http://git-master/r/117592 GVS: Gerrit_Virtual_Submit Reviewed-by: Rakesh Kumar Reviewed-by: Pavan Kunapuli Reviewed-by: Laxman Dewangan --- arch/arm/mach-tegra/board-enterprise-pinmux.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-pinmux.c b/arch/arm/mach-tegra/board-enterprise-pinmux.c index 721eb0d27576..c946d2ee5f40 100644 --- a/arch/arm/mach-tegra/board-enterprise-pinmux.c +++ b/arch/arm/mach-tegra/board-enterprise-pinmux.c @@ -84,6 +84,9 @@ static __initdata struct tegra_drive_pingroup_config enterprise_drive_pinmux[] = /* UART3 */ SET_DRIVE(UART3, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* SDMMC1 */ + SET_DRIVE(SDIO1, DISABLE, DISABLE, DIV_1, 46, 42, FAST, FAST), }; #define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io) \ -- cgit v1.2.3 From 8615a322ddf8c836579c56aabb0c56c891d9849c Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Mon, 23 Jul 2012 13:30:28 +0530 Subject: ARM: tegra: enable REGULATOR_TPS51632 Enable regualtor REGULATOR_TPS51632 which is used for cpu regulator. Change-Id: I5ba78608e6c5480e8b0d8d54ee59c9bba0b58428 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/117602 Reviewed-by: Automatic_Commit_Validation_User --- arch/arm/configs/tegra3_android_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/tegra3_android_defconfig b/arch/arm/configs/tegra3_android_defconfig index 24a24706ca48..fe9c794bb043 100644 --- a/arch/arm/configs/tegra3_android_defconfig +++ b/arch/arm/configs/tegra3_android_defconfig @@ -324,6 +324,7 @@ CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MAX8973=y CONFIG_REGULATOR_MAX77663=y CONFIG_REGULATOR_RC5T583=y +CONFIG_REGULATOR_TPS51632=y CONFIG_REGULATOR_TPS6586X=y CONFIG_REGULATOR_TPS65910=y CONFIG_REGULATOR_TPS62360=y -- cgit v1.2.3 From 3a50dd6e2b0183e9189ab746296d9ff6398fb86d Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Thu, 1 Mar 2012 15:20:40 -0800 Subject: ARM: tegra: clock: Set SCLK floor for CPU mode switch Set SCLK floor to 80MHz for Tegra3 CPU mode switch. Bug 933984 Change-Id: Ibbb0a24cd763c11b3cead60efe26096bae3e6ddd Signed-off-by: Alex Frid Reviewed-on: http://git-master/r/106035 Reviewed-by: Prajakta Gudadhe Tested-by: Jay Cheng (cherry picked from commit 842f7ddb7a188e36a2ff153dc0d8ed38b5e28319) Reviewed-on: http://git-master/r/113981 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/common.c | 1 + arch/arm/mach-tegra/tegra3_clocks.c | 10 +++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 59b4f954ee79..aa6f0192c5d2 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -217,6 +217,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "sbc5.sclk", NULL, 40000000, false}, { "sbc6.sclk", NULL, 40000000, false}, { "wake.sclk", NULL, 40000000, true }, + { "cpu_mode.sclk", NULL, 80000000, false }, { "cbus", "pll_c", 416000000, false }, { "pll_c_out1", "pll_c", 208000000, false }, { "mselect", "pll_p", 102000000, true }, diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 87592e2ee3c5..9344a84cf62a 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -319,6 +319,7 @@ static int tegra3_emc_relock_set_rate(struct clk *emc, unsigned long old_rate, static unsigned long cpu_stay_on_backup_max; static struct clk *emc_bridge; +static struct clk *cpu_mode_sclk; static bool detach_shared_bus; module_param(detach_shared_bus, bool, 0644); @@ -1050,6 +1051,8 @@ static int tegra3_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p) flags |= (p->u.cpu.mode == MODE_LP) ? TEGRA_POWER_CLUSTER_LP : TEGRA_POWER_CLUSTER_G; + clk_enable(cpu_mode_sclk); /* set SCLK floor for cluster switch */ + /* Since in both LP and G mode CPU main and backup sources are the same, set rate on the new parent just synchronizes super-clock muxes before mode switch with no PLL re-locking */ @@ -1057,6 +1060,7 @@ static int tegra3_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p) if (ret) { pr_err("%s: Failed to set rate %lu for %s\n", __func__, rate, p->name); + clk_disable(cpu_mode_sclk); return ret; } @@ -1072,6 +1076,7 @@ static int tegra3_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p) clk_disable(p); pr_err("%s: Failed to switch %s mode to %s\n", __func__, c->name, p->name); + clk_disable(cpu_mode_sclk); return ret; } @@ -1080,6 +1085,7 @@ static int tegra3_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p) clk_disable(c->parent); clk_reparent(c, p); + clk_disable(cpu_mode_sclk); return 0; } @@ -4403,7 +4409,8 @@ struct clk tegra_list_clks[] = { SHARED_CLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), SHARED_CLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), SHARED_CLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("cpu_mode.sclk","cpu_mode", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), SHARED_CLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0), SHARED_CLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING), SHARED_CLK("floor.sclk", "floor_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, 0), @@ -5393,6 +5400,7 @@ void __init tegra_soc_init_clocks(void) tegra3_init_one_clock(&tegra_clk_out_list[i]); emc_bridge = &tegra_clk_emc_bridge; + cpu_mode_sclk = tegra_get_clock_by_name("cpu_mode.sclk"); /* Initialize to default */ tegra_init_cpu_edp_limits(0); -- cgit v1.2.3 From 50331bba385d880f74dd9dcbce8a32d6f4e49f8c Mon Sep 17 00:00:00 2001 From: Krishna Yarlagadda Date: Wed, 18 Jul 2012 17:04:33 +0530 Subject: ARM: tegra: usb: regulator on during lp0 on T20 Tegra 2 requires regulator to be on during lp0 Bug 1012273 Change-Id: I750892fd391be327e617c70b7da4c984019a32fa Signed-off-by: Krishna Yarlagadda Reviewed-on: http://git-master/r/116743 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/usb_phy.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c index 62884df14269..4cc80e68d89c 100644 --- a/arch/arm/mach-tegra/usb_phy.c +++ b/arch/arm/mach-tegra/usb_phy.c @@ -405,6 +405,8 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy) } if (phy->vdd_reg) { + if (phy->vdd_reg_on) + regulator_disable(phy->vdd_reg); regulator_put(phy->vdd_reg); } @@ -470,17 +472,12 @@ int tegra_usb_phy_power_off(struct tegra_usb_phy *phy) } } - if (phy->vdd_reg && phy->vdd_reg_on) { -#ifndef CONFIG_ARCH_TEGRA_2x_SOC - regulator_disable(phy->vdd_reg); - phy->vdd_reg_on = false; -#else - if (tegra_get_revision() >= TEGRA_REVISION_A03) { + if (phy->vdd_reg && phy->vdd_reg_on) + if (phy->pdata->has_hostpc || + phy->pdata->builtin_host_disabled) { regulator_disable(phy->vdd_reg); phy->vdd_reg_on = false; } -#endif - } phy->phy_power_on = false; -- cgit v1.2.3 From 7e2377b9f79b5f8bc4b519444dc5e6441b2d8671 Mon Sep 17 00:00:00 2001 From: Krishna Yarlagadda Date: Fri, 20 Jul 2012 11:50:47 +0530 Subject: ARM: tegra: usb: Turn off built in host on otg Disable built in host support on OTG port for Whistler and Enterprise boards. Bug 1012273 Bug 947300 Change-Id: I88574c37795ee204e0cc67ed71f424443950494f Signed-off-by: Krishna Yarlagadda Reviewed-on: http://git-master/r/117307 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-enterprise.c | 1 + arch/arm/mach-tegra/board-whistler.c | 2 ++ 2 files changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c index e703b56fd939..f9e5b05e6d3c 100644 --- a/arch/arm/mach-tegra/board-enterprise.c +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -722,6 +722,7 @@ static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = { static struct tegra_usb_platform_data tegra_udc_pdata = { .port_otg = true, .has_hostpc = true, + .builtin_host_disabled = true, .phy_intf = TEGRA_USB_PHY_INTF_UTMI, .op_mode = TEGRA_USB_OPMODE_DEVICE, .u_data.dev = { diff --git a/arch/arm/mach-tegra/board-whistler.c b/arch/arm/mach-tegra/board-whistler.c index 06e704e47870..4bd5ed8471d4 100644 --- a/arch/arm/mach-tegra/board-whistler.c +++ b/arch/arm/mach-tegra/board-whistler.c @@ -421,6 +421,7 @@ static int __init whistler_touch_init(void) static struct tegra_usb_platform_data tegra_udc_pdata = { .port_otg = true, .has_hostpc = false, + .builtin_host_disabled = true, .phy_intf = TEGRA_USB_PHY_INTF_UTMI, .op_mode = TEGRA_USB_OPMODE_DEVICE, .u_data.dev = { @@ -445,6 +446,7 @@ static struct tegra_usb_platform_data tegra_udc_pdata = { static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = { .port_otg = true, .has_hostpc = false, + .builtin_host_disabled = true, .phy_intf = TEGRA_USB_PHY_INTF_UTMI, .op_mode = TEGRA_USB_OPMODE_HOST, .u_data.host = { -- cgit v1.2.3 From f94229cc7a6d469154145bd13add16a4cef0dc6a Mon Sep 17 00:00:00 2001 From: Rakesh Iyer Date: Thu, 12 Jul 2012 14:56:12 -0700 Subject: arm: tegra: dvfs: update AP37 dvfs entry Update Tegra3 AP37 dvfs table entries. Bug 841336 Reviewed-on: http://git-master/r/115509 (cherry picked from commit fda92ca92eb421b554fcb50117c92ec59b4b515a) Change-Id: Ib15ba4731f0770a8af2272c51a90c7dc0fd8f6b9 Signed-off-by: Rakesh Iyer Reviewed-on: http://git-master/r/117926 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani Tested-by: Bharat Nihalani GVS: Gerrit_Virtual_Submit --- arch/arm/mach-tegra/tegra3_dvfs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c index 96b7fb54d8c7..9b06d3eda86b 100644 --- a/arch/arm/mach-tegra/tegra3_dvfs.c +++ b/arch/arm/mach-tegra/tegra3_dvfs.c @@ -189,8 +189,8 @@ static struct dvfs cpu_dvfs_table[] = { CPU_DVFS("cpu_g", 14, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), CPU_DVFS("cpu_g", 15, -1, MHZ, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), - CPU_DVFS("cpu_g", 12, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1470, 1470, 1500, 1500, 1500, 1500, 1540, 1540, 1700), - CPU_DVFS("cpu_g", 12, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 940, 1160, 1160, 1240, 1240, 1240, 1280, 1280, 1360, 1360, 1390, 1390, 1470, 1470, 1500, 1500, 1520, 1520, 1520, 1520, 1590, 1700), + CPU_DVFS("cpu_g", 12, 3, MHZ, 1, 475, 475, 475, 475, 620, 620, 620, 620, 760, 760, 760, 760, 760, 910, 910, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1500, 1500, 1700), + CPU_DVFS("cpu_g", 12, 4, MHZ, 475, 475, 475, 475, 475, 620, 620, 620, 760, 760, 760, 760, 910, 910, 910, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1700), CPU_DVFS("cpu_g", 13, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1470, 1470, 1500, 1500, 1500, 1500, 1540, 1540, 1700), CPU_DVFS("cpu_g", 13, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 940, 1160, 1160, 1240, 1240, 1240, 1280, 1280, 1360, 1360, 1390, 1390, 1470, 1470, 1500, 1500, 1520, 1520, 1520, 1520, 1590, 1700), @@ -216,7 +216,7 @@ static struct dvfs cpu_0_dvfs_table[] = { CPU_DVFS("cpu_0", 6, 4, MHZ, 475, 620, 620, 620, 760, 760, 760, 910, 910, 1000, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1700), CPU_DVFS("cpu_0", 12, 3, MHZ, 475, 475, 620, 620, 620, 760, 760, 760, 910, 910, 910, 1000, 1000, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1700), - CPU_DVFS("cpu_0", 12, 4, MHZ, 475, 620, 620, 620, 760, 760, 760, 910, 910, 1000, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1700), + CPU_DVFS("cpu_0", 12, 4, MHZ, 475, 620, 620, 620, 760, 760, 760, 910, 910, 1000, 1000, 1000, 1000, 1000, 1000, 1150, 1150, 1150, 1150, 1300, 1300, 1300, 1300, 1400, 1400, 1400, 1500, 1500, 1500, 1500, 1500, 1600, 1600, 1600, 1600, 1600, 1600, 1600, 1700), }; #define CORE_DVFS(_clk_name, _speedo_id, _auto, _mult, _freqs...) \ -- cgit v1.2.3 From b2010ea221679291ced813178b21efdae54b7baf Mon Sep 17 00:00:00 2001 From: Suresh Mangipudi Date: Tue, 24 Jul 2012 12:46:47 +0530 Subject: arm: tegra: usb: Fix First SOF corruption. In ULPI phy first SOF after Reset may be corrupt. Fixing this issue. Bug 1012500 Change-Id: I45ee1b4c8e0a29298c94813030d22291b79e417b Signed-off-by: Suresh Mangipudi Reviewed-on: http://git-master/r/117635 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/tegra3_usb_phy.c | 28 ++++++++++++++++++++++++++++ arch/arm/mach-tegra/tegra_usb_phy.h | 1 + 2 files changed, 29 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index 3152bdf9e107..0b8ab076693d 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -2576,7 +2576,16 @@ static int ulpi_null_phy_init(struct tegra_usb_phy *phy) static int ulpi_null_phy_irq(struct tegra_usb_phy *phy) { + unsigned long val; + void __iomem *base = phy->regs; + usb_phy_fence_read(phy); + if (phy->bus_reseting){ + val = readl(base + USB_USBCMD); + val |= USB_USBCMD_RS; + writel(val, base + USB_USBCMD); + phy->bus_reseting = false; + } return IRQ_HANDLED; } @@ -2602,6 +2611,23 @@ static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy) return 0; } +static int ulpi_phy_bus_reset(struct tegra_usb_phy *phy) +{ + unsigned long val; + void __iomem *base = phy->regs; + + DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); + + /*DISABLE RUN BIT */ + + val = readl(base + USB_USBCMD); + val &= ~USB_USBCMD_RS; + writel(val, base + USB_USBCMD); + phy->bus_reseting = true; + + return 0; +} + static int ulpi_null_phy_restore(struct tegra_usb_phy *phy) { struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi; @@ -2774,6 +2800,7 @@ static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy) } udelay(10); + phy->bus_reseting = false; phy->phy_clk_on = true; phy->hw_accessible = true; @@ -2857,6 +2884,7 @@ static struct tegra_usb_phy_ops ulpi_null_phy_ops = { .resume = ulpi_null_phy_resume, .post_resume = ulpi_null_phy_post_resume, .reset = ulpi_null_phy_cmd_reset, + .bus_reset = ulpi_phy_bus_reset, }; static struct tegra_usb_phy_ops ulpi_link_phy_ops; diff --git a/arch/arm/mach-tegra/tegra_usb_phy.h b/arch/arm/mach-tegra/tegra_usb_phy.h index 731632d23679..7e85a4b02282 100644 --- a/arch/arm/mach-tegra/tegra_usb_phy.h +++ b/arch/arm/mach-tegra/tegra_usb_phy.h @@ -96,6 +96,7 @@ struct tegra_usb_phy { bool hw_accessible; bool ulpi_clk_padout_ena; bool pmc_sleepwalk; + bool bus_reseting; }; int usb_phy_reg_status_wait(void __iomem *reg, u32 mask, -- cgit v1.2.3 From bf132a4184143d5780ca747d024768e021b590d5 Mon Sep 17 00:00:00 2001 From: Rakesh Iyer Date: Thu, 19 Jul 2012 12:44:08 -0700 Subject: video: tegra: dc: synchronize dsi clock-gating The one shot thread will clock gate the modules periodically. This will ensure relevant paths in dc driver have an active dc clock and dsi host. Bug 1013172 Change-Id: Ibb505e35044f31405c06cb9fa0d6fdf78aafd4a6 Signed-off-by: Rakesh Iyer Reviewed-on: http://git-master/r/117137 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo GVS: Gerrit_Virtual_Submit Reviewed-by: Animesh Kishore Reviewed-by: Yu-Huan Hsu --- arch/arm/mach-tegra/include/mach/dc.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/include/mach/dc.h b/arch/arm/mach-tegra/include/mach/dc.h index 97f02ce6e95d..161e37616497 100644 --- a/arch/arm/mach-tegra/include/mach/dc.h +++ b/arch/arm/mach-tegra/include/mach/dc.h @@ -565,10 +565,6 @@ struct tegra_dc_pwm_params { void tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg); int tegra_dsi_send_panel_short_cmd(struct tegra_dc *dc, u8 *pdata, u8 data_len); -void tegra_dc_host_suspend(struct tegra_dc *dc); -void tegra_dc_host_resume(struct tegra_dc *dc); -int tegra_dsi_host_suspend(struct tegra_dc *dc); -int tegra_dsi_host_resume(struct tegra_dc *dc); int tegra_dc_update_csc(struct tegra_dc *dc, int win_index); -- cgit v1.2.3 From 6dc1107e55f5b6eefd6c6314624905e33bac5b49 Mon Sep 17 00:00:00 2001 From: Sai Charan Gurrappadi Date: Tue, 10 Jul 2012 17:33:58 -0700 Subject: ARM: tegra: cpuquiet: Notify the cpuquiet governor when the driver is busy Added generic busy/free notifiers that the driver can invoke to let the governor know that it cannot process further core online/offline requests (invoked in our case whenever we switch to the LP cluster). Change-Id: I5e3f7f28f38806a7f87050e8d0c8d2f2cf7521aa Signed-off-by: Sai Charan Gurrappadi Reviewed-on: http://git-master/r/114807 Reviewed-by: Lokesh Pathak Tested-by: Lokesh Pathak --- arch/arm/mach-tegra/cpuquiet.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/cpuquiet.c b/arch/arm/mach-tegra/cpuquiet.c index 26adce230920..e3a16d002b80 100644 --- a/arch/arm/mach-tegra/cpuquiet.c +++ b/arch/arm/mach-tegra/cpuquiet.c @@ -134,7 +134,7 @@ static void apply_core_config(void) static void tegra_cpuquiet_work_func(struct work_struct *work) { - bool update_cr_config = false; + bool state_changed = false; mutex_lock(tegra3_cpu_lock); @@ -148,7 +148,7 @@ static void tegra_cpuquiet_work_func(struct work_struct *work) /*catch-up with governor target speed */ tegra_cpu_set_speed_cap(NULL); /* process pending core requests*/ - update_cr_config = true; + state_changed = true; } } break; @@ -159,6 +159,7 @@ static void tegra_cpuquiet_work_func(struct work_struct *work) if (!clk_set_parent(cpu_clk, cpu_lp_clk)) { /*catch-up with governor target speed*/ tegra_cpu_set_speed_cap(NULL); + state_changed = true; } } break; @@ -169,8 +170,12 @@ static void tegra_cpuquiet_work_func(struct work_struct *work) mutex_unlock(tegra3_cpu_lock); - if (update_cr_config) + if (state_changed && cpq_state == TEGRA_CPQ_SWITCH_TO_LP) { + cpuquiet_device_busy(); + } else if (state_changed && cpq_state == TEGRA_CPQ_SWITCH_TO_G) { apply_core_config(); + cpuquiet_device_free(); + } } static void min_max_constraints_workfunc(struct work_struct *work) @@ -212,6 +217,8 @@ static void min_max_constraints_workfunc(struct work_struct *work) static int min_cpus_notify(struct notifier_block *nb, unsigned long n, void *p) { + bool g_cluster = false; + mutex_lock(tegra3_cpu_lock); if ((n >= 1) && is_lp_cluster()) { @@ -221,6 +228,7 @@ static int min_cpus_notify(struct notifier_block *nb, unsigned long n, void *p) tegra_update_cpu_speed(speed); clk_set_parent(cpu_clk, cpu_g_clk); + g_cluster = true; } tegra_cpu_set_speed_cap(NULL); @@ -228,6 +236,9 @@ static int min_cpus_notify(struct notifier_block *nb, unsigned long n, void *p) schedule_work(&minmax_work); + if (g_cluster) + cpuquiet_device_free(); + return NOTIFY_OK; } @@ -253,6 +264,7 @@ void tegra_auto_hotplug_governor(unsigned int cpu_freq, bool suspend) /* Switch to G-mode if suspend rate is high enough */ if (is_lp_cluster() && (cpu_freq >= idle_bottom_freq)) { clk_set_parent(cpu_clk, cpu_g_clk); + cpuquiet_device_free(); } return; } @@ -306,11 +318,13 @@ static void enable_callback(struct cpuquiet_attribute *attr) mutex_unlock(tegra3_cpu_lock); cancel_delayed_work_sync(&cpuquiet_work); pr_info("Tegra cpuquiet clusterswitch disabled\n"); + cpuquiet_device_busy(); mutex_lock(tegra3_cpu_lock); } else if (enable && cpq_state == TEGRA_CPQ_DISABLED) { cpq_state = TEGRA_CPQ_IDLE; pr_info("Tegra cpuquiet clusterswitch enabled\n"); tegra_cpu_set_speed_cap(NULL); + cpuquiet_device_free(); } mutex_unlock(tegra3_cpu_lock); -- cgit v1.2.3 From 006b6827f963a1fbfc309fd546c14bf4af49fedc Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Wed, 18 Jul 2012 12:52:06 -0700 Subject: ARM: tegra: clock: Add Tegra3 cbus profile cap Change-Id: I4d15ef7a9089bf3519155d9ccf5192bf3dcf0bd6 Signed-off-by: Alex Frid Reviewed-on: http://git-master/r/116873 Reviewed-by: Lokesh Pathak Tested-by: Lokesh Pathak --- arch/arm/mach-tegra/tegra3_clocks.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 9344a84cf62a..de9bc5f2ae03 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -4450,6 +4450,7 @@ struct clk tegra_list_clks[] = { SHARED_CLK("se.cbus", "tegra-se", NULL, &tegra_clk_cbus, "se", 0, 0), #endif SHARED_CLK("cap.cbus", "cap.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING), + SHARED_CLK("cap.profile.cbus", "profile.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING), SHARED_CLK("floor.cbus", "floor.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0), }; -- cgit v1.2.3 From 5b754f99eee15772f43240830c4e76ad8cf220bb Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Wed, 18 Jul 2012 13:49:28 -0700 Subject: ARM: tegra: clock: Add Tegra3 cbus profiling sysfs nodes Added: /sys/kernel/tegra_cap/cbus_cap_level /sys/kernel/tegra_cap/cbus_cap_state Change-Id: I06a32ea4001f1f644da4f230870f39523f9b6df3 Signed-off-by: Alex Frid Reviewed-on: http://git-master/r/116874 Reviewed-by: Lokesh Pathak Tested-by: Lokesh Pathak --- arch/arm/mach-tegra/tegra3_dvfs.c | 79 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c index 9b06d3eda86b..38f6ed0b317c 100644 --- a/arch/arm/mach-tegra/tegra3_dvfs.c +++ b/arch/arm/mach-tegra/tegra3_dvfs.c @@ -780,6 +780,8 @@ static struct core_cap tegra3_core_cap; static struct core_cap kdvfs_core_cap; static struct core_cap user_core_cap; +static struct core_cap user_cbus_cap; + static struct kobject *cap_kobj; /* Arranged in order required for enabling/lowering the cap */ @@ -898,14 +900,91 @@ core_cap_level_store(struct kobject *kobj, struct kobj_attribute *attr, return count; } +static void cbus_cap_update(void) +{ + static struct clk *cbus_cap; + + if (!cbus_cap) { + cbus_cap = tegra_get_clock_by_name("cap.profile.cbus"); + if (!cbus_cap) { + WARN_ONCE(1, "tegra3_dvfs: cbus profiling is not supported"); + return; + } + } + + if (user_cbus_cap.refcnt) + clk_set_rate(cbus_cap, user_cbus_cap.level); + else + clk_set_rate(cbus_cap, clk_get_max_rate(cbus_cap)); +} + +static ssize_t +cbus_cap_state_show(struct kobject *kobj, struct kobj_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", user_cbus_cap.refcnt ? 1 : 0); +} +static ssize_t +cbus_cap_state_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + int state; + + if (sscanf(buf, "%d", &state) != 1) + return -1; + + mutex_lock(&core_cap_lock); + + if (state) { + user_cbus_cap.refcnt++; + if (user_cbus_cap.refcnt == 1) + cbus_cap_update(); + } else if (user_cbus_cap.refcnt) { + user_cbus_cap.refcnt--; + if (user_cbus_cap.refcnt == 0) + cbus_cap_update(); + } + + mutex_unlock(&core_cap_lock); + return count; +} + +static ssize_t +cbus_cap_level_show(struct kobject *kobj, struct kobj_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", user_cbus_cap.level); +} +static ssize_t +cbus_cap_level_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + int level; + + if (sscanf(buf, "%d", &level) != 1) + return -1; + + mutex_lock(&core_cap_lock); + user_cbus_cap.level = level; + cbus_cap_update(); + mutex_unlock(&core_cap_lock); + return count; +} + static struct kobj_attribute cap_state_attribute = __ATTR(core_cap_state, 0644, core_cap_state_show, core_cap_state_store); static struct kobj_attribute cap_level_attribute = __ATTR(core_cap_level, 0644, core_cap_level_show, core_cap_level_store); +static struct kobj_attribute cbus_state_attribute = + __ATTR(cbus_cap_state, 0644, cbus_cap_state_show, cbus_cap_state_store); +static struct kobj_attribute cbus_level_attribute = + __ATTR(cbus_cap_level, 0644, cbus_cap_level_show, cbus_cap_level_store); const struct attribute *cap_attributes[] = { &cap_state_attribute.attr, &cap_level_attribute.attr, + &cbus_state_attribute.attr, + &cbus_level_attribute.attr, NULL, }; -- cgit v1.2.3 From 484a143002681370f7ff6c8c9c07a22cdca9360a Mon Sep 17 00:00:00 2001 From: Nirav Patel Date: Tue, 5 Jun 2012 16:00:34 -0700 Subject: p1852: clocks: remove duplicate host1x clock limit host1x clock limit is already imposed by tegra3_dvfs.c and need not to be explicitly set for p1852 SKU. Hence, removing the clock limit duplication. Bug 925358 Change-Id: I5e936f46ad64b0335561e321d61c4e8b13d7f765 Reviewed-on: http://git-master/r/106637 (cherry picked from commit ccaa3515121b637ce3870bf73f2402846670b63c) Signed-off-by: Nirav Patel Reviewed-on: http://git-master/r/118130 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Varun Wadekar --- arch/arm/mach-tegra/board-p1852.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-p1852.c b/arch/arm/mach-tegra/board-p1852.c index 008b8ad0aac5..b0a593f95121 100644 --- a/arch/arm/mach-tegra/board-p1852.c +++ b/arch/arm/mach-tegra/board-p1852.c @@ -97,7 +97,6 @@ static __initdata struct tegra_clk_init_table p1852_clk_init_table[] = { { "vi", "pll_p", 470000000, false}, { "vi_sensor", "pll_p", 150000000, false}, { "vde", "pll_c", 484000000, true}, - { "host1x", "pll_c", 242000000, true}, { "mpe", "pll_c", 484000000, true}, { "se", "pll_m", 625000000, true}, { "i2c1", "pll_p", 3200000, true}, -- cgit v1.2.3 From 63a0f39a163bdabb2a0e3a8601dfefd44ae9ec93 Mon Sep 17 00:00:00 2001 From: Daniel Fu Date: Fri, 20 Jul 2012 11:27:27 +0800 Subject: ARM: tegra: thermal: fix inform edp governor bug Fixed bug using Tj temp to update thermal zone, It should use EDP temp to update it. bug 1007726 Change-Id: Ibcf2520a4bad7dc977add0b5c855681d2667a7c2 Signed-off-by: Daniel Fu Reviewed-on: http://git-master/r/117250 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Joshua Primero Tested-by: Joshua Primero GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam --- arch/arm/mach-tegra/tegra3_thermal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_thermal.c b/arch/arm/mach-tegra/tegra3_thermal.c index e8b5e5df4afc..9de34a05810c 100644 --- a/arch/arm/mach-tegra/tegra3_thermal.c +++ b/arch/arm/mach-tegra/tegra3_thermal.c @@ -281,9 +281,9 @@ static void tegra_thermal_alert_unlocked(void *data) #ifdef CONFIG_TEGRA_EDP_LIMITS /* inform edp governor */ if (edp_thermal_zone_val != temp_tj) { - long temp_edp = (dev2tj(device, temp_tj) - therm->edp_offset) / 1000; + long temp_edp = (temp_tj - therm->edp_offset) / 1000; tegra_edp_update_thermal_zone(temp_edp); - edp_thermal_zone_val = temp_edp; + edp_thermal_zone_val = temp_tj; } #endif } -- cgit v1.2.3 From d5ff34f7512de563f74c804096d0b7d8a9b214ac Mon Sep 17 00:00:00 2001 From: Vinayak Pane Date: Thu, 12 Jul 2012 17:13:07 -0700 Subject: arm: tegra: xmm: flash modem reset functionality Flash version modem need to do reset with gpio and start enumeration on falling edge of ap wake. Remove unused variable enum_delay_ms. Bug 1003141 Change-Id: Ie43c693c3fead5c89b30c1b97cf1f3e4c05e5588 Signed-off-by: Vinayak Pane Reviewed-on: http://git-master/r/116886 Reviewed-by: Michael Hsu Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ken Chang Tested-by: Ken Chang Reviewed-by: Steve Lin --- arch/arm/mach-tegra/baseband-xmm-power.c | 45 +++++++++++++++++--------------- 1 file changed, 24 insertions(+), 21 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/baseband-xmm-power.c b/arch/arm/mach-tegra/baseband-xmm-power.c index 9482bbecc77d..9513bdc5d45f 100644 --- a/arch/arm/mach-tegra/baseband-xmm-power.c +++ b/arch/arm/mach-tegra/baseband-xmm-power.c @@ -51,8 +51,6 @@ EXPORT_SYMBOL(modem_flash); unsigned long modem_pm = 1; EXPORT_SYMBOL(modem_pm); -unsigned long enum_delay_ms = 1000; /* ignored if !modem_flash */ - module_param(modem_ver, ulong, 0644); MODULE_PARM_DESC(modem_ver, "baseband xmm power - modem software version"); @@ -62,9 +60,6 @@ MODULE_PARM_DESC(modem_flash, module_param(modem_pm, ulong, 0644); MODULE_PARM_DESC(modem_pm, "baseband xmm power - modem power management (1 = pm, 0 = no pm)"); -module_param(enum_delay_ms, ulong, 0644); -MODULE_PARM_DESC(enum_delay_ms, - "baseband xmm power - delay in ms between modem on and enumeration"); static struct usb_device_id xmm_pm_ids[] = { { USB_DEVICE(VENDOR_ID, PRODUCT_ID), @@ -227,6 +222,18 @@ static int baseband_modem_power_on_async( return 0; } +static void xmm_power_reset_on(struct baseband_power_platform_data *pdata) +{ + /* reset / power on sequence */ + gpio_set_value(pdata->modem.xmm.bb_rst, 0); + msleep(40); + gpio_set_value(pdata->modem.xmm.bb_rst, 1); + usleep_range(1000, 1100); + gpio_set_value(pdata->modem.xmm.bb_on, 1); + udelay(70); + gpio_set_value(pdata->modem.xmm.bb_on, 0); +} + static int xmm_power_on(struct platform_device *device) { struct baseband_power_platform_data *pdata = @@ -277,7 +284,19 @@ static int xmm_power_on(struct platform_device *device) __func__); baseband_modem_power_on_async(pdata); } + } else { + /* reset flashed modem then it will respond with + * ap-wake rising followed by falling gpio + */ + + pr_debug("%s: reset flash modem\n", __func__); + modem_power_on = false; + ipc_ap_wake_state = IPC_AP_WAKE_INIT1; + gpio_set_value(pdata->modem.xmm.ipc_hsic_active, 0); + + xmm_power_reset_on(pdata); } + ret = enable_irq_wake(gpio_to_irq(pdata->modem.xmm.ipc_ap_wake)); if (ret < 0) pr_err("%s: enable_irq_wake error\n", __func__); @@ -563,7 +582,6 @@ irqreturn_t xmm_power_ipc_ap_wake_irq(int irq, void *dev_id) /* go to IPC_AP_WAKE_INIT2 state */ ipc_ap_wake_state = IPC_AP_WAKE_INIT2; queue_work(workqueue, &init2_work); - } else pr_debug("%s - IPC_AP_WAKE_INIT1" " - got rising edge\n", __func__); @@ -683,7 +701,6 @@ static void xmm_power_init2_work(struct work_struct *work) pr_err("%s: hsic_register is missing\n", __func__); register_hsic_device = false; } - } static void xmm_power_autopm_resume(struct work_struct *work) @@ -723,19 +740,6 @@ static void xmm_power_l2_resume_work(struct work_struct *work) pr_debug("} %s\n", __func__); } -static void xmm_power_reset_on(struct baseband_power_platform_data *pdata) -{ - /* reset / power on sequence */ - gpio_set_value(pdata->modem.xmm.bb_rst, 0); - msleep(40); - gpio_set_value(pdata->modem.xmm.bb_rst, 1); - usleep_range(1000, 2000); - gpio_set_value(pdata->modem.xmm.bb_on, 1); - udelay(70); - gpio_set_value(pdata->modem.xmm.bb_on, 0); -} - - static void xmm_power_work_func(struct work_struct *work) { struct xmm_power_data *data = @@ -906,7 +910,6 @@ static int xmm_power_driver_probe(struct platform_device *device) int err; pr_debug("%s\n", __func__); - pr_debug("[XMM] enum_delay_ms=%ld\n", enum_delay_ms); /* check for platform data */ if (!pdata) -- cgit v1.2.3 From 971106a7f14552ff7785eedcd97301b75a586474 Mon Sep 17 00:00:00 2001 From: Jay Agarwal Date: Sat, 21 Jul 2012 23:47:33 +0530 Subject: arm: tegra: pci: Organize pcie initialization code 1. Initialize PCIe on every resume whether device is dock/undocked. 2. Poweroff PCIe if Poweron failed at any stage. 3. Make PCIe initialization robust so that it is successful anytime dock is connected i.e while in LP0 or after it's exit or else. Bug 1020949 Change-Id: I79cd75f2bf7164a9b5c8906a370364dba5183ac8 Signed-off-by: Jay Agarwal Reviewed-on: http://git-master/r/117532 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani --- arch/arm/mach-tegra/pcie.c | 109 ++++++++++++++++++--------------------------- 1 file changed, 44 insertions(+), 65 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index 24ca4900daa5..c6f0e4bf2bb8 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -313,11 +313,6 @@ struct tegra_pcie_info { struct tegra_pci_platform_data *plat_data; }tegra_pcie; -#define pmc_writel(value, reg) \ - __raw_writel(value, (u32)reg_pmc_base + (reg)) -#define pmc_readl(reg) \ - __raw_readl((u32)reg_pmc_base + (reg)) - struct resource tegra_pcie_res_mmio = { .name = "PCI IO", .start = MMIO_BASE, @@ -637,9 +632,6 @@ static void tegra_pcie_hotplug_init(void) static void tegra_pcie_attach(void) { - /* this hardcode is just to bypass the check in resume */ - if (!is_dock_conn_at_boot) - tegra_pcie.num_ports = 1; #ifdef CONFIG_PM tegra_pcie_resume(NULL); #endif @@ -904,6 +896,8 @@ static int tegra_pcie_enable_regulators(void) pr_debug("PCIE: Already power rails enabled"); return 0; } + tegra_pcie.power_rails_enabled = 1; + if (tegra_pcie.regulator_hvdd == NULL) { printk(KERN_INFO "PCIE.C: %s : regulator hvdd_pex\n", __func__); @@ -948,8 +942,6 @@ static int tegra_pcie_enable_regulators(void) if (tegra_pcie.regulator_avdd_plle) regulator_enable(tegra_pcie.regulator_avdd_plle); - tegra_pcie.power_rails_enabled = 1; - return 0; } @@ -988,8 +980,6 @@ static int tegra_pcie_power_regate(void) return clk_enable(tegra_pcie.pll_e); } -static int tegra_pcie_power_off(void); - static int tegra_pcie_map_resources(void) { int err; @@ -998,14 +988,13 @@ static int tegra_pcie_map_resources(void) tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ); if (tegra_pcie.regs == NULL) { pr_err("PCIE: Failed to map PCI/AFI registers\n"); - err = -ENOMEM; - goto err_exit; + return -ENOMEM; } err = request_resource(&iomem_resource, &tegra_pcie_res_mmio); if (err) { pr_err("PCIE: Failed to request resources: %d\n", err); - goto err_exit; + return err; } tegra_pcie.res_mmio = &tegra_pcie_res_mmio; @@ -1014,13 +1003,8 @@ static int tegra_pcie_map_resources(void) resource_size(&tegra_pcie_res_mmio)); if (tegra_pcie_io_base == NULL) { pr_err("PCIE: Failed to map IO\n"); - err = -ENOMEM; - goto err_exit; + return -ENOMEM; } - return 0; - -err_exit: - tegra_pcie_power_off(); return err; } @@ -1039,8 +1023,8 @@ void tegra_pcie_unmap_resources(void) tegra_pcie.regs = 0; } } +static int tegra_pcie_power_off(void); -#ifdef CONFIG_PM static int tegra_pcie_power_on(void) { int err = 0; @@ -1049,21 +1033,29 @@ static int tegra_pcie_power_on(void) pr_debug("PCIE: Already powered on"); goto err_exit; } + tegra_pcie.pcie_power_enabled = 1; + err = tegra_pcie_enable_regulators(); - if (err) + if (err) { + pr_err("PCIE: Failed to enable regulators\n"); goto err_exit; + } err = tegra_pcie_power_regate(); - if (err) + if (err) { + pr_err("PCIE: Failed to power regate\n"); goto err_exit; + } err = tegra_pcie_map_resources(); - if (err) + if (err) { + pr_err("PCIE: Failed to map resources\n"); goto err_exit; + } - tegra_pcie.pcie_power_enabled = 1; err_exit: + if (err) + tegra_pcie_power_off(); return err; } -#endif static int tegra_pcie_power_off(void) { @@ -1112,8 +1104,10 @@ error_exit: static void tegra_pcie_clocks_put(void) { - clk_put(tegra_pcie.pll_e); - clk_put(tegra_pcie.pcie_xclk); + if (tegra_pcie.pll_e) + clk_put(tegra_pcie.pll_e); + if (tegra_pcie.pcie_xclk) + clk_put(tegra_pcie.pcie_xclk); } static int tegra_pcie_get_resources(void) @@ -1121,31 +1115,18 @@ static int tegra_pcie_get_resources(void) int err; tegra_pcie.power_rails_enabled = 0; - err = tegra_pcie_enable_regulators(); - if (err) { - pr_err("PCIE: failed to enable power rails %d\n", err); - goto err_pwr_on_rail; - } - tegra_unpowergate_partition(TEGRA_POWERGATE_PCIE); + tegra_pcie.pcie_power_enabled = 0; err = tegra_pcie_clocks_get(); if (err) { pr_err("PCIE: failed to get clocks: %d\n", err); - return err; + goto err_clk_get; } - - err = tegra_pcie_power_regate(); + err = tegra_pcie_power_on(); if (err) { - pr_err("PCIE: failed to power up: %d\n", err); + pr_err("PCIE: Failed to power on: %d\n", err); goto err_pwr_on; } - - err = tegra_pcie_map_resources(); - if (err) { - pr_err("PCIE: failed to map resources: %d\n", err); - goto err_pwr_on; - } - err = request_irq(INT_PCIE_INTR, tegra_pcie_isr, IRQF_SHARED, "PCIE", &tegra_pcie); if (err) { @@ -1156,9 +1137,9 @@ static int tegra_pcie_get_resources(void) return 0; err_pwr_on: + tegra_pcie_power_off(); +err_clk_get: tegra_pcie_clocks_put(); -err_pwr_on_rail: - tegra_pcie_disable_regulators(); return err; } @@ -1291,7 +1272,6 @@ static int tegra_pcie_init(void) tegra_pcie_add_port(port, rp_offset, ctrl_offset); } - tegra_pcie.pcie_power_enabled = 1; if (tegra_pcie.plat_data->use_dock_detect) { unsigned int irq; @@ -1331,7 +1311,6 @@ err_irq: static int tegra_pcie_probe(struct platform_device *pdev) { int ret; - struct pci_dev *dev = NULL; tegra_pcie.plat_data = pdev->dev.platform_data; dev_dbg(&pdev->dev, "PCIE.C: %s : _port_status[0] %d\n", @@ -1342,23 +1321,14 @@ static int tegra_pcie_probe(struct platform_device *pdev) __func__, tegra_pcie.plat_data->port_status[2]); ret = tegra_pcie_init(); - /* disable async PM of pci devices to ensure right order */ - /* suspend/resume calls of tegra and bus driver */ - for_each_pci_dev(dev) - device_disable_async_suspend(&dev->dev); - return ret; } #ifdef CONFIG_PM static int tegra_pcie_suspend(struct device *dev) { - int ret = 0; struct pci_dev *pdev = NULL; - if (!tegra_pcie.num_ports) - return ret; - for_each_pci_dev(pdev) { pci_remove_bus_device(pdev); break; @@ -1366,6 +1336,8 @@ static int tegra_pcie_suspend(struct device *dev) /* disable read/write registers before powering off */ is_pcie_noirq_op = true; + /* reset number of ports since fresh initialization occurs in resume */ + tegra_pcie.num_ports = 0; return tegra_pcie_power_off(); } @@ -1395,24 +1367,31 @@ static int tegra_pcie_resume(struct device *dev) int port, rp_offset = 0; int ctrl_offset = AFI_PEX0_CTRL; - if (!tegra_pcie.num_ports) - return ret; + /* return w/o resume if cardhu dock is not connected */ + if (gpio_get_value(tegra_pcie.plat_data->gpio)) + goto exit; ret = tegra_pcie_power_on(); + if (ret) { + pr_err("PCIE: Failed to power on: %d\n", ret); + return ret; + } /* enable read/write registers after powering on */ is_pcie_noirq_op = false; tegra_pcie_enable_controller(); tegra_pcie_setup_translations(); msi_enable = false; - /* reset number of ports before adding port */ - tegra_pcie.num_ports = 0; for (port = 0; port < MAX_PCIE_SUPPORTED_PORTS; port++) { ctrl_offset += (port * 8); rp_offset = (rp_offset + 0x1000) * port; if (tegra_pcie.plat_data->port_status[port]) tegra_pcie_add_port(port, rp_offset, ctrl_offset); } + if (!tegra_pcie.num_ports) { + tegra_pcie_power_off(); + goto exit; + } tegra_pcie_hotplug_init(); while ((bus = pci_find_next_bus(bus)) != NULL) { @@ -1432,8 +1411,8 @@ static int tegra_pcie_resume(struct device *dev) pci_enable_bridges(bus); pci_bus_add_devices(bus); } - - return ret; +exit: + return 0; } #endif -- cgit v1.2.3 From f9c5e2b04d8823d95e4d84ab0369c352c54e6a96 Mon Sep 17 00:00:00 2001 From: Sanjay Sancheti Date: Mon, 9 Jul 2012 11:15:56 +0530 Subject: p1852: Adding defconfig file for p1852 mods This is a copy of p1852 defconfig with usb support disabled Bug 989824 Change-Id: I40089049a35c18782b2e211b63d20fafe8fb9ee8 Reviewed-on: http://git-master/r/114138 Tested-by: Sanjay Sancheti Reviewed-by: Amlan Kundu Reviewed-by: Varun Wadekar (cherry picked from commit a147ad51d486d4aea9a73a11d4c14a13ad2121bb) Reviewed-on: http://git-master/r/118011 Reviewed-by: Automatic_Commit_Validation_User --- arch/arm/configs/tegra_p1852_mods_defconfig | 206 ++++++++++++++++++++++++++++ 1 file changed, 206 insertions(+) create mode 100644 arch/arm/configs/tegra_p1852_mods_defconfig (limited to 'arch') diff --git a/arch/arm/configs/tegra_p1852_mods_defconfig b/arch/arm/configs/tegra_p1852_mods_defconfig new file mode 100644 index 000000000000..9b8d758d5787 --- /dev/null +++ b/arch/arm/configs/tegra_p1852_mods_defconfig @@ -0,0 +1,206 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_CROSS_COMPILE="arm-eabi-" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_PANIC_TIMEOUT=10 +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_ELF_CORE is not set +CONFIG_ASHMEM=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_TEGRA=y +CONFIG_GPIO_PCA953X=y +CONFIG_ARCH_TEGRA_3x_SOC=y +CONFIG_TEGRA_PCI=y +CONFIG_MACH_P1852=y +CONFIG_TEGRA_PWM=y +CONFIG_TEGRA_P1852_TDM=y +# CONFIG_TEGRA_CPU_DVFS is not set +CONFIG_TEGRA_CLOCK_DEBUG_WRITE=y +# CONFIG_TEGRA_MC_EARLY_ACK is not set +CONFIG_NON_ALIASED_COHERENT_MEM=y +CONFIG_ARM_ERRATA_743622=y +CONFIG_ARM_ERRATA_751472=y +CONFIG_ARM_ERRATA_752520=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_SMP=y +CONFIG_HOTPLUG_CPU=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="mem=448@2048M console=ttyS0,115200n8 earlyprintk init=/bin/ash" +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_INET_ESP=y +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_MULTIPLE_TABLES=y +# CONFIG_ANDROID_PARANOID_NETWORK is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_NOR_TEGRA=y +CONFIG_MTD_NAND_TEGRA=y +CONFIG_MTD_NAND=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_DM_UEVENT=y +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +CONFIG_MII=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_TEGRA=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_TEGRA=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_TEGRA=y +CONFIG_SPI=y +CONFIG_SPI_TEGRA=y +CONFIG_SPI_SLAVE_TEGRA=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_BATTERY_BQ20Z75=y +CONFIG_MFD_TPS6591X=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y +CONFIG_REGULATOR_TPS6591X=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_VIDEO_DEV=y +# CONFIG_TEGRA_AVP is not set +# CONFIG_TEGRA_MEDIASERVER is not set +CONFIG_TEGRA_NVAVP=y +# CONFIG_VGA_ARB is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_FB=y +CONFIG_TEGRA_GRHOST=y +CONFIG_TEGRA_DC=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_TEGRA=y +CONFIG_SND_SOC_TEGRA_P1852=y +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_EMBEDDED_SDIO=y +CONFIG_MMC_PARANOID_SD_INIT=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +CONFIG_MMC_BLOCK_DEFERRED_RESUME=y +CONFIG_MMC_BKOPS=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_TEGRA=y +CONFIG_SWITCH=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_TEGRA=y +CONFIG_STAGING=y +CONFIG_IIO=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +# CONFIG_DNOTIFY is not set +CONFIG_FUSE_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_VM=y +# CONFIG_ARM_UNWIND is not set +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_TWOFISH=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y -- cgit v1.2.3 From da47078147f8080a3f71d7647eb391980924d5dd Mon Sep 17 00:00:00 2001 From: Prem Sasidharan Date: Wed, 27 Jun 2012 18:58:45 -0700 Subject: arm: tegra: cardhu: Change governor type Power improvement for OS IDLE DISPLAY OFF, audio use cases. Governor is changed to conservative governor when panel is suspended. Default governor (interactive governor) is restored when the panel resumes (when user presses the power button). Seeing a power improvement of 22mW (42mW/64mW) for os idle display off and 30mW (57mW/87mW) for audio playback use cases Bug 1002294 Signed-off-by: Prem Sasidharan Change-Id: I06d2bca654bc8ff96fdf18d81a98c6e4ec838235 (cherry picked from commit 7002c3fe264163b6be38cf9e24bdf137f44ed69f) Reviewed-on: http://git-master/r/118196 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani Tested-by: Bharat Nihalani --- arch/arm/mach-tegra/board-cardhu-panel.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-panel.c b/arch/arm/mach-tegra/board-cardhu-panel.c index 6fa33f919dad..e50a4433f11a 100644 --- a/arch/arm/mach-tegra/board-cardhu-panel.c +++ b/arch/arm/mach-tegra/board-cardhu-panel.c @@ -1213,11 +1213,19 @@ static void cardhu_panel_early_suspend(struct early_suspend *h) fb_blank(registered_fb[0], FB_BLANK_POWERDOWN); if (num_registered_fb > 1) fb_blank(registered_fb[1], FB_BLANK_NORMAL); + +#ifdef CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND + cpufreq_store_default_gov(); + cpufreq_change_gov(cpufreq_conservative_gov); +#endif } static void cardhu_panel_late_resume(struct early_suspend *h) { unsigned i; +#ifdef CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND + cpufreq_restore_default_gov(); +#endif for (i = 0; i < num_registered_fb; i++) fb_blank(registered_fb[i], FB_BLANK_UNBLANK); } -- cgit v1.2.3 From 56e47baf724c23eb029a800c882728736bcd969f Mon Sep 17 00:00:00 2001 From: Sai Charan Gurrappadi Date: Wed, 25 Jul 2012 11:16:08 -0700 Subject: ARM: tegra: cpuquiet: Fix cpuquiet notifiers The notifiers now properly fire on every cluster switch Change-Id: I381301cf62f25b49532326cc7759696c7f6797b7 Signed-off-by: Sai Charan Gurrappadi Reviewed-on: http://git-master/r/118376 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam --- arch/arm/mach-tegra/cpuquiet.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/cpuquiet.c b/arch/arm/mach-tegra/cpuquiet.c index e3a16d002b80..ed197b1e6c6f 100644 --- a/arch/arm/mach-tegra/cpuquiet.c +++ b/arch/arm/mach-tegra/cpuquiet.c @@ -134,7 +134,7 @@ static void apply_core_config(void) static void tegra_cpuquiet_work_func(struct work_struct *work) { - bool state_changed = false; + int device_busy = -1; mutex_lock(tegra3_cpu_lock); @@ -148,7 +148,7 @@ static void tegra_cpuquiet_work_func(struct work_struct *work) /*catch-up with governor target speed */ tegra_cpu_set_speed_cap(NULL); /* process pending core requests*/ - state_changed = true; + device_busy = 0; } } break; @@ -159,7 +159,7 @@ static void tegra_cpuquiet_work_func(struct work_struct *work) if (!clk_set_parent(cpu_clk, cpu_lp_clk)) { /*catch-up with governor target speed*/ tegra_cpu_set_speed_cap(NULL); - state_changed = true; + device_busy = 1; } } break; @@ -170,9 +170,9 @@ static void tegra_cpuquiet_work_func(struct work_struct *work) mutex_unlock(tegra3_cpu_lock); - if (state_changed && cpq_state == TEGRA_CPQ_SWITCH_TO_LP) { + if (device_busy == 1) { cpuquiet_device_busy(); - } else if (state_changed && cpq_state == TEGRA_CPQ_SWITCH_TO_G) { + } else if (!device_busy) { apply_core_config(); cpuquiet_device_free(); } -- cgit v1.2.3 From f2664172e406f011e323066118f7bbdc38e1811a Mon Sep 17 00:00:00 2001 From: Karthik Ramakrishnan Date: Thu, 14 Jun 2012 17:57:27 -0700 Subject: arm: tegra: enterprise: Turn LCD_RESET low in display off During early suspend, LCD_RESET output needs to be turned low. 3mW power savings during display Off and 1mW on lp0. Bug 969716 Bug 990845 Change-Id: Ia773f0411452fad3eddccb5f293d7f32c4a46a56 signed-off-by: Karthik Ramakrishnan (cherry picked from commit 87322ed7e125ae1ac8d05b623c66f6ab7ea40881) Reviewed-on: http://git-master/r/114057 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-enterprise-panel.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-panel.c b/arch/arm/mach-tegra/board-enterprise-panel.c index 837635bf0731..00b8b29c8318 100644 --- a/arch/arm/mach-tegra/board-enterprise-panel.c +++ b/arch/arm/mach-tegra/board-enterprise-panel.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/board-enterprise-panel.c * - * Copyright (c) 2011-2012, NVIDIA Corporation. + * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -554,16 +554,13 @@ static int enterprise_dsi_panel_enable(void) } } - if (kernel_1st_panel_init != true) { + if (kernel_1st_panel_init == true) { ret = gpio_request(enterprise_dsi_panel_reset, "panel reset"); if (ret < 0) return ret; - - ret = gpio_direction_output(enterprise_dsi_panel_reset, 0); - if (ret < 0) { - gpio_free(enterprise_dsi_panel_reset); - return ret; - } + kernel_1st_panel_init = false; + } else { + gpio_direction_output(enterprise_dsi_panel_reset, 0); gpio_set_value(enterprise_dsi_panel_reset, 0); udelay(2000); @@ -581,10 +578,7 @@ static int enterprise_dsi_panel_disable(void) regulator_disable(enterprise_lcd_reg); #if DSI_PANEL_RESET - if (kernel_1st_panel_init != true) { - gpio_free(enterprise_dsi_panel_reset); - } else - kernel_1st_panel_init = false; + gpio_direction_output(enterprise_dsi_panel_reset, 0); #endif return 0; } -- cgit v1.2.3 From 7e7cb6ad913a379204c1858d2a409fa748592895 Mon Sep 17 00:00:00 2001 From: Jake Park Date: Tue, 24 Jul 2012 13:59:45 +0900 Subject: ARM: tegra: move secondary start kernel message Using printk before CPU online can make hang or kernel panic. Bug 1017539 Bug 1019700 Signed-off-by: Jake Park Reviewed-on: http://git-master/r/117924 (cherry picked from commit 9d7426fdc7e8c70079d37f529517932370355ac6) Change-Id: Ib55ee06dcaf92af63f8d72ee74939c72dda4296c Reviewed-on: http://git-master/r/118141 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Peter Boonstoppel Reviewed-by: Diwakar Tundlam Reviewed-by: Sang-Hun Lee Tested-by: Sang-Hun Lee --- arch/arm/kernel/smp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index bdfb37c59531..016473c1d794 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -280,8 +280,6 @@ asmlinkage void __cpuinit secondary_start_kernel(void) struct mm_struct *mm = &init_mm; unsigned int cpu = smp_processor_id(); - printk("CPU%u: Booted secondary processor\n", cpu); - /* * All kernel threads share the same mm context; grab a * reference and switch to it. @@ -314,6 +312,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void) * before we continue. */ set_cpu_online(cpu, true); + printk("CPU%u: Booted secondary processor\n", cpu); /* * Setup the percpu timer for this CPU. -- cgit v1.2.3 From 907bac80691c7df5b5b57cbf27f91e8bb1dcf434 Mon Sep 17 00:00:00 2001 From: Ankit Gupta Date: Fri, 13 Jul 2012 14:58:18 +0530 Subject: ARM: tegra: integration of slave mode support. Add configurability support for i2s parameters accross all board. ARM: tegra: board: add i2s params Add configurability support for i2s parameters accross all board files. Signed-off-by: Ankit Gupta Change-Id: If58788b5126280b7e1dc8c66e9c96d0e71229b5e Reviewed-on: http://git-master/r/111476 (cherry-picked from commit cac52867b0a0cad3b3c5bf46f08b0b94d0be2e02) ARM: tegra: include: add configurability support for i2s params. Add several variables for i2s configuration in platform data structure. Signed-off-by: Ankit Gupta Change-Id: Iea3930f308954471f170513234c2c02a8559ef98 Reviewed-on: http://git-master/r/111473 (cherry picked from commit 35e749770f6046fc82860f1152db2f5f579b9508) Reviewed-on: http://git-master/r/118071 Reviewed-by: Sumit Bhattacharya Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Peterson --- arch/arm/mach-tegra/board-cardhu.c | 46 ++++++++++++++--- arch/arm/mach-tegra/board-enterprise.c | 57 ++++++++++++++-------- arch/arm/mach-tegra/board-harmony.c | 18 ++++++- arch/arm/mach-tegra/board-kai.c | 19 ++++++-- arch/arm/mach-tegra/board-ventana.c | 18 ++++++- arch/arm/mach-tegra/board-whistler.c | 32 +++++++++--- .../arm/mach-tegra/include/mach/tegra_asoc_pdata.h | 15 +++--- 7 files changed, 159 insertions(+), 46 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c index 80cab77df587..16ad11943533 100644 --- a/arch/arm/mach-tegra/board-cardhu.c +++ b/arch/arm/mach-tegra/board-cardhu.c @@ -2,6 +2,7 @@ * arch/arm/mach-tegra/board-cardhu.c * * Copyright (c) 2011-2012, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2011-2012, NVIDIA Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -724,12 +725,25 @@ static struct platform_device tegra_rtc_device = { .num_resources = ARRAY_SIZE(tegra_rtc_resources), }; -static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = { +static struct tegra_asoc_platform_data cardhu_audio_wm8903_pdata = { .gpio_spkr_en = TEGRA_GPIO_SPKR_EN, .gpio_hp_det = TEGRA_GPIO_HP_DET, .gpio_hp_mute = -1, .gpio_int_mic_en = -1, .gpio_ext_mic_en = -1, + .i2s_param[HIFI_CODEC] = { + .audio_port_id = 0, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_I2S, + }, + .i2s_param[BASEBAND] = { + .audio_port_id = -1, + }, + .i2s_param[BT_SCO] = { + .audio_port_id = 3, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_DSP_A, + }, }; static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = { @@ -738,6 +752,19 @@ static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = { .gpio_hp_mute = -1, .gpio_int_mic_en = -1, .gpio_ext_mic_en = -1, + .i2s_param[HIFI_CODEC] = { + .audio_port_id = 0, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_I2S, + }, + .i2s_param[BASEBAND] = { + .audio_port_id = -1, + }, + .i2s_param[BT_SCO] = { + .audio_port_id = 3, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_DSP_A, + }, }; static struct platform_device cardhu_audio_wm8903_device = { @@ -763,14 +790,17 @@ static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = { .gpio_int_mic_en = -1, .gpio_ext_mic_en = -1, /*defaults for Verbier-Cardhu board with TI AIC326X codec*/ - .audio_port_id = { - [HIFI_CODEC] = 0, - [BASEBAND] = -1, - [BT_SCO] = 3, + .i2s_param[HIFI_CODEC] = { + .audio_port_id = 0, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_I2S, + .sample_size = 16, }, - .baseband_param = { - .rate = -1, - .channels = -1, + .i2s_param[BT_SCO] = { + .sample_size = 16, + .audio_port_id = 3, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_DSP_A, }, }; diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c index f9e5b05e6d3c..f9791a7b0e48 100644 --- a/arch/arm/mach-tegra/board-enterprise.c +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -467,8 +467,6 @@ static void __init enterprise_uart_init(void) ARRAY_SIZE(enterprise_uart_devices)); } - - static struct resource tegra_rtc_resources[] = { [0] = { .start = TEGRA_RTC_BASE, @@ -500,16 +498,27 @@ static struct tegra_asoc_platform_data enterprise_audio_pdata = { .gpio_hp_mute = -1, .gpio_int_mic_en = -1, .gpio_ext_mic_en = -1, - .debounce_time_hp = -1, + .debounce_time_hp = -1, /*defaults for Enterprise board*/ - .audio_port_id = { - [HIFI_CODEC] = 0, - [BASEBAND] = 2, - [BT_SCO] = 3, + .i2s_param[HIFI_CODEC] = { + .audio_port_id = 0, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_I2S, + .sample_size = 16, }, - .baseband_param = { - .rate = 8000, - .channels = 1, + .i2s_param[BASEBAND] = { + .audio_port_id = 2, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_DSP_A, + .sample_size = 16, + .rate = 8000, + .channels = 1, + }, + .i2s_param[BT_SCO] = { + .audio_port_id = 3, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_DSP_A, + .sample_size = 16, }, }; @@ -528,15 +537,25 @@ static struct tegra_asoc_platform_data enterprise_audio_aic326x_pdata = { .gpio_int_mic_en = -1, .gpio_ext_mic_en = -1, /*defaults for Verbier-Enterprise (E1197) board with TI AIC326X codec*/ - .audio_port_id = { - [HIFI_CODEC] = 0, - [BASEBAND] = 2, - [BT_SCO] = 3, + .i2s_param[HIFI_CODEC] = { + .audio_port_id = 0, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_I2S, + .sample_size = 16, + }, + .i2s_param[BASEBAND] = { + .audio_port_id = 2, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_DSP_A, + .sample_size = 16, + .rate = 8000, + .channels = 1, }, - .baseband_param = { - .rate = 8000, - .channels = 1, - .bit_format = TEGRA_DAIFMT_DSP_A, + .i2s_param[BT_SCO] = { + .sample_size = 16, + .audio_port_id = 3, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_DSP_A, }, }; @@ -849,7 +868,7 @@ static void enterprise_audio_init(void) tegra_get_board_info(&board_info); if (board_info.board_id == BOARD_E1197) - enterprise_audio_pdata.audio_port_id[HIFI_CODEC] = 1; + enterprise_audio_pdata.i2s_param[HIFI_CODEC].audio_port_id = 1; platform_add_devices(enterprise_audio_devices, ARRAY_SIZE(enterprise_audio_devices)); diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c index dd14435cc17c..0e1dfe58b278 100644 --- a/arch/arm/mach-tegra/board-harmony.c +++ b/arch/arm/mach-tegra/board-harmony.c @@ -3,6 +3,7 @@ * * Copyright (C) 2010 Google, Inc. * Copyright (C) 2011 NVIDIA, Inc. + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -43,7 +44,7 @@ #include #include -#include +#include #include #include #include @@ -230,12 +231,25 @@ static void harmony_keys_init(void) tegra_gpio_enable(harmony_gpio_keys_buttons[i].gpio); } -static struct tegra_wm8903_platform_data harmony_audio_pdata = { +static struct tegra_asoc_platform_data harmony_audio_pdata = { .gpio_spkr_en = TEGRA_GPIO_SPKR_EN, .gpio_hp_det = TEGRA_GPIO_HP_DET, .gpio_hp_mute = -1, .gpio_int_mic_en = TEGRA_GPIO_INT_MIC_EN, .gpio_ext_mic_en = TEGRA_GPIO_EXT_MIC_EN, + .i2s_param[HIFI_CODEC] = { + .audio_port_id = 0, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_I2S, + }, + .i2s_param[BASEBAND] = { + .audio_port_id = -1, + }, + .i2s_param[BT_SCO] = { + .audio_port_id = 3, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_DSP_A, + }, }; static struct platform_device harmony_audio_device = { diff --git a/arch/arm/mach-tegra/board-kai.c b/arch/arm/mach-tegra/board-kai.c index 07fbccfd8138..83874f89d836 100644 --- a/arch/arm/mach-tegra/board-kai.c +++ b/arch/arm/mach-tegra/board-kai.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/board-kai.c * - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -52,7 +52,7 @@ #include #include #include -#include +#include #include #include #include @@ -575,12 +575,25 @@ static struct platform_device tegra_rtc_device = { .num_resources = ARRAY_SIZE(tegra_rtc_resources), }; -static struct tegra_rt5640_platform_data kai_audio_pdata = { +static struct tegra_asoc_platform_data kai_audio_pdata = { .gpio_spkr_en = TEGRA_GPIO_SPKR_EN, .gpio_hp_det = TEGRA_GPIO_HP_DET, .gpio_hp_mute = -1, .gpio_int_mic_en = TEGRA_GPIO_INT_MIC_EN, .gpio_ext_mic_en = TEGRA_GPIO_EXT_MIC_EN, + .i2s_param[HIFI_CODEC] = { + .audio_port_id = 0, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_I2S, + }, + .i2s_param[BASEBAND] = { + .audio_port_id = -1, + }, + .i2s_param[BT_SCO] = { + .audio_port_id = 3, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_DSP_A, + }, }; static struct platform_device kai_audio_device = { diff --git a/arch/arm/mach-tegra/board-ventana.c b/arch/arm/mach-tegra/board-ventana.c index c8c9ac49745f..4e01850ea40e 100644 --- a/arch/arm/mach-tegra/board-ventana.c +++ b/arch/arm/mach-tegra/board-ventana.c @@ -2,6 +2,7 @@ * arch/arm/mach-tegra/board-ventana.c * * Copyright (c) 2010-2011 NVIDIA Corporation. + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -49,7 +50,7 @@ #include #include #include -#include +#include #include #include @@ -350,12 +351,25 @@ static struct platform_device tegra_camera = { .id = -1, }; -static struct tegra_wm8903_platform_data ventana_audio_pdata = { +static struct tegra_asoc_platform_data ventana_audio_pdata = { .gpio_spkr_en = TEGRA_GPIO_SPKR_EN, .gpio_hp_det = TEGRA_GPIO_HP_DET, .gpio_hp_mute = -1, .gpio_int_mic_en = TEGRA_GPIO_INT_MIC_EN, .gpio_ext_mic_en = TEGRA_GPIO_EXT_MIC_EN, + .i2s_param[HIFI_CODEC] = { + .audio_port_id = 0, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_I2S, + }, + .i2s_param[BASEBAND] = { + .audio_port_id = -1, + }, + .i2s_param[BT_SCO] = { + .audio_port_id = 3, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_DSP_A, + }, }; static struct platform_device ventana_audio_device = { diff --git a/arch/arm/mach-tegra/board-whistler.c b/arch/arm/mach-tegra/board-whistler.c index 4bd5ed8471d4..92fa6e502abe 100644 --- a/arch/arm/mach-tegra/board-whistler.c +++ b/arch/arm/mach-tegra/board-whistler.c @@ -352,12 +352,32 @@ static struct platform_device tegra_camera = { }; static struct tegra_asoc_platform_data whistler_audio_pdata = { - .gpio_spkr_en = -1, - .gpio_hp_det = TEGRA_GPIO_HP_DET, - .gpio_hp_mute = -1, - .gpio_int_mic_en = -1, - .gpio_ext_mic_en = -1, - .debounce_time_hp = 200, + .gpio_spkr_en = -1, + .gpio_hp_det = TEGRA_GPIO_HP_DET, + .gpio_hp_mute = -1, + .gpio_int_mic_en = -1, + .gpio_ext_mic_en = -1, + .debounce_time_hp = 200, + .i2s_param[HIFI_CODEC] = { + .audio_port_id = 0, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_I2S, + .sample_size = 16, + }, + .i2s_param[BASEBAND] = { + .audio_port_id = 2, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_DSP_A, + .sample_size = 16, + .rate = 8000, + .channels = 1, + }, + .i2s_param[BT_SCO] = { + .sample_size = 16, + .audio_port_id = 3, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_DSP_A, + }, }; static struct platform_device whistler_audio_aic326x_device = { diff --git a/arch/arm/mach-tegra/include/mach/tegra_asoc_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_asoc_pdata.h index fff2fcc68269..7aada6940b39 100644 --- a/arch/arm/mach-tegra/include/mach/tegra_asoc_pdata.h +++ b/arch/arm/mach-tegra/include/mach/tegra_asoc_pdata.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/include/mach/tegra_asoc_pdata.h * - * Copyright 2012 NVIDIA, Inc. + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -25,20 +25,23 @@ #define TEGRA_DAIFMT_RIGHT_J 3 #define TEGRA_DAIFMT_LEFT_J 4 -struct baseband_config { +struct i2s_config { + int audio_port_id; + int is_i2s_master; + int i2s_mode; + int sample_size; int rate; int channels; - int bit_format; - int is_master; }; struct tegra_asoc_platform_data { + const char *codec_name; + const char *codec_dai_name; int gpio_spkr_en; int gpio_hp_det; int gpio_hp_mute; int gpio_int_mic_en; int gpio_ext_mic_en; unsigned int debounce_time_hp; - int audio_port_id[NUM_I2S_DEVICES]; - struct baseband_config baseband_param; + struct i2s_config i2s_param[NUM_I2S_DEVICES]; }; -- cgit v1.2.3 From 3d51e1972471a6daf203b7e0b05e42afe117f3a7 Mon Sep 17 00:00:00 2001 From: Mohit Kataria Date: Thu, 19 Jul 2012 19:14:31 +0530 Subject: ARM: Tegra: p1852: defconfig: disabled TEGRA_SE_ON_CBUS and set CONFIG_TEGRA_CBUS_CLOCK_DIVIDER=1 * Disabled CONFIG_TEGRA_SE_ON_CBUS So that se clock can be derived from clocks other than which are driving cbus. * Changed CONFIG_TEGRA_CBUS_CLOCK_DIVIDER=1 So that pllc can run at same frequency as cbus is running at. Bug 978870 Change-Id: I66898e3f16adad3625efb1a484b438c168419a68 Signed-off-by: Mohit Kataria Reviewed-on: http://git-master/r/117995 (cherry picked from commit b5d42b0432119ddebcc38f6f40761e3dea3d9f6d) Reviewed-on: http://git-master/r/117312 GVS: Gerrit_Virtual_Submit Reviewed-by: Varun Wadekar --- arch/arm/configs/tegra_p1852_gnu_linux_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/tegra_p1852_gnu_linux_defconfig b/arch/arm/configs/tegra_p1852_gnu_linux_defconfig index 7a1435a4024a..e6b401c23e2b 100644 --- a/arch/arm/configs/tegra_p1852_gnu_linux_defconfig +++ b/arch/arm/configs/tegra_p1852_gnu_linux_defconfig @@ -35,6 +35,8 @@ CONFIG_TEGRA_P1852_TDM=y # CONFIG_TEGRA_CPU_DVFS is not set CONFIG_TEGRA_CLOCK_DEBUG_WRITE=y # CONFIG_TEGRA_MC_EARLY_ACK is not set +# CONFIG_TEGRA_SE_ON_CBUS is not set +CONFIG_TEGRA_CBUS_CLOCK_DIVIDER=1 CONFIG_NON_ALIASED_COHERENT_MEM=y CONFIG_ARM_ERRATA_742230=y CONFIG_ARM_ERRATA_743622=y -- cgit v1.2.3 From dc251e8eb5a55ec2acd3f2bccaf3d5d5c1e8bed2 Mon Sep 17 00:00:00 2001 From: Krishna Reddy Date: Wed, 18 Jul 2012 13:51:10 -0700 Subject: arm: configs: tegra3: Enable fault injection for slab alloctor. Even though config option is enabled, the fault injection is not enabled by default. It need to be enabled through debugfs interface during test. Change-Id: Iaba52d27a97bc4ecdc04e79e29ab25e03438bbc0 Signed-off-by: Krishna Reddy Reviewed-on: http://git-master/r/116851 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu (cherry picked from commit 892f0239562de8cd5a6a93deeaec826e45b368b0) Reviewed-on: http://git-master/r/118192 --- arch/arm/configs/tegra3_android_defconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/tegra3_android_defconfig b/arch/arm/configs/tegra3_android_defconfig index fe9c794bb043..825b6e3b00c1 100644 --- a/arch/arm/configs/tegra3_android_defconfig +++ b/arch/arm/configs/tegra3_android_defconfig @@ -461,6 +461,10 @@ CONFIG_TIMER_STATS=y # CONFIG_DEBUG_PREEMPT is not set CONFIG_DEBUG_INFO=y CONFIG_DEBUG_VM=y +CONFIG_FAULT_INJECTION=y +CONFIG_FAILSLAB=y +CONFIG_FAULT_INJECTION_DEBUG_FS=y +CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y CONFIG_FUNCTION_TRACER=y # CONFIG_FUNCTION_GRAPH_TRACER is not set CONFIG_TRACEDUMP=y -- cgit v1.2.3 From e402db9b3737209c9981aea5970328d7c1cb06ce Mon Sep 17 00:00:00 2001 From: Ilan Aelion Date: Wed, 27 Jun 2012 18:58:11 -0600 Subject: misc: tegra-throughput: adding throughput dev node Creates a miscdev at /dev/tegra-throughput which gl will use to set a target frame rate. In addition it receives notifications from dc on flip events. On each notification the percentage ratio of the actual frame time to the target frame time is calculated. In subsequent changes this ratio will be reported to other modules as a throughput hint. Bug 991589 Change-Id: Ieaa2b2755b63d2d071de31e3ef819d4c3b51a956 Signed-off-by: Ilan Aelion Reviewed-on: http://git-master/r/116865 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam Reviewed-by: Jon Mayo --- arch/arm/mach-tegra/include/mach/dc.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/include/mach/dc.h b/arch/arm/mach-tegra/include/mach/dc.h index 161e37616497..47210c1cd87b 100644 --- a/arch/arm/mach-tegra/include/mach/dc.h +++ b/arch/arm/mach-tegra/include/mach/dc.h @@ -25,6 +25,7 @@ #include #include #include +#include #define TEGRA_MAX_DC 2 #define DC_N_WINDOWS 3 @@ -584,4 +585,8 @@ struct tegra_dc_edid { struct tegra_dc_edid *tegra_dc_get_edid(struct tegra_dc *dc); void tegra_dc_put_edid(struct tegra_dc_edid *edid); +int tegra_dc_register_flip_notifier(struct notifier_block *nb); +int tegra_dc_unregister_flip_notifier(struct notifier_block *nb); +int tegra_dc_get_panel_sync_rate(void); + #endif -- cgit v1.2.3 From e9e4bc232f2698d166f7c63bd5434c352083682a Mon Sep 17 00:00:00 2001 From: Sang-Hun Lee Date: Fri, 27 Jul 2012 09:57:54 -0700 Subject: ARM: tegra: clock: increase Tegra3 pll post-lock delay Bug 1022877 Change-Id: I9200d3345a933ab0ccb31f833184ee4a621228f0 Reviewed-on: http://git-master/r/118774 Reviewed-by: Aleksandr Frid Reviewed-by: Sang-Hun Lee Tested-by: Sang-Hun Lee Reviewed-by: Prajakta Gudadhe --- arch/arm/mach-tegra/clock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index 888808461bb9..c27176b1cc0d 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -27,7 +27,7 @@ #else #define USE_PLL_LOCK_BITS 1 /* Use lock bits for PLL stabiliation */ #define USE_PLLE_SS 1 /* Use spread spectrum coefficients for PLLE */ -#define PLL_POST_LOCK_DELAY 2 /* Safety delay after lock is detected */ +#define PLL_POST_LOCK_DELAY 50 /* Safety delay after lock is detected */ #endif #define DIV_BUS (1 << 0) -- cgit v1.2.3 From 935adef53692ab73a02a7d09876756b30beb5206 Mon Sep 17 00:00:00 2001 From: Michael Frydrych Date: Wed, 11 Jul 2012 11:43:42 +0300 Subject: arm: tegra: la: hack latency allowance formula Remove the ad-hoc scale factor of final latency allowance. Scale the fifo size to pretend that our FIFO is only as deep as the lowest fullness we expect to see. Bug 995270 Change-Id: I78ed2246d2031a2303f81a19fe05c95572a692b0 Signed-off-by: Michael Frydrych Reviewed-on: http://git-master/r/118816 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy Reviewed-by: Graziano Misuraca Tested-by: Graziano Misuraca Reviewed-by: Jon Mayo --- arch/arm/mach-tegra/latency_allowance.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/latency_allowance.c b/arch/arm/mach-tegra/latency_allowance.c index 7698ba39f4ca..f8e5ce579200 100644 --- a/arch/arm/mach-tegra/latency_allowance.c +++ b/arch/arm/mach-tegra/latency_allowance.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/latency_allowance.c * - * Copyright (C) 2011 NVIDIA Corporation + * Copyright (C) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -100,6 +100,9 @@ printk(KERN_INFO pr_fmt(fmt), ##__VA_ARGS__); \ } +/* Bug 995270 */ +#define HACK_LA_FIFO 1 + static struct dentry *latency_debug_dir; struct la_client_info { @@ -384,7 +387,9 @@ int tegra_set_latency_allowance(enum tegra_la_id id, int la_to_set; unsigned long reg_read; unsigned long reg_write; + unsigned int fifo_size_in_atoms; int bytes_per_atom = normal_atom_size; + const int fifo_scale = 4; /* 25% of the FIFO */ struct la_client_info *ci; VALIDATE_ID(id); @@ -394,11 +399,19 @@ int tegra_set_latency_allowance(enum tegra_la_id id, bytes_per_atom = fdc_atom_size; ci = &la_info[id]; + fifo_size_in_atoms = ci->fifo_size_in_atoms; + +#if HACK_LA_FIFO + /* pretend that our FIFO is only as deep as the lowest fullness + * we expect to see */ + if (id >= ID(DISPLAY_0A) && id <= ID(DISPLAY_HCB)) + fifo_size_in_atoms /= fifo_scale; +#endif if (bandwidth_in_mbps == 0) { la_to_set = MC_LA_MAX_VALUE; } else { - ideal_la = (ci->fifo_size_in_atoms * bytes_per_atom * 1000) / + ideal_la = (fifo_size_in_atoms * bytes_per_atom * 1000) / (bandwidth_in_mbps * ns_per_tick); la_to_set = ideal_la - (ci->expiration_in_ns/ns_per_tick) - 1; } @@ -409,11 +422,6 @@ int tegra_set_latency_allowance(enum tegra_la_id id, la_to_set = (la_to_set > MC_LA_MAX_VALUE) ? MC_LA_MAX_VALUE : la_to_set; scaling_info[id].actual_la_to_set = la_to_set; - /* until display can use latency allowance scaling, use a more - * aggressive LA setting. Bug 862709 */ - if (id >= ID(DISPLAY_0A) && id <= ID(DISPLAY_HCB)) - la_to_set /= 3; - spin_lock(&safety_lock); reg_read = readl(ci->reg_addr); reg_write = (reg_read & ~ci->mask) | -- cgit v1.2.3 From 6d24e4887d377c0318514aea091cf6e3b5e7cf53 Mon Sep 17 00:00:00 2001 From: Venu Byravarasu Date: Tue, 24 Jul 2012 18:12:22 +0530 Subject: arm: tegra3: usb_phy: Add support for HSIC wakeup As part of this patch following changes are made: 1. HSIC regulator enable/disable is added 2. HSIC phy close is added. bug 1010916 Change-Id: I4607a3ac13417a201b62708c6fef5d1117dfdcc5 Signed-off-by: Venu Byravarasu Reviewed-on: http://git-master/r/116984 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty --- arch/arm/mach-tegra/tegra3_usb_phy.c | 58 ++++++++++++++++++++++++++++++++++++ arch/arm/mach-tegra/tegra_usb_phy.h | 1 + 2 files changed, 59 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index 0b8ab076693d..171e2ec91ada 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -2065,10 +2065,58 @@ static void uhsic_phy_restore_end(struct tegra_usb_phy *phy) } } +static int hsic_rail_enable(struct tegra_usb_phy *phy) +{ + int ret; + + if (phy->hsic_reg == NULL) { + phy->hsic_reg = regulator_get(NULL, "avdd_hsic"); + if (IS_ERR_OR_NULL(phy->hsic_reg)) { + pr_err("HSIC: Could not get regulator avdd_hsic\n"); + phy->hsic_reg = NULL; + return PTR_ERR(phy->hsic_reg); + } + } + + ret = regulator_enable(phy->hsic_reg); + if (ret < 0) { + pr_err("%s avdd_hsic could not be enabled\n", __func__); + return ret; + } + + return 0; +} + +static int hsic_rail_disable(struct tegra_usb_phy *phy) +{ + int ret; + + if (phy->hsic_reg == NULL) { + pr_warn("%s: unbalanced disable\n", __func__); + return -EIO; + } + + ret = regulator_disable(phy->hsic_reg); + if (ret < 0) { + pr_err("HSIC regulator avdd_hsic cannot be disabled\n"); + return ret; + } + + return 0; +} + static int uhsic_phy_open(struct tegra_usb_phy *phy) { unsigned long parent_rate; int i; + int ret; + + phy->hsic_reg = NULL; + ret = hsic_rail_enable(phy); + if (ret < 0) { + pr_err("%s avdd_hsic could not be enabled\n", __func__); + return ret; + } DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk)); @@ -2088,6 +2136,15 @@ static int uhsic_phy_open(struct tegra_usb_phy *phy) return 0; } +static void uhsic_phy_close(struct tegra_usb_phy *phy) +{ + int ret; + + ret = hsic_rail_disable(phy); + if (ret < 0) + pr_err("%s avdd_hsic could not be disabled\n", __func__); +} + static int uhsic_phy_irq(struct tegra_usb_phy *phy) { usb_phy_fence_read(phy); @@ -2863,6 +2920,7 @@ static struct tegra_usb_phy_ops utmi_phy_ops = { static struct tegra_usb_phy_ops uhsic_phy_ops = { .open = uhsic_phy_open, + .close = uhsic_phy_close, .irq = uhsic_phy_irq, .power_on = uhsic_phy_power_on, .power_off = uhsic_phy_power_off, diff --git a/arch/arm/mach-tegra/tegra_usb_phy.h b/arch/arm/mach-tegra/tegra_usb_phy.h index 7e85a4b02282..674e8b8ffd18 100644 --- a/arch/arm/mach-tegra/tegra_usb_phy.h +++ b/arch/arm/mach-tegra/tegra_usb_phy.h @@ -80,6 +80,7 @@ struct tegra_usb_phy { struct clk *emc_clk; struct clk *sys_clk; struct regulator *vdd_reg; + struct regulator *hsic_reg; struct regulator *vbus_reg; struct tegra_usb_phy_ops *ops; struct tegra_xtal_freq *freq; -- cgit v1.2.3 From a8fccaec15ed648acd510f05534653fae6b4caa0 Mon Sep 17 00:00:00 2001 From: Venu Byravarasu Date: Fri, 20 Jul 2012 15:18:27 +0530 Subject: arm: tegra: Add HSIC to list of wake up sources bug 1010916 Change-Id: I6d01e8d19be1583b7454cc731f8f30ec58eec672 Signed-off-by: Venu Byravarasu Reviewed-on: http://git-master/r/117338 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty --- arch/arm/mach-tegra/wakeups-t3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/wakeups-t3.c b/arch/arm/mach-tegra/wakeups-t3.c index ef471cb035db..dd042f8fafc0 100644 --- a/arch/arm/mach-tegra/wakeups-t3.c +++ b/arch/arm/mach-tegra/wakeups-t3.c @@ -66,7 +66,8 @@ static struct tegra_wake_info tegra_wake_event_data_t3[] = { {-EINVAL, POLARITY_NONE}, /* TEGRA_USB3_ID, */ /* wake38 */ {INT_USB, POLARITY_LEVEL_HI}, /* TEGRA_USB1_UTMIP, */ /* wake39 */ {INT_USB2, POLARITY_LEVEL_HI}, /* TEGRA_USB2_UTMIP, */ /* wake40 */ - {INT_USB3, POLARITY_LEVEL_HI} /* TEGRA_USB3_UTMIP, */ /* wake41 */ + {INT_USB3, POLARITY_LEVEL_HI}, /* TEGRA_USB3_UTMIP, */ /* wake41 */ + {INT_USB2, POLARITY_LEVEL_HI}, /* TEGRA_USB2_UHSIC, */ /* wake42 */ }; struct tegra_wake_info *tegra_wake_event_data = tegra_wake_event_data_t3; -- cgit v1.2.3 From 97f9f654114aad07c828b05d057a11e03b1af803 Mon Sep 17 00:00:00 2001 From: Rakesh Iyer Date: Wed, 25 Jul 2012 14:10:35 -0700 Subject: ARM: tegra: cardhu: report height/width for E1506 For accurate Dots-per-inch computation we need to report height/width for the E1506 panel. Bug 1014380. Change-Id: Ic78b6843f65f44d6162e3c4313aae37bd0e96ba1 Signed-off-by: Rakesh Iyer Reviewed-on: http://git-master/r/118438 Reviewed-by: Lokesh Pathak Tested-by: Lokesh Pathak --- arch/arm/mach-tegra/board-cardhu-panel.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-panel.c b/arch/arm/mach-tegra/board-cardhu-panel.c index e50a4433f11a..64a50d41eaf7 100644 --- a/arch/arm/mach-tegra/board-cardhu-panel.c +++ b/arch/arm/mach-tegra/board-cardhu-panel.c @@ -1288,6 +1288,9 @@ static void cardhu_panel_preinit(void) cardhu_dsi.panel_send_dc_frames = true, cardhu_dsi_fb_data.xres = 720; cardhu_dsi_fb_data.yres = 1280; + /* Set height and width in mm. */ + cardhu_disp1_out.height = 95; + cardhu_disp1_out.width = 53; } cardhu_disp1_pdata.fb = &cardhu_dsi_fb_data; -- cgit v1.2.3 From 4012b752d64fd88efc3797e42ad8fedb29045e06 Mon Sep 17 00:00:00 2001 From: Jong Kim Date: Fri, 20 Jul 2012 17:15:57 -0700 Subject: ARM: tegra3: clock: Put graphic clks to safe range Initialize graphic and video input clocks in to safe frequency ranges. bug 966041 Change-Id: I48a035b42bad5a6d36f56e2b0610baf0703c3bcd Signed-off-by: Jong Kim Reviewed-on: http://git-master/r/117484 Reviewed-by: Lokesh Pathak Tested-by: Lokesh Pathak --- arch/arm/mach-tegra/tegra3_clocks.c | 79 +++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index de9bc5f2ae03..828a806ff99f 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -5200,9 +5200,17 @@ static struct syscore_ops tegra_clk_syscore_ops = { #define CLK_RSTENB_DEV_V_0_DAM1_BIT (1 << 13) #define CLK_RSTENB_DEV_V_0_DAM0_BIT (1 << 12) #define CLK_RSTENB_DEV_V_0_AUDIO_BIT (1 << 10) +#define CLK_RSTENB_DEV_V_0_3D2_BIT (1 << 2) #define CLK_RSTENB_DEV_L_0_HOST1X_BIT (1 << 28) #define CLK_RSTENB_DEV_L_0_DISP1_BIT (1 << 27) +#define CLK_RSTENB_DEV_L_0_3D_BIT (1 << 24) +#define CLK_RSTENB_DEV_L_0_2D_BIT (1 << 21) +#define CLK_RSTENB_DEV_L_0_VI_BIT (1 << 20) +#define CLK_RSTENB_DEV_L_0_EPP_BIT (1 << 19) + +#define CLK_RSTENB_DEV_H_0_VDE_BIT (1 << 29) +#define CLK_RSTENB_DEV_H_0_MPE_BIT (1 << 28) #define DISP1_CLK_REG_OFFSET 0x138 #define DISP1_CLK_SRC_SHIFT 29 @@ -5249,6 +5257,31 @@ static struct syscore_ops tegra_clk_syscore_ops = { #define AUDIO_CLK_DIV_DEFAULT (\ (0 << AUDIO_CLK_DIV_SHIFT)) +#define VCLK_SRC_SHIFT 30 +#define VCLK_SRC_MASK (0x3 << VCLK_SRC_SHIFT) +#define VCLK_SRC_PLLM_OUT0 0 +#define VCLK_SRC_PLLC_OUT0 1 +#define VCLK_SRC_PLLP_OUT0 2 +#define VCLK_SRC_PLLA_OUT0 3 +#define VCLK_SRC_DEFAULT (VCLK_SRC_PLLM_OUT0 << VCLK_SRC_SHIFT) +#define VCLK_IDLE_DIV_SHIFT 8 +#define VCLK_IDLE_DIV_MASK (0xff << VCLK_IDLE_DIV_SHIFT) +#define VCLK_IDLE_DIV_DEFAULT (0 << VCLK_IDLE_DIV_SHIFT) +#define VCLK_DIV_SHIFT 0 +#define VCLK_DIV_MASK (0xff << VCLK_DIV_SHIFT) +#define VCLK_DIV_DEFAULT (0xa << VCLK_DIV_SHIFT) + +#define VI_CLK_REG_OFFSET 0x148 +#define VI_CLK_SEL_VI_SENSOR_CLK (1 << 25) +#define VI_CLK_SEL_EXTERNAL_CLK (1 << 24) +#define VI_SENSOR_CLK_REG_OFFSET 0x1a8 +#define G3D_CLK_REG_OFFSET 0x158 +#define G2D_CLK_REG_OFFSET 0x15c +#define EPP_CLK_REG_OFFSET 0x16c +#define MPE_CLK_REG_OFFSET 0x170 +#define VDE_CLK_REG_OFFSET 0x170 +#define G3D2_CLK_REG_OFFSET 0x3b0 + static void __init clk_setbit(u32 reg, u32 bit) { u32 val = clk_readl(reg); @@ -5283,6 +5316,43 @@ static void __init clk_setbits(u32 reg, u32 bits, u32 mask) udelay(2); } +static void __init vclk_init(int tag, u32 src, u32 rebit) +{ + u32 rst, enb; + + switch (tag) { + case 'L': + rst = RST_DEVICES_L; + enb = CLK_OUT_ENB_L; + break; + case 'H': + rst = RST_DEVICES_H; + enb = CLK_OUT_ENB_H; + break; + case 'U': + rst = RST_DEVICES_U; + enb = CLK_OUT_ENB_U; + break; + case 'V': + rst = RST_DEVICES_V; + enb = CLK_OUT_ENB_V; + break; + case 'W': + rst = RST_DEVICES_W; + enb = CLK_OUT_ENB_W; + break; + default: + /* Quietly ignore. */ + return; + } + + clk_setbit(rst, rebit); + clk_clrbit(enb, rebit); + clk_setbits(src, VCLK_SRC_DEFAULT, VCLK_SRC_MASK); + clk_setbits(src, VCLK_DIV_DEFAULT, VCLK_DIV_MASK); + clk_clrbit(rst, rebit); +} + static int __init tegra_soc_preinit_clocks(void) { /* @@ -5358,6 +5428,15 @@ static int __init tegra_soc_preinit_clocks(void) AUDIO_CLK_SRC_DEFAULT, AUDIO_CLK_SRC_MASK); clk_clrbit(RST_DEVICES_V, CLK_RSTENB_DEV_V_0_AUDIO_BIT); + /* Pre-initialize Video clocks. */ + vclk_init('L', G3D_CLK_REG_OFFSET, CLK_RSTENB_DEV_L_0_3D_BIT); + vclk_init('L', G2D_CLK_REG_OFFSET, CLK_RSTENB_DEV_L_0_2D_BIT); + vclk_init('L', VI_CLK_REG_OFFSET, CLK_RSTENB_DEV_L_0_VI_BIT); + vclk_init('L', EPP_CLK_REG_OFFSET, CLK_RSTENB_DEV_L_0_EPP_BIT); + vclk_init('H', VDE_CLK_REG_OFFSET, CLK_RSTENB_DEV_H_0_VDE_BIT); + vclk_init('H', MPE_CLK_REG_OFFSET, CLK_RSTENB_DEV_H_0_MPE_BIT); + vclk_init('V', G3D2_CLK_REG_OFFSET, CLK_RSTENB_DEV_V_0_3D2_BIT); + return 0; } #endif /* CONFIG_TEGRA_PREINIT_CLOCKS */ -- cgit v1.2.3 From 4582bcef392ae029336673f5685a18fc67ac041a Mon Sep 17 00:00:00 2001 From: Anshul Jain Date: Mon, 23 Jul 2012 14:59:32 -0700 Subject: ARM: tegra: dvfs: Adjust VDD_CPU to offset aging Add silicon aging for VDD_CPU, this recovers some of millivolts based on the age of the chip. BUG 1006420 Change-Id: Idddb5861ab039e7ece262dec3697a69c3534ccf2 Signed-off-by: Anshul Jain Reviewed-on: http://git-master/r/116911 Reviewed-by: Aleksandr Frid Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam GVS: Gerrit_Virtual_Submit --- arch/arm/mach-tegra/dvfs.c | 5 +++ arch/arm/mach-tegra/dvfs.h | 5 ++- arch/arm/mach-tegra/fuse.c | 44 +++++++++++++++++++ arch/arm/mach-tegra/fuse.h | 1 + arch/arm/mach-tegra/tegra3_dvfs.c | 46 ++++++++++++++++++-- arch/arm/mach-tegra/timer.c | 91 +++++++++++++++++++++++++++++++++++++++ arch/arm/mach-tegra/timer.h | 3 ++ 7 files changed, 191 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/dvfs.c b/arch/arm/mach-tegra/dvfs.c index cb33e3db862f..43f42cdf527d 100644 --- a/arch/arm/mach-tegra/dvfs.c +++ b/arch/arm/mach-tegra/dvfs.c @@ -38,6 +38,7 @@ #include "board.h" #include "clock.h" #include "dvfs.h" +#include "timer.h" #define DVFS_RAIL_STATS_BIN 25 #define DVFS_RAIL_STATS_SCALE 2 @@ -681,9 +682,13 @@ int __init tegra_dvfs_late_init(void) { bool connected = true; struct dvfs_rail *rail; + int cur_linear_age = tegra_get_linear_age(); mutex_lock(&dvfs_lock); + if (cur_linear_age >= 0) + tegra_dvfs_age_cpu(cur_linear_age); + list_for_each_entry(rail, &dvfs_rail_list, node) if (dvfs_rail_connect_to_regulator(rail)) connected = false; diff --git a/arch/arm/mach-tegra/dvfs.h b/arch/arm/mach-tegra/dvfs.h index 91901b361724..7cacd954b914 100644 --- a/arch/arm/mach-tegra/dvfs.h +++ b/arch/arm/mach-tegra/dvfs.h @@ -22,7 +22,7 @@ #define _TEGRA_DVFS_H_ #define MAX_DVFS_FREQS 40 -#define DVFS_RAIL_STATS_TOP_BIN 40 +#define DVFS_RAIL_STATS_TOP_BIN 42 struct clk; struct dvfs_rail; @@ -165,11 +165,14 @@ static inline int tegra_cpu_dvfs_alter(int edp_thermal_index, #ifndef CONFIG_ARCH_TEGRA_2x_SOC int tegra_dvfs_rail_disable_prepare(struct dvfs_rail *rail); int tegra_dvfs_rail_post_enable(struct dvfs_rail *rail); +void tegra_dvfs_age_cpu(int cur_linear_age); #else static inline int tegra_dvfs_rail_disable_prepare(struct dvfs_rail *rail) { return 0; } static inline int tegra_dvfs_rail_post_enable(struct dvfs_rail *rail) { return 0; } +static inline void tegra_dvfs_age_cpu(int cur_linear_age) +{ return; } #endif #endif diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index 6df9da994fb9..bb7c242ef47e 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c @@ -62,6 +62,21 @@ #endif +#define TEGRA_AGE_0_6 0x2cc /*Spare bit 34*/ +#define TEGRA_AGE_1_6 0x308 /*Spare bit 49*/ +#define TEGRA_AGE_0_5 0x2c8 /*Spare bit 33*/ +#define TEGRA_AGE_1_5 0x304 /*Spare bit 48*/ +#define TEGRA_AGE_0_4 0x2c4 /*Spare bit 32*/ +#define TEGRA_AGE_1_4 0x300 /*Spare bit 47*/ +#define TEGRA_AGE_0_3 0x2c0 /*Spare bit 31*/ +#define TEGRA_AGE_1_3 0x2fc /*Spare bit 46*/ +#define TEGRA_AGE_0_2 0x2bc /*Spare bit 30*/ +#define TEGRA_AGE_1_2 0x2f8 /*Spare bit 45*/ +#define TEGRA_AGE_0_1 0x2b8 /*Spare bit 29*/ +#define TEGRA_AGE_1_1 0x2f4 /*Spare bit 44*/ +#define TEGRA_AGE_0_0 0x2b4 /*Spare bit 28*/ +#define TEGRA_AGE_1_0 0x2f0 /*Spare bit 43*/ + struct tegra_id { enum tegra_chipid chipid; unsigned int major, minor, netlist, patch; @@ -172,6 +187,35 @@ int tegra_fuse_get_tsensor_spare_bits(u32 *spare_bits) EXPORT_SYMBOL(tegra_fuse_get_tsensor_spare_bits); #endif +#define TEGRA_READ_AGE_BIT(n, bit, age) {\ + bit = tegra_fuse_readl(TEGRA_AGE_0_##n);\ + bit |= tegra_fuse_readl(TEGRA_AGE_1_##n);\ + bit = bit << n;\ + age |= bit;\ +} + +int tegra_get_age(void) +{ + int linear_age, age_bit; + linear_age = age_bit = 0; + + TEGRA_READ_AGE_BIT(6, age_bit, linear_age); + TEGRA_READ_AGE_BIT(5, age_bit, linear_age); + TEGRA_READ_AGE_BIT(4, age_bit, linear_age); + TEGRA_READ_AGE_BIT(3, age_bit, linear_age); + TEGRA_READ_AGE_BIT(2, age_bit, linear_age); + TEGRA_READ_AGE_BIT(1, age_bit, linear_age); + TEGRA_READ_AGE_BIT(0, age_bit, linear_age); + + /*Default Aug, 2012*/ + if (linear_age <= 0) + linear_age = 8; + + pr_info("TEGRA: Linear age: %d\n", linear_age); + + return linear_age; +} + unsigned long long tegra_chip_uid(void) { #if defined(CONFIG_ARCH_TEGRA_2x_SOC) diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h index 37f591af5695..0b04938988c7 100644 --- a/arch/arm/mach-tegra/fuse.h +++ b/arch/arm/mach-tegra/fuse.h @@ -36,6 +36,7 @@ int tegra_cpu_process_id(void); int tegra_core_process_id(void); int tegra_soc_speedo_id(void); void tegra_init_speedo_data(void); +int tegra_get_age(void); #ifndef CONFIG_ARCH_TEGRA_2x_SOC int tegra_package_id(void); diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c index 38f6ed0b317c..feb69a4621ed 100644 --- a/arch/arm/mach-tegra/tegra3_dvfs.c +++ b/arch/arm/mach-tegra/tegra3_dvfs.c @@ -21,6 +21,7 @@ #include #include #include +#include #include "clock.h" #include "dvfs.h" @@ -28,12 +29,16 @@ #include "board.h" #include "tegra3_emc.h" +#define CPU_MILLIVOLTS {\ + 750, 762, 775, 787, 800, 825, 837, 850, 862, 875, 887, 900, 912, 916, 925, 937, 950, 962, 975, 987, 1000, 1007, 1012, 1025, 1037, 1050, 1062, 1075, 1087, 1100, 1112, 1125, 1137, 1150, 1162, 1175, 1187, 1200, 1212, 1237}; + static bool tegra_dvfs_cpu_disabled; static bool tegra_dvfs_core_disabled; static struct dvfs *cpu_dvfs; -static const int cpu_millivolts[MAX_DVFS_FREQS] = { - 750, 762, 775, 787, 800, 825, 837, 850, 862, 875, 887, 900, 912, 916, 925, 937, 950, 962, 975, 987, 1000, 1007, 1012, 1025, 1037, 1050, 1062, 1075, 1087, 1100, 1112, 1125, 1137, 1150, 1162, 1175, 1187, 1200, 1212, 1237}; +static int cpu_millivolts[MAX_DVFS_FREQS] = CPU_MILLIVOLTS; + +static const int cpu_millivolts_aged[MAX_DVFS_FREQS] = CPU_MILLIVOLTS; static const unsigned int cpu_cold_offs_mhz[MAX_DVFS_FREQS] = { 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50}; @@ -54,7 +59,7 @@ static int cpu_below_core = VDD_CPU_BELOW_VDD_CORE; static struct dvfs_rail tegra3_dvfs_rail_vdd_cpu = { .reg_id = "vdd_cpu", .max_millivolts = 1250, - .min_millivolts = 750, + .min_millivolts = 725, .step = VDD_SAFE_STEP, .jmp_to_zero = true, }; @@ -632,6 +637,41 @@ static int __init get_core_nominal_mv_index(int speedo_id) return (i - 1); } +static void tegra_adjust_cpu_mvs(int mvs) +{ + int i; + + BUG_ON(ARRAY_SIZE(cpu_millivolts) != ARRAY_SIZE(cpu_millivolts_aged)); + + for (i = 0; i < ARRAY_SIZE(cpu_millivolts); i++) + cpu_millivolts[i] = cpu_millivolts_aged[i] - mvs; +} + +/** + * Adjust VDD_CPU to offset aging. + * 25mV for 1st year + * 12mV for 2nd and 3rd year + * 0mV for 4th year onwards + */ +void tegra_dvfs_age_cpu(int cur_linear_age) +{ + int chip_linear_age; + int chip_life; + chip_linear_age = tegra_get_age(); + chip_life = cur_linear_age - chip_linear_age; + + /*For T37 and AP37*/ + if (tegra_cpu_speedo_id() == 12 || tegra_cpu_speedo_id() == 13) { + if (chip_linear_age <= 0) { + return; + } else if (chip_life <= 12) { + tegra_adjust_cpu_mvs(25); + } else if (chip_life <= 36) { + tegra_adjust_cpu_mvs(13); + } + } +} + void __init tegra_soc_init_dvfs(void) { int cpu_speedo_id = tegra_cpu_speedo_id(); diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index 83d0e17b50c1..5771bfc9bdde 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -238,6 +239,96 @@ void tegra_twd_resume(struct tegra_twd_context *context) } #endif +#ifdef CONFIG_RTC_CLASS +/** + * has_readtime - check rtc device has readtime ability + * @dev: current device + * @name_ptr: name to be returned + * + * This helper function checks to see if the rtc device can be + * used for reading time + */ +static int has_readtime(struct device *dev, void *name_ptr) +{ + struct rtc_device *candidate = to_rtc_device(dev); + + if (!candidate->ops->read_time) + return 0; + + return 1; +} + +/** + * tegra_get_linear_age - helper function to return linear age + * from Jan 2012. + * + * @return + * 1 - Jan 2012, + * 2 - Feb 2012, + * ..... + * 13 - Jan 2013 + */ +int tegra_get_linear_age(void) +{ + struct rtc_time tm; + int year, month, linear_age; + struct rtc_device *rtc_dev = NULL; + const char *name = NULL; + int ret; + struct device *dev = NULL; + + linear_age = -1; + year = month = 0; + dev = class_find_device(rtc_class, NULL, &name, has_readtime); + + if (!dev) { + pr_err("DVFS: No device with readtime capability\n"); + goto done; + } + + name = dev_name(dev); + + pr_info("DVFS: Got RTC device name:%s\n", name); + + if (name) + rtc_dev = rtc_class_open((char *)name); + + if (!rtc_dev) { + pr_err("DVFS: No RTC device\n"); + goto error_dev; + } + + ret = rtc_read_time(rtc_dev, &tm); + + if (ret < 0) { + pr_err("DVFS: Can't read RTC time\n"); + goto error_rtc; + } + + year = tm.tm_year; + /*Normalize it to 2012*/ + year -= 112; + month = tm.tm_mon + 1; + + if (year >= 0) + linear_age = year * 12 + month; + +error_rtc: + rtc_class_close(rtc_dev); +error_dev: + put_device(dev); +done: + return linear_age; + +} + +#else +int tegra_get_linear_age() +{ + return -1; +} +#endif + static void __init tegra_init_timer(void) { struct clk *clk; diff --git a/arch/arm/mach-tegra/timer.h b/arch/arm/mach-tegra/timer.h index 4a91792f5d99..47628330dceb 100644 --- a/arch/arm/mach-tegra/timer.h +++ b/arch/arm/mach-tegra/timer.h @@ -45,11 +45,14 @@ struct tegra_twd_context { int tegra_twd_get_state(struct tegra_twd_context *context); void tegra_twd_suspend(struct tegra_twd_context *context); void tegra_twd_resume(struct tegra_twd_context *context); +int tegra_get_linear_age(void); #else static inline int tegra_twd_get_state(struct tegra_twd_context *context) { return -ENODEV; } static inline void tegra_twd_suspend(struct tegra_twd_context *context) {} static inline void tegra_twd_resume(struct tegra_twd_context *context) {} +static inline int tegra_get_linear_age() +{ return -1; } #endif #endif /* _MACH_TEGRA_TIMER_H_ */ -- cgit v1.2.3 From 63e2ffbb48e8ad9639e3f01442802a326114b530 Mon Sep 17 00:00:00 2001 From: Xiao Bo Zhao Date: Thu, 19 Jul 2012 19:56:28 -0700 Subject: ARM: tegra: Added sysfs knob that checks app profile support Currently app profile is only supported for AP37 hence added sysfs knob that uses cpu_speedo_id in order to check app profile support Bug 1003531 Change-Id: I12b9bc1700b3c925a1f1d51bb00584e7e5d6f0a3 Signed-off-by: Xiao Bo Zhao Reviewed-on: http://git-master/r/117852 Reviewed-by: Aleksandr Frid Reviewed-by: Bharat Nihalani Reviewed-by: Diwakar Tundlam --- arch/arm/mach-tegra/tegra3_speedo.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_speedo.c b/arch/arm/mach-tegra/tegra3_speedo.c index 78afb2804088..2889f656f47a 100644 --- a/arch/arm/mach-tegra/tegra3_speedo.c +++ b/arch/arm/mach-tegra/tegra3_speedo.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/tegra3_speedo.c * - * Copyright (c) 2011, NVIDIA Corporation. + * Copyright (c) 2011-2012, NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,6 +23,8 @@ #include #include #include +#include +#include #include "fuse.h" @@ -128,6 +130,11 @@ static int core_process_id; static int cpu_speedo_id; static int soc_speedo_id; static int package_id; +/* + * Only AP37 supports App Profile + * This informs user space of support without exposing cpu id's + */ +static int enable_app_profiles; static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp) { @@ -267,6 +274,7 @@ static void rev_sku_to_speedo_ids(int rev, int sku) cpu_speedo_id = 12; soc_speedo_id = 2; threshold_index = 9; + enable_app_profiles = 1; break; default: pr_err("Tegra3 Rev-A02: Reserved pkg: %d\n", @@ -560,3 +568,15 @@ int tegra_core_speedo_mv(void) BUG(); } } + +static int get_enable_app_profiles(char *val, const struct kernel_param *kp) +{ + return param_get_uint(val, kp); +} + +static struct kernel_param_ops tegra_profiles_ops = { + .get = get_enable_app_profiles, +}; + +module_param_cb(tegra_enable_app_profiles, + &tegra_profiles_ops, &enable_app_profiles, 0444); -- cgit v1.2.3 From 4bf13aec557cea6d36247b1a561321066fc9ed76 Mon Sep 17 00:00:00 2001 From: Xiao Bo Zhao Date: Mon, 9 Jul 2012 14:53:18 -0700 Subject: arm: tegra: Added sysfs knobs for RT thresholds Added different bias levels to RT and added the option to modify the bias level through sysfs knobs Bug 1003531 Reviewed-on: http://git-master/r/114271 Reviewed-by: Aleksandr Frid Reviewed-by: Automatic_Commit_Validation_User Tested-by: Xiao Bo Zhao Reviewed-by: Yu-Huan Hsu (cherry picked from commit 654bc674034f384d8826806fb443d4e9c67b9b3b) Change-Id: I2e647a65fb89926dd9f0b2ac3edc3dca8eb659a1 Reviewed-on: http://git-master/r/118201 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid Tested-by: Xiao Bo Zhao Reviewed-by: Diwakar Tundlam Reviewed-by: Sai Gurrappadi Reviewed-by: Bharat Nihalani --- arch/arm/mach-tegra/cpu-tegra3.c | 58 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 53 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/cpu-tegra3.c b/arch/arm/mach-tegra/cpu-tegra3.c index 051381297f6f..e833680617cf 100644 --- a/arch/arm/mach-tegra/cpu-tegra3.c +++ b/arch/arm/mach-tegra/cpu-tegra3.c @@ -3,7 +3,7 @@ * * CPU auto-hotplug for Tegra3 CPUs * - * Copyright (c) 2011-2012, NVIDIA Corporation. + * Copyright (c) 2011-2012, NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -189,10 +189,33 @@ enum { }; #define NR_FSHIFT 2 -static unsigned int nr_run_thresholds[] = { + +static unsigned int rt_profile_sel; + +/* avg run threads * 4 (e.g., 9 = 2.25 threads) */ + +static unsigned int rt_profile_default[] = { +/* 1, 2, 3, 4 - on-line cpus target */ + 5, 9, 10, UINT_MAX +}; + +static unsigned int rt_profile_1[] = { /* 1, 2, 3, 4 - on-line cpus target */ - 5, 9, 10, UINT_MAX /* avg run threads * 4 (e.g., 9 = 2.25 threads) */ + 8, 9, 10, UINT_MAX }; + +static unsigned int rt_profile_2[] = { +/* 1, 2, 3, 4 - on-line cpus target */ + 5, 13, 14, UINT_MAX +}; + +static unsigned int *rt_profiles[] = { + rt_profile_default, + rt_profile_1, + rt_profile_2 +}; + + static unsigned int nr_run_hysteresis = 2; /* 0.5 thread */ static unsigned int nr_run_last; @@ -216,8 +239,10 @@ static noinline int tegra_cpu_speed_balance(void) * TEGRA_CPU_SPEED_BIASED to keep CPU core composition unchanged * TEGRA_CPU_SPEED_SKEWED to remove CPU core off-line */ - for (nr_run = 1; nr_run < ARRAY_SIZE(nr_run_thresholds); nr_run++) { - unsigned int nr_threshold = nr_run_thresholds[nr_run - 1]; + + unsigned int *current_profile = rt_profiles[rt_profile_sel]; + for (nr_run = 1; nr_run < ARRAY_SIZE(rt_profile_default); nr_run++) { + unsigned int nr_threshold = current_profile[nr_run - 1]; if (nr_run_last <= nr_run) nr_threshold += nr_run_hysteresis; if (avg_nr_run <= (nr_threshold << (FSHIFT - NR_FSHIFT))) @@ -527,6 +552,25 @@ static const struct file_operations hp_stats_fops = { .release = single_release, }; +static int rt_bias_get(void *data, u64 *val) +{ + *val = rt_profile_sel; + return 0; +} +static int rt_bias_set(void *data, u64 val) +{ + if (val < ARRAY_SIZE(rt_profiles)) + rt_profile_sel = (u32)val; + + pr_debug("rt_profile_sel set to %d\nthresholds are now [%d, %d, %d]\n", + rt_profile_sel, + rt_profiles[rt_profile_sel][0], + rt_profiles[rt_profile_sel][1], + rt_profiles[rt_profile_sel][2]); + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(rt_bias_fops, rt_bias_get, rt_bias_set, "%llu\n"); + static int min_cpus_get(void *data, u64 *val) { *val = pm_qos_request(PM_QOS_MIN_ONLINE_CPUS); @@ -577,6 +621,10 @@ static int __init tegra_auto_hotplug_debug_init(void) "stats", S_IRUGO, hp_debugfs_root, NULL, &hp_stats_fops)) goto err_out; + if (!debugfs_create_file( + "core_bias", S_IRUGO, hp_debugfs_root, NULL, &rt_bias_fops)) + goto err_out; + return 0; err_out: -- cgit v1.2.3 From 074b6813735ca8bead4c91720a37a3c8aed6766f Mon Sep 17 00:00:00 2001 From: Xiao Bo Zhao Date: Tue, 24 Jul 2012 19:21:08 -0700 Subject: ARM: tegra: Add profile that disables runnable threads Add profile [0, 0, 0] which effectively disables runnable threads Bug 1003531 Change-Id: Ia45e533d5a6531b06c44c6d95f2f7cfd93cf976e Signed-off-by: Xiao Bo Zhao Reviewed-on: http://git-master/r/118219 Reviewed-by: Aleksandr Frid Reviewed-by: Bharat Nihalani Reviewed-by: Diwakar Tundlam --- arch/arm/mach-tegra/cpu-tegra3.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/cpu-tegra3.c b/arch/arm/mach-tegra/cpu-tegra3.c index e833680617cf..fc96dd6e14b2 100644 --- a/arch/arm/mach-tegra/cpu-tegra3.c +++ b/arch/arm/mach-tegra/cpu-tegra3.c @@ -209,10 +209,15 @@ static unsigned int rt_profile_2[] = { 5, 13, 14, UINT_MAX }; +static unsigned int rt_profile_off[] = { /* disables runable thread */ + 0, 0, 0, UINT_MAX +}; + static unsigned int *rt_profiles[] = { rt_profile_default, rt_profile_1, - rt_profile_2 + rt_profile_2, + rt_profile_off }; -- cgit v1.2.3 From 9913737d7ce69f3bd68e37e0ad22a9c2c5c50979 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Thu, 26 Jul 2012 15:21:09 +0530 Subject: ARM: tegra: dvfs: enable regulator before using it The dvfs system require the regulator for regulating the voltage. The regulator should be enable before using it to make sure the reference count enabling rail of that rail should be properly counted. Change-Id: Ib8b673ecb7939ac80f46bdf90ffec27b8f62df6b Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/118598 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/dvfs.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/dvfs.c b/arch/arm/mach-tegra/dvfs.c index 43f42cdf527d..c36b81d2c402 100644 --- a/arch/arm/mach-tegra/dvfs.c +++ b/arch/arm/mach-tegra/dvfs.c @@ -309,6 +309,13 @@ static int dvfs_rail_connect_to_regulator(struct dvfs_rail *rail) rail->reg = reg; } + v = regulator_enable(rail->reg); + if (v < 0) { + pr_err("tegra_dvfs: failed on enabling regulator %s\n, err %d", + rail->reg_id, v); + return v; + } + v = regulator_get_voltage(rail->reg); if (v < 0) { pr_err("tegra_dvfs: failed initial get %s voltage\n", -- cgit v1.2.3 From f2519724748766b0daef5d380a3a5414b77a437b Mon Sep 17 00:00:00 2001 From: Nitin Pai Date: Tue, 10 Jul 2012 19:01:34 +0530 Subject: arm: tegra: p1852: Fixes for I2S master mode Change the Drive strength of DAP1 for I2S to operate in both master and slave mode. Changed the Pull Up/Down mechanism for I2S4 to operate in master/slave mode. Bug 1009249 Signed-off-by: Nitin Pai Reviewed-on: http://git-master/r/114587 (cherry picked from commit 29ec5dfb81b823880f393bece5daf5396ef77629) Change-Id: I24a252370b993150a553c9f81fb44e6d8f86589a Reviewed-on: http://git-master/r/118251 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-p1852-pinmux.c | 24 ++++++++++++++---------- arch/arm/mach-tegra/board-p1852.c | 10 +++++++++- arch/arm/mach-tegra/board-p1852.h | 1 + 3 files changed, 24 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-p1852-pinmux.c b/arch/arm/mach-tegra/board-p1852-pinmux.c index 21f310b0ef16..bb28e278dc89 100644 --- a/arch/arm/mach-tegra/board-p1852-pinmux.c +++ b/arch/arm/mach-tegra/board-p1852-pinmux.c @@ -119,13 +119,8 @@ static __initdata struct tegra_drive_pingroup_config p1852_drive_pinmux[] = { SET_DRIVE(GMH, DISABLE, ENABLE, DIV_1, 0, 12, SLOWEST, SLOWEST), /* I2S/TDM */ -#ifdef CONFIG_TEGRA_MODS SET_DRIVE(DAP1, ENABLE, ENABLE, DIV_1, 20, 20, SLOWEST, SLOWEST), SET_DRIVE(DAP3, ENABLE, ENABLE, DIV_1, 20, 20, SLOWEST, SLOWEST), -#else - SET_DRIVE(DAP1, ENABLE, ENABLE, DIV_1, 3, 3, SLOWEST, SLOWEST), - SET_DRIVE(DAP3, ENABLE, ENABLE, DIV_1, 3, 3, SLOWEST, SLOWEST), -#endif /* SPI */ SET_DRIVE(UAD, DISABLE, ENABLE, DIV_1, 4, 1, SLOWEST, SLOWEST), @@ -184,6 +179,9 @@ static __initdata struct tegra_drive_pingroup_config p1852_drive_pinmux[] = { } +static __initdata struct tegra_pingroup_config p1852_pinmux_i2s4_master[] = { + DEFAULT_PINMUX(SDMMC4_CLK, NAND, PULL_UP, NORMAL, INPUT), +}; static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { /* SDMMC1 pinmux */ @@ -291,10 +289,10 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), /* DAP3 */ - LVPAD_PINMUX(SDMMC4_DAT4, I2S4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LVPAD_PINMUX(SDMMC4_DAT5, I2S4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LVPAD_PINMUX(SDMMC4_DAT6, I2S4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LVPAD_PINMUX(SDMMC4_DAT7, I2S4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + DEFAULT_PINMUX(SDMMC4_DAT4, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT5, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT6, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT7, I2S4, NORMAL, NORMAL, INPUT), /* NOR pinmux */ DEFAULT_PINMUX(GMI_AD0, GMI, NORMAL, NORMAL, INPUT), @@ -427,7 +425,7 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, NORMAL, NORMAL, INPUT), - LVPAD_PINMUX(SDMMC4_CLK, NAND, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + DEFAULT_PINMUX(SDMMC4_CLK, NAND, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(SDMMC3_DAT3, RSVD0, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(VI_D1, RSVD1, NORMAL, NORMAL, INPUT), @@ -445,6 +443,12 @@ int __init p1852_pinmux_init(void) return 0; } +int p1852_pinmux_set_i2s4_master(void) +{ + tegra_pinmux_config_table(p1852_pinmux_i2s4_master, + ARRAY_SIZE(p1852_pinmux_i2s4_master)); + return 0; +} #define GPIO_INIT_PIN_MODE(_gpio, _is_input, _value) \ { \ .gpio_nr = _gpio, \ diff --git a/arch/arm/mach-tegra/board-p1852.c b/arch/arm/mach-tegra/board-p1852.c index b0a593f95121..e9cf1440b01d 100644 --- a/arch/arm/mach-tegra/board-p1852.c +++ b/arch/arm/mach-tegra/board-p1852.c @@ -198,7 +198,6 @@ static void __init p1852_uart_init(void) platform_add_devices(p1852_uart_devices, ARRAY_SIZE(p1852_uart_devices)); } - #if defined(CONFIG_TEGRA_P1852_TDM) static struct tegra_p1852_platform_data p1852_audio_tdm_pdata = { .codec_info[0] = { @@ -241,6 +240,7 @@ static struct tegra_p1852_platform_data p1852_audio_i2s_pdata = { .name = "tegra-i2s-1", .pcm_driver = "tegra-pcm-audio", .i2s_format = format_i2s, + /* Defines whether the Audio codec chip is master or slave */ .master = 1, }, .codec_info[1] = { @@ -250,6 +250,7 @@ static struct tegra_p1852_platform_data p1852_audio_i2s_pdata = { .name = "tegra-i2s-2", .pcm_driver = "tegra-pcm-audio", .i2s_format = format_i2s, + /* Defines whether the Audio codec chip is master or slave */ .master = 0, }, }; @@ -277,6 +278,8 @@ static struct platform_device tegra_snd_p1852 = { static void p1852_i2s_audio_init(void) { + struct tegra_p1852_platform_data *pdata; + platform_device_register(&tegra_pcm_device); platform_device_register(&tegra_tdm_pcm_device); platform_device_register(&generic_codec_1); @@ -285,6 +288,11 @@ static void p1852_i2s_audio_init(void) platform_device_register(&tegra_i2s_device4); platform_device_register(&tegra_ahub_device); platform_device_register(&tegra_snd_p1852); + + /* Change pinmux of I2S4 for master mode */ + pdata = tegra_snd_p1852.dev.platform_data; + if (!pdata->codec_info[1].master) + p1852_pinmux_set_i2s4_master(); } diff --git a/arch/arm/mach-tegra/board-p1852.h b/arch/arm/mach-tegra/board-p1852.h index 529bd3840e63..7de6a6b358e6 100644 --- a/arch/arm/mach-tegra/board-p1852.h +++ b/arch/arm/mach-tegra/board-p1852.h @@ -100,6 +100,7 @@ int p1852_sdhci_init(void); int p1852_pinmux_init(void); +int p1852_pinmux_set_i2s4_master(void); int p1852_panel_init(void); int p1852_gpio_init(void); int p1852_pins_state_init(void); -- cgit v1.2.3 From 830b927faaf4236217f42c9e1f22d9147869c30b Mon Sep 17 00:00:00 2001 From: Vinod Atyam Date: Thu, 26 Jul 2012 14:51:33 +0530 Subject: ARM: tegra: usb_phy: Fix remotewakeup resume code 1) After remote wakeup resume code is not waiting until RESUME and SUSPEND bit cleared. Instead it is waiting for RESUME bit to get set. This is updated properly now. 2) During resume, no need to depend on port speed to take HSIC in high speed. Bug 1019619 Change-Id: I3d06255da65045bdf5c6a4deb10a3c6f96aef661 Signed-off-by: Vinod Atyam Reviewed-on: http://git-master/r/118582 Reviewed-by: Rohan Somvanshi Tested-by: Rohan Somvanshi --- arch/arm/mach-tegra/tegra3_usb_phy.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index 171e2ec91ada..b47166387aa2 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -988,7 +988,8 @@ static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy) /* Program the field PTC based on the saved speed mode */ val = readl(base + USB_PORTSC); val &= ~USB_PORTSC_PTC(~0); - if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH) + if ((phy->port_speed == USB_PHY_PORT_SPEED_HIGH) || + (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC)) val |= USB_PORTSC_PTC(5); else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL) val |= USB_PORTSC_PTC(6); @@ -2019,7 +2020,7 @@ static void uhsic_phy_restore_end(struct tegra_usb_phy *phy) unsigned long val; void __iomem *base = phy->regs; - int wait_time_us = 3000; /* FPR should be set by this time */ + int wait_time_us = 25000; /* FPR should be set by this time */ DBG("%s(%d)\n", __func__, __LINE__); @@ -2035,7 +2036,8 @@ static void uhsic_phy_restore_end(struct tegra_usb_phy *phy) return; } wait_time_us--; - } while (!(val & USB_PORTSC_RESUME)); + } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP)); + /* wait for 25 ms to port resume complete */ msleep(25); /* disable PMC master control */ -- cgit v1.2.3 From b4e9ece3b32afea9ca8d761c285fc9bc4c70b967 Mon Sep 17 00:00:00 2001 From: Rakesh Bodla Date: Sat, 28 Jul 2012 00:08:08 +0530 Subject: ARM: tegra: usb: free allocated resources in error Free allocated resources at approriate error conditions. Change-Id: I548f6ac7ad65eae93f9f49b0a5fa7ffff9685241 Signed-off-by: Rakesh Bodla Reviewed-on: http://git-master/r/119039 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty --- arch/arm/mach-tegra/usb_phy.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c index 4cc80e68d89c..00a44dd2536c 100644 --- a/arch/arm/mach-tegra/usb_phy.c +++ b/arch/arm/mach-tegra/usb_phy.c @@ -173,7 +173,8 @@ static int tegra_usb_phy_get_clocks(struct tegra_usb_phy *phy) phy->pllu_clk = clk_get_sys(NULL, "pll_u"); if (IS_ERR(phy->pllu_clk)) { ERR("inst:[%d] Can't get pllu_clk clock\n", phy->inst); - return PTR_ERR(phy->pllu_clk); + err = PTR_ERR(phy->pllu_clk); + goto fail_pll; } clk_enable(phy->pllu_clk); @@ -221,6 +222,7 @@ fail_ctrlr_clk: clk_disable(phy->pllu_clk); clk_put(phy->pllu_clk); +fail_pll: return err; } @@ -263,13 +265,15 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { ERR("inst:[%d] failed to get I/O memory\n", phy->inst); - return ERR_PTR(-ENXIO); + err = -ENXIO; + goto fail_io; } phy->regs = ioremap(res->start, resource_size(res)); if (!phy->regs) { ERR("inst:[%d] Failed to remap I/O memory\n", phy->inst); - return ERR_PTR(-ENOMEM); + err = -ENOMEM; + goto fail_io; } phy->vdd_reg = regulator_get(NULL, "avdd_usb"); @@ -372,6 +376,9 @@ fail_init: fail_clk: regulator_put(phy->vdd_reg); iounmap(phy->regs); +fail_io: + kfree(phy); + return ERR_PTR(err); } @@ -410,8 +417,10 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy) regulator_put(phy->vdd_reg); } - tegra_usb_phy_release_clocks(phy); + + kfree(phy->pdata); + kfree(phy); } irqreturn_t tegra_usb_phy_irq(struct tegra_usb_phy *phy) -- cgit v1.2.3 From 2c752ad14af6316048bf8f06a170445f8e5f01a4 Mon Sep 17 00:00:00 2001 From: Rakesh Bodla Date: Mon, 30 Jul 2012 15:16:18 +0530 Subject: ARM: tegra: usb: keep usb vdd regulator on Adding the conditions during which USB vdd regulator should be kept ON. Bug 1024425 Bug 1012078 Bug 1018538 Change-Id: I3319c91ecc02891ea4467f73be2b84a3817dab36 Signed-off-by: Rakesh Bodla Reviewed-on: http://git-master/r/119279 Reviewed-by: Rohan Somvanshi Tested-by: Rohan Somvanshi --- arch/arm/mach-tegra/usb_phy.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c index 00a44dd2536c..80a3337e58fe 100644 --- a/arch/arm/mach-tegra/usb_phy.c +++ b/arch/arm/mach-tegra/usb_phy.c @@ -136,7 +136,7 @@ static irqreturn_t usb_phy_dev_vbus_pmu_irq_thr(int irq, void *pdata) if (phy->vdd_reg && !phy->vdd_reg_on) { regulator_enable(phy->vdd_reg); - phy->vdd_reg_on = 1; + phy->vdd_reg_on = true; /* * Optimal time to get the regulator turned on * before detecting vbus interrupt. @@ -469,25 +469,30 @@ int tegra_usb_phy_power_off(struct tegra_usb_phy *phy) clk_disable(phy->sys_clk); if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) { if (!phy->pdata->u_data.host.hot_plug && - !phy->pdata->u_data.host.remote_wakeup_supported) + !phy->pdata->u_data.host.remote_wakeup_supported) { clk_disable(phy->ctrlr_clk); + phy->ctrl_clk_on = false; + if (phy->vdd_reg && phy->vdd_reg_on) { + regulator_disable(phy->vdd_reg); + phy->vdd_reg_on = false; + } + } } else { - /* In device mode clock is turned on by pmu irq handler - * if pmu irq is not available clocks will not be turned off/on + /* In device mode clock regulator/clocks will be turned off + * only if pmu interrupt is present on the board and host mode + * support through OTG is supported on the board. */ - if (phy->pdata->u_data.dev.vbus_pmu_irq) { + if (phy->pdata->u_data.dev.vbus_pmu_irq && + phy->pdata->builtin_host_disabled) { clk_disable(phy->ctrlr_clk); phy->ctrl_clk_on = false; + if (phy->vdd_reg && phy->vdd_reg_on) { + regulator_disable(phy->vdd_reg); + phy->vdd_reg_on = false; + } } } - if (phy->vdd_reg && phy->vdd_reg_on) - if (phy->pdata->has_hostpc || - phy->pdata->builtin_host_disabled) { - regulator_disable(phy->vdd_reg); - phy->vdd_reg_on = false; - } - phy->phy_power_on = false; return err; -- cgit v1.2.3 From 1339ef85328052f13af1fcb6d16134949591c480 Mon Sep 17 00:00:00 2001 From: Bitan Biswas Date: Fri, 27 Jul 2012 16:09:39 +0530 Subject: ARM: tegra: wifi dpd control for reset Wifi On/Off needs to toggle GPIO pins under SDMMC that could be in IO DPD mode. bug 1021526 Change-Id: If514059372d2242c6f6512b30534536cbff455dd Signed-off-by: Bitan Biswas Reviewed-on: http://git-master/r/118940 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Pavan Kunapuli Tested-by: Pavan Kunapuli --- arch/arm/mach-tegra/board-cardhu-sdhci.c | 21 +++++++++++++++++++++ arch/arm/mach-tegra/board-enterprise-sdhci.c | 21 +++++++++++++++++++++ arch/arm/mach-tegra/board-kai-sdhci.c | 19 +++++++++++++++++++ 3 files changed, 61 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-sdhci.c b/arch/arm/mach-tegra/board-cardhu-sdhci.c index d8be9fe6747f..df7177fb34a7 100644 --- a/arch/arm/mach-tegra/board-cardhu-sdhci.c +++ b/arch/arm/mach-tegra/board-cardhu-sdhci.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "gpio-names.h" #include "board.h" @@ -251,11 +252,31 @@ static int cardhu_wifi_set_carddetect(int val) static int cardhu_wifi_power(int on) { + struct tegra_io_dpd *sd_dpd; + pr_debug("%s: %d\n", __func__, on); + + /* + * FIXME : we need to revisit IO DPD code + * on how should multiple pins under DPD get controlled + * + * cardhu GPIO WLAN enable is part of SDMMC3 pin group + */ + sd_dpd = tegra_io_dpd_get(&tegra_sdhci_device2.dev); + if (sd_dpd) { + mutex_lock(&sd_dpd->delay_lock); + tegra_io_dpd_disable(sd_dpd); + mutex_unlock(&sd_dpd->delay_lock); + } gpio_set_value(CARDHU_WLAN_PWR, on); mdelay(100); gpio_set_value(CARDHU_WLAN_RST, on); mdelay(200); + if (sd_dpd) { + mutex_lock(&sd_dpd->delay_lock); + tegra_io_dpd_enable(sd_dpd); + mutex_unlock(&sd_dpd->delay_lock); + } return 0; } diff --git a/arch/arm/mach-tegra/board-enterprise-sdhci.c b/arch/arm/mach-tegra/board-enterprise-sdhci.c index 7a5632601fe6..8032f8105bed 100644 --- a/arch/arm/mach-tegra/board-enterprise-sdhci.c +++ b/arch/arm/mach-tegra/board-enterprise-sdhci.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "gpio-names.h" #include "board.h" @@ -221,11 +222,31 @@ static int enterprise_wifi_set_carddetect(int val) static int enterprise_wifi_power(int on) { + struct tegra_io_dpd *sd_dpd; + pr_debug("%s: %d\n", __func__, on); + + /* + * FIXME : we need to revisit IO DPD code + * on how should multiple pins under DPD get controlled + * + * enterprise GPIO WLAN enable is part of SDMMC1 pin group + */ + sd_dpd = tegra_io_dpd_get(&tegra_sdhci_device0.dev); + if (sd_dpd) { + mutex_lock(&sd_dpd->delay_lock); + tegra_io_dpd_disable(sd_dpd); + mutex_unlock(&sd_dpd->delay_lock); + } gpio_set_value(ENTERPRISE_WLAN_PWR, on); mdelay(100); gpio_set_value(ENTERPRISE_WLAN_RST, on); mdelay(200); + if (sd_dpd) { + mutex_lock(&sd_dpd->delay_lock); + tegra_io_dpd_enable(sd_dpd); + mutex_unlock(&sd_dpd->delay_lock); + } return 0; } diff --git a/arch/arm/mach-tegra/board-kai-sdhci.c b/arch/arm/mach-tegra/board-kai-sdhci.c index 0fa39ccf475d..70ba7bcdb202 100644 --- a/arch/arm/mach-tegra/board-kai-sdhci.c +++ b/arch/arm/mach-tegra/board-kai-sdhci.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "gpio-names.h" #include "board.h" @@ -202,8 +203,21 @@ static int kai_wifi_set_carddetect(int val) static int kai_wifi_power(int power_on) { + struct tegra_io_dpd *sd_dpd; pr_err("Powering %s wifi\n", (power_on ? "on" : "off")); + /* + * FIXME : we need to revisit IO DPD code + * on how should multiple pins under DPD get controlled + * + * kai GPIO WLAN enable is part of SDMMC3 pin group + */ + sd_dpd = tegra_io_dpd_get(&tegra_sdhci_device2.dev); + if (sd_dpd) { + mutex_lock(&sd_dpd->delay_lock); + tegra_io_dpd_disable(sd_dpd); + mutex_unlock(&sd_dpd->delay_lock); + } if (power_on) { gpio_set_value(KAI_WLAN_EN, 1); mdelay(15); @@ -214,6 +228,11 @@ static int kai_wifi_power(int power_on) } else { gpio_set_value(KAI_WLAN_EN, 0); } + if (sd_dpd) { + mutex_lock(&sd_dpd->delay_lock); + tegra_io_dpd_enable(sd_dpd); + mutex_unlock(&sd_dpd->delay_lock); + } return 0; } -- cgit v1.2.3 From 5791cf051fa1c520c29100b5c76d38d52ac3fd41 Mon Sep 17 00:00:00 2001 From: Vinayak Pane Date: Fri, 20 Jul 2012 19:02:29 -0700 Subject: arm: tegra: usb_phy: add close operation for hsic hsic phy_power_off keeps hsic bus in suspend state through PMC interface. The bus should go in reset state at phy_close otherwise the connected device will not enumerate after ehci-remove. Bug 1003141 Change-Id: Ifa91d06a3c10221e74de67c68ea1f930d843d19f Signed-off-by: Vinayak Pane --- arch/arm/mach-tegra/tegra3_usb_phy.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index b47166387aa2..f164b409d29b 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -1810,6 +1810,31 @@ static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy) mdelay(1); } +static void uhsic_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy) +{ + unsigned long val; + void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); + + DBG("%s:%d\n", __func__, __LINE__); + + /* turn off pad detectors for HSIC*/ + val = readl(pmc_base + PMC_USB_AO); + val |= (HSIC_RESERVED_P0 | STROBE_VAL_PD_P0 | DATA_VAL_PD_P0); + writel(val, pmc_base + PMC_USB_AO); + + /* enable pull downs on HSIC PMC */ + val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B | + UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C | + UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D; + writel(val, pmc_base + PMC_SLEEPWALK_UHSIC); + + /* Turn over pad configuration to PMC */ + val = readl(pmc_base + PMC_SLEEP_CFG); + val &= ~UHSIC_WAKE_VAL_P0(~0); + val |= UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) | UHSIC_MASTER_ENABLE_P0; + writel(val, pmc_base + PMC_SLEEP_CFG); +} + static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy) { unsigned long val; @@ -2142,6 +2167,9 @@ static void uhsic_phy_close(struct tegra_usb_phy *phy) { int ret; + DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); + uhsic_powerdown_pmc_wake_detect(phy); + ret = hsic_rail_disable(phy); if (ret < 0) pr_err("%s avdd_hsic could not be disabled\n", __func__); -- cgit v1.2.3 From 31ff5d8c3831dccb12a9c6841cd04c81aafed2b5 Mon Sep 17 00:00:00 2001 From: Penny Chiu Date: Wed, 25 Jul 2012 15:35:25 +0800 Subject: arm: tegra: usb_phy: Separate the consumer supply Add usb host controller device names for avdd_usb consumer supply. This change will make all usb host controller devices have separate regulator debugfs. Bug 946361 Change-Id: I8f2a49bffc4623eac2e3f71333b602fb7a6caf7d Signed-off-by: Penny Chiu --- arch/arm/mach-tegra/board-cardhu-power.c | 5 ++++- arch/arm/mach-tegra/usb_phy.c | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-power.c b/arch/arm/mach-tegra/board-cardhu-power.c index ace103f5ba6b..ae355a3a5abd 100644 --- a/arch/arm/mach-tegra/board-cardhu-power.c +++ b/arch/arm/mach-tegra/board-cardhu-power.c @@ -538,7 +538,10 @@ static struct regulator_consumer_supply fixed_reg_en_3v3_sys_supply[] = { REGULATOR_SUPPLY("hvdd_pex_pmu", NULL), REGULATOR_SUPPLY("avdd_hdmi", NULL), REGULATOR_SUPPLY("vpp_fuse", NULL), - REGULATOR_SUPPLY("avdd_usb", NULL), + REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"), + REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"), + REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"), + REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"), REGULATOR_SUPPLY("vdd_ddr_rx", NULL), REGULATOR_SUPPLY("vcore_nand", NULL), REGULATOR_SUPPLY("hvdd_sata", NULL), diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c index 80a3337e58fe..aed8ec2bf9d8 100644 --- a/arch/arm/mach-tegra/usb_phy.c +++ b/arch/arm/mach-tegra/usb_phy.c @@ -276,7 +276,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct platform_device *pdev) goto fail_io; } - phy->vdd_reg = regulator_get(NULL, "avdd_usb"); + phy->vdd_reg = regulator_get(&pdev->dev, "avdd_usb"); if (IS_ERR_OR_NULL(phy->vdd_reg)) { ERR("inst:[%d] couldn't get regulator avdd_usb: %ld\n", phy->inst, PTR_ERR(phy->vdd_reg)); -- cgit v1.2.3 From 1c3b7b8eeef8a197b0a9bb5703722e8778569c98 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Thu, 26 Jul 2012 17:09:56 +0530 Subject: ARM: tegra: enterprise:all configuration through regulator init data In place of using the separate platform data for configuring regualtor's init states, pass all information through regulator init data only. Change-Id: I76f05bfa0da1b8867e7d4d5578ed9067eed6a882 Signed-off-by: Laxman Dewangan --- arch/arm/mach-tegra/board-enterprise-power.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index eb9f1d53dea4..37d4576feb96 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -272,7 +272,7 @@ TPS_PDATA_INIT(smps4, a02, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PRE TPS_PDATA_INIT(smps4, a03, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); TPS_PDATA_INIT(ldo1, a02, 1000, 3300, tps80031_rails(VIO), 0, 0, 0, -1, 0, 0, 0, 0, 0); TPS_PDATA_INIT(ldo1, a03, 1000, 3300, tps80031_rails(VIO), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldo2, common, 1000, 3300, 0, 1, 1, 1, 1000, 1, 1, 0, 0, 0); +TPS_PDATA_INIT(ldo2, common, 1000, 1000, 0, 1, 1, 1, -1, 0, 0, 0, 0, 0); TPS_PDATA_INIT(ldo3, common, 1000, 3300, tps80031_rails(VIO), 0, 0, 0, -1, 0, 0, 0, PWR_OFF_ON_SLEEP, 0); TPS_PDATA_INIT(ldo4, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); TPS_PDATA_INIT(ldo4, a03, 1000, 3300, tps80031_rails(VIO), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); @@ -286,7 +286,7 @@ TPS_PDATA_INIT(ldoln, a03, 1000, 3300, tps80031_rails(VIO), 0, 0, 0, -1, 0, 0, 0 TPS_PDATA_INIT(ldousb, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, USBLDO_INPUT_VSYS, PWR_OFF_ON_SLEEP, 0); TPS_PDATA_INIT(ldousb, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, USBLDO_INPUT_VSYS, PWR_REQ_INPUT_PREQ1, 0); TPS_PDATA_INIT(vana, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(vana, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 1, 0, PWR_OFF_ON_SLEEP, 0); +TPS_PDATA_INIT(vana, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_OFF_ON_SLEEP, 0); TPS_PDATA_INIT(vbus, common, 0, 5000, 0, 0, 0, 0, -1, 0, 0, (VBUS_SW_ONLY | VBUS_DISCHRG_EN_PDN), 0, 100000); static struct tps80031_rtc_platform_data rtc_data = { -- cgit v1.2.3 From 5bc340e408aa3f009651735c71f3c97676fbe79f Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 25 Jul 2012 13:27:22 +0530 Subject: regulator: tps80031: rename regulator-name enums Renaming the regulator name from TPS80031_ID_* to TPS80031_REGULATOR_* for better readability. Change-Id: I6176cb213d23e44061549fd1e81306756a324523 Signed-off-by: Laxman Dewangan --- arch/arm/mach-tegra/board-enterprise-power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index 37d4576feb96..4698c75b56b6 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -340,7 +340,7 @@ static struct tps80031_bg_platform_data battery_gauge_data = { #define TPS_REG(_id, _data, _sname) \ { \ - .id = TPS80031_ID_##_id, \ + .id = TPS80031_REGULATOR_##_id, \ .name = "tps80031-regulator", \ .platform_data = &pdata_##_data##_##_sname, \ } -- cgit v1.2.3 From 524a9932de822961cd6fda49560af637bf8e9722 Mon Sep 17 00:00:00 2001 From: Amlan Kundu Date: Mon, 30 Jul 2012 12:35:17 +0530 Subject: arm: tegra: p1852: Add android defconfig for p1852 bug 1025348 Change-Id: I0206c273af45b51fdd67e94c80f915a33950a929 Signed-off-by: Amlan Kundu --- arch/arm/configs/tegra_p1852_android_defconfig | 339 +++++++++++++++++++++++++ 1 file changed, 339 insertions(+) create mode 100644 arch/arm/configs/tegra_p1852_android_defconfig (limited to 'arch') diff --git a/arch/arm/configs/tegra_p1852_android_defconfig b/arch/arm/configs/tegra_p1852_android_defconfig new file mode 100644 index 000000000000..4550c9ec6405 --- /dev/null +++ b/arch/arm/configs/tegra_p1852_android_defconfig @@ -0,0 +1,339 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_CROSS_COMPILE="arm-eabi-" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_PANIC_TIMEOUT=10 +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_ELF_CORE is not set +CONFIG_ASHMEM=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_TEGRA=y +CONFIG_GPIO_PCA953X=y +CONFIG_ARCH_TEGRA_3x_SOC=y +CONFIG_MACH_P1852=y +CONFIG_TEGRA_DEBUG_UARTB=y +CONFIG_TEGRA_PWM=y +# CONFIG_TEGRA_CPU_DVFS is not set +CONFIG_TEGRA_CLOCK_DEBUG_WRITE=y +CONFIG_USB_HOTPLUG=y +CONFIG_ARM_ERRATA_743622=y +CONFIG_ARM_ERRATA_751472=y +CONFIG_ARM_ERRATA_752520=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_SMP=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_INET_ESP=y +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_NETFILTER=y +CONFIG_NETFILTER_NETLINK_LOG=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NETFILTER_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_LOG=y +CONFIG_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_U32=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_ACT_GACT=y +CONFIG_NET_ACT_MIRRED=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_NAND_TEGRA=y +CONFIG_MTD_NAND=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_MISC_DEVICES=y +CONFIG_AD525X_DPOT=y +CONFIG_AD525X_DPOT_I2C=y +CONFIG_APDS9802ALS=y +CONFIG_SENSORS_NCT1008=y +CONFIG_UID_STAT=y +CONFIG_BCM4329_RFKILL=y +CONFIG_TEGRA_CRYPTO_DEV=y +CONFIG_MAX1749_VIBRATOR=y +CONFIG_EEPROM_AT24=y +CONFIG_TI_ST=y +CONFIG_ST_GPS=m +CONFIG_MPU_SENSORS_TIMERIRQ=y +CONFIG_MPU_SENSORS_MPU3050=m +CONFIG_MPU_SENSORS_MPU6050B1=m +CONFIG_MPU_SENSORS_KXTF9=m +CONFIG_MPU_SENSORS_MPU6050_ACCEL=m +CONFIG_MPU_SENSORS_AK8963=m +CONFIG_MPU_SENSORS_AK8975=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_DM_UEVENT=y +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +CONFIG_USB_USBNET=y +CONFIG_USB_NET_SMSC75XX=y +CONFIG_USB_NET_SMSC95XX=y +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +CONFIG_USB_NET_RAW_IP=y +CONFIG_PPP=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=y +CONFIG_PPP_SYNC_TTY=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_MPPE=y +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_TEGRA=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_TEGRA=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_TEGRA=y +CONFIG_SPI=y +CONFIG_SPI_TEGRA=y +CONFIG_SPI_SLAVE_TEGRA=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_PDA_POWER=y +CONFIG_BATTERY_BQ20Z75=y +CONFIG_BATTERY_BQ27x00=y +CONFIG_CHARGER_SMB349=y +CONFIG_BATTERY_MAX17048=y +CONFIG_CHARGER_GPIO=y +CONFIG_SENSORS_TEGRA_TSENSOR=y +CONFIG_SENSORS_INA219=y +CONFIG_THERMAL=y +CONFIG_MFD_TPS6586X=y +CONFIG_MFD_TPS65910=y +CONFIG_MFD_MAX77663=y +CONFIG_MFD_TPS6591X=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y +CONFIG_REGULATOR_TPS6591X=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_VIDEO_DEV=y +# CONFIG_TEGRA_AVP is not set +# CONFIG_TEGRA_MEDIASERVER is not set +CONFIG_TEGRA_NVAVP=y +# CONFIG_VGA_ARB is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_FB=y +CONFIG_TEGRA_GRHOST=y +CONFIG_TEGRA_DC=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_TEGRA=y +CONFIG_SND_SOC_TEGRA_P1852=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ACM=y +CONFIG_USB_WDM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_LIBUSUAL=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SERIAL_OPTION=y +CONFIG_USB_SERIAL_BASEBAND=m +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_TEGRA=y +CONFIG_USB_G_ANDROID=y +CONFIG_USB_TEGRA_OTG=y +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_EMBEDDED_SDIO=y +CONFIG_MMC_PARANOID_SD_INIT=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +CONFIG_MMC_BLOCK_DEFERRED_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_TEGRA=y +CONFIG_SWITCH=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_TEGRA=y +CONFIG_STAGING=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_RAM_CONSOLE=y +CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_IIO=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +# CONFIG_DNOTIFY is not set +CONFIG_FUSE_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_VM=y +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_TWOFISH=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set -- cgit v1.2.3 From 966ba0797dde76a3c7d91f6f2653b382c825bf3d Mon Sep 17 00:00:00 2001 From: Amlan Kundu Date: Mon, 16 Jul 2012 15:05:23 +0530 Subject: arm: tegra: p1852: Add USB_G_ANDROID support + require for android adb bug 1005255 Change-Id: If2c8d197f987ddd43a9b6a6cc602ac1e2f4ae2f8 Signed-off-by: Amlan Kundu Reviewed-on: http://git-master/r/114562 (cherry-picked from 6640721b05059f03325abadfebe2f08026a41a88) --- arch/arm/mach-tegra/board-p1852.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-p1852.c b/arch/arm/mach-tegra/board-p1852.c index e9cf1440b01d..229344799112 100644 --- a/arch/arm/mach-tegra/board-p1852.c +++ b/arch/arm/mach-tegra/board-p1852.c @@ -479,6 +479,32 @@ static int __init p1852_touch_init(void) #endif // CONFIG_TOUCHSCREEN_ATMEL_MXT +#if defined(CONFIG_USB_G_ANDROID) +static struct tegra_usb_platform_data tegra_udc_pdata = { + .port_otg = false, + .has_hostpc = true, + .phy_intf = TEGRA_USB_PHY_INTF_UTMI, + .op_mode = TEGRA_USB_OPMODE_DEVICE, + .u_data.dev = { + .vbus_pmu_irq = 0, + .vbus_gpio = -1, + .charging_supported = false, + .remote_wakeup_supported = false, + }, + .u_cfg.utmi = { + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .elastic_limit = 16, + .term_range_adj = 6, + .xcvr_setup = 63, + .xcvr_setup_offset = 6, + .xcvr_use_fuses = 1, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + .xcvr_use_lsb = 1, + }, +}; +#else static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = { .port_otg = false, .has_hostpc = true, @@ -504,6 +530,7 @@ static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = { .xcvr_use_lsb = 1, }, }; +#endif static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = { .port_otg = false, @@ -559,9 +586,16 @@ static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = { static void p1852_usb_init(void) { + /* Need to parse sku info to decide host/device mode */ + + /* G_ANDROID require device mode */ +#if defined(CONFIG_USB_G_ANDROID) + tegra_udc_device.dev.platform_data = &tegra_udc_pdata; + platform_device_register(&tegra_udc_device); +#else tegra_ehci1_device.dev.platform_data = &tegra_ehci1_utmi_pdata; platform_device_register(&tegra_ehci1_device); - +#endif tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata; platform_device_register(&tegra_ehci2_device); -- cgit v1.2.3 From eb290c5b0d896832a409fa64f9f2d9ddef353a39 Mon Sep 17 00:00:00 2001 From: Vishal Singh Date: Thu, 19 Jul 2012 19:20:49 +0530 Subject: ARM: configs: tegra: enable ISO9660 fs Enabling ISO9660 file system (and its JOLIET extension) support in kernel. Bug 1018276. Change-Id: I1acaf5dc3a571b75a81860485d3c668ea82d822c Signed-off-by: Vishal Singh Reviewed-on: http://git-master/r/117372 Tested-by: Vishal Singh Reviewed-by: Sandeep Trasi (cherry picked from commit c35638147c3fa9d56f124b4d6c0435aadad53d97) --- arch/arm/configs/tegra_p1852_gnu_linux_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/tegra_p1852_gnu_linux_defconfig b/arch/arm/configs/tegra_p1852_gnu_linux_defconfig index e6b401c23e2b..7e4f4ab3e750 100644 --- a/arch/arm/configs/tegra_p1852_gnu_linux_defconfig +++ b/arch/arm/configs/tegra_p1852_gnu_linux_defconfig @@ -192,6 +192,8 @@ CONFIG_EXT3_FS_SECURITY=y CONFIG_EXT4_FS=y # CONFIG_DNOTIFY is not set CONFIG_FUSE_FS=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y # CONFIG_MISC_FILESYSTEMS is not set -- cgit v1.2.3 From 807b6ac9fe205ece24ba7b27935c6bb133573c36 Mon Sep 17 00:00:00 2001 From: Bitan Biswas Date: Mon, 30 Jul 2012 21:32:05 +0530 Subject: ARM: tegra: cardhu: WAKE19 disable We see repeated WAKE19 (VBUS) resumes when USB device cable is connected for E1186/E1187 cardhu boards. Hence, this change disables the WAKE19 to prevent the problem bug 1025421 Change-Id: If7ebf68ebf257a9bea58652042d77f0c19f40366 Signed-off-by: Bitan Biswas --- arch/arm/mach-tegra/board-cardhu-power.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-power.c b/arch/arm/mach-tegra/board-cardhu-power.c index ae355a3a5abd..4f96c5cc5d05 100644 --- a/arch/arm/mach-tegra/board-cardhu-power.c +++ b/arch/arm/mach-tegra/board-cardhu-power.c @@ -1161,25 +1161,30 @@ int __init cardhu_suspend_init(void) if (board_info.fab == BOARD_FAB_A03) cardhu_suspend_data.corereq_high = true; if (board_info.fab < BOARD_FAB_A03) - /* post E1291-A02 revisions WAKE19/USB1-VBUS wake supported */ + /* post E1291-A02 revisions VBUS wake supported */ tegra_disable_wake_source(TEGRA_WAKE_USB1_VBUS); break; case BOARD_E1198: if (board_info.fab < BOARD_FAB_A02) - /* post E1198-A01 revisions WAKE19/USB1-VBUS wake supported */ + /* post E1198-A01 revisions VBUS wake supported */ tegra_disable_wake_source(TEGRA_WAKE_USB1_VBUS); break; case BOARD_PM269: case BOARD_PM305: case BOARD_PM311: break; - case BOARD_E1187: - case BOARD_E1186: case BOARD_E1256: case BOARD_E1257: cardhu_suspend_data.cpu_timer = 5000; cardhu_suspend_data.cpu_off_timer = 5000; break; + case BOARD_E1187: + case BOARD_E1186: + /* VBUS repeated wakeup seen on older E1186 boards */ + tegra_disable_wake_source(TEGRA_WAKE_USB1_VBUS); + cardhu_suspend_data.cpu_timer = 5000; + cardhu_suspend_data.cpu_off_timer = 5000; + break; default: break; } -- cgit v1.2.3 From d3bbbd74315428209cb8f16a9dd20e297cbe3af1 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 31 Jul 2012 15:22:40 +0530 Subject: ARM: tegra: harmony: get rid of tegra_gpio_enable() The gpio mode of pin is configured when setting direction and hence this call is no more required. Change-Id: Ic36636535be7be9b799b9f6bf0c56aac89675e63 Signed-off-by: Laxman Dewangan --- arch/arm/mach-tegra/board-harmony-panel.c | 6 ------ arch/arm/mach-tegra/board-harmony.c | 12 ------------ 2 files changed, 18 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-harmony-panel.c b/arch/arm/mach-tegra/board-harmony-panel.c index d4cd3f461b66..79ff5939f7ab 100644 --- a/arch/arm/mach-tegra/board-harmony-panel.c +++ b/arch/arm/mach-tegra/board-harmony-panel.c @@ -57,8 +57,6 @@ static int harmony_backlight_init(struct device *dev) ret = gpio_direction_output(harmony_bl_enb, 1); if (ret < 0) gpio_free(harmony_bl_enb); - else - tegra_gpio_enable(harmony_bl_enb); return ret; } @@ -337,19 +335,15 @@ int __init harmony_panel_init(void) gpio_request(harmony_en_vdd_pnl, "en_vdd_pnl"); gpio_direction_output(harmony_en_vdd_pnl, 1); - tegra_gpio_enable(harmony_en_vdd_pnl); gpio_request(harmony_bl_vdd, "bl_vdd"); gpio_direction_output(harmony_bl_vdd, 1); - tegra_gpio_enable(harmony_bl_vdd); gpio_request(harmony_lvds_shutdown, "lvds_shdn"); gpio_direction_output(harmony_lvds_shutdown, 1); - tegra_gpio_enable(harmony_lvds_shutdown); gpio_request(harmony_hdmi_hpd, "hdmi_hpd"); gpio_direction_input(harmony_hdmi_hpd); - tegra_gpio_enable(harmony_hdmi_hpd); #if defined(CONFIG_TEGRA_NVMAP) harmony_carveouts[1].base = tegra_carveout_start; diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c index 0e1dfe58b278..0e8a9f18c6d9 100644 --- a/arch/arm/mach-tegra/board-harmony.c +++ b/arch/arm/mach-tegra/board-harmony.c @@ -223,14 +223,6 @@ static struct platform_device harmony_gpio_keys_device = { } }; -static void harmony_keys_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(harmony_gpio_keys_buttons); i++) - tegra_gpio_enable(harmony_gpio_keys_buttons[i].gpio); -} - static struct tegra_asoc_platform_data harmony_audio_pdata = { .gpio_spkr_en = TEGRA_GPIO_SPKR_EN, .gpio_hp_det = TEGRA_GPIO_HP_DET, @@ -500,8 +492,6 @@ static int __init harmony_wifi_prepower(void) pr_warning("Unable to get gpio for WLAN Power and Reset\n"); else { - tegra_gpio_enable(TEGRA_GPIO_WLAN_PWR_LOW); - tegra_gpio_enable(TEGRA_GPIO_WLAN_RST_LOW); /* toggle in this order as per spec */ gpio_direction_output(TEGRA_GPIO_WLAN_PWR_LOW, 0); gpio_direction_output(TEGRA_GPIO_WLAN_RST_LOW, 0); @@ -528,8 +518,6 @@ static void __init tegra_harmony_init(void) harmony_pinmux_init(); - harmony_keys_init(); - harmony_uart_init(); tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1; -- cgit v1.2.3 From 791ce48846be8b9cf0c4373393ccd7292c05e7b4 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 31 Jul 2012 15:24:53 +0530 Subject: ARM: tegra: aruba: get rid of tegra_gpio_enable() The gpio mode of pin is configured when setting direction and hence this call is no more required. Change-Id: I9e07a452f81c31abf29260cd3d833ee275d4d694 Signed-off-by: Laxman Dewangan --- arch/arm/mach-tegra/board-aruba-panel.c | 2 -- arch/arm/mach-tegra/board-aruba-sdhci.c | 3 --- arch/arm/mach-tegra/board-aruba-sensors.c | 2 -- arch/arm/mach-tegra/board-aruba.c | 9 --------- 4 files changed, 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-aruba-panel.c b/arch/arm/mach-tegra/board-aruba-panel.c index 01ade01a0eb6..2f33d34d6b59 100644 --- a/arch/arm/mach-tegra/board-aruba-panel.c +++ b/arch/arm/mach-tegra/board-aruba-panel.c @@ -50,8 +50,6 @@ static int aruba_backlight_init(struct device *dev) { ret = gpio_direction_output(aruba_bl_enb, 1); if (ret < 0) gpio_free(aruba_bl_enb); - else - tegra_gpio_enable(aruba_bl_enb); return ret; }; diff --git a/arch/arm/mach-tegra/board-aruba-sdhci.c b/arch/arm/mach-tegra/board-aruba-sdhci.c index 26b04a9021e1..cf29137b773f 100644 --- a/arch/arm/mach-tegra/board-aruba-sdhci.c +++ b/arch/arm/mach-tegra/board-aruba-sdhci.c @@ -224,9 +224,6 @@ static int __init aruba_wifi_init(void) gpio_request(ARUBA_WLAN_PWR, "wlan_power"); gpio_request(ARUBA_WLAN_RST, "wlan_rst"); - tegra_gpio_enable(ARUBA_WLAN_PWR); - tegra_gpio_enable(ARUBA_WLAN_RST); - gpio_direction_output(ARUBA_WLAN_PWR, 0); gpio_direction_output(ARUBA_WLAN_RST, 0); diff --git a/arch/arm/mach-tegra/board-aruba-sensors.c b/arch/arm/mach-tegra/board-aruba-sensors.c index f5ba3d761634..34891ae6f6c2 100644 --- a/arch/arm/mach-tegra/board-aruba-sensors.c +++ b/arch/arm/mach-tegra/board-aruba-sensors.c @@ -43,14 +43,12 @@ static void aruba_isl29018_init(void) { - tegra_gpio_enable(ISL29018_IRQ_GPIO); gpio_request(ISL29018_IRQ_GPIO, "isl29018"); gpio_direction_input(ISL29018_IRQ_GPIO); } static void aruba_akm8975_init(void) { - tegra_gpio_enable(AKM8975_IRQ_GPIO); gpio_request(AKM8975_IRQ_GPIO, "akm8975"); gpio_direction_input(AKM8975_IRQ_GPIO); } diff --git a/arch/arm/mach-tegra/board-aruba.c b/arch/arm/mach-tegra/board-aruba.c index 2fc524ccef93..bb47beeffbdc 100644 --- a/arch/arm/mach-tegra/board-aruba.c +++ b/arch/arm/mach-tegra/board-aruba.c @@ -459,14 +459,6 @@ static struct platform_device *aruba_devices[] __initdata = { #endif }; -static void aruba_keys_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(aruba_keys); i++) - tegra_gpio_enable(aruba_keys[i].gpio); -} - static int __init aruba_touch_init(void) { return 0; @@ -518,7 +510,6 @@ static void __init tegra_aruba_init(void) aruba_i2c_init(); aruba_regulator_init(); aruba_touch_init(); - aruba_keys_init(); aruba_usb_init(); aruba_panel_init(); aruba_sensors_init(); -- cgit v1.2.3 From 93c0203357dd05068309c1141a802585f7c6be27 Mon Sep 17 00:00:00 2001 From: Simone Willett Date: Tue, 31 Jul 2012 16:30:10 -0700 Subject: Revert "regulator: tps80031: rename regulator-name enums" This reverts commit 5bc340e408aa3f009651735c71f3c97676fbe79f Change-Id: I70e40e9cf025c73fde46d1a5577547dc37182a64 Reviewed-on: http://git-master/r/119800 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-enterprise-power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index 4698c75b56b6..37d4576feb96 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -340,7 +340,7 @@ static struct tps80031_bg_platform_data battery_gauge_data = { #define TPS_REG(_id, _data, _sname) \ { \ - .id = TPS80031_REGULATOR_##_id, \ + .id = TPS80031_ID_##_id, \ .name = "tps80031-regulator", \ .platform_data = &pdata_##_data##_##_sname, \ } -- cgit v1.2.3 From ce9fc97cf95c463dff8156dffd5632e5336e4adc Mon Sep 17 00:00:00 2001 From: Chaitanya Bandi Date: Tue, 10 Jul 2012 18:29:19 +0530 Subject: arm: tegra: enterprise: Use pll_p as clk source for PWR_I2C Using pll_p as clock source for PWR_I2C and set bus frequency to 390Khz to make clock divider as 0x82. Bug 1001924 Change-Id: Ib7936b0da9a754cc6b4858eb40a941eee606ac65 Signed-off-by: Chaitanya Bandi Reviewed-on: http://git-master/r/114577 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-enterprise.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c index f9791a7b0e48..1803e74abe2f 100644 --- a/arch/arm/mach-tegra/board-enterprise.c +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -195,6 +195,7 @@ static __initdata struct tegra_clk_init_table enterprise_clk_init_table[] = { { "audio3", "i2s3_sync", 0, false}, { "vi", "pll_p", 0, false}, { "vi_sensor", "pll_p", 0, false}, + { "i2c5", "pll_p", 3200000, false}, { NULL, NULL, 0, 0}, }; @@ -238,7 +239,7 @@ static struct tegra_i2c_platform_data enterprise_i2c4_platform_data = { static struct tegra_i2c_platform_data enterprise_i2c5_platform_data = { .adapter_nr = 4, .bus_count = 1, - .bus_clk_rate = { 400000, 0 }, + .bus_clk_rate = { 390000, 0 }, .scl_gpio = {TEGRA_GPIO_PZ6, 0}, .sda_gpio = {TEGRA_GPIO_PZ7, 0}, .arb_recovery = arb_lost_recovery, -- cgit v1.2.3 From 50008402a6f093e48dee05fc88bc54750b97ae25 Mon Sep 17 00:00:00 2001 From: Abhishek Shukla Date: Fri, 27 Jul 2012 13:04:18 +0530 Subject: ARM: tegra: usb_phy: Fix fake remote wakeup 1. Move hsic line value detectors power on config to the beginning of the sequence before enabling interrupt on hsic line wake event. This avoids any fake event caused by any glitches introduced by this switching. 2. Clear any prior interrupts for the line wake event before enabling interrupt for the line wake event. This also clears any fake events generated because of any glitches. 3. Fix wake event type to NONE in the disable routine during resume interrupt. Bug 1019619 Bug 1018416 Signed-off-by: Abhishek Shukla Change-Id: I934fa2514897c4c23bc62ff8365f6fffe7915bd0 Reviewed-on: http://git-master/r/116699 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/tegra3_usb_phy.c | 61 +++++++++++++++++++++++++----------- 1 file changed, 42 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index f164b409d29b..ac87111dbd7d 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -1869,6 +1869,30 @@ static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy) val |= UHSIC_PWR; writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG); + /* Make sure nothing is happening on the line with respect to PMC */ + val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE); + val &= ~UHSIC_STROBE_VAL; + val &= ~UHSIC_DATA_VAL; + writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE); + + /* Clear walk enable */ + val = readl(pmc_base + PMC_SLEEPWALK_CFG); + val &= ~UHSIC_LINEVAL_WALK_EN; + writel(val, pmc_base + PMC_SLEEPWALK_CFG); + + /* Make sure wake value for line is none */ + val = readl(pmc_base + PMC_SLEEP_CFG); + val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY); + val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE); + writel(val, pmc_base + PMC_SLEEP_CFG); + + /* turn on pad detectors */ + val = readl(pmc_base + PMC_USB_AO); + val &= ~(STROBE_VAL_PD_P0 | DATA_VAL_PD_P0); + writel(val, pmc_base + PMC_USB_AO); + + /* Add small delay before usb detectors provide stable line values */ + udelay(1); /* Enable which type of event can trigger a walk, * in this case usb_line_wake */ @@ -1885,19 +1909,16 @@ static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy) val |= UHSIC_DATA_RPD_A; val &= ~UHSIC_STROBE_RPD_A; val |= UHSIC_STROBE_RPU_A; - writel(val, pmc_base + PMC_SLEEPWALK_UHSIC); val &= ~UHSIC_DATA_RPD_B; val |= UHSIC_DATA_RPU_B; val &= ~UHSIC_STROBE_RPU_B; val |= UHSIC_STROBE_RPD_B; - writel(val, pmc_base + PMC_SLEEPWALK_UHSIC); val &= ~UHSIC_DATA_RPD_C; val |= UHSIC_DATA_RPU_C; val &= ~UHSIC_STROBE_RPU_C; val |= UHSIC_STROBE_RPD_C; - writel(val, pmc_base + PMC_SLEEPWALK_UHSIC); val &= ~UHSIC_DATA_RPD_D; val |= UHSIC_DATA_RPU_D; @@ -1905,19 +1926,21 @@ static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy) val |= UHSIC_STROBE_RPD_D; writel(val, pmc_base + PMC_SLEEPWALK_UHSIC); - /* turn on pad detectors */ - val = readl(pmc_base + PMC_USB_AO); - val &= ~(STROBE_VAL_PD_P0 | DATA_VAL_PD_P0); - writel(val, pmc_base + PMC_USB_AO); - /* Add small delay before usb detectors provide stable line values */ - udelay(1); - phy->remote_wakeup = false; - /* Turn over pad configuration to PMC for line wake events*/ + /* Setting Wake event*/ val = readl(pmc_base + PMC_SLEEP_CFG); - val &= ~UHSIC_WAKE_VAL(~0); + val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY); val |= UHSIC_WAKE_VAL(WAKE_VAL_SD10); + writel(val, pmc_base + PMC_SLEEP_CFG); + + /* Clear the walk pointers and wake alarm */ + val = readl(pmc_base + PMC_TRIGGERS); + val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0; + writel(val, pmc_base + PMC_TRIGGERS); + + /* Turn over pad configuration to PMC for line wake events*/ + val = readl(pmc_base + PMC_SLEEP_CFG); val |= UHSIC_MASTER_ENABLE; writel(val, pmc_base + PMC_SLEEP_CFG); @@ -1936,14 +1959,10 @@ static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy) DBG("%s (%d)\n", __func__, __LINE__); val = readl(pmc_base + PMC_SLEEP_CFG); - val &= ~UHSIC_WAKE_VAL(0x0); + val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY); val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE); writel(val, pmc_base + PMC_SLEEP_CFG); - val = readl(pmc_base + PMC_TRIGGERS); - val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0; - writel(val, pmc_base + PMC_TRIGGERS); - val = readl(base + UHSIC_PMC_WAKEUP0); val &= ~EVENT_INT_ENB; writel(val, base + UHSIC_PMC_WAKEUP0); @@ -1958,6 +1977,10 @@ static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy) val |= (STROBE_VAL_PD_P0 | DATA_VAL_PD_P0); writel(val, pmc_base + PMC_USB_AO); + val = readl(pmc_base + PMC_TRIGGERS); + val |= (UHSIC_CLR_WALK_PTR_P0 | UHSIC_CLR_WAKE_ALARM_P0); + writel(val, pmc_base + PMC_TRIGGERS); + phy->remote_wakeup = false; } @@ -1972,12 +1995,12 @@ static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy) val = readl(pmc_base + UTMIP_UHSIC_STATUS); if (UHSIC_WAKE_ALARM & val) { val = readl(pmc_base + PMC_SLEEP_CFG); - val &= ~UHSIC_WAKE_VAL(0x0); + val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY); val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE); writel(val, pmc_base + PMC_SLEEP_CFG); val = readl(pmc_base + PMC_TRIGGERS); - val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0; + val |= UHSIC_CLR_WAKE_ALARM_P0; writel(val, pmc_base + PMC_TRIGGERS); val = readl(base + UHSIC_PMC_WAKEUP0); -- cgit v1.2.3 From e7a7520c6494c6610835bd6e5c83e790a05892eb Mon Sep 17 00:00:00 2001 From: Vinayak Pane Date: Tue, 24 Jul 2012 21:13:56 -0700 Subject: arm: tegra: xmm: repair ipc_ap_wake_state at reset Preparing strict checking for ipc_ap_wake_state during modem initialization. Modify the flashless xmm wake irq part to avoid mixing with flashed modem irq handler. Remove unused init1 workqueue from the driver. Bug 1003141 Change-Id: I7b06b1783a140c0cc5121478e4983fab39862d7c Signed-off-by: Vinayak Pane Reviewed-on: http://git-master/r/118475 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Steve Lin --- arch/arm/mach-tegra/baseband-xmm-power.c | 111 ++++++++++-------------------- arch/arm/mach-tegra/baseband-xmm-power.h | 15 +++- arch/arm/mach-tegra/baseband-xmm-power2.c | 21 ++---- 3 files changed, 53 insertions(+), 94 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/baseband-xmm-power.c b/arch/arm/mach-tegra/baseband-xmm-power.c index 9513bdc5d45f..cc330c86c581 100644 --- a/arch/arm/mach-tegra/baseband-xmm-power.c +++ b/arch/arm/mach-tegra/baseband-xmm-power.c @@ -77,18 +77,9 @@ static struct gpio tegra_baseband_gpios[] = { { -1, GPIOF_IN, "IPC_HSIC_SUS_REQ" }, }; -static enum { - IPC_AP_WAKE_UNINIT, - IPC_AP_WAKE_IRQ_READY, - IPC_AP_WAKE_INIT1, - IPC_AP_WAKE_INIT2, - IPC_AP_WAKE_L, - IPC_AP_WAKE_H, -} ipc_ap_wake_state; - static enum baseband_xmm_powerstate_t baseband_xmm_powerstate; +static enum ipc_ap_wake_state_t ipc_ap_wake_state; static struct workqueue_struct *workqueue; -static struct work_struct init1_work; static struct work_struct init2_work; static struct work_struct L2_resume_work; static struct work_struct autopm_resume_work; @@ -256,7 +247,6 @@ static int xmm_power_on(struct platform_device *device) /* reset the state machine */ baseband_xmm_powerstate = BBXMM_PS_INIT; modem_sleep_flag = false; - ipc_ap_wake_state = IPC_AP_WAKE_INIT2; pr_debug("%s wake_st(%d) modem version %lu\n", __func__, ipc_ap_wake_state, modem_ver); @@ -264,6 +254,8 @@ static int xmm_power_on(struct platform_device *device) /* register usb host controller */ if (!modem_flash) { pr_debug("%s - %d\n", __func__, __LINE__); + + ipc_ap_wake_state = IPC_AP_WAKE_INIT2; /* register usb host controller only once */ if (register_hsic_device) { pr_debug("%s: register usb host controller\n", @@ -291,7 +283,7 @@ static int xmm_power_on(struct platform_device *device) pr_debug("%s: reset flash modem\n", __func__); modem_power_on = false; - ipc_ap_wake_state = IPC_AP_WAKE_INIT1; + ipc_ap_wake_state = IPC_AP_WAKE_IRQ_READY; gpio_set_value(pdata->modem.xmm.ipc_hsic_active, 0); xmm_power_reset_on(pdata); @@ -552,41 +544,11 @@ void baseband_xmm_set_power_status(unsigned int status) } EXPORT_SYMBOL_GPL(baseband_xmm_set_power_status); -irqreturn_t xmm_power_ipc_ap_wake_irq(int irq, void *dev_id) + +irqreturn_t xmm_power_ipc_ap_wake_irq(int value) { struct baseband_power_platform_data *data = xmm_power_drv_data.pdata; struct xmm_power_data *drv = &xmm_power_drv_data; - int value; - - value = gpio_get_value(data->modem.xmm.ipc_ap_wake); - pr_debug("%s g(%d), wake_st(%d)\n", __func__, value, ipc_ap_wake_state); - - /* modem initialization/bootup part*/ - if (unlikely(ipc_ap_wake_state < IPC_AP_WAKE_IRQ_READY)) { - pr_err("%s - spurious irq\n", __func__); - return IRQ_HANDLED; - } else if (ipc_ap_wake_state == IPC_AP_WAKE_IRQ_READY) { - if (!value) { - pr_debug("%s - IPC_AP_WAKE_INIT1" - " - got falling edge\n", __func__); - /* go to IPC_AP_WAKE_INIT1 state */ - ipc_ap_wake_state = IPC_AP_WAKE_INIT1; - queue_work(workqueue, &init1_work); - } else - pr_debug("%s - IPC_AP_WAKE_INIT1" - " - wait for falling edge\n", __func__); - return IRQ_HANDLED; - } else if (ipc_ap_wake_state == IPC_AP_WAKE_INIT1) { - if (!value) { - pr_debug("%s - got falling edge at INIT1\n", __func__); - /* go to IPC_AP_WAKE_INIT2 state */ - ipc_ap_wake_state = IPC_AP_WAKE_INIT2; - queue_work(workqueue, &init2_work); - } else - pr_debug("%s - IPC_AP_WAKE_INIT1" - " - got rising edge\n", __func__); - return IRQ_HANDLED; - } /* modem wakeup part */ if (!value) { @@ -646,41 +608,41 @@ irqreturn_t xmm_power_ipc_ap_wake_irq(int irq, void *dev_id) /* save gpio state */ ipc_ap_wake_state = IPC_AP_WAKE_H; } - return IRQ_HANDLED; } EXPORT_SYMBOL(xmm_power_ipc_ap_wake_irq); -static void xmm_power_init1_work(struct work_struct *work) +static irqreturn_t ipc_ap_wake_irq(int irq, void *dev_id) { - struct baseband_power_platform_data *pdata = xmm_power_drv_data.pdata; + struct baseband_power_platform_data *data = xmm_power_drv_data.pdata; int value; - pr_debug("%s {\n", __func__); - - /* check if IPC_HSIC_ACTIVE high */ - value = gpio_get_value(pdata->modem.xmm.ipc_hsic_active); - if (value != 1) { - pr_err("%s - expected IPC_HSIC_ACTIVE high!\n", __func__); - return; - } - - /* wait 100 ms */ - msleep(100); - - /* set IPC_HSIC_ACTIVE low */ - gpio_set_value(pdata->modem.xmm.ipc_hsic_active, 0); - - /* wait 10 ms */ - usleep_range(10000, 11000); - - /* set IPC_HSIC_ACTIVE high */ - gpio_set_value(pdata->modem.xmm.ipc_hsic_active, 1); + value = gpio_get_value(data->modem.xmm.ipc_ap_wake); + pr_debug("%s g(%d), wake_st(%d)\n", __func__, value, ipc_ap_wake_state); - /* wait 20 ms */ - msleep(20); + /* modem wakeup part */ + if (likely(ipc_ap_wake_state >= IPC_AP_WAKE_INIT2)) + return xmm_power_ipc_ap_wake_irq(value); - pr_debug("%s }\n", __func__); + /* modem initialization/bootup part*/ + if (unlikely(ipc_ap_wake_state < IPC_AP_WAKE_IRQ_READY)) { + pr_err("%s - spurious irq\n", __func__); + } else if (ipc_ap_wake_state == IPC_AP_WAKE_IRQ_READY) { + if (value) { + /* make state ready for falling edge */ + ipc_ap_wake_state = IPC_AP_WAKE_INIT1; + pr_debug("%s - got rising edge\n", __func__); + } + } else if (ipc_ap_wake_state == IPC_AP_WAKE_INIT1) { + if (!value) { + pr_debug("%s - got falling edge at INIT1\n", __func__); + /* go to IPC_AP_WAKE_INIT2 state */ + ipc_ap_wake_state = IPC_AP_WAKE_INIT2; + queue_work(workqueue, &init2_work); + } else + pr_debug("%s - unexpected rising edge\n", __func__); + } + return IRQ_HANDLED; } static void xmm_power_init2_work(struct work_struct *work) @@ -960,7 +922,7 @@ static int xmm_power_driver_probe(struct platform_device *device) ipc_ap_wake_state = IPC_AP_WAKE_UNINIT; err = request_threaded_irq( gpio_to_irq(pdata->modem.xmm.ipc_ap_wake), - NULL, xmm_power_ipc_ap_wake_irq, + NULL, ipc_ap_wake_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "IPC_AP_WAKE_IRQ", NULL); if (err < 0) { @@ -973,9 +935,9 @@ static int xmm_power_driver_probe(struct platform_device *device) if (err < 0) pr_err("%s: enable_irq_wake error\n", __func__); - pr_debug("%s: AP_WAKE_INIT1\n", __func__); - /* ver 1130 or later starts in INIT1 state */ - ipc_ap_wake_state = IPC_AP_WAKE_INIT1; + pr_debug("%s: set state IPC_AP_WAKE_IRQ_READY\n", __func__); + /* ver 1130 or later start in IRQ_READY state */ + ipc_ap_wake_state = IPC_AP_WAKE_IRQ_READY; } /* init work queue */ @@ -990,7 +952,6 @@ static int xmm_power_driver_probe(struct platform_device *device) queue_work(workqueue, &xmm_power_drv_data.work); /* init work objects */ - INIT_WORK(&init1_work, xmm_power_init1_work); INIT_WORK(&init2_work, xmm_power_init2_work); INIT_WORK(&L2_resume_work, xmm_power_l2_resume_work); INIT_WORK(&autopm_resume_work, xmm_power_autopm_resume); diff --git a/arch/arm/mach-tegra/baseband-xmm-power.h b/arch/arm/mach-tegra/baseband-xmm-power.h index 69140891319d..b9d85eafda1d 100644 --- a/arch/arm/mach-tegra/baseband-xmm-power.h +++ b/arch/arm/mach-tegra/baseband-xmm-power.h @@ -15,7 +15,7 @@ */ #ifndef BASEBAND_XMM_POWER_H -#define BASREBAND_XMM_POWER_H +#define BASEBAND_XMM_POWER_H #include #include @@ -102,9 +102,18 @@ enum baseband_xmm_powerstate_t { BBXMM_PS_LAST = -1, }; -irqreturn_t xmm_power_ipc_ap_wake_irq(int irq, void *dev_id); +enum ipc_ap_wake_state_t { + IPC_AP_WAKE_UNINIT, + IPC_AP_WAKE_IRQ_READY, + IPC_AP_WAKE_INIT1, + IPC_AP_WAKE_INIT2, + IPC_AP_WAKE_L, + IPC_AP_WAKE_H, +}; + +irqreturn_t xmm_power_ipc_ap_wake_irq(int value); void baseband_xmm_set_power_status(unsigned int status); extern struct xmm_power_data xmm_power_drv_data; -#endif /* BASREBAND_XMM_POWER_H */ +#endif /* BASEBAND_XMM_POWER_H */ diff --git a/arch/arm/mach-tegra/baseband-xmm-power2.c b/arch/arm/mach-tegra/baseband-xmm-power2.c index 3c6285c0a070..905759dca329 100644 --- a/arch/arm/mach-tegra/baseband-xmm-power2.c +++ b/arch/arm/mach-tegra/baseband-xmm-power2.c @@ -49,16 +49,7 @@ MODULE_PARM_DESC(XYZ, static struct workqueue_struct *workqueue; static bool free_ipc_ap_wake_irq; - -static enum { - IPC_AP_WAKE_UNINIT, - IPC_AP_WAKE_IRQ_READY, - IPC_AP_WAKE_INIT1, - IPC_AP_WAKE_INIT2, - IPC_AP_WAKE_L, - IPC_AP_WAKE_H, -} ipc_ap_wake_state; - +static enum ipc_ap_wake_state_t ipc_ap_wake_state; static irqreturn_t xmm_power2_ipc_ap_wake_irq(int irq, void *dev_id) { @@ -66,8 +57,6 @@ static irqreturn_t xmm_power2_ipc_ap_wake_irq(int irq, void *dev_id) struct xmm_power_data *data = dev_id; struct baseband_power_platform_data *pdata = data->pdata; - pr_debug("%s\n", __func__); - /* check for platform data */ if (!pdata) return IRQ_HANDLED; @@ -79,8 +68,8 @@ static irqreturn_t xmm_power2_ipc_ap_wake_irq(int irq, void *dev_id) pr_err("%s - spurious irq\n", __func__); else if (ipc_ap_wake_state == IPC_AP_WAKE_IRQ_READY) { if (!value) { - pr_debug("%s: IPC_AP_WAKE_INIT1 got falling edge\n", - __func__); + pr_debug("%s: IPC_AP_WAKE_IRQ_READY got falling edge\n", + __func__); /* go to IPC_AP_WAKE_INIT2 state */ ipc_ap_wake_state = IPC_AP_WAKE_INIT2; /* queue work */ @@ -88,7 +77,7 @@ static irqreturn_t xmm_power2_ipc_ap_wake_irq(int irq, void *dev_id) BBXMM_WORK_INIT_FLASHLESS_PM_STEP2; queue_work(workqueue, &data->work); } else - pr_debug("%s: IPC_AP_WAKE_INIT1" + pr_debug("%s: IPC_AP_WAKE_IRQ_READY" " wait for falling edge\n", __func__); } else { if (!value) { @@ -98,7 +87,7 @@ static irqreturn_t xmm_power2_ipc_ap_wake_irq(int irq, void *dev_id) pr_debug("%s - rising\n", __func__); ipc_ap_wake_state = IPC_AP_WAKE_H; } - return xmm_power_ipc_ap_wake_irq(irq, dev_id); + return xmm_power_ipc_ap_wake_irq(value); } return IRQ_HANDLED; -- cgit v1.2.3 From 01aac51e032582311a57fcee6728fd84b82d89b4 Mon Sep 17 00:00:00 2001 From: naveenk Date: Thu, 26 Jul 2012 14:26:55 +0530 Subject: Revert "Modified the hot-plug governor down_delay to be 500ms instead of 2s" This is required as it is causing performance regression for SD, eMMC and USB Bug 1006055 Bug 1021754 This reverts commit 2f5a59bbeee465fb33d012b8dc714fa0c1637209. Change-Id: Ie54c28859ead976b5c554191d42eb22569370063 Signed-off-by: naveen kumar arepalli Reviewed-on: http://git-master/r/118575 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/cpu-tegra3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/cpu-tegra3.c b/arch/arm/mach-tegra/cpu-tegra3.c index fc96dd6e14b2..ec63622b4705 100644 --- a/arch/arm/mach-tegra/cpu-tegra3.c +++ b/arch/arm/mach-tegra/cpu-tegra3.c @@ -41,7 +41,7 @@ #define INITIAL_STATE TEGRA_HP_DISABLED #define UP2G0_DELAY_MS 70 #define UP2Gn_DELAY_MS 100 -#define DOWN_DELAY_MS 500 +#define DOWN_DELAY_MS 2000 static struct mutex *tegra3_cpu_lock; -- cgit v1.2.3 From bf475b5c3f084af205957fa2be68ef9f3cf57c3b Mon Sep 17 00:00:00 2001 From: Rakesh Iyer Date: Thu, 26 Jul 2012 14:30:05 -0700 Subject: ARM: tegra: cardhu: report height/width for cardhu For accurate Dots-per-inch computation we need to report height/width for the cardhu panel. Bug 1003707. Change-Id: I9a3413d06d97bed532ffc501000ca9bc2360e842 Signed-off-by: Rakesh Iyer Reviewed-on: http://git-master/r/118777 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo Reviewed-by: Bharat Nihalani --- arch/arm/mach-tegra/board-cardhu-panel.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-panel.c b/arch/arm/mach-tegra/board-cardhu-panel.c index 64a50d41eaf7..105c08a59100 100644 --- a/arch/arm/mach-tegra/board-cardhu-panel.c +++ b/arch/arm/mach-tegra/board-cardhu-panel.c @@ -1249,6 +1249,11 @@ static void cardhu_panel_preinit(void) cardhu_disp1_out.n_modes = ARRAY_SIZE(cardhu_panel_modes); cardhu_disp1_out.enable = cardhu_panel_enable; cardhu_disp1_out.disable = cardhu_panel_disable; + if (board_info.board_id == BOARD_E1291) { + /* Set height and width in mm. */ + cardhu_disp1_out.height = 127; + cardhu_disp1_out.width = 216; + } cardhu_disp1_pdata.fb = &cardhu_fb_data; } else { -- cgit v1.2.3 From c3e88db583fec3126ad100775de777a30d9114c6 Mon Sep 17 00:00:00 2001 From: Krishna Yarlagadda Date: Tue, 31 Jul 2012 16:18:50 +0530 Subject: ARM: tegra: usb: Clear pmc wake alarm After a pmc wake, walk pointer and wake alarm should be cleared. Currently wake alarm is cleared only in case of remote wakeup. Clearing wake alarm for all cases of pmc wake. Bug 1024496 Change-Id: I5374d792fe1564fd4a04a48d9fa9de2c93cc94dd Signed-off-by: Krishna Yarlagadda Reviewed-on: http://git-master/r/119619 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/tegra3_usb_phy.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index ac87111dbd7d..d1612d71e5de 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -742,6 +742,7 @@ static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy) val = readl(pmc_base + PMC_TRIGGERS); val |= UTMIP_CLR_WALK_PTR(inst); + val |= UTMIP_CLR_WAKE_ALARM(inst); writel(val, pmc_base + PMC_TRIGGERS); phy->remote_wakeup = false; -- cgit v1.2.3 From ee9e01c5345ff373fa1f64024dde5f06d80d498f Mon Sep 17 00:00:00 2001 From: Vishal Singh Date: Fri, 27 Jul 2012 12:28:00 +0530 Subject: ARM: 7017/1: Use generic BUG() handler ARM uses its own BUG() handler which makes its output slightly different from other archtectures. One of the problems is that the ARM implementation doesn't report the function with the BUG() in it, but always reports the PC being in __bug(). The generic implementation doesn't have this problem. Currently we get something like: kernel BUG at fs/proc/breakme.c:35! Unable to handle kernel NULL pointer dereference at virtual address 00000000 ... PC is at __bug+0x20/0x2c With this patch it displays: kernel BUG at fs/proc/breakme.c:35! Internal error: Oops - undefined instruction: 0 [#1] PREEMPT SMP ... PC is at write_breakme+0xd0/0x1b4 This implementation uses an undefined instruction to implement BUG, and sets up a bug table containing the relevant information. Many versions of gcc do not support %c properly for ARM (inserting a # when they shouldn't) so we work around this using distasteful macro magic. v1: Initial version to replace existing ARM BUG() implementation with something more similar to other architectures. v2: Add Thumb support, remove backtrace whitespace output changes. Change to use macros instead of requiring the asm %d flag to work (thanks to Dave Martin ) v3: Remove old BUG() implementation in favor of this one. Remove the Backtrace: message (will submit this separately). Rebase to linux-2.6.git master. v4: Allow BUGS in modules (these were not reported correctly in v3) (thanks to Stephen Boyd for suggesting that.) Remove __bug() as this is no longer needed. v5: Add %progbits as the section flags. Signed-off-by: Simon Glass Reviewed-by: Stephen Boyd Tested-by: Stephen Boyd Signed-off-by: Russell King (cherry picked from commit 87e040b6456fd3416a1f6831c1eedaef5c0a94ff) Change-Id: Ic7692288dff6e4a15c732eb030295bd196a87fb4 Signed-off-by: Manoj Chourasia Reviewed-on: http://git-master/r/117356 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Vishal Singh Reviewed-by: Sandeep Trasi (cherry picked from commit 6708ffd0b44f4d09d8fe745471641545655091fb) Reviewed-on: http://git-master/r/119328 Reviewed-by: Bob Johnston Reviewed-by: Varun Wadekar --- arch/arm/Kconfig | 17 +++++++++++ arch/arm/include/asm/bug.h | 70 ++++++++++++++++++++++++++++++++++++++----- arch/arm/kernel/traps.c | 33 +++++++++++++------- arch/arm/kernel/vmlinux.lds.S | 21 ++++++++++++- 4 files changed, 122 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 16b259ab7aac..0e57155f5050 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1,3 +1,16 @@ +# Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . config ARM bool default y @@ -218,6 +231,10 @@ config ARM_PATCH_PHYS_VIRT_16BIT to allow physical memory down to a theoretical minimum of 64K boundaries. +config GENERIC_BUG + def_bool y + depends on BUG + source "init/Kconfig" source "kernel/Kconfig.freezer" diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h index 4d88425a4169..6b7f60c9b944 100644 --- a/arch/arm/include/asm/bug.h +++ b/arch/arm/include/asm/bug.h @@ -1,23 +1,77 @@ +/* + * arch/arm/include/asm/bug.h + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ #ifndef _ASMARM_BUG_H #define _ASMARM_BUG_H #ifdef CONFIG_BUG + +/* + * Use a suitable undefined instruction to use for ARM/Thumb2 bug handling. + * We need to be careful not to conflict with those used by other modules and + * the register_undef_hook() system. + */ +#ifdef CONFIG_THUMB2_KERNEL +#define BUG_INSTR_VALUE 0xde02 +#define BUG_INSTR_TYPE ".hword " +#else +#define BUG_INSTR_VALUE 0xe7f001f2 +#define BUG_INSTR_TYPE ".word " +#endif + + +#define BUG() _BUG(__FILE__, __LINE__, BUG_INSTR_VALUE) +#define _BUG(file, line, value) __BUG(file, line, value) + #ifdef CONFIG_DEBUG_BUGVERBOSE -extern void __bug(const char *file, int line) __attribute__((noreturn)); -/* give file/line information */ -#define BUG() __bug(__FILE__, __LINE__) +/* + * The extra indirection is to ensure that the __FILE__ string comes through + * OK. Many version of gcc do not support the asm %c parameter which would be + * preferable to this unpleasantness. We use mergeable string sections to + * avoid multiple copies of the string appearing in the kernel image. + */ -#else +#define __BUG(__file, __line, __value) \ +do { \ + BUILD_BUG_ON(sizeof(struct bug_entry) != 12); \ + asm volatile("1:\t" BUG_INSTR_TYPE #__value "\n" \ + ".pushsection .rodata.str, \"aMS\", %progbits, 1\n" \ + "2:\t.asciz " #__file "\n" \ + ".popsection\n" \ + ".pushsection __bug_table,\"a\"\n" \ + "3:\t.word 1b, 2b\n" \ + "\t.hword " #__line ", 0\n" \ + ".popsection"); \ + unreachable(); \ +} while (0) -/* this just causes an oops */ -#define BUG() do { *(int *)0 = 0; } while (1) +#else /* not CONFIG_DEBUG_BUGVERBOSE */ -#endif +#define __BUG(__file, __line, __value) \ +do { \ + asm volatile(BUG_INSTR_TYPE #__value); \ + unreachable(); \ +} while (0) +#endif /* CONFIG_DEBUG_BUGVERBOSE */ #define HAVE_ARCH_BUG -#endif +#endif /* CONFIG_BUG */ #include diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 4ef9f0d04e5a..2534d2a1a164 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -4,6 +4,8 @@ * Copyright (C) 1995-2009 Russell King * Fragments that appear the same as linux/arch/i386/kernel/traps.c (C) Linus Torvalds * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -21,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -270,6 +273,8 @@ void die(const char *str, struct pt_regs *regs, int err) spin_lock_irq(&die_lock); console_verbose(); bust_spinlocks(1); + if (!user_mode(regs)) + report_bug(regs->ARM_pc, regs); ret = __die(str, err, thread, regs); if (regs && kexec_should_crash(thread->task)) @@ -301,6 +306,24 @@ void arm_notify_die(const char *str, struct pt_regs *regs, } } +#ifdef CONFIG_GENERIC_BUG + +int is_valid_bugaddr(unsigned long pc) +{ +#ifdef CONFIG_THUMB2_KERNEL + unsigned short bkpt; +#else + unsigned long bkpt; +#endif + + if (probe_kernel_address((unsigned *)pc, bkpt)) + return 0; + + return bkpt == BUG_INSTR_VALUE; +} + +#endif + static LIST_HEAD(undef_hook); static DEFINE_SPINLOCK(undef_lock); @@ -708,16 +731,6 @@ baddataabort(int code, unsigned long instr, struct pt_regs *regs) arm_notify_die("unknown data abort code", regs, &info, instr, 0); } -void __attribute__((noreturn)) __bug(const char *file, int line) -{ - printk(KERN_CRIT"kernel BUG at %s:%d!\n", file, line); - *(int *)0 = 0; - - /* Avoid "noreturn function does return" */ - for (;;); -} -EXPORT_SYMBOL(__bug); - void __readwrite_bug(const char *fn) { printk("%s called, but not implemented\n", fn); diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index 4e66f62b8d41..1719a8ccde9c 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -1,3 +1,21 @@ +/* + * arch/arm/kernel/vmlinux.lds.S + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + /* ld script to make ARM Linux kernel * taken from the i386 version by Russell King * Written by Martin Mares @@ -21,7 +39,8 @@ #define ARM_CPU_KEEP(x) #endif -#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK) +#if (defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)) || \ + defined(CONFIG_GENERIC_BUG) #define ARM_EXIT_KEEP(x) x #define ARM_EXIT_DISCARD(x) #else -- cgit v1.2.3 From 21e7b23eca07c80d55e187c3658a4a31fcfa9776 Mon Sep 17 00:00:00 2001 From: Steve Lin Date: Mon, 30 Jul 2012 17:34:00 -0700 Subject: arm: tegra: baseband: Fix sysfs node permissions Restricting the modem sysfs node permissions to owner only. Bug 1025901 Change-Id: I85095c06b6f5329403b66389a5f27383464f2c64 Signed-off-by: Steve Lin Reviewed-on: http://git-master/r/119436 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Chinmay Kamat Reviewed-by: Alexandre Berdery --- arch/arm/mach-tegra/tegra_usb_modem_power.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra_usb_modem_power.c b/arch/arm/mach-tegra/tegra_usb_modem_power.c index bb9495a329a6..63e4b177bfad 100644 --- a/arch/arm/mach-tegra/tegra_usb_modem_power.c +++ b/arch/arm/mach-tegra/tegra_usb_modem_power.c @@ -400,7 +400,8 @@ static ssize_t load_unload_usb_host(struct device *dev, return count; } -static DEVICE_ATTR(load_host, 0666, show_usb_host, load_unload_usb_host); +static DEVICE_ATTR(load_host, S_IRUSR | S_IWUSR, show_usb_host, + load_unload_usb_host); static int mdm_init(struct tegra_usb_modem *modem, struct platform_device *pdev) { -- cgit v1.2.3 From 68e51b81e37a98250df31d21723af5e443a5688f Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 31 Jul 2012 14:14:16 +0530 Subject: ARM: tegra: usb_phy: get rid of tegra_gpio_enable() The gpio mode of pin is configured when setting direction and hence this call is no more required. Change-Id: I6629743f34ffc6fa3b505deff5b9dc940b7160ef Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/119603 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/usb_phy.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c index aed8ec2bf9d8..c01f88f0f0d3 100644 --- a/arch/arm/mach-tegra/usb_phy.c +++ b/arch/arm/mach-tegra/usb_phy.c @@ -322,8 +322,6 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct platform_device *pdev) req failed\n", phy->inst); goto fail_init; } - if (gpio < TEGRA_NR_GPIOS) - tegra_gpio_enable(gpio); if (gpio_direction_output(gpio, 1) < 0) { ERR("inst:[%d] host vbus gpio \ dir failed\n", phy->inst); -- cgit v1.2.3 From 486084915599184bd2e05e6373f7d85cddbc2ded Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 31 Jul 2012 14:18:18 +0530 Subject: ARM: tegra: usb_modem: get rid of tegra_gpio_enable() The gpio mode of pin is configured when setting direction and hence this call is no more required. Change-Id: I19fea4d4752b72809bf65fbd0a0b255705ec33f8 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/119604 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/tegra_usb_modem_power.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra_usb_modem_power.c b/arch/arm/mach-tegra/tegra_usb_modem_power.c index 63e4b177bfad..8e93a7cdca97 100644 --- a/arch/arm/mach-tegra/tegra_usb_modem_power.c +++ b/arch/arm/mach-tegra/tegra_usb_modem_power.c @@ -307,8 +307,6 @@ static int mdm_request_wakeable_irq(struct tegra_usb_modem *modem, if (ret) return ret; - tegra_gpio_enable(irq_gpio); - /* enable IRQ for GPIO */ *irq = gpio_to_irq(irq_gpio); -- cgit v1.2.3 From 36a9f3f185cab0fb5c5595b7a3cc9a3d91cc9e0e Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 31 Jul 2012 14:23:58 +0530 Subject: ARM: tegra: i2c_recovery: get rid of tegra_gpio_enable() The gpio mode of pin is configured when setting direction and hence this call is no more required. Change-Id: Ic266be441125c751736cada81ac17f4d36e4db5d Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/119605 --- arch/arm/mach-tegra/i2c_error_recovery.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/i2c_error_recovery.c b/arch/arm/mach-tegra/i2c_error_recovery.c index a3ac4e122a8f..2993a6b3abc5 100644 --- a/arch/arm/mach-tegra/i2c_error_recovery.c +++ b/arch/arm/mach-tegra/i2c_error_recovery.c @@ -44,7 +44,6 @@ int arb_lost_recovery(int scl_gpio, int sda_gpio) scl_gpio, ret); return -EINVAL;; } - tegra_gpio_enable(scl_gpio); ret = gpio_request(sda_gpio, "sda_gpio"); if (ret < 0) { @@ -52,7 +51,6 @@ int arb_lost_recovery(int scl_gpio, int sda_gpio) sda_gpio, ret); goto err; } - tegra_gpio_enable(sda_gpio); gpio_direction_input(sda_gpio); while (retry--) { @@ -82,9 +80,7 @@ int arb_lost_recovery(int scl_gpio, int sda_gpio) } gpio_free(scl_gpio); - tegra_gpio_disable(scl_gpio); gpio_free(sda_gpio); - tegra_gpio_disable(sda_gpio); if (likely(recovered_successfully)) { pr_err("arbitration lost recovered by re-try-count 0x%08x\n", @@ -97,7 +93,6 @@ int arb_lost_recovery(int scl_gpio, int sda_gpio) err: gpio_free(scl_gpio); - tegra_gpio_disable(scl_gpio); return ret; } -- cgit v1.2.3 From 0e13ef96d56a712a936a72e87149e49cb6be579b Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 31 Jul 2012 14:28:19 +0530 Subject: ARM: tegra: cardhu: get rid of tegra_gpio_enable() in panel init The gpio mode of pin is configured when setting direction and hence this call is no more required. Change-Id: I394cb55d90c625f1608a0ac80b24228b57b351c1 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/119607 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-cardhu-panel.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-panel.c b/arch/arm/mach-tegra/board-cardhu-panel.c index 105c08a59100..89695840fe08 100644 --- a/arch/arm/mach-tegra/board-cardhu-panel.c +++ b/arch/arm/mach-tegra/board-cardhu-panel.c @@ -873,13 +873,9 @@ static int cardhu_dsi_panel_disable(void) } else if (is_panel_218) { gpio_free(cardhu_dsi_pnl_reset); } else if (is_panel_1506) { - tegra_gpio_disable(e1506_bl_enb); gpio_free(e1506_bl_enb); - tegra_gpio_disable(cardhu_dsi_pnl_reset); gpio_free(cardhu_dsi_pnl_reset); - tegra_gpio_disable(e1506_panel_enb); gpio_free(e1506_panel_enb); - tegra_gpio_disable(e1506_dsi_vddio); gpio_free(e1506_dsi_vddio); } return err; @@ -1392,7 +1388,6 @@ skip_lvds: gpio_direction_input(cardhu_hdmi_hpd); #if !(DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE) - tegra_gpio_enable(e1506_lcd_te); gpio_request(e1506_lcd_te, "lcd_te"); gpio_direction_input(e1506_lcd_te); #endif -- cgit v1.2.3 From e5974e531fdfa3e4763d2f40f8278ccb29cd129d Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 31 Jul 2012 14:37:52 +0530 Subject: ARM: tegra: get rid of tegra_gpio_enable() in touch init The gpio mode of pin is configured when setting direction and hence this call is no more required. Change-Id: I3e3e49fb3b970b090f2184c21601f676356212a4 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/119608 Reviewed-by: Robert Collins Reviewed-by: David Jung --- arch/arm/mach-tegra/board-touch-kai-synaptics-spi.c | 4 ---- arch/arm/mach-tegra/board-touch-raydium_spi.c | 2 -- 2 files changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-touch-kai-synaptics-spi.c b/arch/arm/mach-tegra/board-touch-kai-synaptics-spi.c index 989cf3339be4..718047acf896 100644 --- a/arch/arm/mach-tegra/board-touch-kai-synaptics-spi.c +++ b/arch/arm/mach-tegra/board-touch-kai-synaptics-spi.c @@ -38,11 +38,9 @@ static struct rmi_f19_button_map synaptics_button_map = { static int synaptics_touchpad_gpio_setup(void *gpio_data, bool configure) { if (configure) { - tegra_gpio_enable(SYNAPTICS_ATTN_GPIO); gpio_request(SYNAPTICS_ATTN_GPIO, "synaptics-irq"); gpio_direction_input(SYNAPTICS_ATTN_GPIO); - tegra_gpio_enable(SYNAPTICS_RESET_GPIO); gpio_request(SYNAPTICS_RESET_GPIO, "synaptics-reset"); gpio_direction_output(SYNAPTICS_RESET_GPIO, 0); @@ -52,8 +50,6 @@ static int synaptics_touchpad_gpio_setup(void *gpio_data, bool configure) } else { gpio_free(SYNAPTICS_ATTN_GPIO); gpio_free(SYNAPTICS_RESET_GPIO); - tegra_gpio_disable(SYNAPTICS_ATTN_GPIO); - tegra_gpio_disable(SYNAPTICS_RESET_GPIO); } return 0; } diff --git a/arch/arm/mach-tegra/board-touch-raydium_spi.c b/arch/arm/mach-tegra/board-touch-raydium_spi.c index eb13fc4a44ab..b4ed0310054c 100644 --- a/arch/arm/mach-tegra/board-touch-raydium_spi.c +++ b/arch/arm/mach-tegra/board-touch-raydium_spi.c @@ -201,11 +201,9 @@ struct spi_board_info rm31080a_spi_board[1] = { int __init touch_init_raydium(int irq_gpio, int reset_gpio, int platform) { int err = 0; - tegra_gpio_enable(irq_gpio); gpio_request(irq_gpio, "raydium-irq"); gpio_direction_input(irq_gpio); - tegra_gpio_enable(reset_gpio); gpio_request(reset_gpio, "raydium-reset"); gpio_direction_output(reset_gpio, 0); -- cgit v1.2.3 From 826dd44a11e9ef74c35c3a07e6c7f9bf0df70ca2 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 31 Jul 2012 14:59:23 +0530 Subject: ARM: tegra: enterprise: get rid of tegra_gpio_enable() The gpio mode of pin is configured when setting direction and hence this call is no more required. Change-Id: I3f81c54d2e1933684689df88814b98f617da3545 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/119611 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-enterprise-power.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index 37d4576feb96..3cd6b44f7a41 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -751,8 +751,6 @@ int __init enterprise_regulator_init(void) battery_gauge_data.battery_present = 0; } - tegra_gpio_enable(TEGRA_GPIO_PF7); - if (board_info.fab < BOARD_FAB_A03) { tps_platform.num_subdevs = ARRAY_SIZE(tps80031_devs_a02); tps_platform.subdevs = tps80031_devs_a02; -- cgit v1.2.3 From 54c710020c117465058e12a77b66257177bc328c Mon Sep 17 00:00:00 2001 From: Simone Willett Date: Tue, 31 Jul 2012 16:32:09 -0700 Subject: Revert "Revert "regulator: tps80031: rename regulator-name enums"" This reverts commit 70e40e9cf025c73fde46d1a5577547dc37182a64 Change-Id: Iaf390c0d3ea16686f619f321bceea572ee7434fc Reviewed-on: http://git-master/r/119802 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-enterprise-power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index 3cd6b44f7a41..2d958644a8ab 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -340,7 +340,7 @@ static struct tps80031_bg_platform_data battery_gauge_data = { #define TPS_REG(_id, _data, _sname) \ { \ - .id = TPS80031_ID_##_id, \ + .id = TPS80031_REGULATOR_##_id, \ .name = "tps80031-regulator", \ .platform_data = &pdata_##_data##_##_sname, \ } -- cgit v1.2.3 From 1b94c725d9572f8d7713c8a84d59ca3c7996e8b7 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 1 Aug 2012 14:14:29 +0530 Subject: ARM: tegra: enterpise: name all regulator rails Provide name for all tps80031 regulator rails locally in place of depending on the name provided by driver. Change-Id: I845d0b27077ff6362ab1d19ba7c057260de3722e Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/119973 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-enterprise-power.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index 2d958644a8ab..1c836d64c74a 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -239,6 +239,7 @@ static struct regulator_consumer_supply tps80031_battery_charge_supply[] = { static struct tps80031_regulator_platform_data pdata_##_id##_##_sname = { \ .regulator = { \ .constraints = { \ + .name = tps80031_rails(_id), \ .min_uV = (_minmv)*1000, \ .max_uV = (_maxmv)*1000, \ .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ @@ -270,19 +271,19 @@ TPS_PDATA_INIT(smps2, common, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_ TPS_PDATA_INIT(smps3, common, 600, 2100, 0, 1, 0, 0, -1, 0, 0, 0, 0, 0); TPS_PDATA_INIT(smps4, a02, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); TPS_PDATA_INIT(smps4, a03, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldo1, a02, 1000, 3300, tps80031_rails(VIO), 0, 0, 0, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(ldo1, a03, 1000, 3300, tps80031_rails(VIO), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(ldo1, a02, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, 0, 0); +TPS_PDATA_INIT(ldo1, a03, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); TPS_PDATA_INIT(ldo2, common, 1000, 1000, 0, 1, 1, 1, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(ldo3, common, 1000, 3300, tps80031_rails(VIO), 0, 0, 0, -1, 0, 0, 0, PWR_OFF_ON_SLEEP, 0); +TPS_PDATA_INIT(ldo3, common, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_OFF_ON_SLEEP, 0); TPS_PDATA_INIT(ldo4, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(ldo4, a03, 1000, 3300, tps80031_rails(VIO), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(ldo4, a03, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); TPS_PDATA_INIT(ldo5, common, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); TPS_PDATA_INIT(ldo6, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); TPS_PDATA_INIT(ldo6, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldo7, a02, 1000, 3300, tps80031_rails(VIO), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(ldo7, a02, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); TPS_PDATA_INIT(ldo7, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldoln, a02, 1000, 3300, tps80031_rails(SMPS3), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldoln, a03, 1000, 3300, tps80031_rails(VIO), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(ldoln, a02, 1000, 3300, tps80031_rails(smps3), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(ldoln, a03, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); TPS_PDATA_INIT(ldousb, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, USBLDO_INPUT_VSYS, PWR_OFF_ON_SLEEP, 0); TPS_PDATA_INIT(ldousb, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, USBLDO_INPUT_VSYS, PWR_REQ_INPUT_PREQ1, 0); TPS_PDATA_INIT(vana, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); @@ -594,7 +595,7 @@ static struct gpio gpio_reg_sdmmc3_vdd_sel_gpios[] = { }, \ } -GPIO_REG(4, sdmmc3_vdd_sel, tps80031_rails(SMPS4), +GPIO_REG(4, sdmmc3_vdd_sel, tps80031_rails(smps4), true, false, 0, 1000, 3300); /* Macro for defining fixed regulator sub device data */ -- cgit v1.2.3 From d9b961a08ca88964276824fba2916154b0e7a0ca Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 1 Aug 2012 14:21:19 +0530 Subject: regulator: tps80031: make regualtor_init_data as pointer type The platform data of tps80031 have the regualtor_init_data as non-pointer type. Converting this as pointer type for aligning to regulator driver policy and easy support for DT. Change-Id: I07f574953b09e0ed9ec3735d0ee7999ca35bee61 Reviewed-on: http://git-master/r/119974 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-enterprise-power.c | 38 ++++++++++++++-------------- 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index 1c836d64c74a..b457cda6ace0 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -236,26 +236,26 @@ static struct regulator_consumer_supply tps80031_battery_charge_supply[] = { #define TPS_PDATA_INIT(_id, _sname, _minmv, _maxmv, _supply_reg, _always_on, \ _boot_on, _apply_uv, _init_uV, _init_enable, _init_apply, \ _flags, _ectrl, _delay) \ - static struct tps80031_regulator_platform_data pdata_##_id##_##_sname = { \ - .regulator = { \ - .constraints = { \ - .name = tps80031_rails(_id), \ - .min_uV = (_minmv)*1000, \ - .max_uV = (_maxmv)*1000, \ - .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ - REGULATOR_MODE_STANDBY), \ - .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ - REGULATOR_CHANGE_STATUS | \ - REGULATOR_CHANGE_VOLTAGE), \ - .always_on = _always_on, \ - .boot_on = _boot_on, \ - .apply_uV = _apply_uv, \ - }, \ - .num_consumer_supplies = \ - ARRAY_SIZE(tps80031_##_id##_supply_##_sname), \ - .consumer_supplies = tps80031_##_id##_supply_##_sname, \ - .supply_regulator = _supply_reg, \ + static struct regulator_init_data reg_idata_##_id##_##_sname = { \ + .constraints = { \ + .name = tps80031_rails(_id), \ + .min_uV = (_minmv)*1000, \ + .max_uV = (_maxmv)*1000, \ + .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ + REGULATOR_MODE_STANDBY), \ + .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ + REGULATOR_CHANGE_STATUS | \ + REGULATOR_CHANGE_VOLTAGE), \ + .always_on = _always_on, \ + .boot_on = _boot_on, \ + .apply_uV = _apply_uv, \ }, \ + .num_consumer_supplies = \ + ARRAY_SIZE(tps80031_##_id##_supply_##_sname), \ + .consumer_supplies = tps80031_##_id##_supply_##_sname, \ + }; \ + static struct tps80031_regulator_platform_data pdata_##_id##_##_sname = { \ + .reg_init_data = ®_idata_##_id##_##_sname, \ .init_uV = _init_uV * 1000, \ .init_enable = _init_enable, \ .init_apply = _init_apply, \ -- cgit v1.2.3 From d228a8472dfa7b12e8841bc340ce54b9a7c1db10 Mon Sep 17 00:00:00 2001 From: Suresh Mangipudi Date: Wed, 1 Aug 2012 11:20:58 +0530 Subject: arm: tegra: usb: link ulpi resume sequence lp0 resume for link_ulpi_phy has been modified.To fix the issue of frequent disconnects while resuming from LP0. Bug 997267 Change-Id: If92b8245b154e9b872b80d80a2ab359c87107a39 Signed-off-by: Suresh Mangipudi Reviewed-on: http://git-master/r/119511 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/tegra2_usb_phy.c | 186 +++++++++++++++++++++++++++-------- arch/arm/mach-tegra/tegra_usb_phy.h | 1 + 2 files changed, 147 insertions(+), 40 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra2_usb_phy.c b/arch/arm/mach-tegra/tegra2_usb_phy.c index c7f4a771b1d8..aae2fe9bf56a 100644 --- a/arch/arm/mach-tegra/tegra2_usb_phy.c +++ b/arch/arm/mach-tegra/tegra2_usb_phy.c @@ -47,11 +47,13 @@ #define USB_USBSTS_SRI (1 << 7) #define USB_USBSTS_HCH (1 << 12) +#define USB_USBINTR 0x148 + #define USB_ASYNCLISTADDR 0x158 #define USB_TXFILLTUNING 0x164 #define USB_FIFO_TXFILL_THRES(x) (((x) & 0x1f) << 16) -#define USB_FIFO_TXFILL_MASK 0x1f0000 +#define USB_FIFO_TXFILL_MASK 0x3f0000 #define ULPI_VIEWPORT 0x170 #define ULPI_WAKEUP (1 << 31) @@ -69,6 +71,7 @@ #define USB_PORTSC_PP (1 << 12) #define USB_PORTSC_LS(x) (((x) & 0x3) << 10) #define USB_PORTSC_SUSP (1 << 7) +#define USB_PORTSC_RESUME (1 << 6) #define USB_PORTSC_OCC (1 << 5) #define USB_PORTSC_PEC (1 << 3) #define USB_PORTSC_PE (1 << 2) @@ -710,7 +713,8 @@ static int utmi_phy_power_off(struct tegra_usb_phy *phy) val |= USB_PHY_CLK_VALID_INT_ENB; writel(val, base + USB_SUSP_CTRL); } else { - /* Disable PHY clock valid interrupts while going into suspend*/ + /* Disable PHY clock valid interrupts + while going into suspend*/ val = readl(base + USB_SUSP_CTRL); val &= ~USB_PHY_CLK_VALID_INT_ENB; writel(val, base + USB_SUSP_CTRL); @@ -932,7 +936,8 @@ static int utmi_phy_resume(struct tegra_usb_phy *phy) if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RESET, 0, 2500) < 0) { - pr_err("%s: timeout waiting for reset\n", __func__); + pr_err("%s: timeout waiting for reset\n", + __func__); } val = readl(base + USB_USBMODE_REG_OFFSET); @@ -949,7 +954,8 @@ static int utmi_phy_resume(struct tegra_usb_phy *phy) if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) { - pr_err("%s: timeout waiting for run bit\n", __func__); + pr_err("%s: timeout waiting for run bit\n", + __func__); } /* Enable Port Power */ @@ -959,7 +965,8 @@ static int utmi_phy_resume(struct tegra_usb_phy *phy) udelay(10); DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n", - readl(base + USB_USBSTS), readl(base + USB_PORTSC)); + readl(base + USB_USBSTS), + readl(base + USB_PORTSC)); } } else { /* Restoring the pad powers */ @@ -1354,7 +1361,7 @@ static int ulpi_link_phy_open(struct tegra_usb_phy *phy) phy->ulpi_vp = otg_ulpi_create(&ulpi_viewport_access_ops, 0); phy->ulpi_vp->io_priv = phy->regs + ULPI_VIEWPORT; - + phy->linkphy_init = true; return err; } @@ -1450,49 +1457,74 @@ static int ulpi_link_phy_power_on(struct tegra_usb_phy *phy) } val = readl(base + USB_SUSP_CTRL); - val |= UHSIC_RESET; - writel(val, base + USB_SUSP_CTRL); - val = readl(base + ULPI_TIMING_CTRL_0); - val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; - writel(val, base + ULPI_TIMING_CTRL_0); + /* Case for lp0 */ + if (!(val & UHSIC_RESET)) { + val |= UHSIC_RESET; + writel(val, base + USB_SUSP_CTRL); - val = readl(base + USB_SUSP_CTRL); - val |= ULPI_PHY_ENABLE; - writel(val, base + USB_SUSP_CTRL); + val = 0; + writel(val, base + ULPI_TIMING_CTRL_1); - val = readl(base + USB_SUSP_CTRL); - val |= USB_SUSP_CLR; - writel(val, base + USB_SUSP_CTRL); + ulpi_set_trimmer(phy); - if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, - USB_PHY_CLK_VALID, 2500)) - pr_err("%s: timeout waiting for phy to stabilize\n", __func__); + val = readl(base + ULPI_TIMING_CTRL_0); + val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; + writel(val, base + ULPI_TIMING_CTRL_0); +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, TEGRA_TRI_NORMAL); + tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, TEGRA_TRI_NORMAL); + tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, TEGRA_TRI_NORMAL); +#endif + val = readl(base + USB_SUSP_CTRL); + val |= ULPI_PHY_ENABLE; + writel(val, base + USB_SUSP_CTRL); - if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_CLKEN, - USB_CLKEN, 2500)) - pr_err("%s: timeout waiting for AHB clock\n", __func__); + if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, + USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500) < 0) + pr_err("%s: timeout waiting for phy" \ + "to stabilize\n", __func__); - val = readl(base + USB_SUSP_CTRL); - val &= ~USB_SUSP_CLR; - writel(val, base + USB_SUSP_CTRL); + val = readl(base + USB_TXFILLTUNING); + if ((val & USB_FIFO_TXFILL_MASK) != + USB_FIFO_TXFILL_THRES(0x10)) { + val = USB_FIFO_TXFILL_THRES(0x10); + writel(val, base + USB_TXFILLTUNING); + } + } else { + /* Case for auto resume*/ + val = readl(base + USB_SUSP_CTRL); + val |= USB_SUSP_CLR; + writel(val, base + USB_SUSP_CTRL); - val = 0; - writel(val, base + ULPI_TIMING_CTRL_1); + if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, + USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500) < 0) + pr_err("%s: timeout waiting for phy" \ + "to stabilize\n", __func__); - ulpi_set_trimmer(phy); + if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, + USB_CLKEN, USB_CLKEN, 2500) < 0) + pr_err("%s: timeout waiting for AHB clock\n", __func__); - /* Fix VbusInvalid due to floating VBUS */ - ret = otg_io_write(phy->ulpi_vp, 0x40, 0x08); - if (ret) { - pr_err("%s: ulpi write failed\n", __func__); - return ret; + val = readl(base + USB_SUSP_CTRL); + val &= ~USB_SUSP_CLR; + writel(val, base + USB_SUSP_CTRL); } + if (phy->linkphy_init) { + /* To be done only incase of coldboot*/ + /* Fix VbusInvalid due to floating VBUS */ + ret = otg_io_write(phy->ulpi_vp, 0x40, 0x08); + if (ret) { + pr_err("%s: ulpi write failed\n", __func__); + return ret; + } - ret = otg_io_write(phy->ulpi_vp, 0x80, 0x0B); - if (ret) { - pr_err("%s: ulpi write failed\n", __func__); - return ret; + ret = otg_io_write(phy->ulpi_vp, 0x80, 0x0B); + if (ret) { + pr_err("%s: ulpi write failed\n", __func__); + return ret; + } + phy->linkphy_init = false; } val = readl(base + USB_PORTSC); @@ -1510,6 +1542,7 @@ static inline void ulpi_link_phy_set_tristate(bool enable) #ifdef CONFIG_ARCH_TEGRA_2x_SOC int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL; + tegra_pinmux_set_tristate(TEGRA_PINGROUP_CDEV2, tristate); tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate); tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate); tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate); @@ -1535,6 +1568,7 @@ static void ulpi_link_phy_restore_end(struct tegra_usb_phy *phy) { unsigned long val; void __iomem *base = phy->regs; + int ret; DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); @@ -1543,6 +1577,13 @@ static void ulpi_link_phy_restore_end(struct tegra_usb_phy *phy) writel(val, base + ULPI_TIMING_CTRL_0); ulpi_link_phy_set_tristate(false); + + udelay(10); + ret = otg_io_write(phy->ulpi_vp, 0x55, 0x04); + if (ret) { + pr_err("%s: ulpi write failed\n", __func__); + return; + } } static int ulpi_link_phy_resume(struct tegra_usb_phy *phy) @@ -1562,7 +1603,70 @@ static int ulpi_link_phy_resume(struct tegra_usb_phy *phy) return status; } -static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable) +static int ulpi_link_phy_pre_resume(struct tegra_usb_phy *phy, + bool remote_wakeup) +{ + int status = 0; + unsigned long val; + void __iomem *base = phy->regs; + DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); + + val = readl(base + USB_PORTSC); + if (val & USB_PORTSC_RESUME) { + + val = readl(base + USB_USBCMD); + val &= ~USB_USBCMD_RS; + writel(val, base + USB_USBCMD); + + /* detect remote wakeup */ + msleep(20); + + val = readl(base + USB_PORTSC); + + /* Poll until the controller clears RESUME and SUSPEND */ + if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, + USB_PORTSC_RESUME, 0, 2500)) + pr_err("%s: timeout waiting for RESUME\n", __func__); + if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, + USB_PORTSC_SUSP, 0, 2500)) + pr_err("%s: timeout waiting for SUSPEND\n", __func__); + + /* Since we skip remote wakeup event, + put controller in suspend again and + resume port later */ + val = readl(base + USB_PORTSC); + val |= USB_PORTSC_SUSP; + writel(val, base + USB_PORTSC); + mdelay(4); + /* Wait until port suspend completes */ + if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, + USB_PORTSC_SUSP, USB_PORTSC_SUSP, 2500)) + pr_err("%s: timeout waiting for" \ + "PORT_SUSPEND\n", __func__); + + /* Disable interrupts */ + writel(0, base + USB_USBINTR); + /* Clear the run bit to stop SOFs - 2LS WAR */ + val = readl(base + USB_USBCMD); + val &= ~USB_USBCMD_RS; + writel(val, base + USB_USBCMD); + if (usb_phy_reg_status_wait(base + USB_USBSTS, + USB_USBSTS_HCH, USB_USBSTS_HCH, 2000)) { + pr_err("%s: timeout waiting for" \ + "USB_USBSTS_HCH\n", __func__); + } + usb_phy_wait_for_sof(phy); + + val = readl(base + USB_USBCMD); + val |= USB_USBCMD_RS; + writel(val, base + USB_USBCMD); + } + return status; +} + + +static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, + bool enable) { unsigned long val; void __iomem *base = phy->regs; @@ -1795,7 +1899,8 @@ static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy) val = readl(base + ULPIS2S_CTRL); val |= ULPIS2S_ENA; val |= ULPIS2S_SUPPORT_DISCONNECT; - val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1); + val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) + ? 3 : 1); val |= ULPIS2S_PLLU_MASTER_BLASTER60; writel(val, base + ULPIS2S_CTRL); @@ -1906,6 +2011,7 @@ static struct tegra_usb_phy_ops ulpi_link_phy_ops = { .power_on = ulpi_link_phy_power_on, .power_off = ulpi_link_phy_power_off, .resume = ulpi_link_phy_resume, + .pre_resume = ulpi_link_phy_pre_resume, }; static struct tegra_usb_phy_ops ulpi_null_phy_ops = { diff --git a/arch/arm/mach-tegra/tegra_usb_phy.h b/arch/arm/mach-tegra/tegra_usb_phy.h index 674e8b8ffd18..05aa88296619 100644 --- a/arch/arm/mach-tegra/tegra_usb_phy.h +++ b/arch/arm/mach-tegra/tegra_usb_phy.h @@ -98,6 +98,7 @@ struct tegra_usb_phy { bool ulpi_clk_padout_ena; bool pmc_sleepwalk; bool bus_reseting; + bool linkphy_init; }; int usb_phy_reg_status_wait(void __iomem *reg, u32 mask, -- cgit v1.2.3 From 940211c305fe0bed54b19847633800b77c369a46 Mon Sep 17 00:00:00 2001 From: Roger Hsieh Date: Mon, 30 Jul 2012 16:20:38 +0800 Subject: arm: tegra: fuse: check SENSE_DONE after fuse programming Make fuse burning take effect by checking SENSE_DONE. Without this chip options will not be available on fuse registers until power on reset or LP0 resume. Bug 1020726 Change-Id: Id547d1ea51b023ba904f5751c2ad65667375777d Signed-off-by: Roger Hsieh Reviewed-on: http://git-master/r/119271 Reviewed-by: Varun Wadekar --- arch/arm/mach-tegra/tegra_odm_fuses.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra_odm_fuses.c b/arch/arm/mach-tegra/tegra_odm_fuses.c index 06b831c31967..ae82ed56f0f0 100644 --- a/arch/arm/mach-tegra/tegra_odm_fuses.c +++ b/arch/arm/mach-tegra/tegra_odm_fuses.c @@ -53,6 +53,7 @@ #define NFUSES 64 #define STATE_IDLE (0x4 << 16) +#define SENSE_DONE (0x1 << 30) /* since fuse burning is irreversible, use this for testing */ #define ENABLE_FUSE_BURNING 1 @@ -607,6 +608,17 @@ static void fuse_program_array(int pgm_cycles) } fuse_power_disable(); + + /* + * Wait until done (polling) + * this one needs to use fuse_sense done, the FSM follows a periodic + * sequence that includes idle + */ + do { + udelay(1); + reg = tegra_fuse_readl(FUSE_CTRL); + } while ((reg & (0x1 << 30)) != SENSE_DONE); + } static int fuse_set(enum fuse_io_param io_param, u32 *param, int size) -- cgit v1.2.3 From 65688c4123a896291b5d08e511a609aaedd1b319 Mon Sep 17 00:00:00 2001 From: Tom Cherry Date: Tue, 8 May 2012 15:41:16 -0700 Subject: arm: tegra: enterprise: change BB to DAP5 from DAP3 for A04 Due to a hardware issue, Audio Baseband lines are changed for A04 board from DAP3 to DAP5. All other boards retain the same older line Bug 980383 Change-Id: If9ecfaa7328a9a7148f95d604926975172c0886a Signed-off-by: Tom Cherry Reviewed-On: http://git-master/r/#change,109067 (cherry picked from commit c3de03de4d97937e6a989ae6c79c8c430afd300e) Reviewed-on: http://git-master/r/105168 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-enterprise-pinmux.c | 6 +++--- arch/arm/mach-tegra/board-enterprise.c | 31 +++++++++++++++++++++++---- 2 files changed, 30 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-pinmux.c b/arch/arm/mach-tegra/board-enterprise-pinmux.c index c946d2ee5f40..4fcd7360833c 100644 --- a/arch/arm/mach-tegra/board-enterprise-pinmux.c +++ b/arch/arm/mach-tegra/board-enterprise-pinmux.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/board-enterprise-pinmux.c * - * Copyright (C) 2011 NVIDIA Corporation + * Copyright (C) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -276,8 +276,8 @@ static __initdata struct tegra_pingroup_config enterprise_pinmux_common[] = { DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PCC1, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB0, I2S4, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT), diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c index 1803e74abe2f..ebad27b5d963 100644 --- a/arch/arm/mach-tegra/board-enterprise.c +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/board-enterprise.c * - * Copyright (c) 2011-2012, NVIDIA Corporation. + * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -182,7 +182,6 @@ static __initdata struct tegra_clk_init_table enterprise_clk_init_table[] = { { "blink", "clk_32k", 32768, true}, { "i2s0", "pll_a_out0", 0, false}, { "i2s1", "pll_a_out0", 0, false}, - { "i2s2", "pll_a_out0", 0, false}, { "i2s3", "pll_a_out0", 0, false}, { "spdif_out", "pll_a_out0", 0, false}, { "d_audio", "clk_m", 12000000, false}, @@ -199,6 +198,18 @@ static __initdata struct tegra_clk_init_table enterprise_clk_init_table[] = { { NULL, NULL, 0, 0}, }; +static __initdata struct tegra_clk_init_table enterprise_clk_i2s2_table[] = { + /* name parent rate enabled */ + { "i2s2", "pll_a_out0", 0, false}, + { NULL, NULL, 0, 0}, +}; + +static __initdata struct tegra_clk_init_table enterprise_clk_i2s4_table[] = { + /* name parent rate enabled */ + { "i2s4", "pll_a_out0", 0, false}, + { NULL, NULL, 0, 0}, +}; + static struct tegra_i2c_platform_data enterprise_i2c1_platform_data = { .adapter_nr = 0, .bus_count = 1, @@ -508,7 +519,6 @@ static struct tegra_asoc_platform_data enterprise_audio_pdata = { .sample_size = 16, }, .i2s_param[BASEBAND] = { - .audio_port_id = 2, .is_i2s_master = 1, .i2s_mode = TEGRA_DAIFMT_DSP_A, .sample_size = 16, @@ -851,7 +861,6 @@ static struct platform_device *enterprise_audio_devices[] __initdata = { &tegra_dam_device2, &tegra_i2s_device0, &tegra_i2s_device1, - &tegra_i2s_device2, &tegra_i2s_device3, &tegra_spdif_device, &spdif_dit_device, @@ -870,6 +879,13 @@ static void enterprise_audio_init(void) if (board_info.board_id == BOARD_E1197) enterprise_audio_pdata.i2s_param[HIFI_CODEC].audio_port_id = 1; + else if (board_info.fab == BOARD_FAB_A04) { + enterprise_audio_pdata.i2s_param[BASEBAND].audio_port_id = 4; + platform_device_register(&tegra_i2s_device4); + } else { + enterprise_audio_pdata.i2s_param[BASEBAND].audio_port_id = 2; + platform_device_register(&tegra_i2s_device2); + } platform_add_devices(enterprise_audio_devices, ARRAY_SIZE(enterprise_audio_devices)); @@ -980,6 +996,13 @@ static void enterprise_nfc_init(void) static void __init tegra_enterprise_init(void) { + struct board_info board_info; + tegra_get_board_info(&board_info); + if (board_info.fab == BOARD_FAB_A04) + tegra_clk_init_from_table(enterprise_clk_i2s4_table); + else + tegra_clk_init_from_table(enterprise_clk_i2s2_table); + tegra_thermal_init(&thermal_data, throttle_list, ARRAY_SIZE(throttle_list)); -- cgit v1.2.3 From 79fa97af045b942bb61507bbeffb0fa6d7055347 Mon Sep 17 00:00:00 2001 From: Karthik Ramakrishnan Date: Wed, 20 Jun 2012 00:23:07 -0700 Subject: arm: tegra: enterprise: Pinmux changes for Enterprise A04 Pinmux configurations updated according to the schematics of Enterprise A04. The unused pins are marked Tristate and turned low. The directions are updated for other pins. Bug 990845 Change-Id: I787bdd77848af59b5c33d030f0c040e7431d6c06 Signed-Off-By: Karthik Ramakrishnan Reviewed-on: http://git-master/r/105205 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-enterprise-pinmux.c | 322 ++++++++++++++++---------- 1 file changed, 202 insertions(+), 120 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-pinmux.c b/arch/arm/mach-tegra/board-enterprise-pinmux.c index 4fcd7360833c..1a19dbf95f4a 100644 --- a/arch/arm/mach-tegra/board-enterprise-pinmux.c +++ b/arch/arm/mach-tegra/board-enterprise-pinmux.c @@ -156,7 +156,6 @@ static __initdata struct tegra_pingroup_config enterprise_pinmux_common[] = { /* SDMMC4 pinmux */ DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, PULL_UP, NORMAL, INPUT), @@ -195,47 +194,7 @@ static __initdata struct tegra_pingroup_config enterprise_pinmux_common[] = { DEFAULT_PINMUX(ULPI_DATA5, ULPI, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_DATA6, ULPI, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_DATA7, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_CLK, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DIR, ULPI, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_NXT, ULPI, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_PWR1, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_PWR2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_CS0_N, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_DC0, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D0, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_D1, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_D2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D3, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_D4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D5, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D6, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D7, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_D8, DISPLAYA, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(LCD_D9, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D11, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D12, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D13, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D14, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D15, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D16, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D17, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D18, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D19, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D20, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D22, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_CS1_N, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_M1, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_DC1, DISPLAYA, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(VI_D1, SDMMC2, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(VI_D2, SDMMC2, NORMAL, NORMAL, INPUT), @@ -246,84 +205,27 @@ static __initdata struct tegra_pingroup_config enterprise_pinmux_common[] = { DEFAULT_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(VI_MCLK, VI, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU0, UARTA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU1, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PU2, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PU3, UARTA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PU6, PWM3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(GMI_AD9, NAND, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), #if IS_EXTERNAL_PWM DEFAULT_PINMUX(GMI_AD11, PWM3, NORMAL, NORMAL, OUTPUT), #endif - DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PCC1, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB0, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(KB_ROW0, KBC, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(KB_ROW1, KBC, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(KB_ROW2, KBC, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(KB_ROW3, KBC, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW10, KBC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW12, KBC, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(KB_COL0, KBC, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(KB_COL1, KBC, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(KB_COL2, KBC, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL3, KBC, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(KB_COL4, KBC, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(KB_COL5, KBC, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PV0, RSVD, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(CLK_32K_OUT, BLINK, PULL_DOWN, TRISTATE, OUTPUT), DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT), -#if 0 /* For HDA realtek Codec */ - DEFAULT_PINMUX(SPDIF_IN, DAP2, PULL_DOWN, NORMAL, INPUT), -#else - DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT), -#endif -#if 0 /* For HDA realtek Codec */ - DEFAULT_PINMUX(DAP2_FS, HDA, PULL_DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DIN, HDA, PULL_DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DOUT, HDA, PULL_DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_SCLK, HDA, PULL_DOWN, NORMAL, INPUT), -#else - DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), -#endif DEFAULT_PINMUX(SPI2_CS1_N, SPI2, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), @@ -336,25 +238,8 @@ static __initdata struct tegra_pingroup_config enterprise_pinmux_common[] = { DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), CEC_PINMUX(HDMI_CEC, CEC, NORMAL, TRISTATE, OUTPUT, DEFAULT, DISABLE), DEFAULT_PINMUX(HDMI_INT, RSVD0, NORMAL, TRISTATE, INPUT), - - /* Gpios */ - /* SDMMC1 CD gpio */ - DEFAULT_PINMUX(GMI_IORDY, RSVD1, PULL_UP, NORMAL, INPUT), - /* SDMMC1 WP gpio */ DEFAULT_PINMUX(VI_D11, RSVD1, PULL_UP, NORMAL, INPUT), - - /* Touch panel GPIO */ - /* Touch IRQ */ - DEFAULT_PINMUX(GMI_AD12, NAND, NORMAL, NORMAL, INPUT), - - /* Touch RESET */ - DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD15, NAND, PULL_UP, TRISTATE, INPUT), - - /* Power rails GPIO */ - DEFAULT_PINMUX(KB_ROW8, KBC, PULL_UP, NORMAL, INPUT), - VI_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), VI_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), @@ -366,6 +251,97 @@ static __initdata struct tegra_pingroup_config enterprise_pinmux_common[] = { static __initdata struct tegra_pingroup_config enterprise_pinmux_a03[] = { DEFAULT_PINMUX(LCD_PWR0, DISPLAYA, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(LCD_D10, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_CLK, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DIR, ULPI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_NXT, ULPI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV3, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_PWR1, DISPLAYA, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_PWR2, DISPLAYA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(LCD_CS0_N, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_DC0, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(LCD_D0, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D1, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D2, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D3, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D4, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D5, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D6, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D7, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D8, DISPLAYA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(LCD_D9, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D11, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D12, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D13, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D14, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D15, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D16, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D17, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D18, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D19, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D20, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D22, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_CS1_N, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_M1, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_DC1, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU0, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU1, UARTA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PU2, UARTA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PU3, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU4, PWM1, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PU6, PWM3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PCC1, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB0, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW10, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW12, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL3, KBC, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PV0, RSVD, PULL_UP, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI, SPI1, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI1_SCK, SPI1, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI1_MISO, SPI1, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_IORDY, RSVD1, PULL_UP, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD12, NAND, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW8, KBC, PULL_UP, TRISTATE, INPUT), }; static __initdata struct tegra_pingroup_config enterprise_unused_pinmux_common[] = { @@ -426,9 +402,100 @@ static __initdata struct tegra_pingroup_config enterprise_unused_pinmux_common[] DEFAULT_PINMUX(SPI2_MISO, SPI2, PULL_DOWN, TRISTATE, OUTPUT), }; -static __initdata struct tegra_pingroup_config enterprise_unused_pinmux_a02[] = { - DEFAULT_PINMUX(LCD_D10, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), - DEFAULT_PINMUX(LCD_PWR0, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), +static __initdata struct tegra_pingroup_config enterprise_pinmux_a02[] = { + DEFAULT_PINMUX(LCD_D10, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_PWR0, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_CLK, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DIR, ULPI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_NXT, ULPI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_PWR1, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_PWR2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS0_N, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D0, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D1, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D8, DISPLAYA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(LCD_D9, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_M1, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_DC1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU0, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU1, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU2, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU3, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU6, PWM3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW10, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL3, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV0, RSVD, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_IORDY, RSVD1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD12, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8, KBC, PULL_UP, NORMAL, INPUT), }; static struct tegra_gpio_table gpio_table[] = { @@ -515,6 +582,19 @@ static __initdata struct pin_info_low_power_mode enterprise_unused_gpio_pins_a02 PIN_GPIO_LPM("LCD_PWR0", TEGRA_GPIO_PB2, 0, 0), }; +static __initdata struct pin_info_low_power_mode enterprise_gpio_pins_a03[] = { + PIN_GPIO_LPM("GPIO_PV3", TEGRA_GPIO_PV3, 0, 0), + PIN_GPIO_LPM("LCD_DC0", TEGRA_GPIO_PN6, 0, 0), + PIN_GPIO_LPM("LCD_D5", TEGRA_GPIO_PE5, 0, 0), + PIN_GPIO_LPM("LCD_D20", TEGRA_GPIO_PM4, 0, 0), + PIN_GPIO_LPM("LCD_DC1", TEGRA_GPIO_PD2, 0, 0), + PIN_GPIO_LPM("GPIO_PU4", TEGRA_GPIO_PU4, 0, 0), + PIN_GPIO_LPM("KB_COL3", TEGRA_GPIO_PQ3, 0, 0), + PIN_GPIO_LPM("SPI1_MOSI", TEGRA_GPIO_PX4, 0, 0), + PIN_GPIO_LPM("SPI1_MISO", TEGRA_GPIO_PX7, 0, 0), + PIN_GPIO_LPM("SPI1_SCK", TEGRA_GPIO_PX5, 0, 0), +}; + static void enterprise_set_unused_pin_gpio(struct pin_info_low_power_mode *lpm_pin_info, int list_count) { @@ -564,13 +644,15 @@ int __init enterprise_pinmux_init(void) ARRAY_SIZE(enterprise_unused_gpio_pins_common)); if (board_info.fab < BOARD_FAB_A03) { - tegra_pinmux_config_table(enterprise_unused_pinmux_a02, - ARRAY_SIZE(enterprise_unused_pinmux_a02)); + tegra_pinmux_config_table(enterprise_pinmux_a02, + ARRAY_SIZE(enterprise_pinmux_a02)); enterprise_set_unused_pin_gpio(enterprise_unused_gpio_pins_a02, ARRAY_SIZE(enterprise_unused_gpio_pins_a02)); } else { tegra_pinmux_config_table(enterprise_pinmux_a03, ARRAY_SIZE(enterprise_pinmux_a03)); + enterprise_set_unused_pin_gpio(enterprise_gpio_pins_a03, + ARRAY_SIZE(enterprise_gpio_pins_a03)); } return 0; -- cgit v1.2.3 From 34217c931dabd98a4b3a46d424b5758f8538e20f Mon Sep 17 00:00:00 2001 From: Prem Sasidharan Date: Fri, 27 Jul 2012 15:22:15 -0700 Subject: arm: tegra: cardhu: Disable ACCELIRQ Setting MPU_ACCEL_IRQ_GPIO to 0. This helps prevent creation of device node /dev/accelirq and enable timerirq to provide polling ticks for the MPU sensors. The MPU sensors are not currently operating in interrupt mode, the sensors needs to be polled at regular interval. MPU sensor HAL enables the polling timer in the absense of /dev/accelirq device node. Bug 947670 Signed-off-by: Prem Sasidharan Change-Id: I8a2c60da00e7d288ec785aa204bdb3207d717028 Reviewed-on: http://git-master/r/119098 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Erik Lilliebjerg Reviewed-by: Yu-Huan Hsu --- arch/arm/mach-tegra/board-cardhu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu.h b/arch/arm/mach-tegra/board-cardhu.h index 7c6a132421f0..3dd3d23d9414 100644 --- a/arch/arm/mach-tegra/board-cardhu.h +++ b/arch/arm/mach-tegra/board-cardhu.h @@ -231,7 +231,7 @@ extern struct tegra_uart_platform_data cardhu_irda_pdata; #define MPU_GYRO_BUS_NUM 2 #define MPU_GYRO_ORIENTATION { 0, -1, 0, -1, 0, 0, 0, 0, -1 } #define MPU_ACCEL_NAME "kxtf9" -#define MPU_ACCEL_IRQ_GPIO TEGRA_GPIO_PL1 +#define MPU_ACCEL_IRQ_GPIO 0 /* DISABLE ACCELIRQ: TEGRA_GPIO_PL1 */ #define MPU_ACCEL_ADDR 0x0F #define MPU_ACCEL_BUS_NUM 2 #define MPU_ACCEL_ORIENTATION { 0, -1, 0, -1, 0, 0, 0, 0, -1 } -- cgit v1.2.3 From ae0fe0f2527af92bc0ba9213ea0668ec6c7b19e8 Mon Sep 17 00:00:00 2001 From: Venu Byravarasu Date: Mon, 30 Jul 2012 18:17:34 +0530 Subject: arm: tegra: usb_phy: Hard code HSIC phy params As HSIC does not have any customizable phy params, hard coding them in the phy driver. bug 1024260 Change-Id: I64d5c7f91b077134b54b0aadaf44f129ceaa99e5 Signed-off-by: Venu Byravarasu Reviewed-on: http://git-master/r/119299 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/tegra2_usb_phy.c | 14 +++++++++----- arch/arm/mach-tegra/tegra3_usb_phy.c | 14 +++++++++----- 2 files changed, 18 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra2_usb_phy.c b/arch/arm/mach-tegra/tegra2_usb_phy.c index aae2fe9bf56a..892e3ba8ec71 100644 --- a/arch/arm/mach-tegra/tegra2_usb_phy.c +++ b/arch/arm/mach-tegra/tegra2_usb_phy.c @@ -280,6 +280,11 @@ #define DBG(stuff...) do {} while (0) #endif +/* define HSIC phy params */ +#define HSIC_SYNC_START_DELAY 9 +#define HSIC_IDLE_WAIT_DELAY 17 +#define HSIC_ELASTIC_UNDERRUN_LIMIT 16 +#define HSIC_ELASTIC_OVERRUN_LIMIT 16 static DEFINE_SPINLOCK(utmip_pad_lock); static int utmip_pad_count; @@ -1058,7 +1063,6 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) { unsigned long val; void __iomem *base = phy->regs; - struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic; DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); if (phy->phy_clk_on) { @@ -1084,13 +1088,13 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) writel(val, base + USB_SUSP_CTRL); val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0); - val |= UHSIC_IDLE_WAIT(config->idle_wait_delay); - val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit); - val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit); + val |= UHSIC_IDLE_WAIT(HSIC_IDLE_WAIT_DELAY); + val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(HSIC_ELASTIC_UNDERRUN_LIMIT); + val |= UHSIC_ELASTIC_OVERRUN_LIMIT(HSIC_ELASTIC_OVERRUN_LIMIT); writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0); val = readl(base + UHSIC_HSRX_CFG1); - val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay); + val |= UHSIC_HS_SYNC_START_DLY(HSIC_SYNC_START_DELAY); writel(val, base + UHSIC_HSRX_CFG1); val = readl(base + UHSIC_MISC_CFG0); diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index d1612d71e5de..38d8c414b194 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -473,6 +473,11 @@ #define PHY_DBG(stuff...) do {} while (0) #endif +/* define HSIC phy params */ +#define HSIC_SYNC_START_DELAY 9 +#define HSIC_IDLE_WAIT_DELAY 17 +#define HSIC_ELASTIC_UNDERRUN_LIMIT 16 +#define HSIC_ELASTIC_OVERRUN_LIMIT 16 static u32 utmip_rctrl_val, utmip_tctrl_val; static DEFINE_SPINLOCK(utmip_pad_lock); @@ -2212,7 +2217,6 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) { unsigned long val; void __iomem *base = phy->regs; - struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic; DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); @@ -2238,13 +2242,13 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) writel(val, base + USB_SUSP_CTRL); val = readl(base + UHSIC_HSRX_CFG0); - val |= UHSIC_IDLE_WAIT(config->idle_wait_delay); - val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit); - val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit); + val |= UHSIC_IDLE_WAIT(HSIC_IDLE_WAIT_DELAY); + val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(HSIC_ELASTIC_UNDERRUN_LIMIT); + val |= UHSIC_ELASTIC_OVERRUN_LIMIT(HSIC_ELASTIC_OVERRUN_LIMIT); writel(val, base + UHSIC_HSRX_CFG0); val = readl(base + UHSIC_HSRX_CFG1); - val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay); + val |= UHSIC_HS_SYNC_START_DLY(HSIC_SYNC_START_DELAY); writel(val, base + UHSIC_HSRX_CFG1); /* WAR HSIC TX */ -- cgit v1.2.3 From f34ad144dd221836787fd9bc6871274174364a66 Mon Sep 17 00:00:00 2001 From: Venu Byravarasu Date: Mon, 30 Jul 2012 16:34:24 +0530 Subject: arm: tegra: remove hsic phy params from boards As HSIC phy params are not customizable, removing them from board files. bug 1024260 Change-Id: I6b7702c95810c683ab3d9f79e975657f3f601cd0 Signed-off-by: Venu Byravarasu Reviewed-on: http://git-master/r/119300 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-cardhu.c | 14 -------------- arch/arm/mach-tegra/board-enterprise.c | 9 --------- 2 files changed, 23 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c index 16ad11943533..5da7abef7b12 100644 --- a/arch/arm/mach-tegra/board-cardhu.c +++ b/arch/arm/mach-tegra/board-cardhu.c @@ -1064,13 +1064,6 @@ static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = { .remote_wakeup_supported = false, .power_off_on_suspend = false, }, - .u_cfg.hsic = { - .sync_start_delay = 9, - .idle_wait_delay = 17, - .term_range_adj = 0, - .elastic_underrun_limit = 16, - .elastic_overrun_limit = 16, - }, .ops = &hsic_xmm_plat_ops, }; #endif @@ -1154,13 +1147,6 @@ static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = { .remote_wakeup_supported = false, .power_off_on_suspend = false, }, - .u_cfg.hsic = { - .sync_start_delay = 9, - .idle_wait_delay = 17, - .term_range_adj = 0, - .elastic_underrun_limit = 16, - .elastic_overrun_limit = 16, - }, .ops = &hsic_plat_ops, }; diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c index ebad27b5d963..0df4167290c0 100644 --- a/arch/arm/mach-tegra/board-enterprise.c +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -737,18 +737,9 @@ static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = { .remote_wakeup_supported = false, .power_off_on_suspend = false, }, - .u_cfg.hsic = { - .sync_start_delay = 9, - .idle_wait_delay = 17, - .term_range_adj = 0, - .elastic_underrun_limit = 16, - .elastic_overrun_limit = 16, - }, .ops = &hsic_xmm_plat_ops, }; - - static struct tegra_usb_platform_data tegra_udc_pdata = { .port_otg = true, .has_hostpc = true, -- cgit v1.2.3 From 4361257643046dc507deb8b7a0b49401ecb51c7f Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 31 Jul 2012 14:26:16 +0530 Subject: ARM: tegra: cardhu: get rid of tegra_gpio_enable() in hsic registration The gpio mode of pin is configured when setting direction and hence this call is no more required. Change-Id: Id54a26bc2f3a968c60364b1d5109dd23ff724b94 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/119606 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-cardhu.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c index 5da7abef7b12..242bbef30936 100644 --- a/arch/arm/mach-tegra/board-cardhu.c +++ b/arch/arm/mach-tegra/board-cardhu.c @@ -1084,10 +1084,6 @@ void hsic_platform_open(void) gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */); if (!reset_gpio) gpio_direction_output(hsic_reset_gpio, 0 /* asserted */); - if (!enable_gpio) - tegra_gpio_enable(hsic_enable_gpio); - if (!reset_gpio) - tegra_gpio_enable(hsic_reset_gpio); /* keep hsic reset asserted for 1 ms */ udelay(1000); /* enable (power on) hsic */ -- cgit v1.2.3 From 7959a57736fcf356ca9c1cbc8031cb8f697b9f2b Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 31 Jul 2012 14:56:22 +0530 Subject: ARM: tegra: ventana: get rid of tegra_gpio_enable() The gpio mode of pin is configured when setting direction and hence this call is no more required. Change-Id: I870c361cfcfff949620c0518afb324faeb5879d3 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/119609 --- arch/arm/mach-tegra/board-ventana.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-ventana.c b/arch/arm/mach-tegra/board-ventana.c index 4e01850ea40e..64db1c5206e8 100644 --- a/arch/arm/mach-tegra/board-ventana.c +++ b/arch/arm/mach-tegra/board-ventana.c @@ -424,9 +424,6 @@ static struct i2c_board_info __initdata i2c_info[] = { static int __init ventana_touch_init_atmel(void) { - tegra_gpio_enable(TEGRA_GPIO_PV6); - tegra_gpio_enable(TEGRA_GPIO_PQ7); - gpio_request(TEGRA_GPIO_PV6, "atmel-irq"); gpio_direction_input(TEGRA_GPIO_PV6); @@ -455,9 +452,6 @@ static struct i2c_board_info __initdata ventana_i2c_bus1_touch_info[] = { static int __init ventana_touch_init_panjit(void) { - tegra_gpio_enable(TEGRA_GPIO_PV6); - - tegra_gpio_enable(TEGRA_GPIO_PQ7); i2c_register_board_info(0, ventana_i2c_bus1_touch_info, 1); return 0; @@ -471,7 +465,6 @@ static int __init ventana_gps_init(void) clk_enable(clk32); } - tegra_gpio_enable(TEGRA_GPIO_PZ3); return 0; } @@ -527,9 +520,6 @@ static void ulpi_link_platform_open(void) int reset_gpio = TEGRA_GPIO_PV1; gpio_request(reset_gpio, "ulpi_phy_reset"); - gpio_direction_output(reset_gpio, 0); - tegra_gpio_enable(reset_gpio); - gpio_direction_output(reset_gpio, 0); msleep(5); gpio_direction_output(reset_gpio, 1); -- cgit v1.2.3 From 31912a0240cc80821ee6ecb8f25ea146178244d6 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 31 Jul 2012 14:57:22 +0530 Subject: ARM: tegra: p1852: get rid of tegra_gpio_enable() The gpio mode of pin is configured when setting direction and hence this call is no more required. Change-Id: Ie3ae3375348cd8cbe94b14bd5ce3a861d73cc30c Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/119610 Reviewed-by: Automatic_Commit_Validation_User --- arch/arm/mach-tegra/board-p1852.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-p1852.c b/arch/arm/mach-tegra/board-p1852.c index 229344799112..aefc21774a7d 100644 --- a/arch/arm/mach-tegra/board-p1852.c +++ b/arch/arm/mach-tegra/board-p1852.c @@ -457,9 +457,6 @@ static __initdata struct tegra_clk_init_table spi_clk_init_table[] = { static int __init p1852_touch_init(void) { - tegra_gpio_enable(TOUCH_GPIO_IRQ_ATMEL_T9); - tegra_gpio_enable(TOUCH_GPIO_RST_ATMEL_T9); - gpio_request(TOUCH_GPIO_IRQ_ATMEL_T9, "atmel-irq"); gpio_direction_input(TOUCH_GPIO_IRQ_ATMEL_T9); -- cgit v1.2.3 From d88c5cce18adf50d472508e38fced959b845e7d8 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Thu, 2 Aug 2012 13:34:01 +0530 Subject: regulator: tps80031: register regulators as mfd sub device Converting tps80031 regulator driver to be register as mfd sub device of the tps65910 and register all its regulators from single probe calls. Add separate platform data for the regulator to be supply from board as part of tps80031 platform data. Change-Id: Ie65b25f3058202070f7f917e64a4a660dd941210 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/119976 --- arch/arm/mach-tegra/board-enterprise-power.c | 143 ++++++++++++++------------- 1 file changed, 76 insertions(+), 67 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index b457cda6ace0..f07e61c95287 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -233,7 +233,7 @@ static struct regulator_consumer_supply tps80031_battery_charge_supply[] = { REGULATOR_SUPPLY("usb_bat_chg", NULL), }; -#define TPS_PDATA_INIT(_id, _sname, _minmv, _maxmv, _supply_reg, _always_on, \ +#define TPS_PDATA_INIT(_reg_id, _id, _sname, _minmv, _maxmv, _supply_reg, _always_on, \ _boot_on, _apply_uv, _init_uV, _init_enable, _init_apply, \ _flags, _ectrl, _delay) \ static struct regulator_init_data reg_idata_##_id##_##_sname = { \ @@ -256,6 +256,7 @@ static struct regulator_consumer_supply tps80031_battery_charge_supply[] = { }; \ static struct tps80031_regulator_platform_data pdata_##_id##_##_sname = { \ .reg_init_data = ®_idata_##_id##_##_sname, \ + .regulator_id = TPS80031_REGULATOR_##_reg_id, \ .init_uV = _init_uV * 1000, \ .init_enable = _init_enable, \ .init_apply = _init_apply, \ @@ -264,31 +265,31 @@ static struct regulator_consumer_supply tps80031_battery_charge_supply[] = { .delay_us = _delay, \ } -TPS_PDATA_INIT(vio, a02, 600, 2100, 0, 1, 0, 0, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(vio, a03, 600, 2100, 0, 1, 0, 0, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(smps1, common, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ2 | PWR_OFF_ON_SLEEP, 0); -TPS_PDATA_INIT(smps2, common, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(smps3, common, 600, 2100, 0, 1, 0, 0, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(smps4, a02, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(smps4, a03, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldo1, a02, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(ldo1, a03, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldo2, common, 1000, 1000, 0, 1, 1, 1, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(ldo3, common, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_OFF_ON_SLEEP, 0); -TPS_PDATA_INIT(ldo4, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(ldo4, a03, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldo5, common, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(ldo6, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldo6, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldo7, a02, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldo7, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldoln, a02, 1000, 3300, tps80031_rails(smps3), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldoln, a03, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldousb, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, USBLDO_INPUT_VSYS, PWR_OFF_ON_SLEEP, 0); -TPS_PDATA_INIT(ldousb, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, USBLDO_INPUT_VSYS, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(vana, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(vana, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_OFF_ON_SLEEP, 0); -TPS_PDATA_INIT(vbus, common, 0, 5000, 0, 0, 0, 0, -1, 0, 0, (VBUS_SW_ONLY | VBUS_DISCHRG_EN_PDN), 0, 100000); +TPS_PDATA_INIT(VIO, vio, a02, 600, 2100, 0, 1, 0, 0, -1, 0, 0, 0, 0, 0); +TPS_PDATA_INIT(VIO, vio, a03, 600, 2100, 0, 1, 0, 0, -1, 0, 0, 0, 0, 0); +TPS_PDATA_INIT(SMPS1, smps1, common, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ2 | PWR_OFF_ON_SLEEP, 0); +TPS_PDATA_INIT(SMPS2, smps2, common, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(SMPS3, smps3, common, 600, 2100, 0, 1, 0, 0, -1, 0, 0, 0, 0, 0); +TPS_PDATA_INIT(SMPS4, smps4, a02, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(SMPS4, smps4, a03, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDO1, ldo1, a02, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, 0, 0); +TPS_PDATA_INIT(LDO1, ldo1, a03, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDO2, ldo2, common, 1000, 1000, 0, 1, 1, 1, -1, 0, 0, 0, 0, 0); +TPS_PDATA_INIT(LDO3, ldo3, common, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_OFF_ON_SLEEP, 0); +TPS_PDATA_INIT(LDO4, ldo4, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); +TPS_PDATA_INIT(LDO4, ldo4, a03, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDO5, ldo5, common, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); +TPS_PDATA_INIT(LDO6, ldo6, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDO6, ldo6, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDO7, ldo7, a02, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDO7, ldo7, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDOLN, ldoln, a02, 1000, 3300, tps80031_rails(smps3), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDOLN, ldoln, a03, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDOUSB, ldousb, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, USBLDO_INPUT_VSYS, PWR_OFF_ON_SLEEP, 0); +TPS_PDATA_INIT(LDOUSB, ldousb, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, USBLDO_INPUT_VSYS, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(VANA, vana, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); +TPS_PDATA_INIT(VANA, vana, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_OFF_ON_SLEEP, 0); +TPS_PDATA_INIT(VBUS, vbus, common, 0, 5000, 0, 0, 0, 0, -1, 0, 0, (VBUS_SW_ONLY | VBUS_DISCHRG_EN_PDN), 0, 100000); static struct tps80031_rtc_platform_data rtc_data = { .irq = ENT_TPS80031_IRQ_BASE + TPS80031_INT_RTC_ALARM, @@ -339,12 +340,6 @@ static struct tps80031_bg_platform_data battery_gauge_data = { .platform_data = &rtc_data, \ } -#define TPS_REG(_id, _data, _sname) \ - { \ - .id = TPS80031_REGULATOR_##_id, \ - .name = "tps80031-regulator", \ - .platform_data = &pdata_##_data##_##_sname, \ - } #define TPS_BATTERY() \ { \ .name = "tps80031-charger", \ @@ -361,45 +356,56 @@ static struct tps80031_bg_platform_data battery_gauge_data = { } #define TPS80031_DEVS_COMMON \ - TPS_REG(SMPS1, smps1, common), \ - TPS_REG(SMPS2, smps2, common), \ - TPS_REG(SMPS3, smps3, common), \ - TPS_REG(LDO2, ldo2, common), \ - TPS_REG(LDO3, ldo3, common), \ - TPS_REG(LDO5, ldo5, common), \ - TPS_REG(VBUS, vbus, common), \ TPS_RTC(), \ TPS_BATTERY(), \ TPS_BATTERY_GAUGE(), \ TPS_GPADC() -static struct tps80031_subdev_info tps80031_devs_a02[] = { - TPS_REG(VIO, vio, a02), - TPS80031_DEVS_COMMON, - TPS_REG(SMPS4, smps4, a02), - TPS_REG(LDO1, ldo1, a02), - TPS_REG(LDO4, ldo4, a02), - TPS_REG(LDO6, ldo6, a02), - TPS_REG(LDO7, ldo7, a02), - TPS_REG(LDOLN, ldoln, a02), - TPS_REG(LDOUSB, ldousb, a02), - TPS_REG(VANA, vana, a02), - +static struct tps80031_subdev_info tps80031_devs[] = { + TPS_RTC(), + TPS_BATTERY(), + TPS_BATTERY_GAUGE(), + TPS_GPADC() }; -static struct tps80031_subdev_info tps80031_devs_a03[] = { - TPS_REG(VIO, vio, a03), - TPS80031_DEVS_COMMON, - TPS_REG(SMPS4, smps4, a03), - TPS_REG(LDO1, ldo1, a03), - TPS_REG(LDO4, ldo4, a03), - TPS_REG(LDO6, ldo6, a03), - TPS_REG(LDO7, ldo7, a03), - TPS_REG(LDOLN, ldoln, a03), - TPS_REG(LDOUSB, ldousb, a03), - TPS_REG(VANA, vana, a03), - +#define TPS_REG_PDATA(_id, _sname) &pdata_##_id##_##_sname +static struct tps80031_regulator_platform_data *tps80031_reg_pdata_a02[] = { + TPS_REG_PDATA(vio, a02), + TPS_REG_PDATA(smps1, common), + TPS_REG_PDATA(smps2, common), + TPS_REG_PDATA(smps3, common), + TPS_REG_PDATA(ldo2, common), + TPS_REG_PDATA(ldo3, common), + TPS_REG_PDATA(ldo5, common), + TPS_REG_PDATA(vbus, common), + TPS_REG_PDATA(smps4, a02), + TPS_REG_PDATA(ldo1, a02), + TPS_REG_PDATA(ldo4, a02), + TPS_REG_PDATA(ldo6, a02), + TPS_REG_PDATA(ldo7, a02), + TPS_REG_PDATA(ldoln, a02), + TPS_REG_PDATA(ldousb, a02), + TPS_REG_PDATA(vana, a02), +}; + +static struct tps80031_regulator_platform_data *tps80031_reg_pdata_a03[] = { + TPS_REG_PDATA(vio, a03), + TPS_REG_PDATA(smps1, common), + TPS_REG_PDATA(smps2, common), + TPS_REG_PDATA(smps3, common), + TPS_REG_PDATA(ldo2, common), + TPS_REG_PDATA(ldo3, common), + TPS_REG_PDATA(ldo5, common), + TPS_REG_PDATA(vbus, common), + TPS_REG_PDATA(smps4, a03), + TPS_REG_PDATA(ldo1, a03), + TPS_REG_PDATA(ldo4, a03), + TPS_REG_PDATA(ldo6, a03), + TPS_REG_PDATA(ldo7, a03), + TPS_REG_PDATA(ldoln, a03), + TPS_REG_PDATA(ldousb, a03), + TPS_REG_PDATA(vana, a03), }; static struct tps80031_clk32k_init_data clk32k_idata[] = { @@ -752,12 +758,15 @@ int __init enterprise_regulator_init(void) battery_gauge_data.battery_present = 0; } + tps_platform.num_subdevs = ARRAY_SIZE(tps80031_devs); + tps_platform.subdevs = tps80031_devs; + if (board_info.fab < BOARD_FAB_A03) { - tps_platform.num_subdevs = ARRAY_SIZE(tps80031_devs_a02); - tps_platform.subdevs = tps80031_devs_a02; + tps_platform.num_regulator_pdata = ARRAY_SIZE(tps80031_reg_pdata_a02); + tps_platform.regulator_pdata = tps80031_reg_pdata_a02; } else { - tps_platform.num_subdevs = ARRAY_SIZE(tps80031_devs_a03); - tps_platform.subdevs = tps80031_devs_a03; + tps_platform.num_regulator_pdata = ARRAY_SIZE(tps80031_reg_pdata_a03); + tps_platform.regulator_pdata = tps80031_reg_pdata_a03; tps_platform.pupd_init_data = pupd_idata; tps_platform.pupd_init_data_size = ARRAY_SIZE(pupd_idata); tps_platform.gpio_init_data = gpio_idata_a03; -- cgit v1.2.3 From 2b15ed406736848ccf8798808e4e08e0cca25aac Mon Sep 17 00:00:00 2001 From: Rakesh Bodla Date: Thu, 2 Aug 2012 11:53:39 +0530 Subject: arm: tegra: usb_phy: use devm_kfree to free memory devm_kfree() should be used to free memory allocated by devm_kzalloc() Memory allocated with devm_kzalloc is automatically freed on driver detach. Kernel crash will be observed if it is freed with kfree(). Bug 1027472 Change-Id: I27ae63c26647f055de60c2837edfd5fd44a9dabc Signed-off-by: Rakesh Bodla Reviewed-on: http://git-master/r/120245 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty GVS: Gerrit_Virtual_Submit Reviewed-by: Vinayak Pane --- arch/arm/mach-tegra/usb_phy.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c index c01f88f0f0d3..3f3c3846a4aa 100644 --- a/arch/arm/mach-tegra/usb_phy.c +++ b/arch/arm/mach-tegra/usb_phy.c @@ -239,20 +239,23 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct platform_device *pdev) if (!pdata) { dev_err(&pdev->dev, "inst:[%d] Platform data missing\n", pdev->id); - return ERR_PTR(-EINVAL); + err = -EINVAL; + goto fail_inval; } phy = devm_kzalloc(&pdev->dev, sizeof(struct tegra_usb_phy), GFP_KERNEL); if (!phy) { ERR("inst:[%d] malloc usb phy failed\n", pdev->id); - return ERR_PTR(-ENOMEM); + err = -ENOMEM; + goto fail_nomem; } phy->pdata = devm_kzalloc(&pdev->dev, plat_data_size, GFP_KERNEL); if (!phy->pdata) { ERR("inst:[%d] malloc usb phy pdata failed\n", pdev->id); - kfree(phy); - return ERR_PTR(-ENOMEM); + devm_kfree(&pdev->dev, phy); + err = -ENOMEM; + goto fail_nomem; } memcpy(phy->pdata, pdata, plat_data_size); @@ -281,6 +284,8 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct platform_device *pdev) ERR("inst:[%d] couldn't get regulator avdd_usb: %ld\n", phy->inst, PTR_ERR(phy->vdd_reg)); phy->vdd_reg = NULL; + err = PTR_ERR(phy->vdd_reg); + goto fail_io; } err = tegra_usb_phy_get_clocks(phy); @@ -375,8 +380,11 @@ fail_clk: regulator_put(phy->vdd_reg); iounmap(phy->regs); fail_io: - kfree(phy); + devm_kfree(&pdev->dev, phy->pdata); + devm_kfree(&pdev->dev, phy); +fail_nomem: +fail_inval: return ERR_PTR(err); } @@ -417,8 +425,8 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy) tegra_usb_phy_release_clocks(phy); - kfree(phy->pdata); - kfree(phy); + devm_kfree(&phy->pdev->dev, phy->pdata); + devm_kfree(&phy->pdev->dev, phy); } irqreturn_t tegra_usb_phy_irq(struct tegra_usb_phy *phy) -- cgit v1.2.3 From a9d87f3b8f9ec811d6f8e0feb10bfb5151cc659c Mon Sep 17 00:00:00 2001 From: Rakesh Iyer Date: Thu, 26 Jul 2012 12:18:05 -0700 Subject: ARM: tegra: cardhu: provide suspend aggr for E1506 DSI clock gating requires a valid value for aggressive suspend. Change-Id: I6847fb94e2db899ff251e16f045fa76b8ad2e737 Signed-off-by: Rakesh Iyer Reviewed-on: http://git-master/r/118733 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-cardhu-panel.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-panel.c b/arch/arm/mach-tegra/board-cardhu-panel.c index 89695840fe08..3133b4c7de25 100644 --- a/arch/arm/mach-tegra/board-cardhu-panel.c +++ b/arch/arm/mach-tegra/board-cardhu-panel.c @@ -1286,7 +1286,8 @@ static void cardhu_panel_preinit(void) cardhu_dsi.n_suspend_cmd = ARRAY_SIZE(dsi_suspend_cmd_1506); cardhu_dsi.dsi_suspend_cmd = dsi_suspend_cmd_1506; - cardhu_dsi.panel_send_dc_frames = true, + cardhu_dsi.panel_send_dc_frames = true; + cardhu_dsi.suspend_aggr = DSI_HOST_SUSPEND_LV0; cardhu_dsi_fb_data.xres = 720; cardhu_dsi_fb_data.yres = 1280; /* Set height and width in mm. */ -- cgit v1.2.3 From 5647ca7f3fe44781a3b9a49f3215d8c629d78f49 Mon Sep 17 00:00:00 2001 From: Rakesh Iyer Date: Thu, 2 Aug 2012 05:19:17 -0700 Subject: ARM: tegra: cardhu: report height/width for cardhu For accurate Dots-per-inch computation we need to report height/width for all cardhu based panels. Bug 1003707. Change-Id: I06c5ee077aa82a9ffd958e1cc7c536b445523da3 Signed-off-by: Rakesh Iyer Reviewed-on: http://git-master/r/120350 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-cardhu-panel.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-panel.c b/arch/arm/mach-tegra/board-cardhu-panel.c index 3133b4c7de25..c106a4317bc0 100644 --- a/arch/arm/mach-tegra/board-cardhu-panel.c +++ b/arch/arm/mach-tegra/board-cardhu-panel.c @@ -1245,11 +1245,9 @@ static void cardhu_panel_preinit(void) cardhu_disp1_out.n_modes = ARRAY_SIZE(cardhu_panel_modes); cardhu_disp1_out.enable = cardhu_panel_enable; cardhu_disp1_out.disable = cardhu_panel_disable; - if (board_info.board_id == BOARD_E1291) { - /* Set height and width in mm. */ - cardhu_disp1_out.height = 127; - cardhu_disp1_out.width = 216; - } + /* Set height and width in mm. */ + cardhu_disp1_out.height = 127; + cardhu_disp1_out.width = 216; cardhu_disp1_pdata.fb = &cardhu_fb_data; } else { @@ -1341,6 +1339,9 @@ int __init cardhu_panel_init(void) #else cardhu_disp1_out.depth = 24; #endif + /* Set height and width in mm. */ + cardhu_disp1_out.height = 127; + cardhu_disp1_out.width = 203; cardhu_fb_data.xres = 1920; cardhu_fb_data.yres = 1200; -- cgit v1.2.3 From c05cdfa7545c1aff454734a9b99d52b7e5e66292 Mon Sep 17 00:00:00 2001 From: Rhyland Klein Date: Thu, 2 Aug 2012 15:09:15 -0400 Subject: ARM: tegra: cardhu: add support for lid switch Chromeos testing includes verifying the lid switch is functional. While cardhu's don't have lids, this can be tested via the lid_switch dip switch on the debug board. Add support for the lid switch via gpio_keys. bug 1027716 Signed-off-by: Rhyland Klein Change-Id: I7b2e31798b6cfa0715980ddd93dd6b5292ca20d3 Reviewed-on: http://git-master/r/120445 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan --- arch/arm/mach-tegra/board-cardhu-kbc.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-kbc.c b/arch/arm/mach-tegra/board-cardhu-kbc.c index c3971403148f..ce9b22cc1170 100644 --- a/arch/arm/mach-tegra/board-cardhu-kbc.c +++ b/arch/arm/mach-tegra/board-cardhu-kbc.c @@ -122,6 +122,17 @@ int __init cardhu_scroll_init(void) .debounce_interval = 10, \ } +#define GPIO_SW_KEY(_id, _gpio, _iswake) \ + { \ + .code = _id, \ + .gpio = _gpio, \ + .active_low = 1, \ + .desc = #_id, \ + .type = EV_SW, \ + .wakeup = _iswake, \ + .debounce_interval = 1, \ + } + #define GPIO_IKEY(_id, _irq, _iswake, _deb) \ { \ .code = _id, \ @@ -165,6 +176,7 @@ static struct gpio_keys_button cardhu_keys_e1291[] = { [4] = GPIO_KEY(KEY_BACK, PQ0, 0), [5] = GPIO_KEY(KEY_MENU, PQ1, 0), [6] = GPIO_IKEY(KEY_POWER, TPS6591X_IRQ_BASE + TPS6591X_INT_PWRON, 1, 100), + [7] = GPIO_SW_KEY(SW_LID, TPS6591X_GPIO_5, 0), }; static struct gpio_keys_button cardhu_keys_e1291_a04[] = { @@ -176,6 +188,7 @@ static struct gpio_keys_button cardhu_keys_e1291_a04[] = { [5] = GPIO_KEY(KEY_MENU, PQ1, 0), [6] = GPIO_KEY(KEY_RESERVED, PV0, 1), [7] = GPIO_IKEY(KEY_POWER, TPS6591X_IRQ_BASE + TPS6591X_INT_PWRON, 1, 100), + [8] = GPIO_SW_KEY(SW_LID, TPS6591X_GPIO_5, 0), }; static struct gpio_keys_platform_data cardhu_keys_e1291_pdata = { -- cgit v1.2.3 From edb920f1cf85c71f534da18bf994a788379fdb56 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Fri, 27 May 2011 22:25:26 -0400 Subject: ARM: zImage: ensure it is always a multiple of 64 bits in size This is needed for proper alignment when the DTB appending feature is used. Signed-off-by: Nicolas Pitre Acked-by: Tony Lindgren Tested-by: Shawn Guo Tested-by: Dave Martin Tested-by: Thomas Abraham Signed-off-by: Chinmay Kamat Change-Id: I18dd4220a40984ab2551ca17a16db37193ffe80c Original: 72bf0bce411d9df0935eb77256604212de8f89cc Reviewed-on: http://git-master/r/108696 Reviewed-by: Stephen Warren GVS: Gerrit_Virtual_Submit Tested-by: Nitin Kumbhar Reviewed-by: Dan Willemsen --- arch/arm/boot/compressed/vmlinux.lds.in | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/compressed/vmlinux.lds.in b/arch/arm/boot/compressed/vmlinux.lds.in index 4e728834a1b9..4919f2ac8b89 100644 --- a/arch/arm/boot/compressed/vmlinux.lds.in +++ b/arch/arm/boot/compressed/vmlinux.lds.in @@ -51,6 +51,10 @@ SECTIONS _got_start = .; .got : { *(.got) } _got_end = .; + + /* ensure the zImage file size is always a multiple of 64 bits */ + /* (without a dummy byte, ld just ignores the empty section) */ + .pad : { BYTE(0); . = ALIGN(8); } _edata = .; . = BSS_START; -- cgit v1.2.3 From 40ca1b687155e07dac9650dc481ed98da6166b13 Mon Sep 17 00:00:00 2001 From: John Bonesio Date: Fri, 27 May 2011 18:45:50 -0400 Subject: ARM: zImage: Allow the appending of a device tree binary This patch provides the ability to boot using a device tree that is appended to the raw binary zImage (e.g. cat zImage .dtb > zImage_w_dtb). Signed-off-by: John Bonesio [nico: ported to latest zImage changes plus additional cleanups/improvements] Signed-off-by: Nicolas Pitre Acked-by: Grant Likely Acked-by: Tony Lindgren Tested-by: Shawn Guo Tested-by: Dave Martin Tested-by: Thomas Abraham Signed-off-by: Chinmay Kamat Change-Id: I93c54694a59b357eb550587b94c986dcb19ab954 Original: e2a6a3aafa9862c4a4b59f2a59b8f923d64a680e Reviewed-on: http://git-master/r/107422 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/Kconfig | 20 ++++++++++++ arch/arm/boot/compressed/head.S | 70 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 87 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0e57155f5050..fc9d147ae30e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1940,6 +1940,26 @@ config ZBOOT_ROM_SH_MOBILE_SDHI endchoice +config ARM_APPENDED_DTB + bool "Use appended device tree blob to zImage (EXPERIMENTAL)" + depends on OF && !ZBOOT_ROM && EXPERIMENTAL + help + With this option, the boot code will look for a device tree binary + (DTB) appended to zImage + (e.g. cat zImage .dtb > zImage_w_dtb). + + This is meant as a backward compatibility convenience for those + systems with a bootloader that can't be upgraded to accommodate + the documented boot protocol using a device tree. + + Beware that there is very little in terms of protection against + this option being confused by leftover garbage in memory that might + look like a DTB header after a reboot if no actual DTB is appended + to zImage. Do not leave this option active in a production kernel + if you don't intend to always append a DTB. Proper passing of the + location into r2 of a bootloader provided DTB is always preferable + to this option. + config CMDLINE string "Default kernel command string" default "" diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 24701d6f72bc..29317fac0958 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -216,6 +216,59 @@ restart: adr r0, LC0 mov r10, r6 #endif + mov r5, #0 @ init dtb size to 0 +#ifdef CONFIG_ARM_APPENDED_DTB +/* + * r0 = delta + * r2 = BSS start + * r3 = BSS end + * r4 = final kernel address + * r5 = appended dtb size (still unknown) + * r6 = _edata + * r7 = architecture ID + * r8 = atags/device tree pointer + * r9 = size of decompressed image + * r10 = end of this image, including bss/stack/malloc space if non XIP + * r11 = GOT start + * r12 = GOT end + * sp = stack pointer + * + * if there are device trees (dtb) appended to zImage, advance r10 so that the + * dtb data will get relocated along with the kernel if necessary. + */ + + ldr lr, [r6, #0] +#ifndef __ARMEB__ + ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian +#else + ldr r1, =0xd00dfeed +#endif + cmp lr, r1 + bne dtb_check_done @ not found + + mov r8, r6 @ use the appended device tree + + /* Get the dtb's size */ + ldr r5, [r6, #4] +#ifndef __ARMEB__ + /* convert r5 (dtb size) to little endian */ + eor r1, r5, r5, ror #16 + bic r1, r1, #0x00ff0000 + mov r5, r5, ror #8 + eor r5, r5, r1, lsr #8 +#endif + + /* preserve 64-bit alignment */ + add r5, r5, #7 + bic r5, r5, #7 + + /* relocate some pointers past the appended dtb */ + add r6, r6, r5 + add r10, r10, r5 + add sp, sp, r5 +dtb_check_done: +#endif + /* * Check to see if we will overwrite ourselves. * r4 = final kernel address @@ -285,14 +338,16 @@ wont_overwrite: * r2 = BSS start * r3 = BSS end * r4 = kernel execution address + * r5 = appended dtb size (0 if not present) * r7 = architecture ID * r8 = atags pointer * r11 = GOT start * r12 = GOT end * sp = stack pointer */ - teq r0, #0 + orrs r1, r0, r5 beq not_relocated + add r11, r11, r0 add r12, r12, r0 @@ -307,12 +362,21 @@ wont_overwrite: /* * Relocate all entries in the GOT table. + * Bump bss entries to _edata + dtb size */ 1: ldr r1, [r11, #0] @ relocate entries in the GOT - add r1, r1, r0 @ table. This fixes up the - str r1, [r11], #4 @ C references. + add r1, r1, r0 @ This fixes up C references + cmp r1, r2 @ if entry >= bss_start && + cmphs r3, r1 @ bss_end > entry + addhi r1, r1, r5 @ entry += dtb size + str r1, [r11], #4 @ next entry cmp r11, r12 blo 1b + + /* bump our bss pointers too */ + add r2, r2, r5 + add r3, r3, r5 + #else /* -- cgit v1.2.3 From c0254013515dc7786bdbb344a3ec1ef0cc8a6410 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Sun, 12 Jun 2011 01:07:33 -0400 Subject: ARM: zImage: make sure appended DTB doesn't get overwritten by kernel .bss The appended DTB gets relocated with the decompressor code to get out of the way of the decompressed kernel. However the kernel's .bss section may be larger than the relocated code and data, and then the DTB gets overwritten. Let's make sure the relocation takes care of moving zImage far enough so no such conflict with .bss occurs. Thanks to Tony Lindgren for figuring out this issue. While at it, let's clean up the code a bit so that the wont_overwrite symbol is used while determining if a conflict exists, making the above change more precise as well as eliminating some ARM/THUMB alternates. Signed-off-by: Nicolas Pitre Acked-by: Tony Lindgren Tested-by: Shawn Guo Tested-by: Dave Martin Tested-by: Thomas Abraham Signed-off-by: Chinmay Kamat Change-Id: I1590dcbb9789f20d4c56a1e1f7c40177acaa8a2d Original: 5ffb04f6690d71fab241b3562ebf52b893ac4ff1 Reviewed-on: http://git-master/r/107767 Reviewed-by: Stephen Warren GVS: Gerrit_Virtual_Submit Tested-by: Nitin Kumbhar Reviewed-by: Dan Willemsen --- arch/arm/boot/compressed/Makefile | 3 +++ arch/arm/boot/compressed/head.S | 19 +++++++++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 0c74a6fab952..4867647b9796 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -104,6 +104,9 @@ endif ccflags-y := -fpic -fno-builtin asflags-y := -Wa,-march=all +# Supply kernel BSS size to the decompressor via a linker symbol. +KBSS_SZ = $(shell size $(obj)/../../../../vmlinux | awk 'END{print $$3}') +LDFLAGS_vmlinux = --defsym _kernel_bss_size=$(KBSS_SZ) # Supply ZRELADDR to the decompressor via a linker symbol. ifneq ($(CONFIG_AUTO_ZRELADDR),y) LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR) diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 29317fac0958..e2d933fa36ab 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -248,6 +248,18 @@ restart: adr r0, LC0 mov r8, r6 @ use the appended device tree + /* + * Make sure that the DTB doesn't end up in the final + * kernel's .bss area. To do so, we adjust the decompressed + * kernel size to compensate if that .bss size is larger + * than the relocated code. + */ + ldr r5, =_kernel_bss_size + adr r1, wont_overwrite + sub r1, r6, r1 + subs r1, r5, r1 + addhi r9, r9, r1 + /* Get the dtb's size */ ldr r5, [r6, #4] #ifndef __ARMEB__ @@ -276,15 +288,14 @@ dtb_check_done: * r10 = end of this image, including bss/stack/malloc space if non XIP * We basically want: * r4 - 16k page directory >= r10 -> OK - * r4 + image length <= current position (pc) -> OK + * r4 + image length <= address of wont_overwrite -> OK */ add r10, r10, #16384 cmp r4, r10 bhs wont_overwrite add r10, r4, r9 - ARM( cmp r10, pc ) - THUMB( mov lr, pc ) - THUMB( cmp r10, lr ) + adr r9, wont_overwrite + cmp r10, r9 bls wont_overwrite /* -- cgit v1.2.3 From c00192e6a9cddb848b5cc8944893e1577085c897 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Tue, 13 Sep 2011 21:42:55 -0400 Subject: ARM: zImage: gather some string functions into string.c This is a small subset of string functions needed by commits to come. Except for memcpy() which is unchanged from its original location, their implementation is meant to be small, and -Os is enforced to prevent gcc from doing pointless loop unrolling. Signed-off-by: Nicolas Pitre Tested-by: Shawn Guo Tested-by: Dave Martin Tested-by: Thomas Abraham Signed-off-by: Chinmay Kamat Change-Id: Ib6fd21beb8ee8804e472fb4ff5eb1cbea2b8e877 Original: df4879fa2603fbf0804a80f9f146ef9023dd621f Reviewed-on: http://git-master/r/107424 Reviewed-by: Stephen Warren GVS: Gerrit_Virtual_Submit Tested-by: Nitin Kumbhar Reviewed-by: Dan Willemsen --- arch/arm/boot/compressed/Makefile | 4 ++ arch/arm/boot/compressed/misc.c | 42 +------------ arch/arm/boot/compressed/string.c | 127 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 132 insertions(+), 41 deletions(-) create mode 100644 arch/arm/boot/compressed/string.c (limited to 'arch') diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 4867647b9796..c20ddc69d950 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -26,6 +26,10 @@ HEAD = head.o OBJS += misc.o decompress.o FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c +# string library code (-Os is enforced to keep it much smaller) +OBJS += string.o +CFLAGS_string.o := -Os + # # Architecture dependencies # diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c index 832d37236c59..8e2a8fca5ed2 100644 --- a/arch/arm/boot/compressed/misc.c +++ b/arch/arm/boot/compressed/misc.c @@ -18,14 +18,9 @@ unsigned int __machine_arch_type; -#define _LINUX_STRING_H_ - #include /* for inline */ -#include /* for size_t */ -#include /* for NULL */ +#include #include -#include - static void putstr(const char *ptr); extern void error(char *x); @@ -101,41 +96,6 @@ static void putstr(const char *ptr) flush(); } - -void *memcpy(void *__dest, __const void *__src, size_t __n) -{ - int i = 0; - unsigned char *d = (unsigned char *)__dest, *s = (unsigned char *)__src; - - for (i = __n >> 3; i > 0; i--) { - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - } - - if (__n & 1 << 2) { - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - } - - if (__n & 1 << 1) { - *d++ = *s++; - *d++ = *s++; - } - - if (__n & 1) - *d++ = *s++; - - return __dest; -} - /* * gzip declarations */ diff --git a/arch/arm/boot/compressed/string.c b/arch/arm/boot/compressed/string.c new file mode 100644 index 000000000000..36e53ef9200f --- /dev/null +++ b/arch/arm/boot/compressed/string.c @@ -0,0 +1,127 @@ +/* + * arch/arm/boot/compressed/string.c + * + * Small subset of simple string routines + */ + +#include + +void *memcpy(void *__dest, __const void *__src, size_t __n) +{ + int i = 0; + unsigned char *d = (unsigned char *)__dest, *s = (unsigned char *)__src; + + for (i = __n >> 3; i > 0; i--) { + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + } + + if (__n & 1 << 2) { + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + } + + if (__n & 1 << 1) { + *d++ = *s++; + *d++ = *s++; + } + + if (__n & 1) + *d++ = *s++; + + return __dest; +} + +void *memmove(void *__dest, __const void *__src, size_t count) +{ + unsigned char *d = __dest; + const unsigned char *s = __src; + + if (__dest == __src) + return __dest; + + if (__dest < __src) + return memcpy(__dest, __src, count); + + while (count--) + d[count] = s[count]; + return __dest; +} + +size_t strlen(const char *s) +{ + const char *sc = s; + + while (*sc != '\0') + sc++; + return sc - s; +} + +int memcmp(const void *cs, const void *ct, size_t count) +{ + const unsigned char *su1 = cs, *su2 = ct, *end = su1 + count; + int res = 0; + + while (su1 < end) { + res = *su1++ - *su2++; + if (res) + break; + } + return res; +} + +int strcmp(const char *cs, const char *ct) +{ + unsigned char c1, c2; + int res = 0; + + do { + c1 = *cs++; + c2 = *ct++; + res = c1 - c2; + if (res) + break; + } while (c1); + return res; +} + +void *memchr(const void *s, int c, size_t count) +{ + const unsigned char *p = s; + + while (count--) + if ((unsigned char)c == *p++) + return (void *)(p - 1); + return NULL; +} + +char *strchr(const char *s, int c) +{ + while (*s != (char)c) + if (*s++ == '\0') + return NULL; + return (char *)s; +} + +#undef memset + +void *memset(void *s, int c, size_t count) +{ + char *xs = s; + while (count--) + *xs++ = c; + return s; +} + +void __memzero(void *s, size_t count) +{ + memset(s, 0, count); +} -- cgit v1.2.3 From f7d783cc292186266622cfebb552fcf695aefd46 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Tue, 13 Sep 2011 22:37:07 -0400 Subject: ARM: zImage: allow supplementing appended DTB with traditional ATAG data Some old bootloaders can't be updated to a device tree capable one, yet they provide ATAGs with memory configuration, the ramdisk address, the kernel cmdline string, etc. To allow a device tree enabled kernel to be used with such bootloaders, it is necessary to convert those ATAGs into FDT properties and fold them into the DTB appended to zImage. Currently the following ATAGs are converted: ATAG_CMDLINE ATAG_MEM ATAG_INITRD2 If the corresponding information already exists in the appended DTB, it is replaced, otherwise the required node is created to hold it. The code looks for ATAGs at the location pointed by the value of r2 upon entry into the zImage code. If no ATAGs are found there, an attempt at finding ATAGs at the typical 0x100 offset from start of RAM is made. Otherwise the DTB is left unchanged. Thisstarted from an older patch from John Bonesio , with contributions from David Brown . Signed-off-by: Nicolas Pitre Tested-by: Shawn Guo Tested-by: Dave Martin Tested-by: Thomas Abraham Signed-off-by: Chinmay Kamat Change-Id: Ifb96adf6976da0f518c9c2cdad6be85f94c8ad1c Original: b90b9a38251e9c89c34179eccde57411ceb5f1aa Reviewed-on: http://git-master/r/107423 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/Kconfig | 12 ++++ arch/arm/boot/compressed/.gitignore | 9 +++ arch/arm/boot/compressed/Makefile | 21 ++++++- arch/arm/boot/compressed/atags_to_fdt.c | 97 +++++++++++++++++++++++++++++++++ arch/arm/boot/compressed/head.S | 32 +++++++++++ arch/arm/boot/compressed/libfdt_env.h | 15 +++++ 6 files changed, 184 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/compressed/atags_to_fdt.c create mode 100644 arch/arm/boot/compressed/libfdt_env.h (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fc9d147ae30e..bc3e8dc005bb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1960,6 +1960,18 @@ config ARM_APPENDED_DTB location into r2 of a bootloader provided DTB is always preferable to this option. +config ARM_ATAG_DTB_COMPAT + bool "Supplement the appended DTB with traditional ATAG information" + depends on ARM_APPENDED_DTB + help + Some old bootloaders can't be updated to a DTB capable one, yet + they provide ATAGs with memory configuration, the ramdisk address, + the kernel cmdline string, etc. Such information is dynamically + provided by the bootloader and can't always be stored in a static + DTB. To allow a device tree enabled kernel to be used with such + bootloaders, this option allows zImage to extract the information + from the ATAG list and store it at run time into the appended DTB. + config CMDLINE string "Default kernel command string" default "" diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore index c6028967d336..e0936a148516 100644 --- a/arch/arm/boot/compressed/.gitignore +++ b/arch/arm/boot/compressed/.gitignore @@ -5,3 +5,12 @@ piggy.lzo piggy.lzma vmlinux vmlinux.lds + +# borrowed libfdt files +fdt.c +fdt.h +fdt_ro.c +fdt_rw.c +fdt_wip.c +libfdt.h +libfdt_internal.h diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index c20ddc69d950..55f86349d547 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -93,19 +93,36 @@ suffix_$(CONFIG_KERNEL_GZIP) = gzip suffix_$(CONFIG_KERNEL_LZO) = lzo suffix_$(CONFIG_KERNEL_LZMA) = lzma +# Borrowed libfdt files for the ATAG compatibility mode + +libfdt := fdt_rw.c fdt_ro.c fdt_wip.c fdt.c +libfdt_hdrs := fdt.h libfdt.h libfdt_internal.h + +libfdt_objs := $(addsuffix .o, $(basename $(libfdt))) + +$(addprefix $(obj)/,$(libfdt) $(libfdt_hdrs)): $(obj)/%: $(srctree)/scripts/dtc/libfdt/% + $(call cmd,shipped) + +$(addprefix $(obj)/,$(libfdt_objs) atags_to_fdt.o): \ + $(addprefix $(obj)/,$(libfdt_hdrs)) + +ifeq ($(CONFIG_ARM_ATAG_DTB_COMPAT),y) +OBJS += $(libfdt_objs) atags_to_fdt.o +endif + targets := vmlinux vmlinux.lds \ piggy.$(suffix_y) piggy.$(suffix_y).o \ font.o font.c head.o misc.o $(OBJS) # Make sure files are removed during clean -extra-y += piggy.gzip piggy.lzo piggy.lzma lib1funcs.S +extra-y += piggy.gzip piggy.lzo piggy.lzma lib1funcs.S $(libfdt) $(libfdt_hdrs) ifeq ($(CONFIG_FUNCTION_TRACER),y) ORIG_CFLAGS := $(KBUILD_CFLAGS) KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) endif -ccflags-y := -fpic -fno-builtin +ccflags-y := -fpic -fno-builtin -I$(obj) asflags-y := -Wa,-march=all # Supply kernel BSS size to the decompressor via a linker symbol. diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c new file mode 100644 index 000000000000..6ce11c481178 --- /dev/null +++ b/arch/arm/boot/compressed/atags_to_fdt.c @@ -0,0 +1,97 @@ +#include +#include + +static int node_offset(void *fdt, const char *node_path) +{ + int offset = fdt_path_offset(fdt, node_path); + if (offset == -FDT_ERR_NOTFOUND) + offset = fdt_add_subnode(fdt, 0, node_path); + return offset; +} + +static int setprop(void *fdt, const char *node_path, const char *property, + uint32_t *val_array, int size) +{ + int offset = node_offset(fdt, node_path); + if (offset < 0) + return offset; + return fdt_setprop(fdt, offset, property, val_array, size); +} + +static int setprop_string(void *fdt, const char *node_path, + const char *property, const char *string) +{ + int offset = node_offset(fdt, node_path); + if (offset < 0) + return offset; + return fdt_setprop_string(fdt, offset, property, string); +} + +static int setprop_cell(void *fdt, const char *node_path, + const char *property, uint32_t val) +{ + int offset = node_offset(fdt, node_path); + if (offset < 0) + return offset; + return fdt_setprop_cell(fdt, offset, property, val); +} + +/* + * Convert and fold provided ATAGs into the provided FDT. + * + * REturn values: + * = 0 -> pretend success + * = 1 -> bad ATAG (may retry with another possible ATAG pointer) + * < 0 -> error from libfdt + */ +int atags_to_fdt(void *atag_list, void *fdt, int total_space) +{ + struct tag *atag = atag_list; + uint32_t mem_reg_property[2 * NR_BANKS]; + int memcount = 0; + int ret; + + /* make sure we've got an aligned pointer */ + if ((u32)atag_list & 0x3) + return 1; + + /* if we get a DTB here we're done already */ + if (*(u32 *)atag_list == fdt32_to_cpu(FDT_MAGIC)) + return 0; + + /* validate the ATAG */ + if (atag->hdr.tag != ATAG_CORE || + (atag->hdr.size != tag_size(tag_core) && + atag->hdr.size != 2)) + return 1; + + /* let's give it all the room it could need */ + ret = fdt_open_into(fdt, fdt, total_space); + if (ret < 0) + return ret; + + for_each_tag(atag, atag_list) { + if (atag->hdr.tag == ATAG_CMDLINE) { + setprop_string(fdt, "/chosen", "bootargs", + atag->u.cmdline.cmdline); + } else if (atag->hdr.tag == ATAG_MEM) { + if (memcount >= sizeof(mem_reg_property)/4) + continue; + mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.start); + mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.size); + } else if (atag->hdr.tag == ATAG_INITRD2) { + uint32_t initrd_start, initrd_size; + initrd_start = atag->u.initrd.start; + initrd_size = atag->u.initrd.size; + setprop_cell(fdt, "/chosen", "linux,initrd-start", + initrd_start); + setprop_cell(fdt, "/chosen", "linux,initrd-end", + initrd_start + initrd_size); + } + } + + if (memcount) + setprop(fdt, "/memory", "reg", mem_reg_property, 4*memcount); + + return fdt_pack(fdt); +} diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index e2d933fa36ab..e45767851a4c 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -246,6 +246,38 @@ restart: adr r0, LC0 cmp lr, r1 bne dtb_check_done @ not found +#ifdef CONFIG_ARM_ATAG_DTB_COMPAT + /* + * OK... Let's do some funky business here. + * If we do have a DTB appended to zImage, and we do have + * an ATAG list around, we want the later to be translated + * and folded into the former here. To be on the safe side, + * let's temporarily move the stack away into the malloc + * area. No GOT fixup has occurred yet, but none of the + * code we're about to call uses any global variable. + */ + add sp, sp, #0x10000 + stmfd sp!, {r0-r3, ip, lr} + mov r0, r8 + mov r1, r6 + sub r2, sp, r6 + bl atags_to_fdt + + /* + * If returned value is 1, there is no ATAG at the location + * pointed by r8. Try the typical 0x100 offset from start + * of RAM and hope for the best. + */ + cmp r0, #1 + sub r0, r4, #(TEXT_OFFSET - 0x100) + mov r1, r6 + sub r2, sp, r6 + blne atags_to_fdt + + ldmfd sp!, {r0-r3, ip, lr} + sub sp, sp, #0x10000 +#endif + mov r8, r6 @ use the appended device tree /* diff --git a/arch/arm/boot/compressed/libfdt_env.h b/arch/arm/boot/compressed/libfdt_env.h new file mode 100644 index 000000000000..1f4e71876b00 --- /dev/null +++ b/arch/arm/boot/compressed/libfdt_env.h @@ -0,0 +1,15 @@ +#ifndef _ARM_LIBFDT_ENV_H +#define _ARM_LIBFDT_ENV_H + +#include +#include +#include + +#define fdt16_to_cpu(x) be16_to_cpu(x) +#define cpu_to_fdt16(x) cpu_to_be16(x) +#define fdt32_to_cpu(x) be32_to_cpu(x) +#define cpu_to_fdt32(x) cpu_to_be32(x) +#define fdt64_to_cpu(x) be64_to_cpu(x) +#define cpu_to_fdt64(x) cpu_to_be64(x) + +#endif -- cgit v1.2.3 From 639ba3d891a9127d42da84225ed04afec8e66451 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Wed, 14 Sep 2011 00:16:21 -0400 Subject: ARM: zImage: prevent constant copy+rebuild of lib1funcs.S The rule to copy this file doesn't have to be forced. However lib1funcs.[So] have to be listed amongst the targets. This prevents zImage from being recreated needlessly. Signed-off-by: Nicolas Pitre Tested-by: Shawn Guo Tested-by: Dave Martin Tested-by: Thomas Abraham Signed-off-by: Chinmay Kamat Change-Id: I0ad0d4564835837abf15f0c590e8452bfef1c3a7 Original: 63d15148b6058ab0037343390e8918503ed81968 Reviewed-on: http://git-master/r/108698 Reviewed-by: Stephen Warren GVS: Gerrit_Virtual_Submit Tested-by: Nitin Kumbhar Reviewed-by: Dan Willemsen --- arch/arm/boot/compressed/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 55f86349d547..e4f32a8e002a 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -112,7 +112,7 @@ endif targets := vmlinux vmlinux.lds \ piggy.$(suffix_y) piggy.$(suffix_y).o \ - font.o font.c head.o misc.o $(OBJS) + lib1funcs.o lib1funcs.S font.o font.c head.o misc.o $(OBJS) # Make sure files are removed during clean extra-y += piggy.gzip piggy.lzo piggy.lzma lib1funcs.S $(libfdt) $(libfdt_hdrs) @@ -147,7 +147,7 @@ LDFLAGS_vmlinux += -T # For __aeabi_uidivmod lib1funcs = $(obj)/lib1funcs.o -$(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE +$(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S $(call cmd,shipped) # We need to prevent any GOTOFF relocs being used with references -- cgit v1.2.3 From 18634fbff1f64df29af12a8b2ce335fc27019b27 Mon Sep 17 00:00:00 2001 From: Dan Willemsen Date: Wed, 14 Sep 2011 17:15:50 -0700 Subject: arm: tegra: Add ATAG_SERIAL parsing Bug 973078 Change-Id: I2860402c887db414717ce313101dc09e8b327f99 Signed-off-by: Chinmay Kamat Reviewed-on: http://git-master/r/108699 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Stephen Warren GVS: Gerrit_Virtual_Submit Tested-by: Nitin Kumbhar Reviewed-by: Dan Willemsen --- arch/arm/boot/compressed/atags_to_fdt.c | 5 +++++ arch/arm/kernel/devtree.c | 14 +++++++++++++- 2 files changed, 18 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c index 6ce11c481178..05c548875e3d 100644 --- a/arch/arm/boot/compressed/atags_to_fdt.c +++ b/arch/arm/boot/compressed/atags_to_fdt.c @@ -87,6 +87,11 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space) initrd_start); setprop_cell(fdt, "/chosen", "linux,initrd-end", initrd_start + initrd_size); + } else if (atag->hdr.tag == ATAG_SERIAL) { + uint32_t serial[2]; + serial[0] = cpu_to_fdt32(atag->u.serialnr.high); + serial[1] = cpu_to_fdt32(atag->u.serialnr.low); + setprop(fdt, "/", "serial-num", serial, 8); } } diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index 1a33e9d6bb1f..e855fcb71bf9 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -75,6 +75,9 @@ struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) unsigned int score, mdesc_score = ~1; unsigned long dt_root; const char *model; + __be32 *serial_prop; + u64 serial = 0; + unsigned long len; if (!dt_phys) return NULL; @@ -118,7 +121,16 @@ struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) model = of_get_flat_dt_prop(dt_root, "compatible", NULL); if (!model) model = ""; - pr_info("Machine: %s, model: %s\n", mdesc_best->name, model); + + serial_prop = of_get_flat_dt_prop(dt_root, "serial-num", &len); + if (serial_prop) { + serial = of_read_number(serial_prop, len / 4); + } + system_serial_high = serial >> 32; + system_serial_low = serial; + + pr_info("Machine: %s, model: %s, serial: %llu\n", mdesc_best->name, + model, serial); /* Retrieve various information from the /chosen node */ of_scan_flat_dt(early_init_dt_scan_chosen, boot_command_line); -- cgit v1.2.3 From 4193ddc2472c64a374639409fb3bd7609c307dcb Mon Sep 17 00:00:00 2001 From: Nitin Kumbhar Date: Mon, 7 May 2012 18:09:41 +0530 Subject: arm: tegra: read board info from device tree Read board_info data from device tree instead of ATAGs, if we're booting with device tree. Bug 1001225 Change-Id: I2d659252a6a91f723bf4bb6c74918774650b87e2 Original-Author: Dan Willemsen Signed-off-by: Nitin Kumbhar Reviewed-on: http://git-master/r/116604 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/common.c | 54 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 49 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index aa6f0192c5d2..b914d5d71462 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -638,11 +639,54 @@ __setup("audio_codec=", tegra_audio_codec_type); void tegra_get_board_info(struct board_info *bi) { - bi->board_id = (system_serial_high >> 16) & 0xFFFF; - bi->sku = (system_serial_high) & 0xFFFF; - bi->fab = (system_serial_low >> 24) & 0xFF; - bi->major_revision = (system_serial_low >> 16) & 0xFF; - bi->minor_revision = (system_serial_low >> 8) & 0xFF; +#ifdef CONFIG_OF + struct device_node *board_info; + u32 prop_val; + int err; + + board_info = of_find_node_by_path("/chosen/board_info"); + if (!IS_ERR_OR_NULL(board_info)) { + memset(bi, 0, sizeof(*bi)); + + err = of_property_read_u32(board_info, "id", &prop_val); + if (err) + pr_err("failed to read /chosen/board_info/id\n"); + else + bi->board_id = prop_val; + + err = of_property_read_u32(board_info, "sku", &prop_val); + if (err) + pr_err("failed to read /chosen/board_info/sku\n"); + else + bi->sku = prop_val; + + err = of_property_read_u32(board_info, "fab", &prop_val); + if (err) + pr_err("failed to read /chosen/board_info/fab\n"); + else + bi->fab = prop_val; + + err = of_property_read_u32(board_info, "major_revision", &prop_val); + if (err) + pr_err("failed to read /chosen/board_info/major_revision\n"); + else + bi->major_revision = prop_val; + + err = of_property_read_u32(board_info, "minor_revision", &prop_val); + if (err) + pr_err("failed to read /chosen/board_info/minor_revision\n"); + else + bi->minor_revision = prop_val; + } else { +#endif + bi->board_id = (system_serial_high >> 16) & 0xFFFF; + bi->sku = (system_serial_high) & 0xFFFF; + bi->fab = (system_serial_low >> 24) & 0xFF; + bi->major_revision = (system_serial_low >> 16) & 0xFF; + bi->minor_revision = (system_serial_low >> 8) & 0xFF; +#ifdef CONFIG_OF + } +#endif } static int __init tegra_pmu_board_info(char *info) -- cgit v1.2.3 From e1e3e20e168dd473047a695071b338f42a012c82 Mon Sep 17 00:00:00 2001 From: Dan Willemsen Date: Mon, 9 Apr 2012 18:06:13 -0700 Subject: arm/dt: Tegra: Add minimal Cardhu file We really just want the /chosen and compatible info for now, and use the existing board files for the rest of the support. We can gradually enhance this file as our internal support improves. Change-Id: If50378c128afb31d0d014c78d9f8f03c86b8d568 Signed-off-by: Dan Willemsen Reviewed-on: http://git-master/r/95477 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Stephen Warren GVS: Gerrit_Virtual_Submit Tested-by: Nitin Kumbhar --- arch/arm/boot/dts/tegra-cardhu.dts | 8 ++++++++ arch/arm/boot/dts/tegra30.dtsi | 5 +++++ arch/arm/mach-tegra/Makefile.boot | 1 + 3 files changed, 14 insertions(+) create mode 100644 arch/arm/boot/dts/tegra-cardhu.dts create mode 100644 arch/arm/boot/dts/tegra30.dtsi (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts new file mode 100644 index 000000000000..35dce0bfb191 --- /dev/null +++ b/arch/arm/boot/dts/tegra-cardhu.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +/include/ "tegra30.dtsi" + +/ { + model = "NVIDIA Tegra30 Cardhu evaluation board"; + compatible = "nvidia,cardhu", "nvidia,tegra30"; +}; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi new file mode 100644 index 000000000000..f568d44601a4 --- /dev/null +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -0,0 +1,5 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra30"; +}; diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index d8cb9173cdf7..c85167cb8574 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot @@ -8,3 +8,4 @@ initrd_phys-$(CONFIG_ARCH_TEGRA_3x_SOC) := 0x80800000 dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb +dtb-$(CONFIG_MACH_CARDHU) += tegra-cardhu.dtb -- cgit v1.2.3 From 5b0a5f9b64af08de1e2ce3b93f5b896ddfed93e5 Mon Sep 17 00:00:00 2001 From: Chinmay Kamat Date: Wed, 20 Jun 2012 14:09:33 -0700 Subject: arm/dt: Tegra: Add minimal ventana file We will gradually enhance this file as our internal support improves. Change-Id: I9343a14a89942226b1e3eb8aa0afa8c186c46a9e Signed-off-by: Chinmay Kamat Reviewed-on: http://git-master/r/110201 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Stephen Warren GVS: Gerrit_Virtual_Submit Tested-by: Nitin Kumbhar Reviewed-by: Dan Willemsen --- arch/arm/boot/dts/tegra-ventana.dts | 8 ++++++++ arch/arm/mach-tegra/Makefile.boot | 1 + 2 files changed, 9 insertions(+) create mode 100644 arch/arm/boot/dts/tegra-ventana.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts new file mode 100644 index 000000000000..39f199755d5c --- /dev/null +++ b/arch/arm/boot/dts/tegra-ventana.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "NVIDIA Tegra2 Ventana evaluation board"; + compatible = "nvidia,ventana", "nvidia,tegra20"; +}; diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index c85167cb8574..b68229f68f61 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot @@ -8,4 +8,5 @@ initrd_phys-$(CONFIG_ARCH_TEGRA_3x_SOC) := 0x80800000 dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb +dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb dtb-$(CONFIG_MACH_CARDHU) += tegra-cardhu.dtb -- cgit v1.2.3 From ca43c179c512eb14e56c3eb11412344307948367 Mon Sep 17 00:00:00 2001 From: Nitin Kumbhar Date: Wed, 16 May 2012 18:19:23 +0530 Subject: arm: tegra: enterprise: dt: add dts file with minimal info Add dts file to enable device tree support on enterprise platform. This currently adds only compatible info to dt. Bug 1001225 Change-Id: I4cc4093062d39baef9871b423840f5f2d01f25e9 Signed-off-by: Nitin Kumbhar Reviewed-on: http://git-master/r/116605 GVS: Gerrit_Virtual_Submit Reviewed-by: Stephen Warren Reviewed-by: Dan Willemsen --- arch/arm/boot/dts/tegra30-enterprise.dts | 8 ++++++++ arch/arm/mach-tegra/Makefile.boot | 1 + 2 files changed, 9 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-enterprise.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra30-enterprise.dts b/arch/arm/boot/dts/tegra30-enterprise.dts new file mode 100644 index 000000000000..c78821ca9b15 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-enterprise.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +/include/ "tegra30.dtsi" + +/ { + model = "NVIDIA Tegra30 Enterprise evaluation board"; + compatible = "nvidia,enterprise", "nvidia,tegra30"; +}; diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index b68229f68f61..929697be2629 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot @@ -10,3 +10,4 @@ dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb dtb-$(CONFIG_MACH_CARDHU) += tegra-cardhu.dtb +dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-enterprise.dtb -- cgit v1.2.3 From ff2c85532acf099a99a063b869c341bc113fc0ec Mon Sep 17 00:00:00 2001 From: Nitin Kumbhar Date: Wed, 13 Jun 2012 19:00:36 -0700 Subject: arm: tegra: whistler: dt: add dts file with minimal info Add dts file to enable device tree support on whistler platform. This currently adds only compatible info to dt. Bug 1001225 Change-Id: I3023639e817529e6bb18ed5fa92b8c35c12d45b8 Signed-off-by: Nitin Kumbhar Reviewed-on: http://git-master/r/116606 GVS: Gerrit_Virtual_Submit Reviewed-by: Stephen Warren Reviewed-by: Dan Willemsen --- arch/arm/boot/dts/tegra20-whistler.dts | 8 ++++++++ arch/arm/mach-tegra/Makefile.boot | 1 + 2 files changed, 9 insertions(+) create mode 100644 arch/arm/boot/dts/tegra20-whistler.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts new file mode 100644 index 000000000000..e3a5939a42aa --- /dev/null +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "NVIDIA Tegra20 Whistler evaluation board"; + compatible = "nvidia,whistler", "nvidia,tegra20"; +}; diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index 929697be2629..4d8452977a5e 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot @@ -9,5 +9,6 @@ initrd_phys-$(CONFIG_ARCH_TEGRA_3x_SOC) := 0x80800000 dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb +dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb dtb-$(CONFIG_MACH_CARDHU) += tegra-cardhu.dtb dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-enterprise.dtb -- cgit v1.2.3 From 1ef8cc928458d72cc312511def9165271f157dc9 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 11 Jun 2012 16:25:07 -0600 Subject: ARM: dt: tegra: rename board files to match SoC Most ARM ${board}.dts files are already named ${soc}-${board}.dts. This change modifies the Tegra board files to be named the same way for consistency. Once a related change is made in U-Boot, this will cause both U-Boot and the kernel to use the same names for the .dts files and SoC identifiers, thus allowing U-Boot's recently added "soc" and "board" environment variables to be used to construct the name of Tegra .dtb files, and hence allow board-generic U-Boot bootcmd scripts to be written. Signed-off-by: Stephen Warren (cherry picked from commit 702b0e4f2f2782962aab7d9a0a40ad68770bb1f6) Conflicts: arch/arm/boot/dts/tegra20-paz00.dts arch/arm/boot/dts/tegra20-trimslice.dts arch/arm/mach-tegra/Makefile.boot Change-Id: I4ec7605331c996d3aff84fc2fc37bcf06f0aba0b Reviewed-on: http://git-master/r/110202 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/boot/dts/tegra-cardhu.dts | 8 ---- arch/arm/boot/dts/tegra-harmony.dts | 70 ---------------------------------- arch/arm/boot/dts/tegra-seaboard.dts | 28 -------------- arch/arm/boot/dts/tegra-ventana.dts | 8 ---- arch/arm/boot/dts/tegra20-harmony.dts | 70 ++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/tegra20-seaboard.dts | 28 ++++++++++++++ arch/arm/boot/dts/tegra20-ventana.dts | 8 ++++ arch/arm/boot/dts/tegra30-cardhu.dts | 8 ++++ arch/arm/mach-tegra/Makefile.boot | 8 ++-- 9 files changed, 118 insertions(+), 118 deletions(-) delete mode 100644 arch/arm/boot/dts/tegra-cardhu.dts delete mode 100644 arch/arm/boot/dts/tegra-harmony.dts delete mode 100644 arch/arm/boot/dts/tegra-seaboard.dts delete mode 100644 arch/arm/boot/dts/tegra-ventana.dts create mode 100644 arch/arm/boot/dts/tegra20-harmony.dts create mode 100644 arch/arm/boot/dts/tegra20-seaboard.dts create mode 100644 arch/arm/boot/dts/tegra20-ventana.dts create mode 100644 arch/arm/boot/dts/tegra30-cardhu.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts deleted file mode 100644 index 35dce0bfb191..000000000000 --- a/arch/arm/boot/dts/tegra-cardhu.dts +++ /dev/null @@ -1,8 +0,0 @@ -/dts-v1/; - -/include/ "tegra30.dtsi" - -/ { - model = "NVIDIA Tegra30 Cardhu evaluation board"; - compatible = "nvidia,cardhu", "nvidia,tegra30"; -}; diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts deleted file mode 100644 index e5818668d091..000000000000 --- a/arch/arm/boot/dts/tegra-harmony.dts +++ /dev/null @@ -1,70 +0,0 @@ -/dts-v1/; - -/memreserve/ 0x1c000000 0x04000000; -/include/ "tegra20.dtsi" - -/ { - model = "NVIDIA Tegra2 Harmony evaluation board"; - compatible = "nvidia,harmony", "nvidia,tegra20"; - - chosen { - bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p2 rw rootwait"; - }; - - memory@0 { - reg = < 0x00000000 0x40000000 >; - }; - - i2c@7000c000 { - clock-frequency = <400000>; - - codec: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupts = < 347 >; - - gpio-controller; - #gpio-cells = <2>; - - /* 0x8000 = Not configured */ - gpio-cfg = < 0x8000 0x8000 0 0x8000 0x8000 >; - }; - }; - - i2c@7000c400 { - clock-frequency = <400000>; - }; - - i2c@7000c500 { - clock-frequency = <400000>; - }; - - i2c@7000d000 { - clock-frequency = <400000>; - }; - - sound { - compatible = "nvidia,harmony-sound", "nvidia,tegra-wm8903"; - - spkr-en-gpios = <&codec 2 0>; - hp-det-gpios = <&gpio 178 0>; - int-mic-en-gpios = <&gpio 184 0>; - ext-mic-en-gpios = <&gpio 185 0>; - }; - - serial@70006300 { - clock-frequency = < 216000000 >; - }; - - sdhci@c8000200 { - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 155 0>; /* gpio PT3 */ - }; - - sdhci@c8000600 { - cd-gpios = <&gpio 58 0>; /* gpio PH2 */ - wp-gpios = <&gpio 59 0>; /* gpio PH3 */ - power-gpios = <&gpio 70 0>; /* gpio PI6 */ - }; -}; diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts deleted file mode 100644 index 64cedca6fc79..000000000000 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ /dev/null @@ -1,28 +0,0 @@ -/dts-v1/; - -/memreserve/ 0x1c000000 0x04000000; -/include/ "tegra20.dtsi" - -/ { - model = "NVIDIA Seaboard"; - compatible = "nvidia,seaboard", "nvidia,tegra20"; - - chosen { - bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait"; - }; - - memory { - device_type = "memory"; - reg = < 0x00000000 0x40000000 >; - }; - - serial@70006300 { - clock-frequency = < 216000000 >; - }; - - sdhci@c8000400 { - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 70 0>; /* gpio PI6 */ - }; -}; diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts deleted file mode 100644 index 39f199755d5c..000000000000 --- a/arch/arm/boot/dts/tegra-ventana.dts +++ /dev/null @@ -1,8 +0,0 @@ -/dts-v1/; - -/include/ "tegra20.dtsi" - -/ { - model = "NVIDIA Tegra2 Ventana evaluation board"; - compatible = "nvidia,ventana", "nvidia,tegra20"; -}; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts new file mode 100644 index 000000000000..e5818668d091 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -0,0 +1,70 @@ +/dts-v1/; + +/memreserve/ 0x1c000000 0x04000000; +/include/ "tegra20.dtsi" + +/ { + model = "NVIDIA Tegra2 Harmony evaluation board"; + compatible = "nvidia,harmony", "nvidia,tegra20"; + + chosen { + bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p2 rw rootwait"; + }; + + memory@0 { + reg = < 0x00000000 0x40000000 >; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + + codec: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupts = < 347 >; + + gpio-controller; + #gpio-cells = <2>; + + /* 0x8000 = Not configured */ + gpio-cfg = < 0x8000 0x8000 0 0x8000 0x8000 >; + }; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + }; + + sound { + compatible = "nvidia,harmony-sound", "nvidia,tegra-wm8903"; + + spkr-en-gpios = <&codec 2 0>; + hp-det-gpios = <&gpio 178 0>; + int-mic-en-gpios = <&gpio 184 0>; + ext-mic-en-gpios = <&gpio 185 0>; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + sdhci@c8000200 { + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 155 0>; /* gpio PT3 */ + }; + + sdhci@c8000600 { + cd-gpios = <&gpio 58 0>; /* gpio PH2 */ + wp-gpios = <&gpio 59 0>; /* gpio PH3 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + }; +}; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts new file mode 100644 index 000000000000..64cedca6fc79 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -0,0 +1,28 @@ +/dts-v1/; + +/memreserve/ 0x1c000000 0x04000000; +/include/ "tegra20.dtsi" + +/ { + model = "NVIDIA Seaboard"; + compatible = "nvidia,seaboard", "nvidia,tegra20"; + + chosen { + bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait"; + }; + + memory { + device_type = "memory"; + reg = < 0x00000000 0x40000000 >; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + sdhci@c8000400 { + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + }; +}; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts new file mode 100644 index 000000000000..39f199755d5c --- /dev/null +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "NVIDIA Tegra2 Ventana evaluation board"; + compatible = "nvidia,ventana", "nvidia,tegra20"; +}; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dts b/arch/arm/boot/dts/tegra30-cardhu.dts new file mode 100644 index 000000000000..35dce0bfb191 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-cardhu.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +/include/ "tegra30.dtsi" + +/ { + model = "NVIDIA Tegra30 Cardhu evaluation board"; + compatible = "nvidia,cardhu", "nvidia,tegra30"; +}; diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index 4d8452977a5e..7eee71774a8a 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot @@ -6,9 +6,9 @@ zreladdr-$(CONFIG_ARCH_TEGRA_3x_SOC) := 0x80008000 params_phys-$(CONFIG_ARCH_TEGRA_3x_SOC) := 0x80000100 initrd_phys-$(CONFIG_ARCH_TEGRA_3x_SOC) := 0x80800000 -dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb -dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb -dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb +dtb-$(CONFIG_MACH_HARMONY) += tegra20-harmony.dtb +dtb-$(CONFIG_MACH_SEABOARD) += tegra20-seaboard.dtb +dtb-$(CONFIG_MACH_VENTANA) += tegra20-ventana.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb -dtb-$(CONFIG_MACH_CARDHU) += tegra-cardhu.dtb +dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu.dtb dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-enterprise.dtb -- cgit v1.2.3 From c8efa3093e01424063632253417a13eec462dc87 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 21 May 2012 14:44:26 -0600 Subject: ARM: tegra: make .dts compilation depend on Tegra2 support Update Makefile.boot to compile *.dts when the appropriate Tegra SoC support is enabled, rather than requiring Kconfig to list each board individually. Remove CONFIG_MACH_VENTANA now that it has no use. Signed-off-by: Stephen Warren (cherry picked from commit 9132b0ed57320996b16eafbf651a04e02ad29092) Conflicts: arch/arm/mach-tegra/Makefile.boot Change-Id: I730271346eff20005ad289dedc54c9c6681e0384 Reviewed-on: http://git-master/r/116607 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/Makefile.boot | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index 7eee71774a8a..6ca6212c711a 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot @@ -6,9 +6,9 @@ zreladdr-$(CONFIG_ARCH_TEGRA_3x_SOC) := 0x80008000 params_phys-$(CONFIG_ARCH_TEGRA_3x_SOC) := 0x80000100 initrd_phys-$(CONFIG_ARCH_TEGRA_3x_SOC) := 0x80800000 -dtb-$(CONFIG_MACH_HARMONY) += tegra20-harmony.dtb -dtb-$(CONFIG_MACH_SEABOARD) += tegra20-seaboard.dtb -dtb-$(CONFIG_MACH_VENTANA) += tegra20-ventana.dtb +dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-harmony.dtb +dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-seaboard.dtb +dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-ventana.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu.dtb dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-enterprise.dtb -- cgit v1.2.3 From df80522dd557e2759552b6c6b0f1f1c8ad1c5614 Mon Sep 17 00:00:00 2001 From: Dan Willemsen Date: Mon, 9 Apr 2012 18:08:04 -0700 Subject: ARM: tegra: cardhu: Add DT boot support Use the existing boardfile for everything, just match using DT. Change-Id: Ie12cad6ab0bfcb94538cd158dd9fc9ca85b91c98 Signed-off-by: Dan Willemsen Reviewed-on: http://git-master/r/95478 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-cardhu.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c index 242bbef30936..9fa78c502747 100644 --- a/arch/arm/mach-tegra/board-cardhu.c +++ b/arch/arm/mach-tegra/board-cardhu.c @@ -1461,6 +1461,11 @@ static void __init tegra_cardhu_reserve(void) tegra_ram_console_debug_reserve(SZ_1M); } +static const char *cardhu_dt_board_compat[] = { + "nvidia,cardhu", + NULL +}; + MACHINE_START(CARDHU, "cardhu") .boot_params = 0x80000100, .map_io = tegra_map_common_io, @@ -1469,4 +1474,5 @@ MACHINE_START(CARDHU, "cardhu") .init_irq = tegra_init_irq, .timer = &tegra_timer, .init_machine = tegra_cardhu_init, + .dt_compat = cardhu_dt_board_compat, MACHINE_END -- cgit v1.2.3 From 293b009a282e1508a4947d84463fdfe820445a50 Mon Sep 17 00:00:00 2001 From: Nitin Kumbhar Date: Mon, 30 Apr 2012 20:23:08 +0530 Subject: arm: ventana: add device tree support for ventana Enable device tree support for ventana by adding board compatible table. Bug 1001225 Change-Id: I3f20c1a7966aff1a8a5fbfc1a7ccf2790419be70 Signed-off-by: Nitin Kumbhar Reviewed-on: http://git-master/r/110203 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-ventana.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-ventana.c b/arch/arm/mach-tegra/board-ventana.c index 64db1c5206e8..e897275e4433 100644 --- a/arch/arm/mach-tegra/board-ventana.c +++ b/arch/arm/mach-tegra/board-ventana.c @@ -652,12 +652,18 @@ void __init tegra_ventana_reserve(void) tegra_ram_console_debug_reserve(SZ_1M); } +static const char *ventana_dt_board_compat[] = { + "nvidia,ventana", + NULL +}; + MACHINE_START(VENTANA, "ventana") .boot_params = 0x00000100, .map_io = tegra_map_common_io, - .reserve = tegra_ventana_reserve, .init_early = tegra_init_early, - .init_irq = tegra_init_irq, + .init_irq = tegra_init_irq, + .reserve = tegra_ventana_reserve, .timer = &tegra_timer, - .init_machine = tegra_ventana_init, + .init_machine = tegra_ventana_init, + .dt_compat = ventana_dt_board_compat, MACHINE_END -- cgit v1.2.3 From 6d68be701eeba639230a4b7beaa45f5fa4469628 Mon Sep 17 00:00:00 2001 From: Nitin Kumbhar Date: Mon, 7 May 2012 12:13:17 +0530 Subject: arm: enterprise: add device tree support for enterprise Enable device tree support for enterprise by adding board compatible table. Bug 1001225 Change-Id: I64038ce47771148f7cf2f1d53503d11729ac56b8 Signed-off-by: Nitin Kumbhar Reviewed-on: http://git-master/r/116608 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-enterprise.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c index 0df4167290c0..46078a82a9b1 100644 --- a/arch/arm/mach-tegra/board-enterprise.c +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -1035,6 +1035,11 @@ static void __init tegra_enterprise_reserve(void) tegra_ram_console_debug_reserve(SZ_1M); } +static const char *enterprise_dt_board_compat[] = { + "nvidia,enterprise", + NULL +}; + MACHINE_START(TEGRA_ENTERPRISE, "tegra_enterprise") .boot_params = 0x80000100, .map_io = tegra_map_common_io, @@ -1043,4 +1048,5 @@ MACHINE_START(TEGRA_ENTERPRISE, "tegra_enterprise") .init_irq = tegra_init_irq, .timer = &tegra_timer, .init_machine = tegra_enterprise_init, + .dt_compat = enterprise_dt_board_compat, MACHINE_END -- cgit v1.2.3 From 0c8ad3fc25b0097dd63516742b9f0133d10b3c20 Mon Sep 17 00:00:00 2001 From: Nitin Kumbhar Date: Wed, 13 Jun 2012 19:15:08 -0700 Subject: arm: whistler: add device tree support for whistler Enable device tree support for whistler by adding board compatible table. Bug 1001225 Change-Id: Ic945d70894fe2deb5039106e794b7fa51c5604bb Signed-off-by: Nitin Kumbhar Reviewed-on: http://git-master/r/116609 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-whistler.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-whistler.c b/arch/arm/mach-tegra/board-whistler.c index 92fa6e502abe..492367076170 100644 --- a/arch/arm/mach-tegra/board-whistler.c +++ b/arch/arm/mach-tegra/board-whistler.c @@ -539,12 +539,18 @@ void __init tegra_whistler_reserve(void) tegra_ram_console_debug_reserve(SZ_1M); } +static const char *whistler_dt_board_compat[] = { + "nvidia,whistler", + NULL +}; + MACHINE_START(WHISTLER, "whistler") .boot_params = 0x00000100, .map_io = tegra_map_common_io, - .reserve = tegra_whistler_reserve, .init_early = tegra_init_early, .init_irq = tegra_init_irq, + .reserve = tegra_whistler_reserve, .timer = &tegra_timer, .init_machine = tegra_whistler_init, + .dt_compat = whistler_dt_board_compat, MACHINE_END -- cgit v1.2.3 From 76fd6572b00e780a2a00cc2ee21b9f30d968cb5e Mon Sep 17 00:00:00 2001 From: Nitin Kumbhar Date: Thu, 3 May 2012 16:25:25 +0530 Subject: arm: config: tegra: android: enable device tree support Enable device tree support for tegra2/tegra3 based android platforms. Bug 1001225 Change-Id: I5caf6302b88d30cca66bfdb957c5b4f1a575a634 Signed-off-by: Nitin Kumbhar Reviewed-on: http://git-master/r/110204 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/configs/tegra3_android_defconfig | 2 ++ arch/arm/configs/tegra_android_defconfig | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/tegra3_android_defconfig b/arch/arm/configs/tegra3_android_defconfig index 825b6e3b00c1..7872f185cb6e 100644 --- a/arch/arm/configs/tegra3_android_defconfig +++ b/arch/arm/configs/tegra3_android_defconfig @@ -53,6 +53,7 @@ CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set CONFIG_HIGHMEM=y CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART=y +CONFIG_USE_OF=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CPU_FREQ=y @@ -186,6 +187,7 @@ CONFIG_CAIF=y CONFIG_NFC=y CONFIG_PN544_NFC=y # CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_MISC_DEVICES=y CONFIG_AD525X_DPOT=y diff --git a/arch/arm/configs/tegra_android_defconfig b/arch/arm/configs/tegra_android_defconfig index eb6abec87b70..fb5ae2a1d999 100644 --- a/arch/arm/configs/tegra_android_defconfig +++ b/arch/arm/configs/tegra_android_defconfig @@ -48,6 +48,7 @@ CONFIG_PREEMPT=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set CONFIG_HIGHMEM=y +CONFIG_USE_OF=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CPU_FREQ=y @@ -172,6 +173,7 @@ CONFIG_CFG80211=y CONFIG_RFKILL=y CONFIG_RFKILL_GPIO=y # CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_MISC_DEVICES=y CONFIG_AD525X_DPOT=y -- cgit v1.2.3 From 9bf22a62cd071336282e3fa5d999f898e77119d1 Mon Sep 17 00:00:00 2001 From: Hyung Taek Ryoo Date: Tue, 31 Jul 2012 15:43:34 -0700 Subject: arm: tegra: optimize L2 enable/disable paths for secureos For the CONFIG_TRUSTED_FOUNDATION code paths, differentiate L2 enable vs. reenable, which are different SMCs (won't trigger an invalidate in the case of a reenable). On an L2 disable SMC, optionally pass a 0 for the L2 ways arg, which skips the full clean/invalidate (and simply just disabled the L2). In order to safely skip flushing the L2 on the disable, we have to be careful what we dirty from the type we flush the L1 and disable the L2. Bug 939415 Signed-off-by: Chris Johnson Change-Id: I756d2ceda83d5d8d6bc5670218e9d874d5e5f62a Reviewed-on: http://git-master/r/119786 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/common.c | 118 ++++++++++++++++++------------------------ arch/arm/mach-tegra/headsmp.S | 7 +-- arch/arm/mach-tegra/pm.c | 28 ++++++---- arch/arm/mach-tegra/pm.h | 3 ++ arch/arm/mach-tegra/sleep.S | 79 +++++++++++++++++++++++----- 5 files changed, 144 insertions(+), 91 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index b914d5d71462..85eb11f64118 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -2,7 +2,7 @@ * arch/arm/mach-tegra/common.c * * Copyright (C) 2010 Google, Inc. - * Copyright (C) 2010-2012 NVIDIA Corporation + * Copyright (C) 2010-2012, NVIDIA Corporation. All rights reserved. * * Author: * Colin Cross @@ -226,61 +226,13 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { NULL, NULL, 0, 0}, }; -#ifdef CONFIG_CACHE_L2X0 #ifdef CONFIG_TRUSTED_FOUNDATIONS -static void tegra_cache_smc(bool enable, u32 arg) -{ - void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; - bool need_affinity_switch; - bool can_switch_affinity; - bool l2x0_enabled; - cpumask_t local_cpu_mask; - cpumask_t saved_cpu_mask; - unsigned long flags; - long ret; - - /* - * ISSUE : Some registers of PL310 controler must be written - * from Secure context (and from CPU0)! - * - * When called form Normal we obtain an abort or do nothing. - * Instructions that must be called in Secure: - * - Write to Control register (L2X0_CTRL==0x100) - * - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104) - * - Invalidate all entries (L2X0_INV_WAY==0x77C), - * mandatory at boot time. - * - Tag and Data RAM Latency Control Registers - * (0x108 & 0x10C) must be written in Secure. - */ - need_affinity_switch = (smp_processor_id() != 0); - can_switch_affinity = !irqs_disabled(); - - WARN_ON(need_affinity_switch && !can_switch_affinity); - if (need_affinity_switch && can_switch_affinity) { - cpu_set(0, local_cpu_mask); - sched_getaffinity(0, &saved_cpu_mask); - ret = sched_setaffinity(0, &local_cpu_mask); - WARN_ON(ret != 0); - } - - local_irq_save(flags); - l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1; - if (enable && !l2x0_enabled) - tegra_generic_smc(0xFFFFF100, 0x00000001, arg); - else if (!enable && l2x0_enabled) - tegra_generic_smc(0xFFFFF100, 0x00000002, arg); - local_irq_restore(flags); - - if (need_affinity_switch && can_switch_affinity) { - ret = sched_setaffinity(0, &saved_cpu_mask); - WARN_ON(ret != 0); - } -} +#define CACHE_LINE_SIZE 32 -static void tegra_l2x0_disable(void) +static inline void tegra_l2x0_disable_tz(void) { - unsigned long flags; static u32 l2x0_way_mask; + BUG_ON(smp_processor_id() != 0); if (!l2x0_way_mask) { void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; @@ -291,30 +243,62 @@ static void tegra_l2x0_disable(void) ways = (aux_ctrl & (1 << 16)) ? 16 : 8; l2x0_way_mask = (1 << ways) - 1; } +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + /* flush all ways on disable */ + tegra_generic_smc_uncached(0xFFFFF100, 0x00000002, l2x0_way_mask); +#elif defined(CONFIG_ARCH_TEGRA_3x_SOC) + if (tegra_is_cpu_in_lp2(0)) { + register unsigned long sp asm ("sp"); - local_irq_save(flags); - tegra_cache_smc(false, l2x0_way_mask); - local_irq_restore(flags); + /* flush only the stack, if entering LP2 */ + __cpuc_flush_dcache_area((void *)sp, (CACHE_LINE_SIZE * 2)); + outer_flush_range(__pa(sp), __pa(sp) + (CACHE_LINE_SIZE * 2)); + + /* pass zero arg, so secureos flushes only its workspace */ + tegra_generic_smc_uncached(0xFFFFF100, 0x00000002, 0x0); + } else { + /* flush all ways on disable, if entering LP0/LP1 */ + tegra_generic_smc_uncached(0xFFFFF100, + 0x00000002, l2x0_way_mask); + } +#endif } -#endif /* CONFIG_TRUSTED_FOUNDATIONS */ -void tegra_init_cache(bool init) +static inline void tegra_init_cache_tz(bool init) { void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; u32 aux_ctrl; -#ifdef CONFIG_TRUSTED_FOUNDATIONS - /* issue the SMC to enable the L2 */ - aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL); - tegra_cache_smc(true, aux_ctrl); + BUG_ON(smp_processor_id() != 0); + + if (init) { + /* init L2 from secureos */ + tegra_generic_smc(0xFFFFF100, 0x00000001, 0x0); + + /* common init called for outer call hookup */ + aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL); + l2x0_init(p, aux_ctrl, 0xFFFFFFFF); - /* after init, reread aux_ctrl and register handlers */ - aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL); - l2x0_init(p, aux_ctrl, 0xFFFFFFFF); + /* use our outer_disable() routine */ + outer_cache.disable = tegra_l2x0_disable_tz; + } else { + /* reenable L2 in secureos */ + aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL); + tegra_generic_smc_uncached(0xFFFFF100, 0x00000004, aux_ctrl); + } +} +#endif /* CONFIG_TRUSTED_FOUNDATIONS */ - /* override outer_disable() with our disable */ - outer_cache.disable = tegra_l2x0_disable; +#ifdef CONFIG_CACHE_L2X0 +void tegra_init_cache(bool init) +{ +#ifdef CONFIG_TRUSTED_FOUNDATIONS + /* enable/re-enable of L2 handled by secureos */ + return tegra_init_cache_tz(init); #else + void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; + u32 aux_ctrl; + #if defined(CONFIG_ARCH_TEGRA_2x_SOC) writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL); writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL); @@ -364,7 +348,7 @@ void tegra_init_cache(bool init) l2x0_enable(); #endif } -#endif +#endif /* CONFIG_CACHE_L2X0 */ static void __init tegra_init_power(void) { diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 4e28a558cc38..63852b99b3d3 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -3,7 +3,7 @@ * * CPU initialization routines for Tegra SoCs * - * Copyright (c) 2009-2011, NVIDIA Corporation. + * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved. * Copyright (c) 2011 Google, Inc. * Author: Colin Cross * Gary King @@ -90,8 +90,9 @@ ENTRY(tegra_resume) str r1, [r0] #ifdef CONFIG_TRUSTED_FOUNDATIONS - /* wake up (should have specified args?) */ - bl tegra_generic_smc + /* wake up */ + mov r0, #0x00000003 + bl tegra_generic_smc_local #endif b tegra_cpu_resume_phys diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 9049e37ca05a..d251e57626aa 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -3,7 +3,7 @@ * * CPU complex suspend & resume functions for Tegra SoCs * - * Copyright (c) 2009-2012, NVIDIA Corporation. + * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -546,17 +546,27 @@ bool tegra_set_cpu_in_lp2(int cpu) return last_cpu; } +bool tegra_is_cpu_in_lp2(int cpu) +{ + bool in_lp2; + + spin_lock(&tegra_lp2_lock); + in_lp2 = cpumask_test_cpu(cpu, &tegra_in_lp2); + spin_unlock(&tegra_lp2_lock); + return in_lp2; +} + static void tegra_sleep_core(enum tegra_suspend_mode mode, unsigned long v2p) { #ifdef CONFIG_TRUSTED_FOUNDATIONS if (mode == TEGRA_SUSPEND_LP0) { - tegra_generic_smc(0xFFFFFFFC, 0xFFFFFFE3, - virt_to_phys(tegra_resume)); + tegra_generic_smc_uncached(0xFFFFFFFC, 0xFFFFFFE3, + virt_to_phys(tegra_resume)); } else { - tegra_generic_smc(0xFFFFFFFC, 0xFFFFFFE6, - (TEGRA_RESET_HANDLER_BASE + - tegra_cpu_reset_handler_offset)); + tegra_generic_smc_uncached(0xFFFFFFFC, 0xFFFFFFE6, + (TEGRA_RESET_HANDLER_BASE + + tegra_cpu_reset_handler_offset)); } #endif #ifdef CONFIG_ARCH_TEGRA_2x_SOC @@ -569,9 +579,9 @@ static void tegra_sleep_core(enum tegra_suspend_mode mode, static inline void tegra_sleep_cpu(unsigned long v2p) { #ifdef CONFIG_TRUSTED_FOUNDATIONS - tegra_generic_smc(0xFFFFFFFC, 0xFFFFFFE4, - (TEGRA_RESET_HANDLER_BASE + - tegra_cpu_reset_handler_offset)); + tegra_generic_smc_uncached(0xFFFFFFFC, 0xFFFFFFE4, + (TEGRA_RESET_HANDLER_BASE + + tegra_cpu_reset_handler_offset)); #endif tegra_sleep_cpu_save(v2p); } diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 498170648819..b78e9b1abc00 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -75,6 +75,7 @@ unsigned long tegra_cpu_power_off_time(void); unsigned long tegra_cpu_lp2_min_residency(void); void tegra_clear_cpu_in_lp2(int cpu); bool tegra_set_cpu_in_lp2(int cpu); +bool tegra_is_cpu_in_lp2(int cpu); int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags); @@ -222,6 +223,8 @@ extern bool tegra_all_cpus_booted __read_mostly; #ifdef CONFIG_TRUSTED_FOUNDATIONS void tegra_generic_smc(u32 type, u32 subtype, u32 arg); +void tegra_generic_smc_local(u32 type, u32 subtype, u32 arg); +void tegra_generic_smc_uncached(u32 type, u32 subtype, u32 arg); #endif /* The debug channel uart base physical address */ diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 973c8677bafe..e86795c5c46a 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/sleep.S * - * Copyright (c) 2010-2011, NVIDIA Corporation. + * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. * Copyright (c) 2011, Google, Inc. * * Author: Colin Cross @@ -440,28 +440,83 @@ ENDPROC(tegra_cpu_pllp) #endif #ifdef CONFIG_TRUSTED_FOUNDATIONS + /* - * tegra_generic_smc + * Confirm we're issuing this SMC from CPU0 (only one + * currently supported) and issue the instruction. * * r0 = smc type * r1 = smc subtype * r2 = argument passed to smc - * - * issues SMC (secure monitor call) instruction with - * the specified parameters. */ -ENTRY(tegra_generic_smc) - adr r3, __tegra_smc_stack - stmia r3, {r4-r12, lr} +.macro smc_issue_smc tmp + cpu_id \tmp + cmp \tmp, #0 + bne . mov r3, #0 mov r4, #0 dsb smc #0 - adr r3, __tegra_smc_stack - ldmia r3, {r4-r12, pc} +.endm + +/* + * Issue SMC with ctx kept on an uncached stack + */ +ENTRY(tegra_generic_smc_uncached) +#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_CACHE_L2X0) + mov32 r3, tegra_cpu_context @ borrow CPU0's non-cached + ldr r3, [r3] @ context grows up + stmia r3, {r4-r12, sp, lr} + + smc_issue_smc r5 + + mov32 r3, tegra_cpu_context @ borrow CPU0's non-cached + ldr r3, [r3] @ context grows up + ldmia r3, {r4-r12, sp, pc} +#else + mov pc, lr +#endif +ENDPROC(tegra_generic_smc_uncached) + +/* + * Issue SMC with ctx kept on a cacheable stack + * (args in R0, R1, R2 and R3 holds save/restore ptr) + */ +ENTRY(tegra_generic_smc_cached) + stmia r3, {r4-r12, sp, lr} + adr r4, __tegra_smc_current_ctx @ save current ptr + str r3, [r4] + + smc_issue_smc r5 + + adr r4, __tegra_smc_current_ctx @ restore from saved ptr + ldr r3, [r4] + ldmia r3, {r4-r12, sp, pc} +ENDPROC(tegra_generic_smc_cached) + .type __tegra_smc_current_ctx, %object +__tegra_smc_current_ctx: + .long 0 + .size __tegra_smc_current_ctx, . - __tegra_smc_current_ctx + +#define TEGRA_SMC_SAVED_WORDS 11 + +/* SMC issued using the current cacheable SP stack */ +ENTRY(tegra_generic_smc) + mov r3, sp @ use current stack + sub r3, #(TEGRA_SMC_SAVED_WORDS << 2) @ context grows up + b tegra_generic_smc_cached ENDPROC(tegra_generic_smc) - .type __tegra_smc_stack, %object + +/* SMC issued using a local cacheable stack */ +ENTRY(tegra_generic_smc_local) + adr r3, __tegra_smc_stack @ use local stack + b tegra_generic_smc_cached +ENDPROC(tegra_generic_smc_local) + .align L1_CACHE_SHIFT + .type __tegra_smc_stack, %object __tegra_smc_stack: - .long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .rept TEGRA_SMC_SAVED_WORDS + .long 0 + .endr .size __tegra_smc_stack, . - __tegra_smc_stack #endif -- cgit v1.2.3 From fd4bc846766e336ab02abcae9d6cde5912a4d8a8 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Sun, 5 Aug 2012 13:15:51 +0530 Subject: ARM: tegra: enterprise: remove macro for common fixed regs The macro FIXED_REGS_COMMON used in only one place and it is no more common across A02 and A04 and hence removing this. Also remove unnecessary back slash. Change-Id: If56512a3f957d06406e9baf369dd409feb82b55b Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/121132 Reviewed-by: Bitan Biswas --- arch/arm/mach-tegra/board-enterprise-power.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index f07e61c95287..9f3f8ae79dbf 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -661,25 +661,21 @@ FIXED_REG(8, lcd_1v8_en, NULL, TEGRA_GPIO_PB2, true, 1800, 0, 0); #define ADD_FIXED_REG(_name) (&fixed_reg_##_name##_dev) - -#define FIXED_REGS_COMMON \ - ADD_FIXED_REG(pmu_5v15_en), \ - ADD_FIXED_REG(pmu_hdmi_5v0_en), \ - ADD_FIXED_REG(vdd_fuse_en), \ - ADD_FIXED_REG(cam_ldo_2v8_en), \ - ADD_FIXED_REG(cam_ldo_1v8_en) - static struct platform_device *fixed_regs_devices_a02[] = { - ADD_FIXED_REG(pmu_5v15_en), \ - ADD_FIXED_REG(pmu_3v3_en), \ - ADD_FIXED_REG(pmu_hdmi_5v0_en), \ - ADD_FIXED_REG(vdd_fuse_en), \ - ADD_FIXED_REG(cam_ldo_2v8_en), \ + ADD_FIXED_REG(pmu_5v15_en), + ADD_FIXED_REG(pmu_3v3_en), + ADD_FIXED_REG(pmu_hdmi_5v0_en), + ADD_FIXED_REG(vdd_fuse_en), + ADD_FIXED_REG(cam_ldo_2v8_en), ADD_FIXED_REG(cam_ldo_1v8_en) }; static struct platform_device *fixed_regs_devices_a03[] = { - FIXED_REGS_COMMON, + ADD_FIXED_REG(pmu_5v15_en), + ADD_FIXED_REG(pmu_hdmi_5v0_en), + ADD_FIXED_REG(vdd_fuse_en), + ADD_FIXED_REG(cam_ldo_2v8_en), + ADD_FIXED_REG(cam_ldo_1v8_en), ADD_FIXED_REG(vdd_sdmmc3_2v85_en), ADD_FIXED_REG(lcd_1v8_en), }; -- cgit v1.2.3 From 0bf836b37cef4345629ecd8efb1a3e7f30628525 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 1 Aug 2012 16:25:25 +0530 Subject: rtc: tps80031: register as mfd sub device register RTC driver of TPS80031 as mfd sub driver in place of adding it as a sub devices. This is inline with the mfd driver policy. Change-Id: I2f9c13478a1e85c9670dd7bc576ec761f2e24733 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/121133 Reviewed-by: Automatic_Commit_Validation_User --- arch/arm/mach-tegra/board-enterprise-power.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index 9f3f8ae79dbf..4bf7f03e8d6d 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -333,13 +333,6 @@ static struct tps80031_bg_platform_data battery_gauge_data = { .battery_present = 1, }; -#define TPS_RTC() \ - { \ - .id = 0, \ - .name = "rtc_tps80031", \ - .platform_data = &rtc_data, \ - } - #define TPS_BATTERY() \ { \ .name = "tps80031-charger", \ @@ -356,14 +349,12 @@ static struct tps80031_bg_platform_data battery_gauge_data = { } #define TPS80031_DEVS_COMMON \ - TPS_RTC(), \ TPS_BATTERY(), \ TPS_BATTERY_GAUGE(), \ TPS_GPADC() static struct tps80031_subdev_info tps80031_devs[] = { - TPS_RTC(), TPS_BATTERY(), TPS_BATTERY_GAUGE(), TPS_GPADC() @@ -451,6 +442,7 @@ static struct tps80031_platform_data tps_platform = { .clk32k_init_data = clk32k_idata, .clk32k_init_data_size = ARRAY_SIZE(clk32k_idata), .use_power_off = true, + .rtc_pdata = &rtc_data, }; static struct i2c_board_info __initdata enterprise_regulators[] = { -- cgit v1.2.3 From 65f9c0c5286dcccd3ed38d479215414c9cf00f1f Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 1 Aug 2012 16:34:12 +0530 Subject: power: tps80031: battery-gauge: register as mfd sub device Register battery gauge driver of TPS80031 as mfd sub driver in place of adding it as a sub devices. This is inline with the mfd driver policy. Change-Id: I15765be19fc138695de2d813e5fa025400747c86 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/121134 Reviewed-by: Bitan Biswas --- arch/arm/mach-tegra/board-enterprise-power.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index 4bf7f03e8d6d..b908edbbca30 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -338,11 +338,6 @@ static struct tps80031_bg_platform_data battery_gauge_data = { .name = "tps80031-charger", \ .platform_data = &bcharger_pdata, \ } -#define TPS_BATTERY_GAUGE() \ - { \ - .name = "tps80031-battery-gauge", \ - .platform_data = &battery_gauge_data, \ - } #define TPS_GPADC() \ { \ .name = "tps80031-gpadc", \ @@ -350,13 +345,11 @@ static struct tps80031_bg_platform_data battery_gauge_data = { #define TPS80031_DEVS_COMMON \ TPS_BATTERY(), \ - TPS_BATTERY_GAUGE(), \ TPS_GPADC() static struct tps80031_subdev_info tps80031_devs[] = { TPS_BATTERY(), - TPS_BATTERY_GAUGE(), TPS_GPADC() }; @@ -443,6 +436,7 @@ static struct tps80031_platform_data tps_platform = { .clk32k_init_data_size = ARRAY_SIZE(clk32k_idata), .use_power_off = true, .rtc_pdata = &rtc_data, + .bg_pdata = &battery_gauge_data, }; static struct i2c_board_info __initdata enterprise_regulators[] = { -- cgit v1.2.3 From 0a93f5c4bb384c3a0fd71b5bc3d231f834554dfd Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 1 Aug 2012 16:44:29 +0530 Subject: power: tps80031: battery-charger: register as mfd sub device Register battery charger driver of TPS80031 as mfd sub driver in place of adding it as a sub devices. This is inline with the mfd driver policy. Change-Id: I8cff39f5c9b22434f7c5b9d4ed9f3865ff4c0001 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/121135 Reviewed-by: Bitan Biswas --- arch/arm/mach-tegra/board-enterprise-power.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index b908edbbca30..86f0bcd05253 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -333,23 +333,16 @@ static struct tps80031_bg_platform_data battery_gauge_data = { .battery_present = 1, }; -#define TPS_BATTERY() \ - { \ - .name = "tps80031-charger", \ - .platform_data = &bcharger_pdata, \ - } #define TPS_GPADC() \ { \ .name = "tps80031-gpadc", \ } #define TPS80031_DEVS_COMMON \ - TPS_BATTERY(), \ TPS_GPADC() static struct tps80031_subdev_info tps80031_devs[] = { - TPS_BATTERY(), TPS_GPADC() }; @@ -437,6 +430,7 @@ static struct tps80031_platform_data tps_platform = { .use_power_off = true, .rtc_pdata = &rtc_data, .bg_pdata = &battery_gauge_data, + .battery_charger_pdata = &bcharger_pdata, }; static struct i2c_board_info __initdata enterprise_regulators[] = { -- cgit v1.2.3 From bb4dfdc63e617afe49eb727f70e6638d7e8759c2 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Sun, 5 Aug 2012 13:27:08 +0530 Subject: mfd: tps80031: gpadc: register as mfd sub device Register General Purpose ADC driver of TPS80031 as mfd sub driver in place of adding it as a sub devices. This is inline with the mfd driver policy. Change-Id: Ib3f86f05716baef96ee534eec5ae262627c6a853 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/121136 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas --- arch/arm/mach-tegra/board-enterprise-power.c | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index 86f0bcd05253..cfcfe9e61ec5 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -333,19 +333,6 @@ static struct tps80031_bg_platform_data battery_gauge_data = { .battery_present = 1, }; -#define TPS_GPADC() \ - { \ - .name = "tps80031-gpadc", \ - } - -#define TPS80031_DEVS_COMMON \ - TPS_GPADC() - - -static struct tps80031_subdev_info tps80031_devs[] = { - TPS_GPADC() -}; - #define TPS_REG_PDATA(_id, _sname) &pdata_##_id##_##_sname static struct tps80031_regulator_platform_data *tps80031_reg_pdata_a02[] = { TPS_REG_PDATA(vio, a02), -- cgit v1.2.3 From 20f1a101e669063e050a26e722bbc292d389352a Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Sun, 5 Aug 2012 13:31:20 +0530 Subject: mfd: tps80031: remove support for subdevs registration The mfd sub devices should get added through the mfd_add_devices() not through legacy style of adding sub devices. Change-Id: If275d41629d799f1e22d95fd442ebe7d3ace448e Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/121137 Reviewed-by: Bitan Biswas --- arch/arm/mach-tegra/board-enterprise-power.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index cfcfe9e61ec5..f974c49c9f50 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -721,9 +721,6 @@ int __init enterprise_regulator_init(void) battery_gauge_data.battery_present = 0; } - tps_platform.num_subdevs = ARRAY_SIZE(tps80031_devs); - tps_platform.subdevs = tps80031_devs; - if (board_info.fab < BOARD_FAB_A03) { tps_platform.num_regulator_pdata = ARRAY_SIZE(tps80031_reg_pdata_a02); tps_platform.regulator_pdata = tps80031_reg_pdata_a02; -- cgit v1.2.3 From 7f9749a0050aa4bbe770f1a061f5ae8c8545dfa8 Mon Sep 17 00:00:00 2001 From: Bitan Biswas Date: Mon, 6 Aug 2012 11:17:25 +0530 Subject: ARM: tegra: lp0 WAKE2 status clear Tegra pmc WAKE2 status registers also need to be cleared before re-entering lp0 mode. Change-Id: I1bd5c48baf86ba23d0352594e97c360d363ce991 Signed-off-by: Bitan Biswas Reviewed-on: http://git-master/r/121185 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan --- arch/arm/mach-tegra/pm-irq.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/pm-irq.c b/arch/arm/mach-tegra/pm-irq.c index 4a3f3c31830c..4e3c06835b2f 100644 --- a/arch/arm/mach-tegra/pm-irq.c +++ b/arch/arm/mach-tegra/pm-irq.c @@ -284,10 +284,15 @@ static int tegra_pm_irq_syscore_suspend(void) wake_enb = 0xffffffff; } - /* Clear PMC Wake Status register while going to suspend */ + /* Clear PMC Wake Status registers while going to suspend */ temp = readl(pmc + PMC_WAKE_STATUS); if (temp) pmc_32kwritel(temp, PMC_WAKE_STATUS); +#ifndef CONFIG_ARCH_TEGRA_2x_SOC + temp = readl(pmc + PMC_WAKE2_STATUS); + if (temp) + pmc_32kwritel(temp, PMC_WAKE2_STATUS); +#endif write_pmc_wake_level(wake_level); -- cgit v1.2.3 From 42910ff9b782d27629c038c4d2f6e0024ee205f1 Mon Sep 17 00:00:00 2001 From: Rakesh Bodla Date: Thu, 2 Aug 2012 17:51:13 +0530 Subject: arm: configs: tegra3: Enable boost cpu frequency Enabling boost CPU frequency for tegra gadget to improve USB performance. Bug 1020850 Change-Id: Ic36686399f8ebd84c24f9d3cb73792ce3bef90be Signed-off-by: Rakesh Bodla Reviewed-on: http://git-master/r/120351 Reviewed-by: Lokesh Pathak Tested-by: Lokesh Pathak --- arch/arm/configs/tegra3_android_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/tegra3_android_defconfig b/arch/arm/configs/tegra3_android_defconfig index 7872f185cb6e..bd20372d6196 100644 --- a/arch/arm/configs/tegra3_android_defconfig +++ b/arch/arm/configs/tegra3_android_defconfig @@ -34,6 +34,7 @@ CONFIG_TEGRA_EMC_SCALING_ENABLE=y CONFIG_TEGRA_CLOCK_DEBUG_WRITE=y CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND=y CONFIG_USB_HOTPLUG=y +CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ=800 CONFIG_TEGRA_DYNAMIC_PWRDET=y CONFIG_TEGRA_USB_MODEM_POWER=y CONFIG_TEGRA_BB_XMM_POWER=y -- cgit v1.2.3 From 39f69f846f7dec18b920a48eb8bd1de6d291dd6e Mon Sep 17 00:00:00 2001 From: Ashwin Joshi Date: Fri, 27 Jul 2012 15:54:22 +0530 Subject: ARM: tegra: e1853: Add board support for e1853 E1853 is T30 based Automotive platform. Changes done: 1. New board specific files added 2. Added new machine number for E1853 3. Added pinmux configuration for E1853 Bug 966833 Bug 1018258 Signed-off-by: Ashwin Joshi Change-Id: Ibf1093f59e10a0a5cfa42a177c21c0db01983196 Reviewed-on: http://git-master/r/118000 Tested-by: Ashwin Joshi Reviewed-by: Sandeep Trasi (cherry picked from commit ad9dd1b3242f23c0f46eaf92ab49f495c06f330f) Reviewed-on: http://git-master/r/119580 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-e1853-panel.c | 146 ++++++ arch/arm/mach-tegra/board-e1853-pinmux.c | 503 +++++++++++++++++++++ arch/arm/mach-tegra/board-e1853-sdhci.c | 83 ++++ arch/arm/mach-tegra/board-e1853.c | 391 ++++++++++++++++ arch/arm/mach-tegra/board-e1853.h | 28 ++ .../mach-tegra/include/mach/tegra_e1853_pdata.h | 55 +++ arch/arm/tools/mach-types | 1 + 7 files changed, 1207 insertions(+) create mode 100644 arch/arm/mach-tegra/board-e1853-panel.c create mode 100644 arch/arm/mach-tegra/board-e1853-pinmux.c create mode 100644 arch/arm/mach-tegra/board-e1853-sdhci.c create mode 100644 arch/arm/mach-tegra/board-e1853.c create mode 100644 arch/arm/mach-tegra/board-e1853.h create mode 100644 arch/arm/mach-tegra/include/mach/tegra_e1853_pdata.h (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-e1853-panel.c b/arch/arm/mach-tegra/board-e1853-panel.c new file mode 100644 index 000000000000..1e6c7ab60907 --- /dev/null +++ b/arch/arm/mach-tegra/board-e1853-panel.c @@ -0,0 +1,146 @@ +/* + * arch/arm/mach-tegra/board-e1853-panel.c + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "board.h" +#include "devices.h" +#include "tegra3_host1x_devices.h" + +static int e1853_panel_enable(void) +{ + return 0; +} + +static int e1853_panel_disable(void) +{ + return 0; +} + +static struct tegra_dc_mode e1853_panel_modes[] = { + { + /* 800x480@60 */ + .pclk = 32460000, + .h_ref_to_sync = 1, + .v_ref_to_sync = 1, + .h_sync_width = 64, + .v_sync_width = 3, + .h_back_porch = 128, + .v_back_porch = 22, + .h_front_porch = 64, + .v_front_porch = 20, + .h_active = 800, + .v_active = 480, + }, +}; + +static struct tegra_fb_data e1853_fb_data = { + .win = 0, + .xres = 800, + .yres = 480, + .bits_per_pixel = 32, +}; + +static struct tegra_dc_out e1853_disp1_out = { + .align = TEGRA_DC_ALIGN_MSB, + .order = TEGRA_DC_ORDER_RED_BLUE, + .type = TEGRA_DC_OUT_RGB, + .modes = e1853_panel_modes, + .n_modes = ARRAY_SIZE(e1853_panel_modes), + .enable = e1853_panel_enable, + .disable = e1853_panel_disable, +}; + +static struct tegra_dc_platform_data e1853_disp1_pdata = { + .flags = TEGRA_DC_FLAG_ENABLED, + .default_out = &e1853_disp1_out, + .emc_clk_rate = 300000000, + .fb = &e1853_fb_data, +}; + +static struct nvmap_platform_carveout e1853_carveouts[] = { + [0] = { + .name = "iram", + .usage_mask = NVMAP_HEAP_CARVEOUT_IRAM, + .base = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE, + .size = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE, + .buddy_size = 0, /* no buddy allocation for IRAM */ + }, + [1] = { + .name = "generic-0", + .usage_mask = NVMAP_HEAP_CARVEOUT_GENERIC, + .base = 0, /* Filled in by e1853_panel_init() */ + .size = 0, /* Filled in by e1853_panel_init() */ + .buddy_size = SZ_32K, + }, +}; + +static struct nvmap_platform_data e1853_nvmap_data = { + .carveouts = e1853_carveouts, + .nr_carveouts = ARRAY_SIZE(e1853_carveouts), +}; + +static struct platform_device *e1853_gfx_devices[] __initdata = { + &tegra_nvmap_device, +}; + +int __init e1853_panel_init(void) +{ + int err; + struct resource *res; + + e1853_carveouts[1].base = tegra_carveout_start; + e1853_carveouts[1].size = tegra_carveout_size; + tegra_nvmap_device.dev.platform_data = &e1853_nvmap_data; + tegra_disp1_device.dev.platform_data = &e1853_disp1_pdata; + + res = nvhost_get_resource_byname(&tegra_disp1_device, + IORESOURCE_MEM, "fbmem"); + if (!res) { + pr_err("No memory resources\n"); + return -ENODEV; + } + res->start = tegra_fb_start; + res->end = tegra_fb_start + tegra_fb_size - 1; + +#ifdef CONFIG_TEGRA_GRHOST + err = tegra3_register_host1x_devices(); + if (err) + return err; +#endif + + err = platform_add_devices(e1853_gfx_devices, + ARRAY_SIZE(e1853_gfx_devices)); + if (!err) + err = nvhost_device_register(&tegra_disp1_device); + +#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_NVAVP) + if (!err) + err = nvhost_device_register(&nvavp_device); +#endif + return err; +} diff --git a/arch/arm/mach-tegra/board-e1853-pinmux.c b/arch/arm/mach-tegra/board-e1853-pinmux.c new file mode 100644 index 000000000000..3f25291609fe --- /dev/null +++ b/arch/arm/mach-tegra/board-e1853-pinmux.c @@ -0,0 +1,503 @@ +/* + * arch/arm/mach-tegra/board-e1853-pinmux.c + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +#include +#include +#include +#include +#include "board.h" +#include "board-e1853.h" +#include "gpio-names.h" + +#define DEFAULT_DRIVE(_name) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_DISABLE, \ + .schmitt = TEGRA_SCHMITT_ENABLE, \ + .drive = TEGRA_DRIVE_DIV_1, \ + .pull_down = TEGRA_PULL_31, \ + .pull_up = TEGRA_PULL_31, \ + .slew_rising = TEGRA_SLEW_SLOWEST, \ + .slew_falling = TEGRA_SLEW_SLOWEST, \ + } +/* Setting the drive strength of pins + * hsm: Enable High speed mode (ENABLE/DISABLE) + * Schimit: Enable/disable schimit (ENABLE/DISABLE) + * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8) + * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive + * strength code. Value from 0 to 31. + * pullup_drive - drive up (rising edge) - Driver Output Pull-Up drive + * strength code. Value from 0 to 31. + * pulldn_slew - Driver Output Pull-Up slew control code - 2bit code + * code 11 is least slewing of signal. code 00 is highest + * slewing of the signal. + * Value - FASTEST, FAST, SLOW, SLOWEST + * pullup_slew - Driver Output Pull-Down slew control code - + * code 11 is least slewing of signal. code 00 is highest + * slewing of the signal. + * Value - FASTEST, FAST, SLOW, SLOWEST + */ +#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_##_hsm, \ + .schmitt = TEGRA_SCHMITT_##_schmitt, \ + .drive = TEGRA_DRIVE_##_drive, \ + .pull_down = TEGRA_PULL_##_pulldn_drive, \ + .pull_up = TEGRA_PULL_##_pullup_drive, \ + .slew_rising = TEGRA_SLEW_##_pulldn_slew, \ + .slew_falling = TEGRA_SLEW_##_pullup_slew, \ + } + +/* !!!FIXME!!!! Update drive strength with characterized value */ +static __initdata struct tegra_drive_pingroup_config e1853_drive_pinmux[] = { + /* ATC1 CFG */ + SET_DRIVE(AT1, ENABLE, ENABLE, DIV_1, 0, 0, SLOWEST, SLOWEST), + /* ATC2 CFG */ + SET_DRIVE(AT2, ENABLE, ENABLE, DIV_1, 0, 0, SLOWEST, SLOWEST), + /* ATC3 CFG */ + SET_DRIVE(AT3, ENABLE, ENABLE, DIV_1, 0, 0, SLOWEST, SLOWEST), + /* ATC4 CFG */ + SET_DRIVE(AT4, DISABLE, DISABLE, DIV_1, 0, 0, SLOWEST, SLOWEST), + + /* All I2C pins are driven to maximum drive strength */ + /* GEN1 I2C */ + SET_DRIVE(DBG, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* GEN2 I2C */ + SET_DRIVE(AT5, DISABLE, ENABLE, DIV_1, 12, 30, FASTEST, FASTEST), + + /* DDC I2C */ + SET_DRIVE(DDC, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* PWR_I2C */ + SET_DRIVE(AO1, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* SDMMC4 */ + SET_DRIVE(GME, DISABLE, ENABLE, DIV_1, 22, 18, SLOWEST, SLOWEST), + SET_DRIVE(GMF, DISABLE, ENABLE, DIV_1, 0, 0, SLOWEST, SLOWEST), + SET_DRIVE(GMG, DISABLE, ENABLE, DIV_1, 15, 6, SLOWEST, SLOWEST), + SET_DRIVE(GMH, DISABLE, ENABLE, DIV_1, 12, 6, SLOWEST, SLOWEST), + + /* LCD */ + SET_DRIVE(LCD1, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + SET_DRIVE(LCD2, DISABLE, ENABLE, DIV_1, 2, 2, FASTEST, FASTEST), + + /* DAP2 */ + SET_DRIVE(DAP2, ENABLE, ENABLE, DIV_1, 0, 0, SLOWEST, SLOWEST), + /* DAP4 */ + SET_DRIVE(DAP4, ENABLE, ENABLE, DIV_1, 0, 0, SLOWEST, SLOWEST), + /* DBG */ + SET_DRIVE(DBG, ENABLE, ENABLE, DIV_1, 20, 0, SLOWEST, SLOWEST), + /* SPI */ + SET_DRIVE(SPI, ENABLE, ENABLE, DIV_1, 0, 0, SLOWEST, SLOWEST), + /* UAA */ + SET_DRIVE(UAA, DISABLE, DISABLE, DIV_1, 0, 0, SLOWEST, SLOWEST), + /* UART2 */ + SET_DRIVE(UART2, ENABLE, ENABLE, DIV_1, 0, 0, SLOWEST, SLOWEST), + /* UART3 */ + SET_DRIVE(UART3, ENABLE, ENABLE, DIV_1, 0, 0, SLOWEST, SLOWEST), + /* GME */ + SET_DRIVE(GME, DISABLE, ENABLE, DIV_1, 1, 4, SLOWEST, SLOWEST), + /* GMF */ + SET_DRIVE(GMF, DISABLE, ENABLE, DIV_1, 0, 0, SLOWEST, SLOWEST), + /* GMG */ + SET_DRIVE(GMG, DISABLE, ENABLE, DIV_1, 3, 0, SLOWEST, SLOWEST), + /* GMH */ + SET_DRIVE(GMH, DISABLE, ENABLE, DIV_1, 0, 12, SLOWEST, SLOWEST), + + /* I2S/TDM */ +#ifdef CONFIG_TEGRA_MODS + SET_DRIVE(DAP1, ENABLE, ENABLE, DIV_1, 20, 20, SLOWEST, SLOWEST), + SET_DRIVE(DAP3, ENABLE, ENABLE, DIV_1, 20, 20, SLOWEST, SLOWEST), +#else + SET_DRIVE(DAP1, ENABLE, ENABLE, DIV_1, 3, 3, SLOWEST, SLOWEST), + SET_DRIVE(DAP3, ENABLE, ENABLE, DIV_1, 3, 3, SLOWEST, SLOWEST), +#endif + + /* SPI */ + SET_DRIVE(UAD, DISABLE, ENABLE, DIV_1, 4, 1, SLOWEST, SLOWEST), + SET_DRIVE(UAB, DISABLE, ENABLE, DIV_1, 4, 1, SLOWEST, SLOWEST), + + /* SDMMC 3 */ + SET_DRIVE(SDIO3, DISABLE, DISABLE, DIV_1, 46, 42, FAST, FAST), +}; + +#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io) \ + { \ + .pingroup = TEGRA_PINGROUP_##_pingroup, \ + .func = TEGRA_MUX_##_mux, \ + .pupd = TEGRA_PUPD_##_pupd, \ + .tristate = TEGRA_TRI_##_tri, \ + .io = TEGRA_PIN_##_io, \ + .lock = TEGRA_PIN_LOCK_DEFAULT, \ + .od = TEGRA_PIN_OD_DEFAULT, \ + .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \ + { \ + .pingroup = TEGRA_PINGROUP_##_pingroup, \ + .func = TEGRA_MUX_##_mux, \ + .pupd = TEGRA_PUPD_##_pupd, \ + .tristate = TEGRA_TRI_##_tri, \ + .io = TEGRA_PIN_##_io, \ + .lock = TEGRA_PIN_LOCK_##_lock, \ + .od = TEGRA_PIN_OD_##_od, \ + .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \ + } + +#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \ + { \ + .pingroup = TEGRA_PINGROUP_##_pingroup, \ + .func = TEGRA_MUX_##_mux, \ + .pupd = TEGRA_PUPD_##_pupd, \ + .tristate = TEGRA_TRI_##_tri, \ + .io = TEGRA_PIN_##_io, \ + .lock = TEGRA_PIN_LOCK_##_lock, \ + .od = TEGRA_PIN_OD_DEFAULT, \ + .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \ + } + +static __initdata struct tegra_pingroup_config e1853_pinmux_common[] = { + + /* CLK-EXTCLK1 */ + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), + + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, PULL_UP, NORMAL, INPUT), + + /* SDMMC2 pinmux */ + DEFAULT_PINMUX(KB_ROW10, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW11, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW13, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW14, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW15, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW6, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW7, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW9, SDMMC2, PULL_UP, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, PULL_UP, NORMAL, INPUT), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C3 pinmux */ + I2C_PINMUX(CAM_I2C_SCL, I2C3, PULL_UP, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SDA, I2C3, PULL_UP, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C4 pinmux */ + I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* PowerI2C pinmux */ + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* UART1 pinmux */ + DEFAULT_PINMUX(GPIO_PU0, UARTA, PULL_UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU1, UARTA, NORMAL, NORMAL, INPUT), + + /* UART2 pinmux */ + DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD, IRDA, PULL_UP, NORMAL, OUTPUT), + + /* UART3 pinmux */ + DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_TXD, UARTC, PULL_UP, NORMAL, OUTPUT), + + /* UART4 pinmux */ + DEFAULT_PINMUX(ULPI_CLK, UARTD, PULL_UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT), + + /* SPI2 pinmux */ + DEFAULT_PINMUX(ULPI_DATA4, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7, SPI2, NORMAL, NORMAL, INPUT), + + /* SPI3 pinmux */ + DEFAULT_PINMUX(ULPI_DATA0, SPI3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA1, SPI3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2, SPI3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3, SPI3, NORMAL, NORMAL, INPUT), + + /* SPI5 pinmux */ + DEFAULT_PINMUX(LCD_SCK, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS0_N, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDIN, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDOUT, SPI5, NORMAL, NORMAL, INPUT), + + /* DAP1 */ + DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), + + /* DAP2 */ + DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), + + /* I2S1 */ + DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), + + /* I2S3 */ + DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), + + /* NOR pinmux */ + DEFAULT_PINMUX(SDMMC4_DAT0, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT1, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT3, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT4, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT5, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT6, GMI, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(GMI_A16, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A17, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19, GMI, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(GMI_AD0, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD1, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD3, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD4, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD5, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD6, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD7, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD8, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD9, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD10, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD11, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD12, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD13, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD14, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD15, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_ADV_N, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CLK, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS0_N, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_OE_N, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_RST_N, GMI, PULL_UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_WAIT, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_WR_N, GMI, NORMAL, NORMAL, OUTPUT), + + /* DISPLAY pinmux */ + DEFAULT_PINMUX(LCD_D0, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D1, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D2, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D3, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D4, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D5, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D6, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D7, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D8, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D9, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D10, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D11, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D12, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D13, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D14, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D15, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D16, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D17, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D18, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D19, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D20, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D22, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_HSYNC, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_PCLK, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_VSYNC, DISPLAYA, NORMAL, NORMAL, OUTPUT), + + /* PCIE */ + DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, PULL_UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, PULL_UP, NORMAL, OUTPUT), + + VI_PINMUX(VI_D2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D8, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D9, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_PCLK, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_HSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_VSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + /* pin config for gpios */ + DEFAULT_PINMUX(PEX_L2_CLKREQ_N, RSVD2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_PRSNT_N, RSVD2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N, RSVD2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC0, RSVD1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC1, RSVD1, PULL_UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_NXT, RSVD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_STP, RSVD, PULL_DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_VSYNC, RSVD1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_HSYNC, RSVD1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR1, RSVD1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR2, RSVD, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_PRSNT_N, RSVD2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV2, RSVD1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7, RSVD, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(CLK_32K_OUT, RSVD1, PULL_DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK3_REQ, RSVD1, PULL_DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV0, RSVD, PULL_DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV1, RSVD, PULL_DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_M1, RSVD1, PULL_DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(VI_MCLK, VI, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_WR_N, RSVD, PULL_DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_PRSNT_N, RSVD2, PULL_DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N, RSVD2, PULL_DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_WAKE_N, RSVD2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_INT, RSVD, PULL_DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW1, RSVD2, PULL_DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW2, RSVD2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW3, RSVD2, PULL_UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW4, RSVD3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(VI_D10, RSVD1, PULL_DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(VI_D11, RSVD1, PULL_UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_PWR0, DISPLAYA, PULL_DOWN, NORMAL, INPUT), + + /* + * unused pins: tristate them all. + */ + DEFAULT_PINMUX(SPI2_CS0_N, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI2_MOSI, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI2_MISO, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PU2, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PU3, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PU4, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PU5, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PU6, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(CLK1_REQ, RSVD2, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI2_CS1_N, SPI2, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPDIF_OUT, SAFE, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(CAM_MCLK, POPSDMMC4, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PCC1, POPSDMMC4, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PCC2, POPSDMMC4, PULL_UP, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB0, POPSDMMC4, PULL_UP, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB3, POPSDMMC4, PULL_UP, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB4, POPSDMMC4, PULL_UP, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB5, POPSDMMC4, PULL_UP, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB6, POPSDMMC4, PULL_UP, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB7, POPSDMMC4, PULL_UP, TRISTATE, OUTPUT), + +}; + +int __init e1853_pinmux_init(void) +{ + tegra_pinmux_config_table(e1853_pinmux_common, + ARRAY_SIZE(e1853_pinmux_common)); + tegra_drive_pinmux_config_table(e1853_drive_pinmux, + ARRAY_SIZE(e1853_drive_pinmux)); + return 0; +} + +static struct gpio e1853_sku8_gpios[] = { + {TEGRA_GPIO_PV0, GPIOF_IN, "v0"}, + {TEGRA_GPIO_PV1, GPIOF_IN, "v1"}, + {TEGRA_GPIO_PY2, GPIOF_OUT_INIT_HIGH, "y2"}, + {TEGRA_GPIO_PY3, GPIOF_IN, "y3"}, + {TEGRA_GPIO_PV6, GPIOF_IN, "v6"}, + {TEGRA_GPIO_PV7, GPIOF_IN, "v7"}, + {TEGRA_GPIO_PW0, GPIOF_IN, "w0"}, + {TEGRA_GPIO_PD2, GPIOF_OUT_INIT_HIGH, "d2"}, + {TEGRA_GPIO_PW1, GPIOF_IN, "w1"}, + {TEGRA_GPIO_PB2, GPIOF_IN, "b2"}, + {TEGRA_GPIO_PC1, GPIOF_IN, "c1"}, + {TEGRA_GPIO_PC6, GPIOF_IN, "c6"}, + {TEGRA_GPIO_PZ3, GPIOF_IN, "z3"}, + {TEGRA_GPIO_PDD0, GPIOF_IN, "dd0"}, + {TEGRA_GPIO_PDD4, GPIOF_IN, "dd4"}, + {TEGRA_GPIO_PCC7, GPIOF_IN, "cc7"}, + {TEGRA_GPIO_PDD7, GPIOF_IN, "dd7"}, + {TEGRA_GPIO_PCC6, GPIOF_IN, "cc6"}, + {TEGRA_GPIO_PDD3, GPIOF_IN, "dd3"}, + {TEGRA_GPIO_PV2, GPIOF_IN, "v2"}, + {TEGRA_GPIO_PA0, GPIOF_OUT_INIT_LOW, "a0"}, + {TEGRA_GPIO_PR1, GPIOF_OUT_INIT_LOW, "r1"}, + {TEGRA_GPIO_PR2, GPIOF_IN, "r2"}, + {TEGRA_GPIO_PR3, GPIOF_IN, "r3"}, + {TEGRA_GPIO_PR4, GPIOF_IN, "r4"}, + {TEGRA_GPIO_PEE1, GPIOF_IN, "ee1"}, + {TEGRA_GPIO_PT2, GPIOF_OUT_INIT_LOW, "t2"}, + {TEGRA_GPIO_PT3, GPIOF_OUT_INIT_HIGH, "t3"}, + {TEGRA_GPIO_PT1, GPIOF_IN, "t1"}, +}; +int __init e1853_gpio_init(void) +{ + int i, pin_count = 0; + struct gpio *gpios_info = NULL; + gpios_info = e1853_sku8_gpios; + pin_count = ARRAY_SIZE(e1853_sku8_gpios); + + gpio_request_array(gpios_info, pin_count); + for (i = 0; i < pin_count; i++) { + tegra_gpio_enable(gpios_info[i].gpio); + gpio_export(gpios_info[i].gpio, true); + } + return 0; +} diff --git a/arch/arm/mach-tegra/board-e1853-sdhci.c b/arch/arm/mach-tegra/board-e1853-sdhci.c new file mode 100644 index 000000000000..5446bb46df15 --- /dev/null +++ b/arch/arm/mach-tegra/board-e1853-sdhci.c @@ -0,0 +1,83 @@ +/* + * arch/arm/mach-tegra/board-e1853-sdhci.c + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "gpio-names.h" +#include "board.h" +#include "board-e1853.h" +#include "devices.h" + +static struct tegra_sdhci_platform_data tegra_sdhci_platform_data1 = { + .cd_gpio = -1, + .wp_gpio = -1, + .power_gpio = -1, + .is_8bit = false, +}; + +static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = { + .cd_gpio = -1, + .wp_gpio = -1, + .power_gpio = -1, + .is_8bit = 1, + .mmc_data = { + .built_in = 1, + } +}; + +static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = { + .cd_gpio = TEGRA_GPIO_PN6, + .wp_gpio = TEGRA_GPIO_PD4, + .power_gpio = TEGRA_GPIO_PN7, + .is_8bit = false, +}; + +static struct tegra_sdhci_platform_data tegra_sdhci_platform_data4 = { + .cd_gpio = -1, + .wp_gpio = -1, + .power_gpio = -1, + .is_8bit = true, +}; + +int __init e1853_sdhci_init(void) +{ + tegra_sdhci_device1.dev.platform_data = &tegra_sdhci_platform_data1; + tegra_sdhci_device2.dev.platform_data = &tegra_sdhci_platform_data2; + tegra_sdhci_device3.dev.platform_data = &tegra_sdhci_platform_data3; + tegra_sdhci_device4.dev.platform_data = &tegra_sdhci_platform_data4; + + platform_device_register(&tegra_sdhci_device1); + platform_device_register(&tegra_sdhci_device2); + platform_device_register(&tegra_sdhci_device3); + platform_device_register(&tegra_sdhci_device4); + + return 0; +} diff --git a/arch/arm/mach-tegra/board-e1853.c b/arch/arm/mach-tegra/board-e1853.c new file mode 100644 index 000000000000..9379ec3b3f18 --- /dev/null +++ b/arch/arm/mach-tegra/board-e1853.c @@ -0,0 +1,391 @@ +/* + * arch/arm/mach-tegra/board-e1853.c + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" +#include "clock.h" +#include "board-e1853.h" +#include "devices.h" +#include "gpio-names.h" +#include "fuse.h" + +static __initdata struct tegra_clk_init_table e1853_clk_init_table[] = { + /* name parent rate enabled */ + { "pll_m", NULL, 0, true}, + { "hda", "pll_p", 108000000, false}, + { "hda2codec_2x", "pll_p", 48000000, false}, + { "pwm", "clk_32k", 32768, false}, + { "blink", "clk_32k", 32768, true}, + { "pll_a", NULL, 552960000, false}, + /* audio cif clock should be faster than i2s */ + { "pll_a_out0", NULL, 24576000, false}, + { "d_audio", "pll_a_out0", 24576000, false}, + { "nor", "pll_p", 86500000, true}, + { "uarta", "pll_p", 480000000, true}, + { "uartb", "pll_p", 480000000, true}, + { "uartc", "pll_p", 480000000, true}, + { "uartd", "pll_p", 480000000, true}, + { "sdmmc2", "pll_p", 52000000, true}, + { "sbc2", "pll_m", 100000000, true}, + { "sbc3", "pll_m", 100000000, true}, + { "sbc4", "pll_m", 100000000, true}, + { "sbc5", "pll_m", 100000000, true}, + { "sbc6", "pll_m", 100000000, true}, + { "cpu_g", "cclk_g", 900000000, true}, + { "i2s0", "pll_a_out0", 24576000, false}, + { "i2s1", "pll_a_out0", 24576000, false}, + { "i2s2", "pll_a_out0", 24576000, false}, + { "i2s3", "pll_a_out0", 24576000, false}, + { "i2s4", "pll_a_out0", 24576000, false}, + { "audio0", "i2s0_sync", 12288000, false}, + { "audio1", "i2s1_sync", 12288000, false}, + { "audio2", "i2s2_sync", 12288000, false}, + { "audio3", "i2s3_sync", 12288000, false}, + { "audio4", "i2s4_sync", 12288000, false}, + { "apbif", "clk_m", 12000000, false}, + { "dam0", "clk_m", 12000000, true}, + { "dam1", "clk_m", 12000000, true}, + { "dam2", "clk_m", 12000000, true}, + { "vi", "pll_p", 470000000, false}, + { "vi_sensor", "pll_p", 150000000, false}, + { "vde", "pll_c", 484000000, true}, + { "host1x", "pll_c", 242000000, true}, + { "mpe", "pll_c", 484000000, true}, + { "se", "pll_m", 625000000, true}, + { "i2c1", "pll_p", 3200000, true}, + { "i2c2", "pll_p", 3200000, true}, + { "i2c3", "pll_p", 3200000, true}, + { "i2c4", "pll_p", 3200000, true}, + { "i2c5", "pll_p", 3200000, true}, + { "sdmmc2", "pll_p", 104000000, false}, + {"wake.sclk", NULL, 334000000, true }, + { NULL, NULL, 0, 0}, +}; + +static struct tegra_i2c_platform_data e1853_i2c1_platform_data = { + .adapter_nr = 0, + .bus_count = 1, + .bus_clk_rate = { 100000, 0 }, +}; + +static struct tegra_i2c_platform_data e1853_i2c2_platform_data = { + .adapter_nr = 1, + .bus_count = 1, + .bus_clk_rate = { 100000, 0 }, + .is_clkon_always = true, +}; + +static struct tegra_i2c_platform_data e1853_i2c4_platform_data = { + .adapter_nr = 3, + .bus_count = 1, + .bus_clk_rate = { 100000, 0 }, +}; + +static struct tegra_i2c_platform_data e1853_i2c5_platform_data = { + .adapter_nr = 4, + .bus_count = 1, + .bus_clk_rate = { 100000, 0 }, +}; + +static struct tegra_pci_platform_data e1853_pci_platform_data = { + .port_status[0] = 1, + .port_status[1] = 1, + .port_status[2] = 1, + .use_dock_detect = 0, + .gpio = 0, +}; + +static void e1853_pcie_init(void) +{ + tegra_pci_device.dev.platform_data = &e1853_pci_platform_data; + platform_device_register(&tegra_pci_device); +} + +static void e1853_i2c_init(void) +{ + tegra_i2c_device1.dev.platform_data = &e1853_i2c1_platform_data; + tegra_i2c_device2.dev.platform_data = &e1853_i2c2_platform_data; + tegra_i2c_device4.dev.platform_data = &e1853_i2c4_platform_data; + tegra_i2c_device5.dev.platform_data = &e1853_i2c5_platform_data; + + platform_device_register(&tegra_i2c_device5); + platform_device_register(&tegra_i2c_device4); + platform_device_register(&tegra_i2c_device2); + platform_device_register(&tegra_i2c_device1); +} + +static struct platform_device *e1853_uart_devices[] __initdata = { + &tegra_uarta_device, + &tegra_uartb_device, + &tegra_uartc_device, + &tegra_uartd_device, +}; +static struct clk *debug_uart_clk; + +static void __init uart_debug_init(void) +{ + /* UARTA is the debug port. */ + pr_info("Selecting UARTA as the debug console\n"); + e1853_uart_devices[0] = &debug_uarta_device; + debug_uart_clk = clk_get_sys("serial8250.0", "uarta"); +} + +static void __init e1853_uart_init(void) +{ + /* Register low speed only if it is selected */ + if (!is_tegra_debug_uartport_hs()) { + uart_debug_init(); + /* Clock enable for the debug channel */ + if (!IS_ERR_OR_NULL(debug_uart_clk)) { + pr_info("The debug console clock name is %s\n", + debug_uart_clk->name); + clk_enable(debug_uart_clk); + clk_set_rate(debug_uart_clk, 408000000); + } else { + pr_err("Not getting the clock %s for debug console\n", + debug_uart_clk->name); + } + } + + platform_add_devices(e1853_uart_devices, + ARRAY_SIZE(e1853_uart_devices)); +} + +#if defined(CONFIG_SPI_TEGRA) && defined(CONFIG_SPI_SPIDEV) +static struct spi_board_info tegra_spi_devices[] __initdata = { + { + .modalias = "spidev", + .bus_num = 1, + .chip_select = 1, + .mode = SPI_MODE_0, + .max_speed_hz = 18000000, + .platform_data = NULL, + .irq = 0, + }, + { + .modalias = "spidev", + .bus_num = 2, + .chip_select = 1, + .mode = SPI_MODE_0, + .max_speed_hz = 18000000, + .platform_data = NULL, + .irq = 0, + }, + { + .modalias = "spidev", + .bus_num = 4, + .chip_select = 2, + .mode = SPI_MODE_0, + .max_speed_hz = 18000000, + .platform_data = NULL, + .irq = 0, + }, +}; + +static void __init e1853_register_spidev(void) +{ + spi_register_board_info(tegra_spi_devices, + ARRAY_SIZE(tegra_spi_devices)); +} +#else +#define e1853_register_spidev() do {} while (0) +#endif + + +static void e1853_spi_init(void) +{ + tegra_spi_device3.name = "spi_slave_tegra"; + platform_device_register(&tegra_spi_device2); + platform_device_register(&tegra_spi_device3); + platform_device_register(&tegra_spi_device5); + e1853_register_spidev(); +} + +static struct platform_device tegra_camera = { + .name = "tegra_camera", + .id = -1, +}; + +static struct platform_device *e1853_devices[] __initdata = { +#if defined(CONFIG_TEGRA_IOVMM_SMMU) + &tegra_smmu_device, +#endif +#if defined(CONFIG_TEGRA_AVP) + &tegra_avp_device, +#endif + &tegra_camera, + &tegra_wdt0_device +}; + +static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = { + .port_otg = false, + .has_hostpc = true, + .phy_intf = TEGRA_USB_PHY_INTF_UTMI, + .op_mode = TEGRA_USB_OPMODE_HOST, + .u_data.host = { + .vbus_gpio = -1, + .vbus_reg = NULL, + .hot_plug = false, + .remote_wakeup_supported = true, + .power_off_on_suspend = true, + }, + .u_cfg.utmi = { + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .elastic_limit = 16, + .term_range_adj = 6, + .xcvr_setup = 63, + .xcvr_setup_offset = 6, + .xcvr_use_fuses = 1, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + .xcvr_use_lsb = 1, + }, +}; + +static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = { + .port_otg = false, + .has_hostpc = true, + .phy_intf = TEGRA_USB_PHY_INTF_UTMI, + .op_mode = TEGRA_USB_OPMODE_HOST, + .u_data.host = { + .vbus_gpio = -1, + .vbus_reg = NULL, + .hot_plug = false, + .remote_wakeup_supported = true, + .power_off_on_suspend = true, + }, + .u_cfg.utmi = { + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .elastic_limit = 16, + .term_range_adj = 6, + .xcvr_setup = 63, + .xcvr_setup_offset = 6, + .xcvr_use_fuses = 1, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + .xcvr_use_lsb = 1, + }, +}; + +static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = { + .port_otg = false, + .has_hostpc = true, + .phy_intf = TEGRA_USB_PHY_INTF_UTMI, + .op_mode = TEGRA_USB_OPMODE_HOST, + .u_data.host = { + .vbus_gpio = -1, + .vbus_reg = NULL, + .hot_plug = false, + .remote_wakeup_supported = true, + .power_off_on_suspend = true, + }, + .u_cfg.utmi = { + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .elastic_limit = 16, + .term_range_adj = 6, + .xcvr_setup = 63, + .xcvr_setup_offset = 6, + .xcvr_use_fuses = 1, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + .xcvr_use_lsb = 1, + }, +}; + +static void e1853_usb_init(void) +{ + tegra_ehci1_device.dev.platform_data = &tegra_ehci1_utmi_pdata; + platform_device_register(&tegra_ehci1_device); + + tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata; + platform_device_register(&tegra_ehci2_device); + + tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata; + platform_device_register(&tegra_ehci3_device); +} + +static void __init tegra_e1853_init(void) +{ + tegra_init_board_info(); + tegra_clk_init_from_table(e1853_clk_init_table); + e1853_pinmux_init(); + e1853_i2c_init(); + e1853_gpio_init(); + e1853_uart_init(); + e1853_usb_init(); + e1853_sdhci_init(); + e1853_spi_init(); + platform_add_devices(e1853_devices, ARRAY_SIZE(e1853_devices)); + e1853_panel_init(); + e1853_pcie_init(); +} + +static void __init tegra_e1853_reserve(void) +{ +#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) + tegra_reserve(0, SZ_8M, 0); +#else + tegra_reserve(SZ_128M, SZ_8M, 0); +#endif +} + +MACHINE_START(E1853, "e1853") + .boot_params = 0x80000100, + .init_irq = tegra_init_irq, + .init_early = tegra_init_early, + .init_machine = tegra_e1853_init, + .map_io = tegra_map_common_io, + .reserve = tegra_e1853_reserve, + .timer = &tegra_timer, +MACHINE_END diff --git a/arch/arm/mach-tegra/board-e1853.h b/arch/arm/mach-tegra/board-e1853.h new file mode 100644 index 000000000000..58b8ab8725af --- /dev/null +++ b/arch/arm/mach-tegra/board-e1853.h @@ -0,0 +1,28 @@ +/* + * arch/arm/mach-tegra/e1853/board-e1853.h + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _MACH_TEGRA_BOARD_E1853_H +#define _MACH_TEGRA_BOARD_E1853_H + +int e1853_sdhci_init(void); +int e1853_pinmux_init(void); +int e1853_panel_init(void); +int e1853_gpio_init(void); +int e1853_pins_state_init(void); + +#endif diff --git a/arch/arm/mach-tegra/include/mach/tegra_e1853_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_e1853_pdata.h new file mode 100644 index 000000000000..633f04855e6e --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/tegra_e1853_pdata.h @@ -0,0 +1,55 @@ +/* + * arch/arm/mach-tegra/include/mach/tegra_e1853_pdata.h + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +#ifndef __MACH_TEGRA_E1853_PDATA_H +#define __MACH_TEGRA_E1853_PDATA_H + +#define NUM_AUDIO_CONTROLLERS 4 + +/* data format supported */ +enum i2s_data_format { + format_i2s = 0x1, + format_dsp = 0x2, + format_rjm = 0x4, + format_ljm = 0x8, + format_tdm = 0x10 +}; + +struct codec_info_s { + /* Name of the Codec Dai on the system */ + char *codec_dai_name; + /* Name of the I2S controller dai its connected to */ + char *cpu_dai_name; + char *codec_name; /* Name of the Codec Driver */ + char *name; /* Name of the Codec-Dai-Link */ + char *pcm_driver; /* Name of the PCM driver */ + enum i2s_data_format i2s_format; + int master; /* Codec is Master or Slave */ + /* TDM format setttings */ + int num_slots; /* Number of TDM slots */ + int slot_width; /* Width of each slot */ + int rx_mask; /* Number of Rx Enabled slots */ + int tx_mask; /* Number of Tx Enabled slots */ + +}; + +struct tegra_e1853_platform_data { + struct codec_info_s codec_info[NUM_AUDIO_CONTROLLERS]; +}; +#endif diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 9e31c03f3663..e15301d86c68 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -1117,3 +1117,4 @@ tegra_enterprise MACH_TEGRA_ENTERPRISE TEGRA_ENTERPRISE 3512 p1852 MACH_P1852 P1852 3651 kai MACH_KAI KAI 3897 p852 MACH_P852 P852 3667 +e1853 MACH_E1853 E1853 4241 -- cgit v1.2.3 From 22e07ac3680f9397a50b3badc5abc4dad355425e Mon Sep 17 00:00:00 2001 From: Ashwin Joshi Date: Thu, 26 Jul 2012 12:55:49 +0530 Subject: ARM: tegra: e1853: Add e1853 defconfig Add a defconfig file for E1853 board Bug 966833 Bug 1018258 Signed-off-by: Ashwin Joshi Change-Id: I7cbde666acbe13fcaca2f56d877e0b4872756c17 Reviewed-on: http://git-master/r/118281 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Ashwin Joshi Reviewed-by: Bhavesh Parekh Reviewed-by: Sandeep Trasi (cherry picked from commit 465ba7c85429964a7937a6683376d72e396ebe47) Reviewed-on: http://git-master/r/119650 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/configs/tegra_e1853_gnu_linux_defconfig | 219 +++++++++++++++++++++++ 1 file changed, 219 insertions(+) create mode 100644 arch/arm/configs/tegra_e1853_gnu_linux_defconfig (limited to 'arch') diff --git a/arch/arm/configs/tegra_e1853_gnu_linux_defconfig b/arch/arm/configs/tegra_e1853_gnu_linux_defconfig new file mode 100644 index 000000000000..8272a7e46d96 --- /dev/null +++ b/arch/arm/configs/tegra_e1853_gnu_linux_defconfig @@ -0,0 +1,219 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_CROSS_COMPILE="arm-eabi-" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_PANIC_TIMEOUT=10 +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_ELF_CORE is not set +CONFIG_ASHMEM=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_TEGRA=y +CONFIG_GPIO_PCA953X=y +CONFIG_ARCH_TEGRA_3x_SOC=y +CONFIG_TEGRA_PCI=y +CONFIG_MACH_E1853=y +CONFIG_TEGRA_PWM=y +CONFIG_TEGRA_TDM=y +# CONFIG_TEGRA_CPU_DVFS is not set +CONFIG_TEGRA_CLOCK_DEBUG_WRITE=y +# CONFIG_TEGRA_MC_EARLY_ACK is not set +CONFIG_ARM_ERRATA_743622=y +CONFIG_ARM_ERRATA_751472=y +CONFIG_ARM_ERRATA_752520=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_SMP=y +CONFIG_HOTPLUG_CPU=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="mem=448@2048M console=ttyS0,115200n8 earlyprintk init=/bin/ash" +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_INET_ESP=y +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_MULTIPLE_TABLES=y +# CONFIG_ANDROID_PARANOID_NETWORK is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_NOR_TEGRA=y +CONFIG_MTD_NAND_TEGRA=y +CONFIG_MTD_NAND=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_DM_UEVENT=y +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +CONFIG_USB_USBNET=y +CONFIG_USB_NET_SMSC75XX=y +CONFIG_USB_NET_SMSC95XX=y +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_TEGRA=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_TEGRA=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_TEGRA=y +CONFIG_SPI=y +CONFIG_SPI_TEGRA=y +CONFIG_SPI_SLAVE_TEGRA=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_PDA_POWER=y +CONFIG_BATTERY_BQ20Z75=y +CONFIG_MFD_TPS6591X=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y +CONFIG_REGULATOR_TPS6591X=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_VIDEO_DEV=y +# CONFIG_TEGRA_AVP is not set +# CONFIG_TEGRA_MEDIASERVER is not set +CONFIG_TEGRA_NVAVP=y +# CONFIG_VGA_ARB is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_FB=y +CONFIG_TEGRA_GRHOST=y +CONFIG_TEGRA_DC=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_TEGRA=y +CONFIG_SND_SOC_TEGRA30_DAM=y +CONFIG_SND_SOC_TEGRA30_I2S=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_STORAGE=y +CONFIG_USB_LIBUSUAL=y +CONFIG_USB_TEGRA_OTG=y +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_EMBEDDED_SDIO=y +CONFIG_MMC_PARANOID_SD_INIT=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +CONFIG_MMC_BLOCK_DEFERRED_RESUME=y +CONFIG_MMC_BKOPS=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_TEGRA=y +CONFIG_SWITCH=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_TEGRA=y +CONFIG_STAGING=y +CONFIG_IIO=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +# CONFIG_DNOTIFY is not set +CONFIG_FUSE_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_VM=y +# CONFIG_ARM_UNWIND is not set +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_TWOFISH=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y -- cgit v1.2.3 From 1d9b36e6dd7afdfeae0c3a0ea5bf4d7d1ba723ff Mon Sep 17 00:00:00 2001 From: Ashwin Joshi Date: Thu, 26 Jul 2012 14:43:11 +0530 Subject: ARM: tegra: e1853: Update pinmux table entries Some of the entries in pinmux table are incorrect. Updated the table with correct entries. Bug 966833 Bug 1018258 Signed-off-by: Ashwin Joshi Change-Id: I7ca486246fd51d83e865a9ef825be33011404a89 Reviewed-on: http://git-master/r/118282 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Ashwin Joshi Reviewed-by: Bhavesh Parekh Reviewed-by: Sandeep Trasi (cherry picked from commit a1aef89788f8660e7579a8ad555f1ef68d4c553b) Reviewed-on: http://git-master/r/119651 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/pinmux-t3-tables.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/pinmux-t3-tables.c b/arch/arm/mach-tegra/pinmux-t3-tables.c index 09729a4cfbae..988e3bebb43f 100644 --- a/arch/arm/mach-tegra/pinmux-t3-tables.c +++ b/arch/arm/mach-tegra/pinmux-t3-tables.c @@ -178,10 +178,10 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE PINGROUP(CLK2_OUT, PW5, SDMMC1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, EXTPERIPH2, INPUT, 0x3068),\ PINGROUP(CLK2_REQ, PCC5, SDMMC1, DAP, RSVD1, RSVD2, RSVD3, DAP, INPUT, 0x306c),\ PINGROUP(LCD_PWR1, PC1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, DISPLAYA, OUTPUT, 0x3070),\ - PINGROUP(LCD_PWR2, PC6, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, DISPLAYA, OUTPUT, 0x3074),\ + PINGROUP(LCD_PWR2, PC6, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, DISPLAYA, OUTPUT, 0x3074),\ PINGROUP(LCD_SDIN, PZ2, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, DISPLAYA, OUTPUT, 0x3078),\ PINGROUP(LCD_SDOUT, PN5, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, DISPLAYA, OUTPUT, 0x307c),\ - PINGROUP(LCD_WR_N, PZ3, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, DISPLAYA, OUTPUT, 0x3080),\ + PINGROUP(LCD_WR_N, PZ3, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, DISPLAYA, OUTPUT, 0x3080),\ PINGROUP(LCD_CS0_N, PN4, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, DISPLAYA, OUTPUT, 0x3084),\ PINGROUP(LCD_DC0, PN6, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, DISPLAYA, OUTPUT, 0x3088),\ PINGROUP(LCD_SCK, PZ4, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, DISPLAYA, OUTPUT, 0x308c),\ @@ -320,7 +320,7 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE PINGROUP(GPIO_PBB5, PBB5, CAM, VGP5, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a0),\ PINGROUP(GPIO_PBB6, PBB6, CAM, VGP6, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a4),\ PINGROUP(GPIO_PBB7, PBB7, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x32a8),\ - PINGROUP(GPIO_PCC2, PCC2, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x32ac),\ + PINGROUP(GPIO_PCC2, PCC2, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x32ac),\ PINGROUP(JTAG_RTCK, PU7, SYS, RTCK, RSVD1, RSVD2, RSVD3, RTCK, INPUT, 0x32b0),\ PINGROUP(PWR_I2C_SCL, PZ6, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, I2CPWR, INPUT, 0x32b4),\ PINGROUP(PWR_I2C_SDA, PZ7, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, I2CPWR, INPUT, 0x32b8),\ @@ -386,7 +386,7 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE PINGROUP(SDMMC3_DAT4, PD1, SDMMC3, PWM1, INVALID, SDMMC3, INVALID, SDMMC3, INPUT, 0x33a8),\ PINGROUP(SDMMC3_DAT5, PD0, SDMMC3, PWM0, INVALID, SDMMC3, INVALID, SDMMC3, INPUT, 0x33ac),\ PINGROUP(SDMMC3_DAT6, PD3, SDMMC3, SPDIF, INVALID, SDMMC3, INVALID, SDMMC3, INPUT, 0x33b0),\ - PINGROUP(SDMMC3_DAT7, PD4, SDMMC3, SPDIF, INVALID, SDMMC3, INVALID, SDMMC3, INPUT, 0x33b4),\ + PINGROUP(SDMMC3_DAT7, PD4, SDMMC3, SPDIF, RSVD, SDMMC3, INVALID, SDMMC3, INPUT, 0x33b4),\ PINGROUP(PEX_L0_PRSNT_N, PDD0, PEXCTL, PCIE, HDA, RSVD2, RSVD3, PCIE, INPUT, 0x33b8),\ PINGROUP(PEX_L0_RST_N, PDD1, PEXCTL, PCIE, HDA, RSVD2, RSVD3, PCIE, INPUT, 0x33bc),\ PINGROUP(PEX_L0_CLKREQ_N, PDD2, PEXCTL, PCIE, HDA, RSVD2, RSVD3, PCIE, INPUT, 0x33c0),\ -- cgit v1.2.3 From 996db8ed6a0bcf47fb3a337262323e931f637e5d Mon Sep 17 00:00:00 2001 From: Kunal Agrawal Date: Tue, 7 Aug 2012 01:16:07 -0700 Subject: pwm: tegra: resource allocation through devm_* Using the devm_* for memory region allocation and clock handler request. As a result, there is no need to explicitly free them and hence saving some code. Change-Id: Id69d40bd44622105ea4f8a37426dd83a694adb8d Signed-off-by: Kunal Agrawal Reviewed-on: http://git-master/r/121581 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan --- arch/arm/mach-tegra/pwm.c | 50 ++++++++++++----------------------------------- 1 file changed, 13 insertions(+), 37 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/pwm.c b/arch/arm/mach-tegra/pwm.c index a268c391cb27..d5533c7d3c05 100644 --- a/arch/arm/mach-tegra/pwm.c +++ b/arch/arm/mach-tegra/pwm.c @@ -87,9 +87,10 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) if (rate >> PWM_SCALE_WIDTH) return -EINVAL; - /* Due to the PWM divider is zero-based, we need to minus 1 to get desired frequency*/ - if (rate>0) - rate--; + /* Due to the PWM divider is zero-based, we need to minus 1 to get + *desired frequency*/ + if (rate > 0) + rate--; val |= (rate << PWM_SCALE_SHIFT); @@ -182,19 +183,16 @@ static int tegra_pwm_probe(struct platform_device *pdev) { struct pwm_device *pwm; struct resource *r; - int ret; - pwm = kzalloc(sizeof(*pwm), GFP_KERNEL); + pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); if (!pwm) { dev_err(&pdev->dev, "failed to allocate memory\n"); return -ENOMEM; } - pwm->clk = clk_get(&pdev->dev, NULL); - if (IS_ERR(pwm->clk)) { - ret = PTR_ERR(pwm->clk); - goto err_free; - } + pwm->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(pwm->clk)) + return PTR_ERR(pwm->clk); pwm->clk_enb = 0; pwm->in_use = 0; @@ -204,22 +202,13 @@ static int tegra_pwm_probe(struct platform_device *pdev) r = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!r) { dev_err(&pdev->dev, "no memory resources defined\n"); - ret = -ENODEV; - goto err_put_clk; - } - - r = request_mem_region(r->start, resource_size(r), pdev->name); - if (!r) { - dev_err(&pdev->dev, "failed to request memory\n"); - ret = -EBUSY; - goto err_put_clk; + return -ENODEV; } - pwm->mmio_base = ioremap(r->start, resource_size(r)); + pwm->mmio_base = devm_request_and_ioremap(&pdev->dev, r); if (!pwm->mmio_base) { - dev_err(&pdev->dev, "failed to ioremap() region\n"); - ret = -ENODEV; - goto err_free_mem; + dev_err(&pdev->dev, "failed to request/ioremap memory\n"); + return -EADDRNOTAVAIL; } platform_set_drvdata(pdev, pwm); @@ -230,13 +219,7 @@ static int tegra_pwm_probe(struct platform_device *pdev) return 0; -err_free_mem: - release_mem_region(r->start, resource_size(r)); -err_put_clk: - clk_put(pwm->clk); -err_free: - kfree(pwm); - return ret; + } static int __devexit tegra_pwm_remove(struct platform_device *pdev) @@ -259,16 +242,9 @@ static int __devexit tegra_pwm_remove(struct platform_device *pdev) mutex_unlock(&pwm_lock); rc = pwm_writel(pwm, 0); - - iounmap(pwm->mmio_base); - release_mem_region(r->start, resource_size(r)); - if (pwm->clk_enb) clk_disable(pwm->clk); - clk_put(pwm->clk); - - kfree(pwm); return rc; } -- cgit v1.2.3 From cd0b0f629c7709411600a944a72b06225a523bac Mon Sep 17 00:00:00 2001 From: Vinayak Pane Date: Tue, 29 May 2012 18:00:26 -0700 Subject: arm: tegra: xmm: protect xmm power state Added protection locks for xmm power state. Moving prints outside of spinlock. Revisit spinlock on global flags and rearrange in irq. Avoid kernel crash in case of remote-wakeup detected. Protect ipc_ap_wake_state in xmm on & off. Bug 1010131 Change-Id: Id53598b09bececd6f4ff1a948a492e6fcc56628c Signed-off-by: Vinayak Pane Reviewed-on: http://git-master/r/108427 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Michael Hsu GVS: Gerrit_Virtual_Submit Reviewed-by: Steve Lin --- arch/arm/mach-tegra/baseband-xmm-power.c | 132 +++++++++++++++++++------------ arch/arm/mach-tegra/baseband-xmm-power.h | 16 ++-- 2 files changed, 90 insertions(+), 58 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/baseband-xmm-power.c b/arch/arm/mach-tegra/baseband-xmm-power.c index cc330c86c581..f85d6e6c48b6 100644 --- a/arch/arm/mach-tegra/baseband-xmm-power.c +++ b/arch/arm/mach-tegra/baseband-xmm-power.c @@ -81,12 +81,12 @@ static enum baseband_xmm_powerstate_t baseband_xmm_powerstate; static enum ipc_ap_wake_state_t ipc_ap_wake_state; static struct workqueue_struct *workqueue; static struct work_struct init2_work; -static struct work_struct L2_resume_work; +static struct work_struct l2_resume_work; static struct work_struct autopm_resume_work; static bool register_hsic_device; static struct wake_lock wakelock; static struct usb_device *usbdev; -static bool CP_initiated_L2toL0; +static bool cp_initiated_l2tol0; static bool modem_power_on; static int power_onoff; static int reenable_autosuspend; @@ -164,6 +164,17 @@ static int tegra_baseband_rail_off(void) return 0; } +static inline enum baseband_xmm_powerstate_t baseband_xmm_get_power_status(void) +{ + enum baseband_xmm_powerstate_t status; + unsigned long flags; + + spin_lock_irqsave(&xmm_lock, flags); + status = baseband_xmm_powerstate; + spin_unlock_irqrestore(&xmm_lock, flags); + return status; +} + static int baseband_modem_power_on(struct baseband_power_platform_data *data) { /* set IPC_HSIC_ACTIVE active */ @@ -230,6 +241,7 @@ static int xmm_power_on(struct platform_device *device) struct baseband_power_platform_data *pdata = device->dev.platform_data; struct xmm_power_data *data = &xmm_power_drv_data; + unsigned long flags; int ret; pr_debug("%s {\n", __func__); @@ -239,13 +251,13 @@ static int xmm_power_on(struct platform_device *device) pr_err("%s: !pdata\n", __func__); return -EINVAL; } - if (baseband_xmm_powerstate != BBXMM_PS_UNINIT) + if (baseband_xmm_get_power_status() != BBXMM_PS_UNINIT) return -EINVAL; tegra_baseband_rail_on(); /* reset the state machine */ - baseband_xmm_powerstate = BBXMM_PS_INIT; + baseband_xmm_set_power_status(BBXMM_PS_INIT); modem_sleep_flag = false; pr_debug("%s wake_st(%d) modem version %lu\n", __func__, @@ -255,7 +267,10 @@ static int xmm_power_on(struct platform_device *device) if (!modem_flash) { pr_debug("%s - %d\n", __func__, __LINE__); + spin_lock_irqsave(&xmm_lock, flags); ipc_ap_wake_state = IPC_AP_WAKE_INIT2; + spin_unlock_irqrestore(&xmm_lock, flags); + /* register usb host controller only once */ if (register_hsic_device) { pr_debug("%s: register usb host controller\n", @@ -282,8 +297,11 @@ static int xmm_power_on(struct platform_device *device) */ pr_debug("%s: reset flash modem\n", __func__); + modem_power_on = false; + spin_lock_irqsave(&xmm_lock, flags); ipc_ap_wake_state = IPC_AP_WAKE_IRQ_READY; + spin_unlock_irqrestore(&xmm_lock, flags); gpio_set_value(pdata->modem.xmm.ipc_hsic_active, 0); xmm_power_reset_on(pdata); @@ -302,14 +320,14 @@ static int xmm_power_off(struct platform_device *device) struct baseband_power_platform_data *pdata = device->dev.platform_data; struct xmm_power_data *data = &xmm_power_drv_data; - int ret; unsigned long flags; pr_debug("%s {\n", __func__); - if (baseband_xmm_powerstate == BBXMM_PS_UNINIT) + if (baseband_xmm_get_power_status() == BBXMM_PS_UNINIT) return -EINVAL; + /* check for device / platform data */ if (!device) { pr_err("%s: !device\n", __func__); @@ -320,7 +338,10 @@ static int xmm_power_off(struct platform_device *device) return -EINVAL; } + spin_lock_irqsave(&xmm_lock, flags); ipc_ap_wake_state = IPC_AP_WAKE_UNINIT; + spin_unlock_irqrestore(&xmm_lock, flags); + ret = disable_irq_wake(gpio_to_irq(pdata->modem.xmm.ipc_ap_wake)); if (ret < 0) pr_err("%s: disable_irq_wake error\n", __func__); @@ -343,13 +364,15 @@ static int xmm_power_off(struct platform_device *device) /* sleep 1ms */ usleep_range(1000, 2000); - baseband_xmm_powerstate = BBXMM_PS_UNINIT; - modem_sleep_flag = false; - CP_initiated_L2toL0 = false; + baseband_xmm_set_power_status(BBXMM_PS_UNINIT); + spin_lock_irqsave(&xmm_lock, flags); + modem_sleep_flag = false; + cp_initiated_l2tol0 = false; wakeup_pending = false; system_suspending = false; spin_unlock_irqrestore(&xmm_lock, flags); + /* start registration process once again on xmm on */ register_hsic_device = true; @@ -430,23 +453,31 @@ static void xmm_power_l2_resume(void) if (!pdata) return; + /* erroneous remote-wakeup might call this from irq */ + if (in_interrupt() || in_atomic()) { + pr_err("%s: not allowed in interrupt\n", __func__); + return; + } + /* claim the wakelock here to avoid any system suspend */ if (!wake_lock_active(&wakelock)) wake_lock_timeout(&wakelock, HZ*2); - modem_sleep_flag = false; + spin_lock_irqsave(&xmm_lock, flags); + modem_sleep_flag = false; wakeup_pending = false; - spin_unlock_irqrestore(&xmm_lock, flags); - if (CP_initiated_L2toL0) { + if (cp_initiated_l2tol0) { + cp_initiated_l2tol0 = false; + queue_work(workqueue, &l2_resume_work); + spin_unlock_irqrestore(&xmm_lock, flags); pr_info("CP L2->L0\n"); - CP_initiated_L2toL0 = false; - queue_work(workqueue, &L2_resume_work); } else { /* set the slave wakeup request */ - pr_info("AP/CP L2->L0\n"); value = gpio_get_value(pdata->modem.xmm.ipc_ap_wake); + spin_unlock_irqrestore(&xmm_lock, flags); if (value) { + pr_info("AP/CP L2->L0\n"); drv->hostwake = 0; /* wake bb */ gpio_set_value(pdata->modem.xmm.ipc_bb_wake, 1); @@ -474,16 +505,21 @@ retry: } } - +/* this function holds xmm_lock */ void baseband_xmm_set_power_status(unsigned int status) { struct baseband_power_platform_data *data = xmm_power_drv_data.pdata; int value = 0; unsigned long flags; - if (baseband_xmm_powerstate == status) + if (baseband_xmm_get_power_status() == status) return; - pr_debug("%s\n", __func__); + + /* avoid prints inside spinlock */ + if (status <= BBXMM_PS_L2) + pr_info("%s\n", status == BBXMM_PS_L0 ? "L0" : "L2"); + + spin_lock_irqsave(&xmm_lock, flags); switch (status) { case BBXMM_PS_L0: if (modem_sleep_flag) { @@ -491,7 +527,6 @@ void baseband_xmm_set_power_status(unsigned int status) * xmm_power_driver_handle_resume(data); */ } - pr_info("L0\n"); baseband_xmm_powerstate = status; if (!wake_lock_active(&wakelock)) wake_lock_timeout(&wakelock, HZ*2); @@ -507,15 +542,13 @@ void baseband_xmm_set_power_status(unsigned int status) } break; case BBXMM_PS_L2: - pr_info("L2\n"); baseband_xmm_powerstate = status; - spin_lock_irqsave(&xmm_lock, flags); if (wakeup_pending) { spin_unlock_irqrestore(&xmm_lock, flags); pr_debug("%s: wakeup pending\n", __func__); xmm_power_l2_resume(); + spin_lock_irqsave(&xmm_lock, flags); } else { - spin_unlock_irqrestore(&xmm_lock, flags); if (wake_lock_active(&wakelock)) wake_unlock(&wakelock); modem_sleep_flag = true; @@ -523,15 +556,14 @@ void baseband_xmm_set_power_status(unsigned int status) break; case BBXMM_PS_L2TOL0: pr_debug("L2TOL0\n"); - spin_lock_irqsave(&xmm_lock, flags); system_suspending = false; wakeup_pending = false; - spin_unlock_irqrestore(&xmm_lock, flags); /* do this only from L2 state */ if (baseband_xmm_powerstate == BBXMM_PS_L2) { baseband_xmm_powerstate = status; - pr_debug("BB XMM POWER STATE = %d\n", status); + spin_unlock_irqrestore(&xmm_lock, flags); xmm_power_l2_resume(); + spin_lock_irqsave(&xmm_lock, flags); } baseband_xmm_powerstate = status; break; @@ -540,6 +572,7 @@ void baseband_xmm_set_power_status(unsigned int status) baseband_xmm_powerstate = status; break; } + spin_unlock_irqrestore(&xmm_lock, flags); pr_debug("BB XMM POWER STATE = %d\n", status); } EXPORT_SYMBOL_GPL(baseband_xmm_set_power_status); @@ -553,38 +586,40 @@ irqreturn_t xmm_power_ipc_ap_wake_irq(int value) /* modem wakeup part */ if (!value) { pr_debug("%s - falling\n", __func__); - if (drv->hostwake == 0) { - /* AP L2 to L0 wakeup */ - pr_debug("received wakeup ap l2->l0\n"); - drv->hostwake = 1; - wake_up_interruptible(&drv->bb_wait); - } + spin_lock(&xmm_lock); + + /* AP L2 to L0 wakeup */ + pr_debug("received wakeup ap l2->l0\n"); + drv->hostwake = 1; + wake_up_interruptible(&drv->bb_wait); + /* First check it a CP ack or CP wake */ value = gpio_get_value(data->modem.xmm.ipc_bb_wake); if (value) { pr_debug("cp ack for bb_wake\n"); ipc_ap_wake_state = IPC_AP_WAKE_L; + spin_unlock(&xmm_lock); return IRQ_HANDLED; } - spin_lock(&xmm_lock); wakeup_pending = true; - if (system_suspending) { - spin_unlock(&xmm_lock); - pr_info("Set wakeup_pending = 1 in system_" - " suspending!!!\n"); - } else { - if (baseband_xmm_powerstate == BBXMM_PS_L2) { - CP_initiated_L2toL0 = true; + if (system_suspending) + pr_info("set wakeup_pending 1 in system_suspending\n"); + else { + if (baseband_xmm_powerstate == BBXMM_PS_L2 || + baseband_xmm_powerstate == BBXMM_PS_L2TOL0) { + cp_initiated_l2tol0 = true; spin_unlock(&xmm_lock); baseband_xmm_set_power_status(BBXMM_PS_L2TOL0); - } else { - CP_initiated_L2toL0 = true; - spin_unlock(&xmm_lock); - } + spin_lock(&xmm_lock); + } else + cp_initiated_l2tol0 = true; + } + /* save gpio state */ ipc_ap_wake_state = IPC_AP_WAKE_L; + spin_unlock(&xmm_lock); } else { pr_debug("%s - rising\n", __func__); value = gpio_get_value(data->modem.xmm.ipc_hsic_active); @@ -846,9 +881,9 @@ static int xmm_power_pm_notifier_event(struct notifier_block *this, if (wakeup_pending && (baseband_xmm_powerstate == BBXMM_PS_L2)) { wakeup_pending = false; + cp_initiated_l2tol0 = true; spin_unlock_irqrestore(&xmm_lock, flags); pr_info("%s : Service Pending CP wakeup\n", __func__); - CP_initiated_L2toL0 = true; baseband_xmm_set_power_status(BBXMM_PS_L2TOL0); return NOTIFY_OK; } @@ -953,13 +988,13 @@ static int xmm_power_driver_probe(struct platform_device *device) /* init work objects */ INIT_WORK(&init2_work, xmm_power_init2_work); - INIT_WORK(&L2_resume_work, xmm_power_l2_resume_work); + INIT_WORK(&l2_resume_work, xmm_power_l2_resume_work); INIT_WORK(&autopm_resume_work, xmm_power_autopm_resume); /* init state variables */ register_hsic_device = true; - CP_initiated_L2toL0 = false; - baseband_xmm_powerstate = BBXMM_PS_UNINIT; + cp_initiated_l2tol0 = false; + baseband_xmm_set_power_status(BBXMM_PS_UNINIT); spin_lock_irqsave(&xmm_lock, flags); wakeup_pending = false; system_suspending = false; @@ -988,9 +1023,8 @@ static int xmm_power_driver_remove(struct platform_device *device) usb_unregister_notify(&usb_xmm_nb); /* free baseband irq(s) */ - if (modem_flash && modem_pm) { + if (modem_flash && modem_pm) free_irq(gpio_to_irq(pdata->modem.xmm.ipc_ap_wake), NULL); - } /* free baseband gpio(s) */ gpio_free_array(tegra_baseband_gpios, diff --git a/arch/arm/mach-tegra/baseband-xmm-power.h b/arch/arm/mach-tegra/baseband-xmm-power.h index b9d85eafda1d..0c8723fe6766 100644 --- a/arch/arm/mach-tegra/baseband-xmm-power.h +++ b/arch/arm/mach-tegra/baseband-xmm-power.h @@ -90,15 +90,13 @@ struct xmm_power_data { }; enum baseband_xmm_powerstate_t { - BBXMM_PS_UNINIT = 0, - BBXMM_PS_INIT = 1, - BBXMM_PS_L0 = 2, - BBXMM_PS_L0TOL2 = 3, - BBXMM_PS_L2 = 4, - BBXMM_PS_L2TOL0 = 5, - BBXMM_PS_L2TOL3 = 6, - BBXMM_PS_L3 = 7, - BBXMM_PS_L3TOL0 = 8, + BBXMM_PS_L0 = 0, + BBXMM_PS_L2 = 1, + BBXMM_PS_L0TOL2 = 2, + BBXMM_PS_L2TOL0 = 3, + BBXMM_PS_UNINIT = 4, + BBXMM_PS_INIT = 5, + BBXMM_PS_L3 = 6, BBXMM_PS_LAST = -1, }; -- cgit v1.2.3 From 48d8c7c91ea5acddf23f74abc801c89c9f16680f Mon Sep 17 00:00:00 2001 From: Rakesh Bodla Date: Wed, 8 Aug 2012 14:36:13 +0530 Subject: arm: tegra: usb_phy: fix null pointer dereference Fixing the null pointer dereference crash. Also modifying USB driver not to give up in case if there is no avdd_usb regulator. Bug 1029852 Change-Id: I3232b7fa1580a0dc1aadd47b138e5eeae05af6f0 Signed-off-by: Rakesh Bodla Reviewed-on: http://git-master/r/121984 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty --- arch/arm/mach-tegra/usb_phy.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c index 3f3c3846a4aa..9288144a1e11 100644 --- a/arch/arm/mach-tegra/usb_phy.c +++ b/arch/arm/mach-tegra/usb_phy.c @@ -284,8 +284,6 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct platform_device *pdev) ERR("inst:[%d] couldn't get regulator avdd_usb: %ld\n", phy->inst, PTR_ERR(phy->vdd_reg)); phy->vdd_reg = NULL; - err = PTR_ERR(phy->vdd_reg); - goto fail_io; } err = tegra_usb_phy_get_clocks(phy); -- cgit v1.2.3 From 89c0dc999188865e0e6d58327d7beafb65587ea2 Mon Sep 17 00:00:00 2001 From: Rakesh Bodla Date: Wed, 8 Aug 2012 11:15:31 +0530 Subject: arm: tegra: usb_phy: remove duplicate code Remove duplicate code. Change-Id: I9c9979f489d93c458f5e494fbb69008b89578b8d Signed-off-by: Rakesh Bodla Reviewed-on: http://git-master/r/121988 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty --- arch/arm/mach-tegra/tegra3_usb_phy.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index 38d8c414b194..460bea14b3e1 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -636,12 +636,6 @@ static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy) val &= ~USBON_VAL(inst); writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE); - /* Enable which type of event can trigger a walk, - in this case usb_line_wake */ - val = readl(pmc_base + PMC_SLEEPWALK_CFG); - val |= UTMIP_LINEVAL_WALK_EN(inst); - writel(val, pmc_base + PMC_SLEEPWALK_CFG); - /* Enable which type of event can trigger a walk, * in this case usb_line_wake */ val = readl(pmc_base + PMC_SLEEPWALK_CFG); -- cgit v1.2.3 From bbdf4403412df9151864bd633519f828ea27c8c6 Mon Sep 17 00:00:00 2001 From: Mohan T Date: Thu, 9 Aug 2012 09:51:11 +0530 Subject: arm: config: tegra3: enable ipv4/ipv6 filters Android jb need ip filters to be enabled to track data uses. Bug 1019233 Change-Id: I8073643a4a7c34e428c02682a3afc5a23fbcf344 Signed-off-by: Mohan T Reviewed-on: http://git-master/r/122051 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Rakesh Kumar GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- arch/arm/configs/tegra3_android_defconfig | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/tegra3_android_defconfig b/arch/arm/configs/tegra3_android_defconfig index bd20372d6196..fa637e81128b 100644 --- a/arch/arm/configs/tegra3_android_defconfig +++ b/arch/arm/configs/tegra3_android_defconfig @@ -146,16 +146,25 @@ CONFIG_IP_NF_MATCH_ECN=y CONFIG_IP_NF_MATCH_TTL=y CONFIG_IP_NF_FILTER=y CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_REJECT_SKERR=y CONFIG_IP_NF_TARGET_LOG=y CONFIG_NF_NAT=y CONFIG_IP_NF_TARGET_MASQUERADE=y CONFIG_IP_NF_TARGET_NETMAP=y CONFIG_IP_NF_TARGET_REDIRECT=y CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_RAW=y CONFIG_IP_NF_ARPTABLES=y CONFIG_IP_NF_ARPFILTER=y CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_TARGET_LOG=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_TARGET_REJECT_SKERR=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y CONFIG_NET_SCHED=y CONFIG_NET_SCH_HTB=y CONFIG_NET_SCH_INGRESS=y -- cgit v1.2.3 From 675dfd18c952e6cf5748aaa305086d86b0358582 Mon Sep 17 00:00:00 2001 From: Vinayak Pane Date: Tue, 17 Jul 2012 19:06:54 -0700 Subject: arm: tegra: xmm: device set to null in unregister hsic_unregister is being called multiple times during two step enumeration process of xmm. In failure cases when enumeration does not complete properly, kernel panic is seen because of extra unregister-ehci device. Bug 1016593 Change-Id: Ibaeb20ed0dab0e906741fdfad78f7d89a3672f60 Signed-off-by: Vinayak Pane Reviewed-on: http://git-master/r/116626 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/baseband-xmm-power.c | 9 ++++----- arch/arm/mach-tegra/baseband-xmm-power.h | 2 +- arch/arm/mach-tegra/baseband-xmm-power2.c | 2 +- arch/arm/mach-tegra/board-enterprise.c | 10 ++++++++-- arch/arm/mach-tegra/include/mach/tegra-bb-power.h | 2 +- 5 files changed, 15 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/baseband-xmm-power.c b/arch/arm/mach-tegra/baseband-xmm-power.c index f85d6e6c48b6..5a7cecde526b 100644 --- a/arch/arm/mach-tegra/baseband-xmm-power.c +++ b/arch/arm/mach-tegra/baseband-xmm-power.c @@ -66,7 +66,7 @@ static struct usb_device_id xmm_pm_ids[] = { .driver_info = 0 }, {} }; - +MODULE_DEVICE_TABLE(usb, xmm_pm_ids); static struct gpio tegra_baseband_gpios[] = { { -1, GPIOF_OUT_INIT_LOW, "BB_RSTn" }, @@ -348,11 +348,10 @@ static int xmm_power_off(struct platform_device *device) /* unregister usb host controller */ if (pdata->hsic_unregister) - pdata->hsic_unregister(data->hsic_device); + pdata->hsic_unregister(&data->hsic_device); else pr_err("%s: hsic_unregister is missing\n", __func__); - /* set IPC_HSIC_ACTIVE low */ gpio_set_value(pdata->modem.xmm.ipc_hsic_active, 0); @@ -819,7 +818,7 @@ static void xmm_device_remove_handler(struct usb_device *udev) if (usbdev == udev) { pr_info("Remove device %d <%s %s>\n", udev->devnum, udev->manufacturer, udev->product); - usbdev = 0; + usbdev = NULL; } } @@ -1038,7 +1037,7 @@ static int xmm_power_driver_remove(struct platform_device *device) /* unregister usb host controller */ if (pdata->hsic_unregister) - pdata->hsic_unregister(data->hsic_device); + pdata->hsic_unregister(&data->hsic_device); else pr_err("%s: hsic_unregister is missing\n", __func__); diff --git a/arch/arm/mach-tegra/baseband-xmm-power.h b/arch/arm/mach-tegra/baseband-xmm-power.h index 0c8723fe6766..55c81833ba04 100644 --- a/arch/arm/mach-tegra/baseband-xmm-power.h +++ b/arch/arm/mach-tegra/baseband-xmm-power.h @@ -41,7 +41,7 @@ enum baseband_type { struct baseband_power_platform_data { enum baseband_type baseband_type; struct platform_device* (*hsic_register)(void); - void (*hsic_unregister)(struct platform_device *); + void (*hsic_unregister)(struct platform_device **); union { struct { int mdm_reset; diff --git a/arch/arm/mach-tegra/baseband-xmm-power2.c b/arch/arm/mach-tegra/baseband-xmm-power2.c index 905759dca329..a79cd6fb499f 100644 --- a/arch/arm/mach-tegra/baseband-xmm-power2.c +++ b/arch/arm/mach-tegra/baseband-xmm-power2.c @@ -108,7 +108,7 @@ static void xmm_power2_step1(struct work_struct *work) /* unregister usb host controller */ if (pdata->hsic_unregister) - pdata->hsic_unregister(data->hsic_device); + pdata->hsic_unregister(&data->hsic_device); else pr_err("%s: hsic_unregister is missing\n", __func__); diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c index 46078a82a9b1..d918a1fb3518 100644 --- a/arch/arm/mach-tegra/board-enterprise.c +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -832,9 +832,15 @@ error: return NULL; } -void tegra_usb_hsic_host_unregister(struct platform_device *pdev) +void tegra_usb_hsic_host_unregister(struct platform_device **platdev) { - platform_device_unregister(pdev); + struct platform_device *pdev = *platdev; + + if (pdev && &pdev->dev) { + platform_device_unregister(pdev); + *platdev = NULL; + } else + pr_err("%s: no platform device\n", __func__); } static void enterprise_usb_init(void) diff --git a/arch/arm/mach-tegra/include/mach/tegra-bb-power.h b/arch/arm/mach-tegra/include/mach/tegra-bb-power.h index e0b7e3de326f..96e36116f04f 100644 --- a/arch/arm/mach-tegra/include/mach/tegra-bb-power.h +++ b/arch/arm/mach-tegra/include/mach/tegra-bb-power.h @@ -50,7 +50,7 @@ union tegra_bb_gpio_id { }; typedef struct platform_device* (*ehci_register_cb)(void); -typedef void (*ehci_unregister_cb)(struct platform_device *); +typedef void (*ehci_unregister_cb)(struct platform_device **); struct tegra_bb_pdata { union tegra_bb_gpio_id *id; -- cgit v1.2.3 From 6e789ddf027ae942bfb7e442cc66e218f919bb28 Mon Sep 17 00:00:00 2001 From: Suresh Mangipudi Date: Wed, 1 Aug 2012 16:57:51 +0530 Subject: arm: tegra: usbphy: disable PLLU clock Disable the MASTER_BLASTER clock for the null phy interface when usb_bus is suspended. Bug 992861 Change-Id: I86ff559148f9a128ee48bbea2564493f4286b420 Signed-off-by: Suresh Mangipudi Reviewed-on: http://git-master/r/120006 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/tegra3_usb_phy.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index 460bea14b3e1..b27c3083d36b 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -2650,6 +2650,9 @@ static void ulpi_null_phy_close(struct tegra_usb_phy *phy) static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy) { + unsigned int val; + void __iomem *base = phy->regs; + DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); if (!phy->phy_clk_on) { @@ -2661,6 +2664,9 @@ static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy) phy->phy_clk_on = false; phy->hw_accessible = false; ulpi_null_phy_set_tristate(true); + val = readl(base + ULPIS2S_CTRL); + val &= ~ULPIS2S_PLLU_MASTER_BLASTER60; + writel(val, base + ULPIS2S_CTRL); return 0; } -- cgit v1.2.3 From c065d9e47085fbb98924d986c3915f279e504fc8 Mon Sep 17 00:00:00 2001 From: Suresh Mangipudi Date: Thu, 9 Aug 2012 13:54:57 +0530 Subject: arm: tegra: usb_phy: remote-wake for LS devices Remote wakeup was not working for low speed devices. Remote wakeup interrupt is now handled properly for low speed devices. Bug 1029608 Change-Id: If224f30ccc6275b97d50120fe04d9aa53d495e2e Signed-off-by: Suresh Mangipudi Reviewed-on: http://git-master/r/122367 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/tegra3_usb_phy.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index b27c3083d36b..af9eaab782c7 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -1222,6 +1222,8 @@ static int utmi_phy_irq(struct tegra_usb_phy *phy) { void __iomem *base = phy->regs; unsigned long val = 0; + bool remote_wakeup = false; + int irq_status = IRQ_HANDLED; if (phy->phy_clk_on) { DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); @@ -1233,8 +1235,10 @@ static int utmi_phy_irq(struct tegra_usb_phy *phy) usb_phy_fence_read(phy); /* check if there is any remote wake event */ - if (utmi_phy_remotewake_detected(phy)) + if (utmi_phy_remotewake_detected(phy)) { pr_info("%s: utmip remote wake detected\n", __func__); + remote_wakeup = true; + } if (phy->pdata->u_data.host.hot_plug) { val = readl(base + USB_SUSP_CTRL); @@ -1244,17 +1248,23 @@ static int utmi_phy_irq(struct tegra_usb_phy *phy) writel(val , (base + USB_SUSP_CTRL)); pr_info("%s: usb device plugged-in\n", __func__); val = readl(base + USB_USBSTS); - if (!(val & USB_USBSTS_PCI)) - return IRQ_NONE; + if (!(val & USB_USBSTS_PCI)) { + irq_status = IRQ_NONE; + goto exit; + } val = readl(base + USB_PORTSC); val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS); writel(val , (base + USB_PORTSC)); } else if (!phy->phy_clk_on) { - return IRQ_NONE; + if (remote_wakeup) + irq_status = IRQ_HANDLED; + else + irq_status = IRQ_NONE; + goto exit; } } - - return IRQ_HANDLED; +exit: + return irq_status; } static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy) -- cgit v1.2.3 From 70c056bb6dfd3c05b6c3befd1b9238f148711166 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 8 Aug 2012 19:14:46 +0530 Subject: ARM: tegra: aruba: get rid of tegra_gpio_disable() The gpio mode is disabled when freeing gpio and hence this call is no more required. Change-Id: I61469ec85713e3599245c59d2311f869ba03335b Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/122115 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas --- arch/arm/mach-tegra/board-aruba-panel.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-aruba-panel.c b/arch/arm/mach-tegra/board-aruba-panel.c index 2f33d34d6b59..488f212422e6 100644 --- a/arch/arm/mach-tegra/board-aruba-panel.c +++ b/arch/arm/mach-tegra/board-aruba-panel.c @@ -57,7 +57,6 @@ static int aruba_backlight_init(struct device *dev) { static void aruba_backlight_exit(struct device *dev) { gpio_set_value(aruba_bl_enb, 0); gpio_free(aruba_bl_enb); - tegra_gpio_disable(aruba_bl_enb); } static int aruba_backlight_notify(struct device *unused, int brightness) -- cgit v1.2.3 From fcf88f1041f77d246b3a3be18ff3c049be4fd25f Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 8 Aug 2012 19:15:50 +0530 Subject: ARM: tegra: harmony: get rid of tegra_gpio_disable() The gpio mode is disabled when freeing gpio and hence this call is no more required. Change-Id: I21f0f098a4ed741984c474996ba13d7390617646 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/122116 Reviewed-by: Bitan Biswas --- arch/arm/mach-tegra/board-harmony-panel.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-harmony-panel.c b/arch/arm/mach-tegra/board-harmony-panel.c index 79ff5939f7ab..ff1c44ad0f3a 100644 --- a/arch/arm/mach-tegra/board-harmony-panel.c +++ b/arch/arm/mach-tegra/board-harmony-panel.c @@ -65,7 +65,6 @@ static void harmony_backlight_exit(struct device *dev) { gpio_set_value(harmony_bl_enb, 0); gpio_free(harmony_bl_enb); - tegra_gpio_disable(harmony_bl_enb); } static int harmony_backlight_notify(struct device *unused, int brightness) -- cgit v1.2.3 From b548449f736bab9aef88a237841bf576e23040ad Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 8 Aug 2012 19:16:16 +0530 Subject: ARM: tegra: enterprise: get rid of tegra_gpio_disable() The gpio mode is enabled when setting direction and disabled when freeing gpio and hence this call is no more required. Change-Id: Ib384ec9295184ee6d3b2edcf76b0c99bcd28e25a Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/122117 Reviewed-by: Bitan Biswas --- arch/arm/mach-tegra/board-enterprise-panel.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-panel.c b/arch/arm/mach-tegra/board-enterprise-panel.c index 00b8b29c8318..366bf921393d 100644 --- a/arch/arm/mach-tegra/board-enterprise-panel.c +++ b/arch/arm/mach-tegra/board-enterprise-panel.c @@ -63,8 +63,6 @@ #define enterprise_lcd_te TEGRA_GPIO_PJ1 -#define enterprise_bl_pwm TEGRA_GPIO_PH3 - #ifdef CONFIG_TEGRA_DC static struct regulator *enterprise_dsi_reg; static bool dsi_regulator_status; @@ -530,10 +528,6 @@ static int enterprise_dsi_panel_enable(void) if (ret) return ret; -#if IS_EXTERNAL_PWM - tegra_gpio_disable(enterprise_bl_pwm); -#endif - #if DSI_PANEL_RESET if (board_info.fab >= BOARD_FAB_A03) { if (enterprise_lcd_reg == NULL) { -- cgit v1.2.3 From fae91d4c905dba57d68fac90f7700e60af1e3bb9 Mon Sep 17 00:00:00 2001 From: Dongfang Shi Date: Fri, 27 Jul 2012 15:58:50 +0530 Subject: E1853 BRINGUP: HDMI bringup - Register HDMI device. - Panel init also registers HOST1x. - HDMI is fully functional - Hotplug detect GPIO, DDC bus works fine. bug 966833 bug 1018258 Change-Id: Ia04fbfb9b9ddcf81cef241f3cd1187cdc87d159d Reviewed-on: http://git-master/r/119118 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Raymond Rees Tested-by: Dongfang Shi (cherry picked from commit c62d307b84a034bae31afce67b8755d500170f58) Reviewed-on: http://git-master/r/119743 Reviewed-by: Bob Johnston GVS: Gerrit_Virtual_Submit Reviewed-by: Varun Wadekar --- arch/arm/mach-tegra/board-e1853-panel.c | 74 +++++++++++++++++++++++++++++---- arch/arm/mach-tegra/board-e1853.c | 4 +- 2 files changed, 67 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-e1853-panel.c b/arch/arm/mach-tegra/board-e1853-panel.c index 1e6c7ab60907..a4d6bc66f4e7 100644 --- a/arch/arm/mach-tegra/board-e1853-panel.c +++ b/arch/arm/mach-tegra/board-e1853-panel.c @@ -30,6 +30,9 @@ #include "board.h" #include "devices.h" #include "tegra3_host1x_devices.h" +#include "gpio-names.h" + +#define E1853_HDMI_HPD TEGRA_GPIO_PB2 static int e1853_panel_enable(void) { @@ -82,6 +85,47 @@ static struct tegra_dc_platform_data e1853_disp1_pdata = { .fb = &e1853_fb_data, }; +static int e1853_hdmi_enable(void) +{ + return 0; +} + +static int e1853_hdmi_disable(void) +{ + return 0; +} + +static struct tegra_fb_data e1853_hdmi_fb_data = { + .win = 0, + .xres = 800, + .yres = 480, + .bits_per_pixel = 32, + .flags = TEGRA_FB_FLIP_ON_PROBE, +}; + +static struct tegra_dc_out e1853_hdmi_out = { + .align = TEGRA_DC_ALIGN_MSB, + .order = TEGRA_DC_ORDER_RED_BLUE, + .parent_clk = "pll_d2_out0", + .type = TEGRA_DC_OUT_HDMI, + .flags = TEGRA_DC_OUT_HOTPLUG_LOW | + TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND, + .max_pixclock = KHZ2PICOS(148500), + /* XXX: Check the GPIO */ + .hotplug_gpio = E1853_HDMI_HPD, + .enable = e1853_hdmi_enable, + .disable = e1853_hdmi_disable, + /* XXX: Check the I2C instance */ + .dcc_bus = 3, +}; + +static struct tegra_dc_platform_data e1853_hdmi_pdata = { + .flags = 0, + .default_out = &e1853_hdmi_out, + .emc_clk_rate = 300000000, + .fb = &e1853_hdmi_fb_data, +}; + static struct nvmap_platform_carveout e1853_carveouts[] = { [0] = { .name = "iram", @@ -117,15 +161,7 @@ int __init e1853_panel_init(void) e1853_carveouts[1].size = tegra_carveout_size; tegra_nvmap_device.dev.platform_data = &e1853_nvmap_data; tegra_disp1_device.dev.platform_data = &e1853_disp1_pdata; - - res = nvhost_get_resource_byname(&tegra_disp1_device, - IORESOURCE_MEM, "fbmem"); - if (!res) { - pr_err("No memory resources\n"); - return -ENODEV; - } - res->start = tegra_fb_start; - res->end = tegra_fb_start + tegra_fb_size - 1; + tegra_disp2_device.dev.platform_data = &e1853_hdmi_pdata; #ifdef CONFIG_TEGRA_GRHOST err = tegra3_register_host1x_devices(); @@ -135,9 +171,29 @@ int __init e1853_panel_init(void) err = platform_add_devices(e1853_gfx_devices, ARRAY_SIZE(e1853_gfx_devices)); + +#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC) + res = nvhost_get_resource_byname(&tegra_disp1_device, + IORESOURCE_MEM, "fbmem"); + if (res) { + res->start = tegra_fb_start; + res->end = tegra_fb_start + tegra_fb_size - 1; + } + if (!err) err = nvhost_device_register(&tegra_disp1_device); + res = nvhost_get_resource_byname(&tegra_disp2_device, + IORESOURCE_MEM, "fbmem"); + if (res) { + res->start = tegra_fb2_start; + res->end = tegra_fb2_start + tegra_fb2_size - 1; + } + + if (!err) + err = nvhost_device_register(&tegra_disp2_device); +#endif + #if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_NVAVP) if (!err) err = nvhost_device_register(&nvavp_device); diff --git a/arch/arm/mach-tegra/board-e1853.c b/arch/arm/mach-tegra/board-e1853.c index 9379ec3b3f18..cec5667fb95b 100644 --- a/arch/arm/mach-tegra/board-e1853.c +++ b/arch/arm/mach-tegra/board-e1853.c @@ -374,9 +374,9 @@ static void __init tegra_e1853_init(void) static void __init tegra_e1853_reserve(void) { #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) - tegra_reserve(0, SZ_8M, 0); + tegra_reserve(0, SZ_8M, SZ_8M); #else - tegra_reserve(SZ_128M, SZ_8M, 0); + tegra_reserve(SZ_128M, SZ_8M, SZ_8M); #endif } -- cgit v1.2.3 From fef755d45e3f4fa8b29fcc66ea2e7a6fd4e80268 Mon Sep 17 00:00:00 2001 From: Antti P Miettinen Date: Fri, 10 Aug 2012 15:18:38 +0300 Subject: tracing: Clock lock trace events Add tracing for clock lock/unlock operations. Bug 960307 Change-Id: Id5c2d8be25900bc701e5dcd73f87c068ab6e5894 Signed-off-by: Antti P Miettinen Reviewed-on: http://git-master/r/122666 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen --- arch/arm/mach-tegra/clock.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index c27176b1cc0d..035a41c99359 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -64,6 +64,7 @@ #include #include #include +#include #include #include @@ -281,6 +282,7 @@ static inline bool clk_cansleep(struct clk *c) static inline void clk_lock_save(struct clk *c, unsigned long *flags) { + trace_clock_lock(c->name, c->rate, smp_processor_id()); if (clk_cansleep(c)) { *flags = 0; mutex_lock(&c->mutex); @@ -295,6 +297,7 @@ static inline void clk_unlock_restore(struct clk *c, unsigned long *flags) mutex_unlock(&c->mutex); else spin_unlock_irqrestore(&c->spinlock, *flags); + trace_clock_unlock(c->name, c->rate, smp_processor_id()); } static inline void clk_lock_init(struct clk *c) -- cgit v1.2.3 From 61a9d84f74163c7f2dbc6868836b916903724f3c Mon Sep 17 00:00:00 2001 From: Rakesh Iyer Date: Mon, 6 Aug 2012 14:06:17 -0700 Subject: ARM: tegra: cardhu: report correct height/width We will report the exact width/height instead of rounding it off for Android's bucketed dpi values. The determination of the bucketed dpi values is handled in user mode. Bug 1003707. Change-Id: Id3d4b9fc325187067e2d3df895ff6a753b730633 Signed-off-by: Rakesh Iyer Reviewed-on: http://git-master/r/121431 Reviewed-by: Kevin Huang (Eng-SW) Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo GVS: Gerrit_Virtual_Submit --- arch/arm/mach-tegra/board-cardhu-panel.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-panel.c b/arch/arm/mach-tegra/board-cardhu-panel.c index c106a4317bc0..530fcfc4ba09 100644 --- a/arch/arm/mach-tegra/board-cardhu-panel.c +++ b/arch/arm/mach-tegra/board-cardhu-panel.c @@ -1246,8 +1246,8 @@ static void cardhu_panel_preinit(void) cardhu_disp1_out.enable = cardhu_panel_enable; cardhu_disp1_out.disable = cardhu_panel_disable; /* Set height and width in mm. */ - cardhu_disp1_out.height = 127; - cardhu_disp1_out.width = 216; + cardhu_disp1_out.height = 125; + cardhu_disp1_out.width = 223; cardhu_disp1_pdata.fb = &cardhu_fb_data; } else { @@ -1269,12 +1269,18 @@ static void cardhu_panel_preinit(void) ARRAY_SIZE(cardhu_dsi_modes_218); cardhu_dsi_fb_data.xres = 864; cardhu_dsi_fb_data.yres = 480; + /* Set height and width in mm. */ + cardhu_disp1_out.height = 47; + cardhu_disp1_out.width = 84; } else if (is_panel_219) { cardhu_disp1_out.modes = cardhu_dsi_modes_219; cardhu_disp1_out.n_modes = ARRAY_SIZE(cardhu_dsi_modes_219); cardhu_dsi_fb_data.xres = 540; cardhu_dsi_fb_data.yres = 960; + /* Set height and width in mm. */ + cardhu_disp1_out.height = 95; + cardhu_disp1_out.width = 53; } else if (is_panel_1506) { cardhu_disp1_out.modes = cardhu_dsi_modes_1506; cardhu_disp1_out.n_modes = @@ -1340,8 +1346,8 @@ int __init cardhu_panel_init(void) cardhu_disp1_out.depth = 24; #endif /* Set height and width in mm. */ - cardhu_disp1_out.height = 127; - cardhu_disp1_out.width = 203; + cardhu_disp1_out.height = 135; + cardhu_disp1_out.width = 217; cardhu_fb_data.xres = 1920; cardhu_fb_data.yres = 1200; -- cgit v1.2.3 From b1514438f2cdefae817328ff69f8b6dc5f2d878b Mon Sep 17 00:00:00 2001 From: Sai Charan Gurrappadi Date: Fri, 10 Aug 2012 15:13:00 -0700 Subject: ARM: tegra: Ignore PmQos when disabled The cpu hotplug drivers should only bother updating state or switching to the G cluster if the driver is not disabled Bug 1032096 Change-Id: Ice938b094bbf48fef47afa3915b1a48362fb256d Signed-off-by: Sai Charan Gurrappadi Reviewed-on: http://git-master/r/122859 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid Reviewed-by: Diwakar Tundlam --- arch/arm/mach-tegra/cpu-tegra3.c | 2 +- arch/arm/mach-tegra/cpuquiet.c | 12 +++++++++++- 2 files changed, 12 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/cpu-tegra3.c b/arch/arm/mach-tegra/cpu-tegra3.c index ec63622b4705..c0d21bfa816a 100644 --- a/arch/arm/mach-tegra/cpu-tegra3.c +++ b/arch/arm/mach-tegra/cpu-tegra3.c @@ -360,7 +360,7 @@ static int min_cpus_notify(struct notifier_block *nb, unsigned long n, void *p) { mutex_lock(tegra3_cpu_lock); - if ((n >= 1) && is_lp_cluster()) { + if ((n >= 1) && is_lp_cluster() && !no_lp) { /* make sure cpu rate is within g-mode range before switching */ unsigned int speed = max((unsigned long)tegra_getspeed(0), clk_get_min_rate(cpu_g_clk) / 1000); diff --git a/arch/arm/mach-tegra/cpuquiet.c b/arch/arm/mach-tegra/cpuquiet.c index ed197b1e6c6f..87aebfe7badb 100644 --- a/arch/arm/mach-tegra/cpuquiet.c +++ b/arch/arm/mach-tegra/cpuquiet.c @@ -188,6 +188,9 @@ static void min_max_constraints_workfunc(struct work_struct *work) int max_cpus = pm_qos_request(PM_QOS_MAX_ONLINE_CPUS) ? : 4; int min_cpus = pm_qos_request(PM_QOS_MIN_ONLINE_CPUS); + if (cpq_state == TEGRA_CPQ_DISABLED) + return; + if (is_lp_cluster()) return; @@ -219,10 +222,14 @@ static int min_cpus_notify(struct notifier_block *nb, unsigned long n, void *p) { bool g_cluster = false; + if (cpq_state == TEGRA_CPQ_DISABLED) + return NOTIFY_OK; + mutex_lock(tegra3_cpu_lock); if ((n >= 1) && is_lp_cluster()) { - /* make sure cpu rate is within g-mode range before switching */ + /* make sure cpu rate is within g-mode + * range before switching */ unsigned long speed = max((unsigned long)tegra_getspeed(0), clk_get_min_rate(cpu_g_clk) / 1000); tegra_update_cpu_speed(speed); @@ -244,6 +251,9 @@ static int min_cpus_notify(struct notifier_block *nb, unsigned long n, void *p) static int max_cpus_notify(struct notifier_block *nb, unsigned long n, void *p) { + if (cpq_state == TEGRA_CPQ_DISABLED) + return NOTIFY_OK; + if (n < num_online_cpus()) schedule_work(&minmax_work); -- cgit v1.2.3 From c921a79e0a8834dc697a2afa8e920311340447c6 Mon Sep 17 00:00:00 2001 From: Shawn Joo Date: Mon, 13 Aug 2012 16:50:48 +0900 Subject: arm: tegra: xmm: adding callback for L0 sequence. adding callback of xmm modem for L3->L0 power sequence. Bug 1030815 Change-Id: I4997f56819726a55fc8268a1011bc98ff6baf8ca Signed-off-by: Shawn Joo Reviewed-on: http://git-master/r/122960 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-enterprise.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c index d918a1fb3518..7e735e96324f 100644 --- a/arch/arm/mach-tegra/board-enterprise.c +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -723,6 +723,7 @@ static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = { .post_suspend = enterprise_usb_hsic_postsupend, .pre_resume = enterprise_usb_hsic_preresume, .port_power = enterprise_usb_hsic_phy_power, + .post_phy_on = enterprise_usb_hsic_phy_power, .post_phy_off = enterprise_usb_hsic_post_phy_off, }; -- cgit v1.2.3 From 18156565232996364bbeef583db5fee07940ca7d Mon Sep 17 00:00:00 2001 From: Krishna Reddy Date: Thu, 9 Aug 2012 11:18:21 -0700 Subject: mm: Fix incorrect cache attribute restoration. armv7 uses cache policy as WRITEALLOC. CPA is restoring the cache attributes to WRITEBACK during set_pages_array_wb(). Fixed issues in pmd to pte prot translation and vice versa. Change-Id: I8406b784f62d559f657ef7bc08e77c83ac6e5690 Signed-off-by: Krishna Reddy Reviewed-on: http://git-master/r/122472 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mm/pageattr.c | 70 +++++++++++++++++++++++++++++++++++--------------- 1 file changed, 49 insertions(+), 21 deletions(-) (limited to 'arch') diff --git a/arch/arm/mm/pageattr.c b/arch/arm/mm/pageattr.c index b7ff7f19b541..526bf59e61cc 100644 --- a/arch/arm/mm/pageattr.c +++ b/arch/arm/mm/pageattr.c @@ -39,6 +39,19 @@ static void inner_flush_cache_all(void) } #if defined(CONFIG_CPA) + +/* + * The arm kernel uses different cache policies(CPOLICY_WRITEBACK, + * CPOLICY_WRITEALLOC, CPOLICY_WRITETHROUGH) based on architecture version + * and smp mode. Using L_PTE_MT_WRITEALLOC or L_PTE_MT_WRITEBACK or + * L_PTE_MT_WRITETHROUGH directly in CPA code can result in restoring incorrect + * PTE attributes. + * pgprot_kernel would always have PTE attributes based on the cache policy + * in use for kernel cache memory. Use this to set the correct PTE attributes + * for kernel cache memory. + * */ +#define L_PTE_MT_KERNEL (pgprot_kernel & L_PTE_MT_MASK) + /* * The current flushing context - we pass it instead of 5 arguments: */ @@ -224,7 +237,8 @@ static inline pgprot_t pte_to_pmd_pgprot(unsigned long pte, { pgprot_t ref_prot; - ref_prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE; + ref_prot = PMD_TYPE_SECT | PMD_DOMAIN(DOMAIN_KERNEL) | + PMD_SECT_AP_WRITE; if (pte & L_PTE_MT_BUFFERABLE) ref_prot |= PMD_SECT_BUFFERABLE; @@ -232,17 +246,23 @@ static inline pgprot_t pte_to_pmd_pgprot(unsigned long pte, if (pte & L_PTE_MT_WRITETHROUGH) ref_prot |= PMD_SECT_CACHEABLE; - if (pte & L_PTE_SHARED) - ref_prot |= PMD_SECT_S; - if (pte & L_PTE_XN) ref_prot |= PMD_SECT_XN; + if (pte & L_PTE_USER) + ref_prot |= PMD_SECT_AP_READ; + + if (pte & (1 << 4)) + ref_prot |= PMD_SECT_TEX(1); + if (pte & L_PTE_RDONLY) - ref_prot &= ~PMD_SECT_AP_WRITE; + ref_prot |= PMD_SECT_APX; + + if (pte & L_PTE_SHARED) + ref_prot |= PMD_SECT_S; - ref_prot |= (ext_prot & (PTE_EXT_AP0 | PTE_EXT_AP1 | PTE_EXT_APX | - PTE_EXT_NG | (7 << 6))) << 6; + if (pte & PTE_EXT_NG) + ref_prot |= PMD_SECT_nG; return ref_prot; } @@ -250,9 +270,10 @@ static inline pgprot_t pte_to_pmd_pgprot(unsigned long pte, static inline pgprot_t pmd_to_pte_pgprot(unsigned long pmd, unsigned long *ext_prot) { - pgprot_t ref_prot = 0; + pgprot_t ref_prot; - ref_prot |= L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_RDONLY; + *ext_prot = 0; + ref_prot = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY; if (pmd & PMD_SECT_BUFFERABLE) ref_prot |= L_PTE_MT_BUFFERABLE; @@ -260,18 +281,23 @@ static inline pgprot_t pmd_to_pte_pgprot(unsigned long pmd, if (pmd & PMD_SECT_CACHEABLE) ref_prot |= L_PTE_MT_WRITETHROUGH; - if (pmd & PMD_SECT_S) - ref_prot |= L_PTE_SHARED; - if (pmd & PMD_SECT_XN) ref_prot |= L_PTE_XN; - if (pmd & PMD_SECT_AP_WRITE) - ref_prot &= ~L_PTE_RDONLY; + if (pmd & PMD_SECT_AP_READ) + ref_prot |= L_PTE_USER; + + if (pmd & PMD_SECT_TEX(1)) + ref_prot |= (1 << 4); - /* AP/APX/TEX bits */ - *ext_prot = (pmd & (PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | - PMD_SECT_APX | PMD_SECT_nG | (7 << 12))) >> 6; + if (pmd & PMD_SECT_APX) + ref_prot |= L_PTE_RDONLY; + + if (pmd & PMD_SECT_S) + ref_prot |= L_PTE_SHARED; + + if (pmd & PMD_SECT_nG) + ref_prot |= PTE_EXT_NG; return ref_prot; } @@ -395,6 +421,7 @@ try_preserve_large_page(pte_t *kpte, unsigned long address, if (numpages < cpa->numpages) cpa->numpages = numpages; + old_pte = *kpte; old_prot = new_prot = req_prot = pmd_to_pte_pgprot(pmd_val(*kpte), &ext_prot); @@ -502,6 +529,7 @@ static int split_large_page(pte_t *kpte, unsigned long address) ref_prot = pmd_to_pte_pgprot(pmd_val(*kpte), &ext_prot); + BUG_ON(ref_prot != pgprot_kernel); /* * Get the target pfn from the original entry: */ @@ -760,7 +788,7 @@ static inline int cache_attr(pgprot_t attr) * We need to flush the cache for all memory type changes * except when a page is being marked write back cacheable */ - return !((pgprot_val(attr) & L_PTE_MT_MASK) == L_PTE_MT_WRITEBACK); + return !((pgprot_val(attr) & L_PTE_MT_MASK) == L_PTE_MT_KERNEL); } static int change_page_attr_set_clr(unsigned long *addr, int numpages, @@ -916,7 +944,7 @@ EXPORT_SYMBOL(set_memory_wc); int set_memory_wb(unsigned long addr, int numpages) { return change_page_attr_set_clr(&addr, numpages, - __pgprot(L_PTE_MT_WRITEBACK), + __pgprot(L_PTE_MT_KERNEL), __pgprot(L_PTE_MT_MASK), 0, 0, NULL); } @@ -934,7 +962,7 @@ EXPORT_SYMBOL(set_memory_iwb); int set_memory_array_wb(unsigned long *addr, int addrinarray) { return change_page_attr_set_clr(addr, addrinarray, - __pgprot(L_PTE_MT_WRITEBACK), + __pgprot(L_PTE_MT_KERNEL), __pgprot(L_PTE_MT_MASK), 0, CPA_ARRAY, NULL); @@ -1017,7 +1045,7 @@ EXPORT_SYMBOL(set_pages_array_wc); int set_pages_array_wb(struct page **pages, int addrinarray) { return _set_pages_array(pages, addrinarray, - L_PTE_MT_WRITEBACK, L_PTE_MT_MASK); + L_PTE_MT_KERNEL, L_PTE_MT_MASK); } EXPORT_SYMBOL(set_pages_array_wb); -- cgit v1.2.3 From 2938982ad420c7fc9927d6d0d136697e5dd56156 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Mon, 13 Aug 2012 11:19:41 +0530 Subject: ARM: tegra: p852: get rid of tegra_gpio_enable() The gpio mode is enabled when setting direction and disabled when freeing gpio and hence this call is no more required. Change-Id: I30647b96fa2a120fb323c18e97bc9936a95c305d Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/122937 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/p852/board-p852-gpio.c | 1 - arch/arm/mach-tegra/p852/board-p852-sdhci.c | 6 +++--- arch/arm/mach-tegra/p852/board-p852.c | 5 ----- 3 files changed, 3 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/p852/board-p852-gpio.c b/arch/arm/mach-tegra/p852/board-p852-gpio.c index 71f568087c5d..6272d36fb849 100644 --- a/arch/arm/mach-tegra/p852/board-p852-gpio.c +++ b/arch/arm/mach-tegra/p852/board-p852-gpio.c @@ -152,7 +152,6 @@ void __init p852_gpio_init(void) gpio_request_array(gpios_info, pin_count); for (i = 0; i < pin_count; i++) { - tegra_gpio_enable(gpios_info[i].gpio); gpio_export(gpios_info[i].gpio, true); } } diff --git a/arch/arm/mach-tegra/p852/board-p852-sdhci.c b/arch/arm/mach-tegra/p852/board-p852-sdhci.c index dc5b81fa3727..54fd42e38ab6 100644 --- a/arch/arm/mach-tegra/p852/board-p852-sdhci.c +++ b/arch/arm/mach-tegra/p852/board-p852-sdhci.c @@ -165,7 +165,7 @@ void __init p852_sdhci_init(void) gpio_request(p852_sdhci_platform_data [i].cd_gpio, gpio_name[cd]); - tegra_gpio_enable + gpio_direction_input (p852_sdhci_platform_data[i]. cd_gpio); } @@ -176,7 +176,7 @@ void __init p852_sdhci_init(void) gpio_request(p852_sdhci_platform_data [i].wp_gpio, gpio_name[wp]); - tegra_gpio_enable + gpio_direction_input (p852_sdhci_platform_data[i]. wp_gpio); } @@ -187,7 +187,7 @@ void __init p852_sdhci_init(void) gpio_request(p852_sdhci_platform_data [i].power_gpio, gpio_name[pw]); - tegra_gpio_enable + gpio_direction_input (p852_sdhci_platform_data[i]. power_gpio); } diff --git a/arch/arm/mach-tegra/p852/board-p852.c b/arch/arm/mach-tegra/p852/board-p852.c index 039d9db6a3a6..0382d7306f42 100644 --- a/arch/arm/mach-tegra/p852/board-p852.c +++ b/arch/arm/mach-tegra/p852/board-p852.c @@ -342,12 +342,10 @@ static void p852_usb_gpio_config(void) if (has_onboard_ethernet) { gpio_request_one(usbeth_mux_gpio, GPIOF_OUT_INIT_LOW, "eth_ena"); - tegra_gpio_enable(usbeth_mux_gpio); /* eth reset */ gpio_request_one(p852_eth_reset, GPIOF_OUT_INIT_LOW, "eth_reset"); - tegra_gpio_enable(p852_eth_reset); udelay(1); gpio_direction_output(p852_eth_reset, 1); @@ -432,7 +430,6 @@ void __init p852_spi_i2s_init(void) gpio_request_one(pdata->gpio_i2s.gpio_no, GPIOF_OUT_INIT_HIGH, "i2s_cpld_dir1"); } - tegra_gpio_enable(pdata->gpio_i2s.gpio_no); if (pdata->gpio_spi.active_state) { gpio_request_one(pdata->gpio_spi.gpio_no, GPIOF_OUT_INIT_LOW, "spi_cpld_dir2"); @@ -441,7 +438,6 @@ void __init p852_spi_i2s_init(void) "spi_cpld_dir2"); } - tegra_gpio_enable(pdata->gpio_spi.gpio_no); spi_register_board_info(&tegra_spi_i2s_device, 1); } #endif @@ -498,7 +494,6 @@ static void ulpi_link_platform_open(void) gpio_request(reset_gpio, "ulpi_phy_reset"); gpio_direction_output(reset_gpio, 0); - tegra_gpio_enable(reset_gpio); gpio_direction_output(reset_gpio, 0); msleep(5); -- cgit v1.2.3 From af5b7f6019328efb542d2370c75b261607b861d6 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Mon, 13 Aug 2012 11:21:45 +0530 Subject: ARM: tegra: p1853: get rid of tegra_gpio_enable() The gpio mode is enabled when setting direction and disabled when freeing gpio and hence this call is no more required. Change-Id: Ic40a506a54ee8fe125c0c1f56a8857fb290fcccb Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/122938 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-e1853-pinmux.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-e1853-pinmux.c b/arch/arm/mach-tegra/board-e1853-pinmux.c index 3f25291609fe..9e81b7035aba 100644 --- a/arch/arm/mach-tegra/board-e1853-pinmux.c +++ b/arch/arm/mach-tegra/board-e1853-pinmux.c @@ -496,7 +496,6 @@ int __init e1853_gpio_init(void) gpio_request_array(gpios_info, pin_count); for (i = 0; i < pin_count; i++) { - tegra_gpio_enable(gpios_info[i].gpio); gpio_export(gpios_info[i].gpio, true); } return 0; -- cgit v1.2.3 From 14e3dc4ad30637bf2fd12cff78397b9f3d50198c Mon Sep 17 00:00:00 2001 From: Ankit Gupta Date: Mon, 13 Aug 2012 12:14:51 +0530 Subject: ARM: tegra: enterprise: set I2S as slave mode. Setting default I2S mode as slave. This will help in power optimization of around 4mW. Change-Id: Ic2d702c332283bd0f6c4f73615e8097fb3b16ef9 Signed-off-by: Ankit Gupta Reviewed-on: http://git-master/r/122943 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-enterprise.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c index 7e735e96324f..0a3024f62dab 100644 --- a/arch/arm/mach-tegra/board-enterprise.c +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -514,7 +514,7 @@ static struct tegra_asoc_platform_data enterprise_audio_pdata = { /*defaults for Enterprise board*/ .i2s_param[HIFI_CODEC] = { .audio_port_id = 0, - .is_i2s_master = 1, + .is_i2s_master = 0, .i2s_mode = TEGRA_DAIFMT_I2S, .sample_size = 16, }, -- cgit v1.2.3 From a8047fabd0ae8fc767ce6f276d8bfb53fc838d05 Mon Sep 17 00:00:00 2001 From: Prem Sasidharan Date: Mon, 13 Aug 2012 13:54:16 -0700 Subject: arm: tegra: E1506 Tristate, pull down LCD pins Tristate and pull down LCD pins D0-D23, LCD_PWR* and LCD_CS*_N pins for E1506 DSI panel. Reduced the power consumption on VDDIO_LCD to 0.37mW for PM269 with E1506 DSI panel. Bug 1007512 Bug 1015349 Signed-off-by: Prem Sasidharan Change-Id: Ic54d1ca71f5ff92742f70915b7b27104c0a508a6 Reviewed-on: http://git-master/r/123172 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo --- arch/arm/mach-tegra/board-cardhu-pinmux.c | 75 +++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-pinmux.c b/arch/arm/mach-tegra/board-cardhu-pinmux.c index 09d7c8911f22..346dccfd715b 100644 --- a/arch/arm/mach-tegra/board-cardhu-pinmux.c +++ b/arch/arm/mach-tegra/board-cardhu-pinmux.c @@ -543,6 +543,38 @@ static __initdata struct tegra_pingroup_config unused_pins_lowpower[] = { }; static __initdata struct tegra_pingroup_config unused_pins_lowpower_e1506[] = { + DEFAULT_PINMUX(LCD_D0, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D1, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D2, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D3, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D4, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D5, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D6, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D7, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D8, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D9, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D10, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D11, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D12, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D13, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D14, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D15, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D16, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D17, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D18, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D19, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D20, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D21, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D22, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D23, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + + DEFAULT_PINMUX(LCD_DC0, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_PWR0, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_PWR1, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_PWR2, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_CS0_N, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_CS1_N, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_PCLK, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), DEFAULT_PINMUX(LCD_WR_N, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), DEFAULT_PINMUX(LCD_HSYNC, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), @@ -767,6 +799,47 @@ struct gpio_init_pin_info vddio_gmi_pins_pm269_e1506[] = { PIN_GPIO_LPM("GMI_CS2", TEGRA_GPIO_PK3, 1, 0), }; +static struct gpio_init_pin_info cardhu_unused_gpio_pins_e1506[] = { + PIN_GPIO_LPM("LCD_D0", TEGRA_GPIO_PE0, 0, 0), + PIN_GPIO_LPM("LCD_D1", TEGRA_GPIO_PE1, 0, 0), + PIN_GPIO_LPM("LCD_D2", TEGRA_GPIO_PE2, 0, 0), + PIN_GPIO_LPM("LCD_D3", TEGRA_GPIO_PE3, 0, 0), + PIN_GPIO_LPM("LCD_D4", TEGRA_GPIO_PE4, 0, 0), + PIN_GPIO_LPM("LCD_D5", TEGRA_GPIO_PE5, 0, 0), + PIN_GPIO_LPM("LCD_D6", TEGRA_GPIO_PE6, 0, 0), + PIN_GPIO_LPM("LCD_D7", TEGRA_GPIO_PE7, 0, 0), + PIN_GPIO_LPM("LCD_D8", TEGRA_GPIO_PF0, 0, 0), + PIN_GPIO_LPM("LCD_D9", TEGRA_GPIO_PF1, 0, 0), + PIN_GPIO_LPM("LCD_D10", TEGRA_GPIO_PF2, 0, 0), + PIN_GPIO_LPM("LCD_D11", TEGRA_GPIO_PF3, 0, 0), + PIN_GPIO_LPM("LCD_D12", TEGRA_GPIO_PF4, 0, 0), + PIN_GPIO_LPM("LCD_D13", TEGRA_GPIO_PF5, 0, 0), + PIN_GPIO_LPM("LCD_D14", TEGRA_GPIO_PF6, 0, 0), + PIN_GPIO_LPM("LCD_D15", TEGRA_GPIO_PF7, 0, 0), + PIN_GPIO_LPM("LCD_D16", TEGRA_GPIO_PM0, 0, 0), + PIN_GPIO_LPM("LCD_D17", TEGRA_GPIO_PM1, 0, 0), + PIN_GPIO_LPM("LCD_D18", TEGRA_GPIO_PM2, 0, 0), + PIN_GPIO_LPM("LCD_D19", TEGRA_GPIO_PM3, 0, 0), + PIN_GPIO_LPM("LCD_D20", TEGRA_GPIO_PM4, 0, 0), + PIN_GPIO_LPM("LCD_D21", TEGRA_GPIO_PM5, 0, 0), + PIN_GPIO_LPM("LCD_D22", TEGRA_GPIO_PM6, 0, 0), + PIN_GPIO_LPM("LCD_D23", TEGRA_GPIO_PM7, 0, 0), + + PIN_GPIO_LPM("LCD_DC0", TEGRA_GPIO_PN6, 0, 0), + PIN_GPIO_LPM("LCD_PWR0", TEGRA_GPIO_PB2, 0, 0), + PIN_GPIO_LPM("LCD_PWR1", TEGRA_GPIO_PC1, 0, 0), + PIN_GPIO_LPM("LCD_PWR2", TEGRA_GPIO_PC6, 0, 0), + PIN_GPIO_LPM("LCD_CS0_N", TEGRA_GPIO_PN4, 0, 0), + PIN_GPIO_LPM("LCD_CS1_N", TEGRA_GPIO_PW0, 0, 0), + PIN_GPIO_LPM("LCD_PCLK", TEGRA_GPIO_PB3, 0, 0), + PIN_GPIO_LPM("LCD_WR_N", TEGRA_GPIO_PZ3, 0, 0), + PIN_GPIO_LPM("LCD_HSYNC", TEGRA_GPIO_PJ3, 0, 0), + PIN_GPIO_LPM("LCD_VSYNC", TEGRA_GPIO_PJ4, 0, 0), + PIN_GPIO_LPM("LCD_SCK", TEGRA_GPIO_PZ4, 0, 0), + PIN_GPIO_LPM("LCD_SDOUT", TEGRA_GPIO_PN5, 0, 0), + PIN_GPIO_LPM("LCD_SDIN", TEGRA_GPIO_PZ2, 0, 0), +}; + static void set_unused_pin_gpio(struct gpio_init_pin_info *lpm_pin_info, int list_count) { @@ -829,6 +902,8 @@ int __init cardhu_pins_state_init(void) if (display_board_info.board_id == BOARD_DISPLAY_E1506) { set_unused_pin_gpio(&vddio_gmi_pins_pm269_e1506[0], ARRAY_SIZE(vddio_gmi_pins_pm269_e1506)); + set_unused_pin_gpio(cardhu_unused_gpio_pins_e1506, + ARRAY_SIZE(cardhu_unused_gpio_pins_e1506)); } else if (display_board_info.board_id != BOARD_DISPLAY_PM313) { set_unused_pin_gpio(&vddio_gmi_pins_pm269_wo_pm313[0], ARRAY_SIZE(vddio_gmi_pins_pm269_wo_pm313)); -- cgit v1.2.3 From 51efb6b201d3a0939e684ef2b530fe485da32531 Mon Sep 17 00:00:00 2001 From: Antti P Miettinen Date: Tue, 14 Aug 2012 13:14:00 +0300 Subject: ARM: tegra: power: Trace LP2 entry and exit Add traces for measuring LP2 entry/exit times. Bug 960304 Change-Id: I20bb0f8d55a7ed6f7e88e10d924871a3d09f2507 Signed-off-by: Antti P Miettinen Reviewed-on: http://git-master/r/123313 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen --- arch/arm/mach-tegra/cpuidle.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index 47d5996e5961..9d36d0fac5d8 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c @@ -45,6 +45,7 @@ #include "cpuidle.h" #include "pm.h" #include "sleep.h" +#include "timer.h" int tegra_lp2_exit_latency; static int tegra_lp2_power_off_time; @@ -117,12 +118,20 @@ static int tegra_idle_enter_lp2(struct cpuidle_device *dev, return tegra_idle_enter_lp3(dev, state); } + trace_printk("LP2 entry at %lu us\n", + (unsigned long)readl(IO_ADDRESS(TEGRA_TMR1_BASE) + + TIMERUS_CNTR_1US)); + local_irq_disable(); enter = ktime_get(); tegra_cpu_idle_stats_lp2_ready(dev->cpu); tegra_idle_lp2(dev, state); + trace_printk("LP2 exit at %lu us\n", + (unsigned long)readl(IO_ADDRESS(TEGRA_TMR1_BASE) + + TIMERUS_CNTR_1US)); + exit = ktime_sub(ktime_get(), enter); us = ktime_to_us(exit); -- cgit v1.2.3 From a119ed4c1e0a0ffb650dd77c5d5f1b71378328c8 Mon Sep 17 00:00:00 2001 From: Krishna Reddy Date: Sun, 29 Jul 2012 15:32:14 -0700 Subject: mm: Avoid freeing init and initrd memory when CPA is enabled. Align memblock reserve for text area to PMD size. Reserve the memory hole between DRAM start and Page table start. Add Sanity check to avoid section split in text area. Bug 1028787 Change-Id: I586e4ad6e3a94aa0c79b302e51156dbe089e481f Signed-off-by: Krishna Reddy Reviewed-on: http://git-master/r/121883 (cherry picked from commit 65d02640b4b0b38263687c7f3e664c873237dc43) Reviewed-on: http://git-master/r/123431 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mm/init.c | 6 +++++- arch/arm/mm/mmu.c | 2 +- arch/arm/mm/pageattr.c | 2 ++ 3 files changed, 8 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 6f81c8e05c3a..cb4e96e1019d 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -339,7 +339,7 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc) #ifdef CONFIG_XIP_KERNEL memblock_reserve(__pa(_sdata), _end - _sdata); #else - memblock_reserve(__pa(_stext), _end - _stext); + memblock_reserve(__pa(_stext), ALIGN(_end - _stext, PMD_SIZE)); #endif #ifdef CONFIG_BLK_DEV_INITRD if (phys_initrd_size && @@ -734,6 +734,7 @@ void __init mem_init(void) void free_initmem(void) { +#ifndef CONFIG_CPA #ifdef CONFIG_HAVE_TCM extern char __tcm_start, __tcm_end; @@ -748,6 +749,7 @@ void free_initmem(void) totalram_pages += free_area(__phys_to_pfn(__pa(__init_begin)), __phys_to_pfn(__pa(__init_end)), "init"); +#endif } #ifdef CONFIG_BLK_DEV_INITRD @@ -756,12 +758,14 @@ static int keep_initrd; void free_initrd_mem(unsigned long start, unsigned long end) { +#ifndef CONFIG_CPA if (!keep_initrd) { poison_init_mem((void *)start, PAGE_ALIGN(end) - start); totalram_pages += free_area(__phys_to_pfn(__pa(start)), __phys_to_pfn(__pa(end)), "initrd"); } +#endif } static int __init keepinitrd_setup(char *__unused) diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index bb80555edac9..992bbc52938c 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -942,7 +942,7 @@ void __init arm_mm_memblock_reserve(void) */ memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t)); -#ifdef CONFIG_SA1111 +#if defined(CONFIG_SA1111) || defined(CONFIG_CPA) /* * Because of the SA1111 DMA bug, we want to preserve our * precious DMA-able memory... diff --git a/arch/arm/mm/pageattr.c b/arch/arm/mm/pageattr.c index 526bf59e61cc..c11064517f56 100644 --- a/arch/arm/mm/pageattr.c +++ b/arch/arm/mm/pageattr.c @@ -503,6 +503,8 @@ static int split_large_page(pte_t *kpte, unsigned long address) pgprot_t ref_prot = 0, ext_prot = 0; int ret = 0; + BUG_ON((address & PMD_MASK) < __pa(_end)); + pbase = pte_alloc_one_kernel(&init_mm, address); if (!pbase) return -ENOMEM; -- cgit v1.2.3 From 361f7676aaecfd0157b89f0e106f59fcc229a839 Mon Sep 17 00:00:00 2001 From: Krishna Reddy Date: Mon, 13 Aug 2012 12:37:32 -0700 Subject: arm: tegra: la: refactor la code. This is necessary to support future tegra SOC's. Change-Id: I2f6ce328e30a6895dce16d82c4097291339155cd Signed-off-by: Krishna Reddy Reviewed-on: http://git-master/r/123146 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo Reviewed-by: Mark Stadler GVS: Gerrit_Virtual_Submit --- .../mach-tegra/include/mach/latency_allowance.h | 31 +- arch/arm/mach-tegra/la_priv_common.h | 71 +++++ arch/arm/mach-tegra/latency_allowance.c | 346 ++++----------------- arch/arm/mach-tegra/tegra3_la_priv.h | 226 ++++++++++++++ 4 files changed, 368 insertions(+), 306 deletions(-) create mode 100644 arch/arm/mach-tegra/la_priv_common.h create mode 100644 arch/arm/mach-tegra/tegra3_la_priv.h (limited to 'arch') diff --git a/arch/arm/mach-tegra/include/mach/latency_allowance.h b/arch/arm/mach-tegra/include/mach/latency_allowance.h index 8644075a88b3..5ebc6f03b810 100644 --- a/arch/arm/mach-tegra/include/mach/latency_allowance.h +++ b/arch/arm/mach-tegra/include/mach/latency_allowance.h @@ -18,19 +18,19 @@ #define _MACH_TEGRA_LATENCY_ALLOWANCE_H_ enum tegra_la_id { - TEGRA_LA_AFIR = 0, - TEGRA_LA_AFIW, + TEGRA_LA_AFIR = 0, /* T30 specific */ + TEGRA_LA_AFIW, /* T30 specific */ TEGRA_LA_AVPC_ARM7R, TEGRA_LA_AVPC_ARM7W, TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B, TEGRA_LA_DISPLAY_0C, - TEGRA_LA_DISPLAY_1B, + TEGRA_LA_DISPLAY_1B, /* T30 specific */ TEGRA_LA_DISPLAY_HC, TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB, TEGRA_LA_DISPLAY_0CB, - TEGRA_LA_DISPLAY_1BB, + TEGRA_LA_DISPLAY_1BB, /* T30 specific */ TEGRA_LA_DISPLAY_HCB, TEGRA_LA_EPPUP, TEGRA_LA_EPPU, @@ -50,27 +50,27 @@ enum tegra_la_id { TEGRA_LA_MPCOREW, TEGRA_LA_MPCORE_LPR, TEGRA_LA_MPCORE_LPW, - TEGRA_LA_MPE_UNIFBR, - TEGRA_LA_MPE_IPRED, - TEGRA_LA_MPE_AMEMRD, - TEGRA_LA_MPE_CSRD, - TEGRA_LA_MPE_UNIFBW, - TEGRA_LA_MPE_CSWR, + TEGRA_LA_MPE_UNIFBR, /* T30 specific */ + TEGRA_LA_MPE_IPRED, /* T30 specific */ + TEGRA_LA_MPE_AMEMRD, /* T30 specific */ + TEGRA_LA_MPE_CSRD, /* T30 specific */ + TEGRA_LA_MPE_UNIFBW, /* T30 specific */ + TEGRA_LA_MPE_CSWR, /* T30 specific */ TEGRA_LA_FDCDRD, TEGRA_LA_IDXSRD, TEGRA_LA_TEXSRD, TEGRA_LA_FDCDWR, TEGRA_LA_FDCDRD2, - TEGRA_LA_IDXSRD2, - TEGRA_LA_TEXSRD2, + TEGRA_LA_IDXSRD2, /* T30 specific */ + TEGRA_LA_TEXSRD2, /* T30 specific */ TEGRA_LA_FDCDWR2, TEGRA_LA_PPCS_AHBDMAR, TEGRA_LA_PPCS_AHBSLVR, TEGRA_LA_PPCS_AHBDMAW, TEGRA_LA_PPCS_AHBSLVW, TEGRA_LA_PTCR, - TEGRA_LA_SATAR, - TEGRA_LA_SATAW, + TEGRA_LA_SATAR, /* T30 specific */ + TEGRA_LA_SATAW, /* T30 specific */ TEGRA_LA_VDE_BSEVR, TEGRA_LA_VDE_MBER, TEGRA_LA_VDE_MCER, @@ -79,11 +79,12 @@ enum tegra_la_id { TEGRA_LA_VDE_DBGW, TEGRA_LA_VDE_MBEW, TEGRA_LA_VDE_TPMW, - TEGRA_LA_VI_RUV, + TEGRA_LA_VI_RUV, /* T30 specific */ TEGRA_LA_VI_WSB, TEGRA_LA_VI_WU, TEGRA_LA_VI_WV, TEGRA_LA_VI_WY, + TEGRA_LA_MAX_ID }; diff --git a/arch/arm/mach-tegra/la_priv_common.h b/arch/arm/mach-tegra/la_priv_common.h new file mode 100644 index 000000000000..5b487e5970c5 --- /dev/null +++ b/arch/arm/mach-tegra/la_priv_common.h @@ -0,0 +1,71 @@ +/* + * arch/arm/mach-tegra/la_priv_common.h + * + * Copyright (C) 2012 NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _MACH_TEGRA_LA_PRIV_H_ +#define _MACH_TEGRA_LA_PRIV_H_ + +/* maximum valid value for latency allowance */ +#define MC_LA_MAX_VALUE 255 + +#define MC_RA(r) \ + ((u32)IO_ADDRESS(TEGRA_MC_BASE) + (MC_##r)) +#define RA(r) \ + ((u32)IO_ADDRESS(TEGRA_MC_BASE) + (MC_LA_##r)) + +#define MASK(x) \ + ((0xFFFFFFFFUL >> (31 - (1 ? x) + (0 ? x))) << (0 ? x)) +#define SHIFT(x) \ + (0 ? x) +#define ID(id) \ + TEGRA_LA_##id + +#define LA_INFO(f, e, a, r, id, ss) \ +{f, e, RA(a), MASK(r), SHIFT(r), ID(id), __stringify(id), ss} + +struct la_client_info { + unsigned int fifo_size_in_atoms; + unsigned int expiration_in_ns; /* worst case expiration value */ + unsigned long reg_addr; + unsigned long mask; + unsigned long shift; + enum tegra_la_id id; + char *name; + bool scaling_supported; +}; + +struct la_scaling_info { + unsigned int threshold_low; + unsigned int threshold_mid; + unsigned int threshold_high; + int scaling_ref_count; + int actual_la_to_set; + int la_set; +}; + +struct la_scaling_reg_info { + enum tegra_la_id id; + unsigned int tl_reg_addr; + unsigned int tl_mask; + unsigned int tl_shift; + unsigned int tm_reg_addr; + unsigned int tm_mask; + unsigned int tm_shift; + unsigned int th_reg_addr; + unsigned int th_mask; + unsigned int th_shift; +}; + +#endif /* _MACH_TEGRA_LA_PRIV_H_ */ diff --git a/arch/arm/mach-tegra/latency_allowance.c b/arch/arm/mach-tegra/latency_allowance.c index f8e5ce579200..d481882ce713 100644 --- a/arch/arm/mach-tegra/latency_allowance.c +++ b/arch/arm/mach-tegra/latency_allowance.c @@ -29,68 +29,8 @@ #include #include #include - -#define MC_ARB_OVERRIDE 0xe8 -#define GLOBAL_LATENCY_SCALING_ENABLE_BIT 7 - -#define MC_LA_AFI_0 0x2e0 -#define MC_LA_AVPC_ARM7_0 0x2e4 -#define MC_LA_DC_0 0x2e8 -#define MC_LA_DC_1 0x2ec -#define MC_LA_DC_2 0x2f0 -#define MC_LA_DCB_0 0x2f4 -#define MC_LA_DCB_1 0x2f8 -#define MC_LA_DCB_2 0x2fc -#define MC_LA_EPP_0 0x300 -#define MC_LA_EPP_1 0x304 -#define MC_LA_G2_0 0x308 -#define MC_LA_G2_1 0x30c -#define MC_LA_HC_0 0x310 -#define MC_LA_HC_1 0x314 -#define MC_LA_HDA_0 0x318 -#define MC_LA_ISP_0 0x31C -#define MC_LA_MPCORE_0 0x320 -#define MC_LA_MPCORELP_0 0x324 -#define MC_LA_MPE_0 0x328 -#define MC_LA_MPE_1 0x32c -#define MC_LA_MPE_2 0x330 -#define MC_LA_NV_0 0x334 -#define MC_LA_NV_1 0x338 -#define MC_LA_NV2_0 0x33c -#define MC_LA_NV2_1 0x340 -#define MC_LA_PPCS_0 0x344 -#define MC_LA_PPCS_1 0x348 -#define MC_LA_PTC_0 0x34c -#define MC_LA_SATA_0 0x350 -#define MC_LA_VDE_0 0x354 -#define MC_LA_VDE_1 0x358 -#define MC_LA_VDE_2 0x35c -#define MC_LA_VDE_3 0x360 -#define MC_LA_VI_0 0x364 -#define MC_LA_VI_1 0x368 -#define MC_LA_VI_2 0x36c - -#define DS_DISP_MCCIF_DISPLAY0A_HYST (0x481 * 4) -#define DS_DISP_MCCIF_DISPLAY0B_HYST (0x482 * 4) -#define DS_DISP_MCCIF_DISPLAY0C_HYST (0x483 * 4) -#define DS_DISP_MCCIF_DISPLAY1B_HYST (0x484 * 4) - -#define DS_DISP_MCCIF_DISPLAY0AB_HYST (0x481 * 4) -#define DS_DISP_MCCIF_DISPLAY0BB_HYST (0x482 * 4) -#define DS_DISP_MCCIF_DISPLAY0CB_HYST (0x483 * 4) -#define DS_DISP_MCCIF_DISPLAY1BB_HYST (0x484 * 4) - -#define VI_MCCIF_VIWSB_HYST (0x9a * 4) -#define VI_MCCIF_VIWU_HYST (0x9b * 4) -#define VI_MCCIF_VIWV_HYST (0x9c * 4) -#define VI_MCCIF_VIWY_HYST (0x9d * 4) - -#define VI_TIMEOUT_WOCAL_VI (0x70 * 4) -#define VI_RESERVE_3 (0x97 * 4) -#define VI_RESERVE_4 (0x98 * 4) - -/* maximum valid value for latency allowance */ -#define MC_LA_MAX_VALUE 255 +#include "la_priv_common.h" +#include "tegra3_la_priv.h" #define ENABLE_LA_DEBUG 0 #define TEST_LA_CODE 0 @@ -104,209 +44,18 @@ #define HACK_LA_FIFO 1 static struct dentry *latency_debug_dir; - -struct la_client_info { - unsigned int fifo_size_in_atoms; - unsigned int expiration_in_ns; /* worst case expiration value */ - unsigned long reg_addr; - unsigned long mask; - unsigned long shift; - enum tegra_la_id id; - char *name; - bool scaling_supported; -}; - static DEFINE_SPINLOCK(safety_lock); - -static const int ns_per_tick = 30; -/* fifo atom size in bytes for non-fdc clients*/ -static const int normal_atom_size = 16; -/* fifo atom size in bytes for fdc clients*/ -static const int fdc_atom_size = 32; - -#define MC_RA(r) \ - ((u32)IO_ADDRESS(TEGRA_MC_BASE) + (MC_##r)) -#define RA(r) \ - ((u32)IO_ADDRESS(TEGRA_MC_BASE) + (MC_LA_##r)) - -#define MASK(x) \ - ((0xFFFFFFFFUL >> (31 - (1 ? x) + (0 ? x))) << (0 ? x)) -#define SHIFT(x) \ - (0 ? x) -#define ID(id) \ - TEGRA_LA_##id - -#define LA_INFO(f, e, a, r, id, ss) \ -{f, e, RA(a), MASK(r), SHIFT(r), ID(id), __stringify(id), ss} - -/* - * The rule for getting the fifo_size_in_atoms is: - * 1.If REORDER_DEPTH exists, use it(default is overridden). - * 2.Else if (write_client) use RFIFO_DEPTH. - * 3.Else (read client) use RDFIFO_DEPTH. - * Refer to project.h file. - */ -struct la_client_info la_info[] = { - LA_INFO(32, 150, AFI_0, 7 : 0, AFIR, false), - LA_INFO(32, 150, AFI_0, 23 : 16, AFIW, false), - LA_INFO(2, 150, AVPC_ARM7_0, 7 : 0, AVPC_ARM7R, false), - LA_INFO(2, 150, AVPC_ARM7_0, 23 : 16, AVPC_ARM7W, false), - LA_INFO(128, 1050, DC_0, 7 : 0, DISPLAY_0A, true), - LA_INFO(64, 1050, DC_0, 23 : 16, DISPLAY_0B, true), - LA_INFO(128, 1050, DC_1, 7 : 0, DISPLAY_0C, true), - LA_INFO(64, 1050, DC_1, 23 : 16, DISPLAY_1B, true), - LA_INFO(2, 1050, DC_2, 7 : 0, DISPLAY_HC, false), - LA_INFO(128, 1050, DCB_0, 7 : 0, DISPLAY_0AB, true), - LA_INFO(64, 1050, DCB_0, 23 : 16, DISPLAY_0BB, true), - LA_INFO(128, 1050, DCB_1, 7 : 0, DISPLAY_0CB, true), - LA_INFO(64, 1050, DCB_1, 23 : 16, DISPLAY_1BB, true), - LA_INFO(2, 1050, DCB_2, 7 : 0, DISPLAY_HCB, false), - LA_INFO(8, 150, EPP_0, 7 : 0, EPPUP, false), - LA_INFO(64, 150, EPP_0, 23 : 16, EPPU, false), - LA_INFO(64, 150, EPP_1, 7 : 0, EPPV, false), - LA_INFO(64, 150, EPP_1, 23 : 16, EPPY, false), - LA_INFO(64, 150, G2_0, 7 : 0, G2PR, false), - LA_INFO(64, 150, G2_0, 23 : 16, G2SR, false), - LA_INFO(48, 150, G2_1, 7 : 0, G2DR, false), - LA_INFO(128, 150, G2_1, 23 : 16, G2DW, false), - LA_INFO(16, 150, HC_0, 7 : 0, HOST1X_DMAR, false), - LA_INFO(8, 150, HC_0, 23 : 16, HOST1XR, false), - LA_INFO(32, 150, HC_1, 7 : 0, HOST1XW, false), - LA_INFO(16, 150, HDA_0, 7 : 0, HDAR, false), - LA_INFO(16, 150, HDA_0, 23 : 16, HDAW, false), - LA_INFO(64, 150, ISP_0, 7 : 0, ISPW, false), - LA_INFO(14, 150, MPCORE_0, 7 : 0, MPCORER, false), - LA_INFO(24, 150, MPCORE_0, 23 : 16, MPCOREW, false), - LA_INFO(14, 150, MPCORELP_0, 7 : 0, MPCORE_LPR, false), - LA_INFO(24, 150, MPCORELP_0, 23 : 16, MPCORE_LPW, false), - LA_INFO(8, 150, MPE_0, 7 : 0, MPE_UNIFBR, false), - LA_INFO(2, 150, MPE_0, 23 : 16, MPE_IPRED, false), - LA_INFO(64, 150, MPE_1, 7 : 0, MPE_AMEMRD, false), - LA_INFO(8, 150, MPE_1, 23 : 16, MPE_CSRD, false), - LA_INFO(8, 150, MPE_2, 7 : 0, MPE_UNIFBW, false), - LA_INFO(8, 150, MPE_2, 23 : 16, MPE_CSWR, false), - LA_INFO(48, 150, NV_0, 7 : 0, FDCDRD, false), - LA_INFO(64, 150, NV_0, 23 : 16, IDXSRD, false), - LA_INFO(64, 150, NV_1, 7 : 0, TEXSRD, false), - LA_INFO(48, 150, NV_1, 23 : 16, FDCDWR, false), - LA_INFO(48, 150, NV2_0, 7 : 0, FDCDRD2, false), - LA_INFO(64, 150, NV2_0, 23 : 16, IDXSRD2, false), - LA_INFO(64, 150, NV2_1, 7 : 0, TEXSRD2, false), - LA_INFO(48, 150, NV2_1, 23 : 16, FDCDWR2, false), - LA_INFO(2, 150, PPCS_0, 7 : 0, PPCS_AHBDMAR, false), - LA_INFO(8, 150, PPCS_0, 23 : 16, PPCS_AHBSLVR, false), - LA_INFO(2, 150, PPCS_1, 7 : 0, PPCS_AHBDMAW, false), - LA_INFO(4, 150, PPCS_1, 23 : 16, PPCS_AHBSLVW, false), - LA_INFO(2, 150, PTC_0, 7 : 0, PTCR, false), - LA_INFO(32, 150, SATA_0, 7 : 0, SATAR, false), - LA_INFO(32, 150, SATA_0, 23 : 16, SATAW, false), - LA_INFO(8, 150, VDE_0, 7 : 0, VDE_BSEVR, false), - LA_INFO(4, 150, VDE_0, 23 : 16, VDE_MBER, false), - LA_INFO(16, 150, VDE_1, 7 : 0, VDE_MCER, false), - LA_INFO(16, 150, VDE_1, 23 : 16, VDE_TPER, false), - LA_INFO(4, 150, VDE_2, 7 : 0, VDE_BSEVW, false), - LA_INFO(16, 150, VDE_2, 23 : 16, VDE_DBGW, false), - LA_INFO(2, 150, VDE_3, 7 : 0, VDE_MBEW, false), - LA_INFO(16, 150, VDE_3, 23 : 16, VDE_TPMW, false), - LA_INFO(8, 1050, VI_0, 7 : 0, VI_RUV, false), - LA_INFO(64, 1050, VI_0, 23 : 16, VI_WSB, true), - LA_INFO(64, 1050, VI_1, 7 : 0, VI_WU, true), - LA_INFO(64, 1050, VI_1, 23 : 16, VI_WV, true), - LA_INFO(64, 1050, VI_2, 7 : 0, VI_WY, true), - -/* end of list. */ - LA_INFO(0, 0, AFI_0, 0 : 0, MAX_ID, false) -}; - -struct la_scaling_info { - unsigned int threshold_low; - unsigned int threshold_mid; - unsigned int threshold_high; - int scaling_ref_count; - int actual_la_to_set; - int la_set; -}; - -struct la_scaling_reg_info { - enum tegra_la_id id; - unsigned int tl_reg_addr; - unsigned int tl_mask; - unsigned int tl_shift; - unsigned int tm_reg_addr; - unsigned int tm_mask; - unsigned int tm_shift; - unsigned int th_reg_addr; - unsigned int th_mask; - unsigned int th_shift; -}; - -#define DISP1_RA(r) \ - ((u32)IO_ADDRESS(TEGRA_DISPLAY_BASE) + DS_DISP_MCCIF_##r##_HYST) -#define DISP2_RA(r) \ - ((u32)IO_ADDRESS(TEGRA_DISPLAY2_BASE) + DS_DISP_MCCIF_##r##_HYST) - -#define DISP_SCALING_REG_INFO(id, r, ra) \ - { \ - ID(id), \ - ra(r), MASK(15 : 8), SHIFT(15 : 8), \ - ra(r), MASK(23 : 16), SHIFT(15 : 8), \ - ra(r), MASK(7 : 0), SHIFT(15 : 8) \ - } - -struct la_scaling_reg_info disp_info[] = { - DISP_SCALING_REG_INFO(DISPLAY_0A, DISPLAY0A, DISP1_RA), - DISP_SCALING_REG_INFO(DISPLAY_0B, DISPLAY0B, DISP1_RA), - DISP_SCALING_REG_INFO(DISPLAY_0C, DISPLAY0C, DISP1_RA), - DISP_SCALING_REG_INFO(DISPLAY_1B, DISPLAY1B, DISP1_RA), - DISP_SCALING_REG_INFO(MAX_ID, DISPLAY1B, DISP1_RA), /*dummy entry*/ - DISP_SCALING_REG_INFO(DISPLAY_0AB, DISPLAY0AB, DISP2_RA), - DISP_SCALING_REG_INFO(DISPLAY_0BB, DISPLAY0BB, DISP2_RA), - DISP_SCALING_REG_INFO(DISPLAY_0CB, DISPLAY0CB, DISP2_RA), - DISP_SCALING_REG_INFO(DISPLAY_1BB, DISPLAY1BB, DISP2_RA), -}; - -#define VI_TH_RA(r) \ - ((u32)IO_ADDRESS(TEGRA_VI_BASE) + VI_MCCIF_##r##_HYST) -#define VI_TM_RA(r) \ - ((u32)IO_ADDRESS(TEGRA_VI_BASE) + VI_TIMEOUT_WOCAL_VI) -#define VI_TL_RA(r) \ - ((u32)IO_ADDRESS(TEGRA_VI_BASE) + VI_RESERVE_##r) - -struct la_scaling_reg_info vi_info[] = { - { - ID(VI_WSB), - VI_TL_RA(4), MASK(7 : 0), SHIFT(7 : 0), - VI_TM_RA(0), MASK(7 : 0), SHIFT(7 : 0), - VI_TH_RA(VIWSB), MASK(7 : 0), SHIFT(7 : 0) - }, - { - ID(VI_WU), - VI_TL_RA(3), MASK(15 : 8), SHIFT(15 : 8), - VI_TM_RA(0), MASK(15 : 8), SHIFT(15 : 8), - VI_TH_RA(VIWU), MASK(7 : 0), SHIFT(7 : 0) - }, - { - ID(VI_WV), - VI_TL_RA(3), MASK(7 : 0), SHIFT(7 : 0), - VI_TM_RA(0), MASK(23 : 16), SHIFT(23 : 16), - VI_TH_RA(VIWV), MASK(7 : 0), SHIFT(7 : 0) - }, - { - ID(VI_WY), - VI_TL_RA(4), MASK(15 : 8), SHIFT(15 : 8), - VI_TM_RA(0), MASK(31 : 24), SHIFT(31 : 24), - VI_TH_RA(VIWY), MASK(7 : 0), SHIFT(7 : 0) - } -}; - +static unsigned short id_to_index[ID(MAX_ID) + 1]; static struct la_scaling_info scaling_info[TEGRA_LA_MAX_ID]; static int la_scaling_enable_count; #define VALIDATE_ID(id) \ do { \ - if (id >= TEGRA_LA_MAX_ID) \ + if (id >= TEGRA_LA_MAX_ID || id_to_index[id] == 0xFFFF) { \ + pr_err("%s: invalid Id=%d", __func__, id); \ return -EINVAL; \ - BUG_ON(la_info[id].id != id); \ + } \ + BUG_ON(la_info_array[id_to_index[id]].id != id); \ } while (0) #define VALIDATE_BW(bw_in_mbps) \ @@ -330,20 +79,22 @@ static void set_thresholds(struct la_scaling_reg_info *info, unsigned int thresh_mid; unsigned int thresh_high; int la_set; + int idx = id_to_index[id]; - reg_read = readl(la_info[id].reg_addr); - la_set = (reg_read & la_info[id].mask) >> la_info[id].shift; + reg_read = readl(la_info_array[idx].reg_addr); + la_set = (reg_read & la_info_array[idx].mask) >> + la_info_array[idx].shift; /* la should be set before enabling scaling. */ - BUG_ON(la_set != scaling_info[id].la_set); + BUG_ON(la_set != scaling_info[idx].la_set); - thresh_low = (scaling_info[id].threshold_low * la_set) / 100; - thresh_mid = (scaling_info[id].threshold_mid * la_set) / 100; - thresh_high = (scaling_info[id].threshold_high * la_set) / 100; + thresh_low = (scaling_info[idx].threshold_low * la_set) / 100; + thresh_mid = (scaling_info[idx].threshold_mid * la_set) / 100; + thresh_high = (scaling_info[idx].threshold_high * la_set) / 100; la_debug("%s: la_set=%d, thresh_low=%d(%d%%), thresh_mid=%d(%d%%)," " thresh_high=%d(%d%%) ", __func__, la_set, - thresh_low, scaling_info[id].threshold_low, - thresh_mid, scaling_info[id].threshold_mid, - thresh_high, scaling_info[id].threshold_high); + thresh_low, scaling_info[idx].threshold_low, + thresh_mid, scaling_info[idx].threshold_mid, + thresh_high, scaling_info[idx].threshold_high); reg_read = readl(info->tl_reg_addr); reg_write = (reg_read & ~info->tl_mask) | @@ -391,14 +142,12 @@ int tegra_set_latency_allowance(enum tegra_la_id id, int bytes_per_atom = normal_atom_size; const int fifo_scale = 4; /* 25% of the FIFO */ struct la_client_info *ci; + int idx = id_to_index[id]; VALIDATE_ID(id); VALIDATE_BW(bandwidth_in_mbps); - if (id == ID(FDCDRD) || id == ID(FDCDWR) || - id == ID(FDCDRD2) || id == ID(FDCDWR2)) - bytes_per_atom = fdc_atom_size; - ci = &la_info[id]; + ci = &la_info_array[idx]; fifo_size_in_atoms = ci->fifo_size_in_atoms; #if HACK_LA_FIFO @@ -416,18 +165,18 @@ int tegra_set_latency_allowance(enum tegra_la_id id, la_to_set = ideal_la - (ci->expiration_in_ns/ns_per_tick) - 1; } - la_debug("\n%s:id=%d,bw=%dmbps, la_to_set=%d", - __func__, id, bandwidth_in_mbps, la_to_set); + la_debug("\n%s:id=%d,idx=%d, bw=%dmbps, la_to_set=%d", + __func__, id, idx, bandwidth_in_mbps, la_to_set); la_to_set = (la_to_set < 0) ? 0 : la_to_set; la_to_set = (la_to_set > MC_LA_MAX_VALUE) ? MC_LA_MAX_VALUE : la_to_set; - scaling_info[id].actual_la_to_set = la_to_set; + scaling_info[idx].actual_la_to_set = la_to_set; spin_lock(&safety_lock); reg_read = readl(ci->reg_addr); reg_write = (reg_read & ~ci->mask) | (la_to_set << ci->shift); writel(reg_write, ci->reg_addr); - scaling_info[id].la_set = la_to_set; + scaling_info[idx].la_set = la_to_set; la_debug("reg_addr=0x%x, read=0x%x, write=0x%x", (u32)ci->reg_addr, (u32)reg_read, (u32)reg_write); spin_unlock(&safety_lock); @@ -450,21 +199,22 @@ int tegra_enable_latency_scaling(enum tegra_la_id id, { unsigned long reg; unsigned long scaling_enable_reg = MC_RA(ARB_OVERRIDE); + int idx = id_to_index[id]; VALIDATE_ID(id); VALIDATE_THRESHOLDS(threshold_low, threshold_mid, threshold_high); - if (la_info[id].scaling_supported == false) + if (la_info_array[idx].scaling_supported == false) goto exit; spin_lock(&safety_lock); la_debug("\n%s: id=%d, tl=%d, tm=%d, th=%d", __func__, id, threshold_low, threshold_mid, threshold_high); - scaling_info[id].threshold_low = threshold_low; - scaling_info[id].threshold_mid = threshold_mid; - scaling_info[id].threshold_high = threshold_high; - scaling_info[id].scaling_ref_count++; + scaling_info[idx].threshold_low = threshold_low; + scaling_info[idx].threshold_mid = threshold_mid; + scaling_info[idx].threshold_high = threshold_high; + scaling_info[idx].scaling_ref_count++; if (id >= ID(DISPLAY_0A) && id <= ID(DISPLAY_1BB)) set_disp_latency_thresholds(id); @@ -485,17 +235,18 @@ void tegra_disable_latency_scaling(enum tegra_la_id id) { unsigned long reg; unsigned long scaling_enable_reg = MC_RA(ARB_OVERRIDE); + int idx; - if (id >= TEGRA_LA_MAX_ID) - return; - BUG_ON(la_info[id].id != id); + BUG_ON(id >= TEGRA_LA_MAX_ID); + idx = id_to_index[id]; + BUG_ON(la_info_array[idx].id != id); - if (la_info[id].scaling_supported == false) + if (la_info_array[idx].scaling_supported == false) return; spin_lock(&safety_lock); la_debug("\n%s: id=%d", __func__, id); - scaling_info[id].scaling_ref_count--; - BUG_ON(scaling_info[id].scaling_ref_count < 0); + scaling_info[idx].scaling_ref_count--; + BUG_ON(scaling_info[idx].scaling_ref_count < 0); if (!--la_scaling_enable_count) { reg = readl(scaling_enable_reg); @@ -512,13 +263,13 @@ static int la_regs_show(struct seq_file *s, void *unused) unsigned long la; /* iterate the list, but don't print MAX_ID */ - for (i = 0; i < ARRAY_SIZE(la_info) - 1; i++) { - la = (readl(la_info[i].reg_addr) & la_info[i].mask) - >> la_info[i].shift; - seq_printf(s, "%-16s: %4lu\n", la_info[i].name, la); + for (i = 0; i < ARRAY_SIZE(la_info_array) - 1; i++) { + la = (readl(la_info_array[i].reg_addr) & la_info_array[i].mask) + >> la_info_array[i].shift; + seq_printf(s, "%-16s: %4lu\n", la_info_array[i].name, la); } - return 0; + return 0; } static int dbg_la_regs_open(struct inode *inode, struct file *file) @@ -550,7 +301,13 @@ late_initcall(tegra_latency_allowance_debugfs_init); static int __init tegra_latency_allowance_init(void) { + unsigned int i; + la_scaling_enable_count = 0; + memset(&id_to_index[0], 0xFF, sizeof(id_to_index)); + + for (i = 0; i < ARRAY_SIZE(la_info_array); i++) + id_to_index[la_info_array[i].id] = i; tegra_set_latency_allowance(TEGRA_LA_G2PR, 20); tegra_set_latency_allowance(TEGRA_LA_G2SR, 20); @@ -562,12 +319,19 @@ static int __init tegra_latency_allowance_init(void) core_initcall(tegra_latency_allowance_init); #if TEST_LA_CODE +#define PRINT_ID_IDX_MAPPING 0 static int __init test_la(void) { + int i; int err; enum tegra_la_id id = 0; int repeat_count = 5; +#if PRINT_ID_IDX_MAPPING + for (i = 0; i < ID(MAX_ID); i++) + pr_info("ID=0x%x, Idx=0x%x", i, id_to_index[i]); +#endif + do { for (id = 0; id < TEGRA_LA_MAX_ID; id++) { err = tegra_set_latency_allowance(id, 200); diff --git a/arch/arm/mach-tegra/tegra3_la_priv.h b/arch/arm/mach-tegra/tegra3_la_priv.h new file mode 100644 index 000000000000..7f3fa7c46931 --- /dev/null +++ b/arch/arm/mach-tegra/tegra3_la_priv.h @@ -0,0 +1,226 @@ +/* + * arch/arm/mach-tegra/tegra3_la_priv.h + * + * Copyright (C) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _MACH_TEGRA_TEGRA3_LA_PRIV_H_ +#define _MACH_TEGRA_TEGRA3_LA_PRIV_H_ + +#if defined(CONFIG_ARCH_TEGRA_3x_SOC) + +#define MC_LA_AFI_0 0x2e0 +#define MC_LA_AVPC_ARM7_0 0x2e4 +#define MC_LA_DC_0 0x2e8 +#define MC_LA_DC_1 0x2ec +#define MC_LA_DC_2 0x2f0 +#define MC_LA_DCB_0 0x2f4 +#define MC_LA_DCB_1 0x2f8 +#define MC_LA_DCB_2 0x2fc +#define MC_LA_EPP_0 0x300 +#define MC_LA_EPP_1 0x304 +#define MC_LA_G2_0 0x308 +#define MC_LA_G2_1 0x30c +#define MC_LA_HC_0 0x310 +#define MC_LA_HC_1 0x314 +#define MC_LA_HDA_0 0x318 +#define MC_LA_ISP_0 0x31C +#define MC_LA_MPCORE_0 0x320 +#define MC_LA_MPCORELP_0 0x324 +#define MC_LA_MPE_0 0x328 +#define MC_LA_MPE_1 0x32c +#define MC_LA_MPE_2 0x330 +#define MC_LA_NV_0 0x334 +#define MC_LA_NV_1 0x338 +#define MC_LA_NV2_0 0x33c +#define MC_LA_NV2_1 0x340 +#define MC_LA_PPCS_0 0x344 +#define MC_LA_PPCS_1 0x348 +#define MC_LA_PTC_0 0x34c +#define MC_LA_SATA_0 0x350 +#define MC_LA_VDE_0 0x354 +#define MC_LA_VDE_1 0x358 +#define MC_LA_VDE_2 0x35c +#define MC_LA_VDE_3 0x360 +#define MC_LA_VI_0 0x364 +#define MC_LA_VI_1 0x368 +#define MC_LA_VI_2 0x36c + +#define MC_ARB_OVERRIDE 0xe8 +#define GLOBAL_LATENCY_SCALING_ENABLE_BIT 7 + +#define DS_DISP_MCCIF_DISPLAY0A_HYST (0x481 * 4) +#define DS_DISP_MCCIF_DISPLAY0B_HYST (0x482 * 4) +#define DS_DISP_MCCIF_DISPLAY0C_HYST (0x483 * 4) +#define DS_DISP_MCCIF_DISPLAY1B_HYST (0x484 * 4) + +#define DS_DISP_MCCIF_DISPLAY0AB_HYST (0x481 * 4) +#define DS_DISP_MCCIF_DISPLAY0BB_HYST (0x482 * 4) +#define DS_DISP_MCCIF_DISPLAY0CB_HYST (0x483 * 4) +#define DS_DISP_MCCIF_DISPLAY1BB_HYST (0x484 * 4) + +#define VI_MCCIF_VIWSB_HYST (0x9a * 4) +#define VI_MCCIF_VIWU_HYST (0x9b * 4) +#define VI_MCCIF_VIWV_HYST (0x9c * 4) +#define VI_MCCIF_VIWY_HYST (0x9d * 4) + +#define VI_TIMEOUT_WOCAL_VI (0x70 * 4) +#define VI_RESERVE_3 (0x97 * 4) +#define VI_RESERVE_4 (0x98 * 4) + +/* + * The rule for getting the fifo_size_in_atoms is: + * 1.If REORDER_DEPTH exists, use it(default is overridden). + * 2.Else if (write_client) use RFIFO_DEPTH. + * 3.Else (read client) use RDFIFO_DEPTH. + * Multiply the value by 2 for wide clients. + * A client is wide, if CMW is larger than MW. + * Refer to project.h file. + */ +struct la_client_info la_info_array[] = { + LA_INFO(32, 150, AFI_0, 7 : 0, AFIR, false), + LA_INFO(32, 150, AFI_0, 23 : 16, AFIW, false), + LA_INFO(2, 150, AVPC_ARM7_0, 7 : 0, AVPC_ARM7R, false), + LA_INFO(2, 150, AVPC_ARM7_0, 23 : 16, AVPC_ARM7W, false), + LA_INFO(128, 1050, DC_0, 7 : 0, DISPLAY_0A, true), + LA_INFO(64, 1050, DC_0, 23 : 16, DISPLAY_0B, true), + LA_INFO(128, 1050, DC_1, 7 : 0, DISPLAY_0C, true), + LA_INFO(64, 1050, DC_1, 23 : 16, DISPLAY_1B, true), + LA_INFO(2, 1050, DC_2, 7 : 0, DISPLAY_HC, false), + LA_INFO(128, 1050, DCB_0, 7 : 0, DISPLAY_0AB, true), + LA_INFO(64, 1050, DCB_0, 23 : 16, DISPLAY_0BB, true), + LA_INFO(128, 1050, DCB_1, 7 : 0, DISPLAY_0CB, true), + LA_INFO(64, 1050, DCB_1, 23 : 16, DISPLAY_1BB, true), + LA_INFO(2, 1050, DCB_2, 7 : 0, DISPLAY_HCB, false), + LA_INFO(8, 150, EPP_0, 7 : 0, EPPUP, false), + LA_INFO(64, 150, EPP_0, 23 : 16, EPPU, false), + LA_INFO(64, 150, EPP_1, 7 : 0, EPPV, false), + LA_INFO(64, 150, EPP_1, 23 : 16, EPPY, false), + LA_INFO(64, 150, G2_0, 7 : 0, G2PR, false), + LA_INFO(64, 150, G2_0, 23 : 16, G2SR, false), + LA_INFO(48, 150, G2_1, 7 : 0, G2DR, false), + LA_INFO(128, 150, G2_1, 23 : 16, G2DW, false), + LA_INFO(16, 150, HC_0, 7 : 0, HOST1X_DMAR, false), + LA_INFO(8, 150, HC_0, 23 : 16, HOST1XR, false), + LA_INFO(32, 150, HC_1, 7 : 0, HOST1XW, false), + LA_INFO(16, 150, HDA_0, 7 : 0, HDAR, false), + LA_INFO(16, 150, HDA_0, 23 : 16, HDAW, false), + LA_INFO(64, 150, ISP_0, 7 : 0, ISPW, false), + LA_INFO(14, 150, MPCORE_0, 7 : 0, MPCORER, false), + LA_INFO(24, 150, MPCORE_0, 23 : 16, MPCOREW, false), + LA_INFO(14, 150, MPCORELP_0, 7 : 0, MPCORE_LPR, false), + LA_INFO(24, 150, MPCORELP_0, 23 : 16, MPCORE_LPW, false), + LA_INFO(8, 150, MPE_0, 7 : 0, MPE_UNIFBR, false), + LA_INFO(2, 150, MPE_0, 23 : 16, MPE_IPRED, false), + LA_INFO(64, 150, MPE_1, 7 : 0, MPE_AMEMRD, false), + LA_INFO(8, 150, MPE_1, 23 : 16, MPE_CSRD, false), + LA_INFO(8, 150, MPE_2, 7 : 0, MPE_UNIFBW, false), + LA_INFO(8, 150, MPE_2, 23 : 16, MPE_CSWR, false), + LA_INFO(96, 150, NV_0, 7 : 0, FDCDRD, false), + LA_INFO(64, 150, NV_0, 23 : 16, IDXSRD, false), + LA_INFO(64, 150, NV_1, 7 : 0, TEXSRD, false), + LA_INFO(96, 150, NV_1, 23 : 16, FDCDWR, false), + LA_INFO(96, 150, NV2_0, 7 : 0, FDCDRD2, false), + LA_INFO(64, 150, NV2_0, 23 : 16, IDXSRD2, false), + LA_INFO(64, 150, NV2_1, 7 : 0, TEXSRD2, false), + LA_INFO(96, 150, NV2_1, 23 : 16, FDCDWR2, false), + LA_INFO(2, 150, PPCS_0, 7 : 0, PPCS_AHBDMAR, false), + LA_INFO(8, 150, PPCS_0, 23 : 16, PPCS_AHBSLVR, false), + LA_INFO(2, 150, PPCS_1, 7 : 0, PPCS_AHBDMAW, false), + LA_INFO(4, 150, PPCS_1, 23 : 16, PPCS_AHBSLVW, false), + LA_INFO(2, 150, PTC_0, 7 : 0, PTCR, false), + LA_INFO(32, 150, SATA_0, 7 : 0, SATAR, false), + LA_INFO(32, 150, SATA_0, 23 : 16, SATAW, false), + LA_INFO(8, 150, VDE_0, 7 : 0, VDE_BSEVR, false), + LA_INFO(4, 150, VDE_0, 23 : 16, VDE_MBER, false), + LA_INFO(16, 150, VDE_1, 7 : 0, VDE_MCER, false), + LA_INFO(16, 150, VDE_1, 23 : 16, VDE_TPER, false), + LA_INFO(4, 150, VDE_2, 7 : 0, VDE_BSEVW, false), + LA_INFO(16, 150, VDE_2, 23 : 16, VDE_DBGW, false), + LA_INFO(2, 150, VDE_3, 7 : 0, VDE_MBEW, false), + LA_INFO(16, 150, VDE_3, 23 : 16, VDE_TPMW, false), + LA_INFO(8, 1050, VI_0, 7 : 0, VI_RUV, false), + LA_INFO(64, 1050, VI_0, 23 : 16, VI_WSB, true), + LA_INFO(64, 1050, VI_1, 7 : 0, VI_WU, true), + LA_INFO(64, 1050, VI_1, 23 : 16, VI_WV, true), + LA_INFO(64, 1050, VI_2, 7 : 0, VI_WY, true), + +/* end of list. */ + LA_INFO(0, 0, AFI_0, 0 : 0, MAX_ID, false) +}; + +#define DISP1_RA(r) \ + ((u32)IO_ADDRESS(TEGRA_DISPLAY_BASE) + DS_DISP_MCCIF_##r##_HYST) +#define DISP2_RA(r) \ + ((u32)IO_ADDRESS(TEGRA_DISPLAY2_BASE) + DS_DISP_MCCIF_##r##_HYST) + +#define DISP_SCALING_REG_INFO(id, r, ra) \ + { \ + ID(id), \ + ra(r), MASK(15 : 8), SHIFT(15 : 8), \ + ra(r), MASK(23 : 16), SHIFT(15 : 8), \ + ra(r), MASK(7 : 0), SHIFT(15 : 8) \ + } + +struct la_scaling_reg_info disp_info[] = { + DISP_SCALING_REG_INFO(DISPLAY_0A, DISPLAY0A, DISP1_RA), + DISP_SCALING_REG_INFO(DISPLAY_0B, DISPLAY0B, DISP1_RA), + DISP_SCALING_REG_INFO(DISPLAY_0C, DISPLAY0C, DISP1_RA), + DISP_SCALING_REG_INFO(DISPLAY_1B, DISPLAY1B, DISP1_RA), + DISP_SCALING_REG_INFO(MAX_ID, DISPLAY1B, DISP1_RA), /*dummy entry*/ + DISP_SCALING_REG_INFO(DISPLAY_0AB, DISPLAY0AB, DISP2_RA), + DISP_SCALING_REG_INFO(DISPLAY_0BB, DISPLAY0BB, DISP2_RA), + DISP_SCALING_REG_INFO(DISPLAY_0CB, DISPLAY0CB, DISP2_RA), + DISP_SCALING_REG_INFO(DISPLAY_1BB, DISPLAY1BB, DISP2_RA), +}; + +#define VI_TH_RA(r) \ + ((u32)IO_ADDRESS(TEGRA_VI_BASE) + VI_MCCIF_##r##_HYST) +#define VI_TM_RA(r) \ + ((u32)IO_ADDRESS(TEGRA_VI_BASE) + VI_TIMEOUT_WOCAL_VI) +#define VI_TL_RA(r) \ + ((u32)IO_ADDRESS(TEGRA_VI_BASE) + VI_RESERVE_##r) + +struct la_scaling_reg_info vi_info[] = { + { + ID(VI_WSB), + VI_TL_RA(4), MASK(7 : 0), SHIFT(7 : 0), + VI_TM_RA(0), MASK(7 : 0), SHIFT(7 : 0), + VI_TH_RA(VIWSB), MASK(7 : 0), SHIFT(7 : 0) + }, + { + ID(VI_WU), + VI_TL_RA(3), MASK(15 : 8), SHIFT(15 : 8), + VI_TM_RA(0), MASK(15 : 8), SHIFT(15 : 8), + VI_TH_RA(VIWU), MASK(7 : 0), SHIFT(7 : 0) + }, + { + ID(VI_WV), + VI_TL_RA(3), MASK(7 : 0), SHIFT(7 : 0), + VI_TM_RA(0), MASK(23 : 16), SHIFT(23 : 16), + VI_TH_RA(VIWV), MASK(7 : 0), SHIFT(7 : 0) + }, + { + ID(VI_WY), + VI_TL_RA(4), MASK(15 : 8), SHIFT(15 : 8), + VI_TM_RA(0), MASK(31 : 24), SHIFT(31 : 24), + VI_TH_RA(VIWY), MASK(7 : 0), SHIFT(7 : 0) + } +}; + +static const int ns_per_tick = 30; +/* Tegra3 MC atom size in bytes */ +static const int normal_atom_size = 16; +#endif + +#endif /* _MACH_TEGRA_TEGRA3_LA_PRIV_H_ */ -- cgit v1.2.3 From aa0cae6ab52a7fc278ee3cc29d56cc4daa807004 Mon Sep 17 00:00:00 2001 From: Ilan Aelion Date: Fri, 10 Aug 2012 13:53:10 -0600 Subject: video: tegra: dc: disuse notifier Due to issues with rcu notifiers on secureos, modifying dc flip notifications to use a simple callback instead. Bug 1028850 Change-Id: Iebf2a6d64d7316e3df2b88444201f9f9a29698c5 Signed-off-by: Ilan Aelion Reviewed-on: http://git-master/r/123103 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo Reviewed-by: Terje Bergstrom Reviewed-by: Nitin Kumbhar --- arch/arm/mach-tegra/include/mach/dc.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/include/mach/dc.h b/arch/arm/mach-tegra/include/mach/dc.h index 47210c1cd87b..b60a913ff083 100644 --- a/arch/arm/mach-tegra/include/mach/dc.h +++ b/arch/arm/mach-tegra/include/mach/dc.h @@ -25,7 +25,6 @@ #include #include #include -#include #define TEGRA_MAX_DC 2 #define DC_N_WINDOWS 3 @@ -585,8 +584,8 @@ struct tegra_dc_edid { struct tegra_dc_edid *tegra_dc_get_edid(struct tegra_dc *dc); void tegra_dc_put_edid(struct tegra_dc_edid *edid); -int tegra_dc_register_flip_notifier(struct notifier_block *nb); -int tegra_dc_unregister_flip_notifier(struct notifier_block *nb); +int tegra_dc_set_flip_callback(void (*callback)(void)); +int tegra_dc_unset_flip_callback(void); int tegra_dc_get_panel_sync_rate(void); #endif -- cgit v1.2.3 From 43ecb3724fa90222dd6cd502aee422364b0c65cb Mon Sep 17 00:00:00 2001 From: Srikanth Nori Date: Mon, 2 Jul 2012 17:35:38 -0700 Subject: ARM: tegra: clocks: Frequency stats for SCLK/CBUS This adds a frequency histogram of the frequencies that SCLK and CBUS clocks go to over time. Stats are presented in the debugfs at /d/clock_stats/cbus and /d/clock_stats/sclk only if debugfs is enabled in config Change-Id: Icae83329612958d8ed4318b2e10c487683d9d734 Signed-off-by: Dan Willemsen Reviewed-on: http://git-master/r/118380 Reviewed-by: Wen Yi Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Cherry --- arch/arm/mach-tegra/Makefile | 1 + arch/arm/mach-tegra/clocks_stats.c | 259 ++++++++++++++++++++++++++++++++++++ arch/arm/mach-tegra/tegra3_clocks.c | 5 +- 3 files changed, 264 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-tegra/clocks_stats.c (limited to 'arch') diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index cf51359c32e7..cb84614919bd 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -19,6 +19,7 @@ obj-y += tegra2_clocks.o obj-y += timer-t2.o else obj-y += tegra3_clocks.o +obj-$(CONFIG_DEBUG_FS) += clocks_stats.o obj-y += timer-t3.o endif obj-y += pinmux.o diff --git a/arch/arm/mach-tegra/clocks_stats.c b/arch/arm/mach-tegra/clocks_stats.c new file mode 100644 index 000000000000..1018a24ddbf9 --- /dev/null +++ b/arch/arm/mach-tegra/clocks_stats.c @@ -0,0 +1,259 @@ +/* + * arch/arm/mach-tegra/clocks_stats.c + * + * Copyright (C) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#include +#include + +#include "clock.h" + +#define STATS_TABLE_MAX_SIZE 64 + +/* + * Generic stats tracking structures and functions + */ +struct stats_entry { + int rate; + cputime64_t time_at_rate; +}; + +struct stats_table { + struct stats_entry *entry; + int last_rate; + cputime64_t last_updated; + spinlock_t spinlock; + unsigned int num_entries; +}; + +struct clock_data { + struct dentry *dentry; + struct list_head node; + struct stats_table table; + struct notifier_block rate_change_nb; +}; + +static LIST_HEAD(clock_stats); +static struct dentry *clock_debugfs_root; + +/* + * Initialize a stats table to zeros + */ +static void init_stats_table(struct stats_table *table) +{ + table->last_rate = -1; + spin_lock_init(&(table->spinlock)); + table->num_entries = 0; + table->last_updated = get_jiffies_64(); +} + +/* + * Populate table with possible rates + */ +static int populate_rates(struct stats_table *table, struct clk *c) +{ + unsigned long rate = 0, rounded_rate = 0; + unsigned int num_rates = 0; + int i = 0; + + /* Calculate number of rates */ + while (rate <= c->max_rate) { + rounded_rate = c->ops->round_rate(c, rate); + if (IS_ERR_VALUE(rounded_rate) || (rounded_rate <= rate)) + break; + + num_rates++; + rate = rounded_rate + 2000; /* 2kHz resolution */ + } + + /* Allocate space for a table of that size */ + table->entry = kmalloc(num_rates * sizeof(struct stats_entry), + GFP_KERNEL); + if (!table->entry) + return -ENOMEM; + rate = 0; + i = 0; + + /* Populate table with possible rates */ + while (rate <= c->max_rate) { + rounded_rate = c->ops->round_rate(c, rate); + if (IS_ERR_VALUE(rounded_rate) || (rounded_rate <= rate)) + break; + + table->entry[i].rate = rounded_rate; + table->entry[i].time_at_rate = 0; + i++; + rate = rounded_rate + 2000; /* 2kHz resolution */ + } + + table->num_entries = num_rates; + + return 0; +} + +/* + * Function is called whenever a rate changes. The time spent + * in the 'old rate' is finalized and the new rate is tracked. + * Entries are tracked in increasing order of rate + */ +static void update_stats_table(struct stats_table *table, int new_rate) +{ + int i = 0; + unsigned long flags; + u64 cur_jiffies = get_jiffies_64(); + + spin_lock_irqsave(&table->spinlock, flags); + + if (new_rate == -1) + new_rate = table->last_rate; + + /* update time spent on old clock */ + for (i = 0; i < table->num_entries; i++) { + if (table->entry[i].rate == table->last_rate) { + table->entry[i].time_at_rate = cputime64_add( + table->entry[i].time_at_rate, + cputime64_sub(cur_jiffies, + table->last_updated)); + } + } + + table->last_updated = cur_jiffies; + table->last_rate = new_rate; + + spin_unlock_irqrestore(&table->spinlock, flags); + +} + +/* + * Print stats table to seq_file + */ +static void dump_stats_table(struct seq_file *s, struct stats_table *table) +{ + int i = 0; + update_stats_table(table, -1); + + seq_printf(s, "%-10s %-10s\n", "rate kHz", "time"); + for (i = 0; i < table->num_entries; i++) { + seq_printf(s, "%-10lu %-10llu\n", + (long unsigned int)(table->entry[i].rate/1000), + cputime64_to_clock_t(table->entry[i].time_at_rate)); + } +} + +static int stats_show(struct seq_file *s, void *data) +{ + struct clock_data *d = (struct clock_data *)(s->private); + dump_stats_table(s, &d->table); + return 0; +} + +static int stats_open(struct inode *inode, struct file *file) +{ + return single_open(file, stats_show, inode->i_private); +} + +static const struct file_operations clock_stats_fops = { + .open = stats_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +/* + * Clock rate change notification callback + */ +static int rate_notify_cb(struct notifier_block *nb, unsigned long rate, + void *v) +{ + struct clock_data *c = + container_of(nb, struct clock_data, rate_change_nb); + update_stats_table(&c->table, rate); + return NOTIFY_OK; +} + +/* + * Call once for each clock to track + */ +static int track_clock(char *clk_name) +{ + int ret = 0; + struct clock_data *d; + struct clk *c = clk_get(NULL, clk_name); + if (IS_ERR(c)) + return PTR_ERR(c); + + d = kmalloc(sizeof(struct clock_data), GFP_KERNEL); + if (d == NULL) + goto err_clk; + + d->rate_change_nb.notifier_call = rate_notify_cb; + + if (!clock_debugfs_root) + goto err_clk; + + d->dentry = debugfs_create_file( + clk_name, S_IRUGO, clock_debugfs_root, d, &clock_stats_fops); + if (!d->dentry) + goto err_clk; + + init_stats_table(&d->table); + ret = populate_rates(&d->table, c); + if (ret) + goto err_out; + + ret = tegra_register_clk_rate_notifier(c, &d->rate_change_nb); + if (ret) + goto err_out; + + list_add(&d->node, &clock_stats); + + clk_put(c); + return 0; + +err_out: + kfree(d->table.entry); + debugfs_remove(d->dentry); +err_clk: + kfree(d); + clk_put(c); + return -ENOMEM; +} + +static int __init tegra_clocks_debug_init(void) +{ + int ret = 0; + + clock_debugfs_root = debugfs_create_dir("clock_stats", NULL); + if (!clock_debugfs_root) + return -ENOMEM; + + /* Start tracking individual clocks */ + ret = track_clock("sbus"); + if (0 != ret) + goto err_out; + + ret = track_clock("cbus"); + if (0 != ret) + goto err_out; + + return 0; + +err_out: + return ret; + +} +late_initcall(tegra_clocks_debug_init); diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 828a806ff99f..9793c7ab052b 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -4232,6 +4232,8 @@ static struct clk tegra_clk_emc_bridge = { .parent = &tegra_clk_emc, }; +static RAW_NOTIFIER_HEAD(cbus_rate_change_nh); + static struct clk tegra_clk_cbus = { .name = "cbus", .parent = &tegra_pll_c, @@ -4243,7 +4245,8 @@ static struct clk tegra_clk_cbus = { .shared_bus_backup = { .input = &tegra_pll_p, .value = 2, - } + }, + .rate_change_nh = &cbus_rate_change_nh, }; #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \ -- cgit v1.2.3 From a6e2dc5aacc56bdbc771cdf0e9e75924c1ea6650 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 31 Jul 2012 15:38:43 +0530 Subject: gpio: tegra: hide tegra_gpio_enable()/disable() The direction apis and irq_set_wake() support the configuration of pins in gpio mode and hence it is not require to export the apis for gpio_enable()/ gpio_disable(). Hiding these api. Change-Id: I5493e4f270df85da21afb6500ac841f4fa4b522a Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/119616 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas GVS: Gerrit_Virtual_Submit --- arch/arm/mach-tegra/include/mach/gpio.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/include/mach/gpio.h b/arch/arm/mach-tegra/include/mach/gpio.h index b7357ab0c4dd..031179a3259d 100644 --- a/arch/arm/mach-tegra/include/mach/gpio.h +++ b/arch/arm/mach-tegra/include/mach/gpio.h @@ -71,8 +71,6 @@ struct tegra_gpio_table { }; void tegra_gpio_config(struct tegra_gpio_table *table, int num); -void tegra_gpio_enable(int gpio); -void tegra_gpio_disable(int gpio); int tegra_gpio_resume_init(void); void tegra_gpio_init_configure(unsigned gpio, bool is_input, int value); void tegra_gpio_set_tristate(int gpio, enum tegra_tristate ts); -- cgit v1.2.3 From 6399f339601cee0f39e48011265d0e324e7dd99e Mon Sep 17 00:00:00 2001 From: Krishna Yarlagadda Date: Tue, 14 Aug 2012 21:36:59 +0530 Subject: ARM: tegra: usb: handle device connect in lp0 When a otg cable is connected along with device during lp0 system will wakeup but might not complete device enumeration before going back to lp0. In this case we have to handle pmc disable. Bug 1024456 Change-Id: I9acbf434e58776c3d58de1b28d442d6b20b256d0 Signed-off-by: Krishna Yarlagadda Reviewed-on: http://git-master/r/123383 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty --- arch/arm/mach-tegra/tegra3_usb_phy.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index af9eaab782c7..b02e9b646284 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -1657,11 +1657,11 @@ static void utmi_phy_restore_start(struct tegra_usb_phy *phy) if (UTMIP_WALK_PTR_VAL(inst) & val) { phy->remote_wakeup = true; } else if(!phy->remote_wakeup) { - if (!((UTMIP_USBON_VAL(phy->inst) | - UTMIP_USBOP_VAL(phy->inst)) & val)) { - utmip_phy_disable_pmc_bus_ctrl(phy); - } + val = readl(pmc_base + PMC_SLEEP_CFG); + if (val & UTMIP_MASTER_ENABLE(inst)) + utmip_phy_disable_pmc_bus_ctrl(phy); } + utmi_phy_enable_obs_bus(phy); } -- cgit v1.2.3 From e2862b9cd75bb9f608db0c33bef47f3952df5f26 Mon Sep 17 00:00:00 2001 From: Charlie Huang Date: Fri, 10 Aug 2012 16:26:34 -0700 Subject: ARM: tegra: cardhu: adjust ov2710 power sequence To fix an instability issue, the power sequence is updated to match the specification for this device. bug 1031318 Change-Id: I3970af7ae8ed2baa6060f548242b0093040afb53 Signed-off-by: Charlie Huang Reviewed-on: http://git-master/r/122867 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Patrick Shehane Reviewed-by: Dan Willemsen --- arch/arm/mach-tegra/board-cardhu-sensors.c | 45 ++++++++++++++++-------------- 1 file changed, 24 insertions(+), 21 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-sensors.c b/arch/arm/mach-tegra/board-cardhu-sensors.c index bb6a2ae5774d..7e9774f290eb 100644 --- a/arch/arm/mach-tegra/board-cardhu-sensors.c +++ b/arch/arm/mach-tegra/board-cardhu-sensors.c @@ -340,7 +340,7 @@ static int cardhu_right_ov5650_power_off(void) gpio_direction_output(CAMERA_CSI_MUX_SEL_GPIO, 0); /* Boards E1198 and E1291 are of Cardhu personality - * and donot have TCA6416 exp for camera */ + * and do not have TCA6416 for camera */ if ((board_info.board_id == BOARD_E1198) || (board_info.board_id == BOARD_E1291)) { gpio_direction_output(CAM1_POWER_DWN_GPIO, 1); @@ -387,16 +387,21 @@ static int cardhu_ov2710_power_on(void) /* CSI-B and front sensor are muxed on cardhu */ gpio_direction_output(CAMERA_CSI_MUX_SEL_GPIO, 1); + /* Enable VDD_1V8_Cam3 */ + if (cardhu_1v8_cam3 == NULL) { + cardhu_1v8_cam3 = regulator_get(NULL, "vdd_1v8_cam3"); + if (WARN_ON(IS_ERR(cardhu_1v8_cam3))) { + pr_err("%s: couldn't get regulator vdd_1v8_cam3: %ld\n", + __func__, PTR_ERR(cardhu_1v8_cam3)); + goto reg_alloc_fail; + } + } + regulator_enable(cardhu_1v8_cam3); + /* Boards E1198 and E1291 are of Cardhu personality - * and donot have TCA6416 exp for camera */ + * and do not have TCA6416 for camera */ if ((board_info.board_id == BOARD_E1198) || (board_info.board_id == BOARD_E1291)) { - - gpio_direction_output(CAM1_POWER_DWN_GPIO, 0); - gpio_direction_output(CAM2_POWER_DWN_GPIO, 0); - gpio_direction_output(CAM3_POWER_DWN_GPIO, 0); - mdelay(10); - if (cardhu_vdd_cam3 == NULL) { cardhu_vdd_cam3 = regulator_get(NULL, "vdd_cam3"); if (WARN_ON(IS_ERR(cardhu_vdd_cam3))) { @@ -406,19 +411,17 @@ static int cardhu_ov2710_power_on(void) } } regulator_enable(cardhu_vdd_cam3); - } - /* Enable VDD_1V8_Cam3 */ - if (cardhu_1v8_cam3 == NULL) { - cardhu_1v8_cam3 = regulator_get(NULL, "vdd_1v8_cam3"); - if (WARN_ON(IS_ERR(cardhu_1v8_cam3))) { - pr_err("%s: couldn't get regulator vdd_1v8_cam3: %ld\n", - __func__, PTR_ERR(cardhu_1v8_cam3)); - goto reg_alloc_fail; - } + mdelay(5); + + gpio_direction_output(CAM1_POWER_DWN_GPIO, 0); + gpio_direction_output(CAM2_POWER_DWN_GPIO, 0); + gpio_direction_output(CAM3_POWER_DWN_GPIO, 0); + mdelay(10); + } - regulator_enable(cardhu_1v8_cam3); - mdelay(5); + + mdelay(20); return 0; @@ -447,12 +450,12 @@ static int cardhu_ov2710_power_off(void) gpio_direction_output(CAM1_POWER_DWN_GPIO, 1); gpio_direction_output(CAM2_POWER_DWN_GPIO, 1); gpio_direction_output(CAM3_POWER_DWN_GPIO, 1); + if (cardhu_vdd_cam3) + regulator_disable(cardhu_vdd_cam3); } if (cardhu_1v8_cam3) regulator_disable(cardhu_1v8_cam3); - if (cardhu_vdd_cam3) - regulator_disable(cardhu_vdd_cam3); return 0; } -- cgit v1.2.3 From b65484c57a46d23decc570350ca1c07bb5be111e Mon Sep 17 00:00:00 2001 From: Ashwin Joshi Date: Fri, 27 Jul 2012 15:58:50 +0530 Subject: ARM: tegra: e1853: Add build support for E1853 E1853 is T30 based automotive platform. Modify Makefile to support build of E1853 board. Also, added config option to Kconfig file. Bug 966833 Bug 1018258 Change-Id: I18dc015b79256fde1c77947198b426a0060a9017 Signed-off-by: Ashwin Joshi Reviewed-on: http://git-master/r/118932 Reviewed-by: Sandeep Trasi Reviewed-by: Automatic_Commit_Validation_User (cherry picked from commit bed57d893803f2ccef8f40bd30bdf1e8a44f184b) Reviewed-on: http://git-master/r/119652 GVS: Gerrit_Virtual_Submit Tested-by: Haribabu Narayanan Reviewed-by: Bob Johnston Reviewed-by: Krishna Reddy --- arch/arm/mach-tegra/Kconfig | 13 +++++++++++++ arch/arm/mach-tegra/Makefile | 5 +++++ 2 files changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index b69f0dc6e24d..f4f4d58452ed 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -187,6 +187,12 @@ config MACH_P1852 help Support for NVIDIA P1852 development platform +config MACH_E1853 + bool "E1853 board" + depends on ARCH_TEGRA_3x_SOC + help + Support for NVIDIA E1853 development platform + config MACH_TEGRA_ENTERPRISE bool "Enterprise board" depends on ARCH_TEGRA_3x_SOC @@ -286,6 +292,13 @@ config TEGRA_P1852_TDM Enables TDM mode driver for P1852 SKUs. If this is not defined then I2S mode is selected by default. +config TEGRA_TDM + bool "Enable TDM mode for Automotive SKUs" + depends on MACH_E1853 + help + Enables TDM mode driver for Automotive SKUs. If this + is not defined then I2S mode is selected by default. + config TEGRA_CARDHU_DSI bool "Support DSI panel on Cardhu" depends on MACH_CARDHU diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index cb84614919bd..3aa3e32848f8 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -183,6 +183,11 @@ obj-${CONFIG_MACH_P1852} += board-p1852-panel.o obj-${CONFIG_MACH_P1852} += board-p1852-pinmux.o obj-${CONFIG_MACH_P1852} += board-p1852-sdhci.o +obj-${CONFIG_MACH_E1853} += board-e1853.o +obj-${CONFIG_MACH_E1853} += board-e1853-panel.o +obj-${CONFIG_MACH_E1853} += board-e1853-pinmux.o +obj-${CONFIG_MACH_E1853} += board-e1853-sdhci.o + obj-${CONFIG_MACH_TEGRA_ENTERPRISE} += board-enterprise.o obj-${CONFIG_MACH_TEGRA_ENTERPRISE} += board-enterprise-panel.o obj-${CONFIG_MACH_TEGRA_ENTERPRISE} += board-enterprise-pinmux.o -- cgit v1.2.3 From e4e2e776a3d4bf1adf37fc061cfdfb92281f3ace Mon Sep 17 00:00:00 2001 From: Raghavendra VK Date: Fri, 3 Aug 2012 21:25:43 -0700 Subject: video: tegra: dc: Add timestamp support bug 1021221 Change-Id: Ifbe007de5bdeafaa15a0b3f2a138086045eba160 Signed-off-by: Raghavendra VK Reviewed-on: http://git-master/r/118179 (cherry picked from commit 74be8d4e7210d7bcea0d55565a7cbb06d6cc960e) Reviewed-on: http://git-master/r/121087 Reviewed-by: Jon Mayo Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Robert Morell --- arch/arm/mach-tegra/include/mach/dc.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/include/mach/dc.h b/arch/arm/mach-tegra/include/mach/dc.h index b60a913ff083..3483fe91ce66 100644 --- a/arch/arm/mach-tegra/include/mach/dc.h +++ b/arch/arm/mach-tegra/include/mach/dc.h @@ -539,6 +539,9 @@ void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val); */ int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n); int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n); +int tegra_dc_config_frame_end_intr(struct tegra_dc *dc, bool enable); +bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts); +bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts); int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode); struct fb_videomode; -- cgit v1.2.3 From 9cdbc5579aaacca5585faa00ffa73cb493c96c72 Mon Sep 17 00:00:00 2001 From: Ray Poudrier Date: Mon, 2 Jul 2012 20:17:42 -0700 Subject: ARM: tegra: enterprise: update memory timings Extend to 60ns tick Bug 1001229 Change-Id: Id2b01218a7c5cb1566d0e8c175defb12c79e6497 Signed-off-by: Ray Poudrier Reviewed-on: http://git-master/r/113122 (cherry picked from commit 176fd3fbaede0d38281fe4bad721856e7fef0833) Reviewed-on: http://git-master/r/116220 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- arch/arm/mach-tegra/board-enterprise-memory.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-memory.c b/arch/arm/mach-tegra/board-enterprise-memory.c index 36a8264c2a21..1fc0d3c3fddd 100644 --- a/arch/arm/mach-tegra/board-enterprise-memory.c +++ b/arch/arm/mach-tegra/board-enterprise-memory.c @@ -116,7 +116,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000164, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00050001, /* MC_EMEM_ARB_CFG */ + 0x00050002, /* MC_EMEM_ARB_CFG */ 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -236,7 +236,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800001c2, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00020001, /* MC_EMEM_ARB_CFG */ + 0x00030003, /* MC_EMEM_ARB_CFG */ 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -356,7 +356,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000287, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00010001, /* MC_EMEM_ARB_CFG */ + 0x00010003, /* MC_EMEM_ARB_CFG */ 0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -476,7 +476,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000001, /* MC_EMEM_ARB_CFG */ + 0x00000003, /* MC_EMEM_ARB_CFG */ 0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -596,7 +596,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000003, /* MC_EMEM_ARB_CFG */ + 0x00000006, /* MC_EMEM_ARB_CFG */ 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -716,7 +716,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000ce6, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000006, /* MC_EMEM_ARB_CFG */ + 0x0000000c, /* MC_EMEM_ARB_CFG */ 0xc0000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ -- cgit v1.2.3 From c7b8e1d6e46bd788d0d360c9fb9087f14a70c8bb Mon Sep 17 00:00:00 2001 From: Ray Poudrier Date: Tue, 3 Jul 2012 11:43:05 -0700 Subject: ARM: tegra: cardhu: update memory timings Extend tick length to 60ns Also add missed Cardhu SKU 1000 table Bug 1001229 Bug 970610 Change-Id: I224158a88d02595d5b911f59b6920b9ed99481ab Signed-off-by: Ray Poudrier Reviewed-on: http://git-master/r/113315 (cherry picked from commit 492193079047d9c5a4fff617a14191438f356e42) Reviewed-on: http://git-master/r/116221 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Wen Yi Reviewed-by: Bharat Nihalani --- arch/arm/mach-tegra/board-cardhu-memory.c | 782 ++++++++++++++++++++++++++---- 1 file changed, 694 insertions(+), 88 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-memory.c b/arch/arm/mach-tegra/board-cardhu-memory.c index 1ed99a9fa1fa..33a66053ee45 100644 --- a/arch/arm/mach-tegra/board-cardhu-memory.c +++ b/arch/arm/mach-tegra/board-cardhu-memory.c @@ -705,7 +705,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000280, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00020001, /* MC_EMEM_ARB_CFG */ + 0x00030003, /* MC_EMEM_ARB_CFG */ 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -825,7 +825,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000001, /* MC_EMEM_ARB_CFG */ + 0x00010003, /* MC_EMEM_ARB_CFG */ 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -945,7 +945,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000001, /* MC_EMEM_ARB_CFG */ + 0x00000003, /* MC_EMEM_ARB_CFG */ 0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -1065,7 +1065,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000003, /* MC_EMEM_ARB_CFG */ + 0x00000006, /* MC_EMEM_ARB_CFG */ 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -1185,8 +1185,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000005, /* MC_EMEM_ARB_CFG */ - 0x80000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x0000000b, /* MC_EMEM_ARB_CFG */ + 0xc0000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ 0x00000009, /* MC_EMEM_ARB_TIMING_RC */ @@ -1305,8 +1305,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80001941, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000006, /* MC_EMEM_ARB_CFG */ - 0x8000004a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x0000000c, /* MC_EMEM_ARB_CFG */ + 0xc000004a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ 0x0000000a, /* MC_EMEM_ARB_TIMING_RC */ @@ -1425,8 +1425,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80001bc0, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000006, /* MC_EMEM_ARB_CFG */ - 0x80000051, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x0000000d, /* MC_EMEM_ARB_CFG */ + 0xc0000051, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ 0x0000000b, /* MC_EMEM_ARB_TIMING_RC */ @@ -1545,8 +1545,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800020ae, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000008, /* MC_EMEM_ARB_CFG */ - 0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x0000000f, /* MC_EMEM_ARB_CFG */ + 0xc0000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ 0x0000000d, /* MC_EMEM_ARB_TIMING_RC */ @@ -1665,8 +1665,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a, /* MC_EMEM_ARB_CFG */ - 0x80000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000014, /* MC_EMEM_ARB_CFG */ + 0xc0000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ 0x00000010, /* MC_EMEM_ARB_TIMING_RC */ @@ -1785,8 +1785,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000c, /* MC_EMEM_ARB_CFG */ - 0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000016, /* MC_EMEM_ARB_CFG */ + 0xc0000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ 0x00000013, /* MC_EMEM_ARB_TIMING_RC */ @@ -1905,8 +1905,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000c, /* MC_EMEM_ARB_CFG */ - 0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000018, /* MC_EMEM_ARB_CFG */ + 0xc0000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ 0x00000013, /* MC_EMEM_ARB_TIMING_RC */ @@ -2025,8 +2025,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000367d, /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000d, /* MC_EMEM_ARB_CFG */ - 0x800000a2, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x0000001b, /* MC_EMEM_ARB_CFG */ + 0xc00000a2, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000005, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000006, /* MC_EMEM_ARB_TIMING_RP */ 0x00000016, /* MC_EMEM_ARB_TIMING_RC */ @@ -2148,7 +2148,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00010001, /* MC_EMEM_ARB_CFG */ + 0x00010003, /* MC_EMEM_ARB_CFG */ 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -2268,7 +2268,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000001, /* MC_EMEM_ARB_CFG */ + 0x00000003, /* MC_EMEM_ARB_CFG */ 0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -2388,7 +2388,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000003, /* MC_EMEM_ARB_CFG */ + 0x00000006, /* MC_EMEM_ARB_CFG */ 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -2508,8 +2508,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000005, /* MC_EMEM_ARB_CFG */ - 0x80000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x0000000b, /* MC_EMEM_ARB_CFG */ + 0xc0000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ 0x00000009, /* MC_EMEM_ARB_TIMING_RC */ @@ -2628,8 +2628,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800018c8, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000006, /* MC_EMEM_ARB_CFG */ - 0x80000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x0000000c, /* MC_EMEM_ARB_CFG */ + 0xc0000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ 0x00000009, /* MC_EMEM_ARB_TIMING_RC */ @@ -2748,8 +2748,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80002d93, /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000b, /* MC_EMEM_ARB_CFG */ - 0x80000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000014, /* MC_EMEM_ARB_CFG */ + 0xc0000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ 0x00000012, /* MC_EMEM_ARB_TIMING_RC */ @@ -2868,8 +2868,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80002d93, /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000b, /* MC_EMEM_ARB_CFG */ - 0x80000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000016, /* MC_EMEM_ARB_CFG */ + 0xc0000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ 0x00000012, /* MC_EMEM_ARB_TIMING_RC */ @@ -2988,8 +2988,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000c, /* MC_EMEM_ARB_CFG */ - 0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000018, /* MC_EMEM_ARB_CFG */ + 0xc0000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ 0x00000013, /* MC_EMEM_ARB_TIMING_RC */ @@ -3111,7 +3111,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000287, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00020001, /* MC_EMEM_ARB_CFG */ + 0x00030003, /* MC_EMEM_ARB_CFG */ 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -3186,14 +3186,14 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = { 0x00004288, /* EMC_FBIO_CFG5 */ 0x007800a4, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000, /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS7 */ + 0x00080000, /* EMC_DLL_XFORM_DQS0 */ + 0x00080000, /* EMC_DLL_XFORM_DQS1 */ + 0x00080000, /* EMC_DLL_XFORM_DQS2 */ + 0x00080000, /* EMC_DLL_XFORM_DQS3 */ + 0x00080000, /* EMC_DLL_XFORM_DQS4 */ + 0x00080000, /* EMC_DLL_XFORM_DQS5 */ + 0x00080000, /* EMC_DLL_XFORM_DQS6 */ + 0x00080000, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ @@ -3210,10 +3210,10 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = { 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000, /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000, /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000, /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000, /* EMC_DLL_XFORM_DQ3 */ + 0x00080000, /* EMC_DLL_XFORM_DQ0 */ + 0x00080000, /* EMC_DLL_XFORM_DQ1 */ + 0x00080000, /* EMC_DLL_XFORM_DQ2 */ + 0x00080000, /* EMC_DLL_XFORM_DQ3 */ 0x000002a0, /* EMC_XM2CMDPADCTRL */ 0x0800211c, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ @@ -3231,7 +3231,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00010001, /* MC_EMEM_ARB_CFG */ + 0x00010003, /* MC_EMEM_ARB_CFG */ 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -3306,14 +3306,14 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = { 0x00004288, /* EMC_FBIO_CFG5 */ 0x007800a4, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000, /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS7 */ + 0x00080000, /* EMC_DLL_XFORM_DQS0 */ + 0x00080000, /* EMC_DLL_XFORM_DQS1 */ + 0x00080000, /* EMC_DLL_XFORM_DQS2 */ + 0x00080000, /* EMC_DLL_XFORM_DQS3 */ + 0x00080000, /* EMC_DLL_XFORM_DQS4 */ + 0x00080000, /* EMC_DLL_XFORM_DQS5 */ + 0x00080000, /* EMC_DLL_XFORM_DQS6 */ + 0x00080000, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ @@ -3330,10 +3330,10 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = { 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000, /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000, /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000, /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000, /* EMC_DLL_XFORM_DQ3 */ + 0x00080000, /* EMC_DLL_XFORM_DQ0 */ + 0x00080000, /* EMC_DLL_XFORM_DQ1 */ + 0x00080000, /* EMC_DLL_XFORM_DQ2 */ + 0x00080000, /* EMC_DLL_XFORM_DQ3 */ 0x000002a0, /* EMC_XM2CMDPADCTRL */ 0x0800211c, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ @@ -3351,7 +3351,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000001, /* MC_EMEM_ARB_CFG */ + 0x00000003, /* MC_EMEM_ARB_CFG */ 0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -3471,7 +3471,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000003, /* MC_EMEM_ARB_CFG */ + 0x00000006, /* MC_EMEM_ARB_CFG */ 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -3591,8 +3591,8 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000005, /* MC_EMEM_ARB_CFG */ - 0x80000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x0000000b, /* MC_EMEM_ARB_CFG */ + 0xc0000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ 0x00000009, /* MC_EMEM_ARB_TIMING_RC */ @@ -3711,8 +3711,8 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800018c8, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000006, /* MC_EMEM_ARB_CFG */ - 0x80000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x0000000c, /* MC_EMEM_ARB_CFG */ + 0xc0000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ 0x00000009, /* MC_EMEM_ARB_TIMING_RC */ @@ -3831,8 +3831,8 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80002d93, /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000b, /* MC_EMEM_ARB_CFG */ - 0x80000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000016, /* MC_EMEM_ARB_CFG */ + 0xc0000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ 0x00000012, /* MC_EMEM_ARB_TIMING_RC */ @@ -3951,8 +3951,8 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000c, /* MC_EMEM_ARB_CFG */ - 0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000018, /* MC_EMEM_ARB_CFG */ + 0xc0000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ 0x00000013, /* MC_EMEM_ARB_TIMING_RC */ @@ -4194,7 +4194,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800001c2, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00020001, /* MC_EMEM_ARB_CFG */ + 0x00030003, /* MC_EMEM_ARB_CFG */ 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -4314,7 +4314,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000287, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00010001, /* MC_EMEM_ARB_CFG */ + 0x00010003, /* MC_EMEM_ARB_CFG */ 0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -4434,7 +4434,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000001, /* MC_EMEM_ARB_CFG */ + 0x00000003, /* MC_EMEM_ARB_CFG */ 0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -4554,7 +4554,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000003, /* MC_EMEM_ARB_CFG */ + 0x00000006, /* MC_EMEM_ARB_CFG */ 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -4914,8 +4914,8 @@ static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800010d9, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000008, /* MC_EMEM_ARB_CFG */ - 0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x0000000f, /* MC_EMEM_ARB_CFG */ + 0xc0000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ 0x00000010, /* MC_EMEM_ARB_TIMING_RC */ @@ -5037,7 +5037,7 @@ static const struct tegra_emc_table cardhu_emc_tables_edb8132b2ma[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800001c5, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00020001, /* MC_EMEM_ARB_CFG */ + 0x00030003, /* MC_EMEM_ARB_CFG */ 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -5157,7 +5157,7 @@ static const struct tegra_emc_table cardhu_emc_tables_edb8132b2ma[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000287, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00010001, /* MC_EMEM_ARB_CFG */ + 0x00010003, /* MC_EMEM_ARB_CFG */ 0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -5277,7 +5277,7 @@ static const struct tegra_emc_table cardhu_emc_tables_edb8132b2ma[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000001, /* MC_EMEM_ARB_CFG */ + 0x00000003, /* MC_EMEM_ARB_CFG */ 0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -5397,7 +5397,7 @@ static const struct tegra_emc_table cardhu_emc_tables_edb8132b2ma[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000003, /* MC_EMEM_ARB_CFG */ + 0x00000006, /* MC_EMEM_ARB_CFG */ 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -5517,8 +5517,8 @@ static const struct tegra_emc_table cardhu_emc_tables_edb8132b2ma[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800010d9, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000008, /* MC_EMEM_ARB_CFG */ - 0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x0000000f, /* MC_EMEM_ARB_CFG */ + 0xc0000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ 0x00000010, /* MC_EMEM_ARB_TIMING_RC */ @@ -5640,7 +5640,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_pm311[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00010001, /* MC_EMEM_ARB_CFG */ + 0x00010003, /* MC_EMEM_ARB_CFG */ 0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -5760,7 +5760,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_pm311[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000001, /* MC_EMEM_ARB_CFG */ + 0x00000003, /* MC_EMEM_ARB_CFG */ 0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -5880,7 +5880,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_pm311[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000003, /* MC_EMEM_ARB_CFG */ + 0x00000006, /* MC_EMEM_ARB_CFG */ 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -6000,8 +6000,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_pm311[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800014d4, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000005, /* MC_EMEM_ARB_CFG */ - 0x8000003d, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x0000000a, /* MC_EMEM_ARB_CFG */ + 0xc000003d, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ 0x00000008, /* MC_EMEM_ARB_TIMING_RC */ @@ -6120,8 +6120,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_pm311[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a, /* MC_EMEM_ARB_CFG */ - 0x80000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000014, /* MC_EMEM_ARB_CFG */ + 0xc0000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ 0x00000010, /* MC_EMEM_ARB_TIMING_RC */ @@ -6151,6 +6151,609 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_pm311[] = { }, }; +static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2g2r[] = { + { + 0x32, /* Rev 3.2 */ + 25500, /* SDRAM frequency */ + { + 0x00000001, /* EMC_RC */ + 0x00000004, /* EMC_RFC */ + 0x00000000, /* EMC_RAS */ + 0x00000000, /* EMC_RP */ + 0x00000002, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000000, /* EMC_RD_RCD */ + 0x00000000, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000005, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ + 0x00000007, /* EMC_QSAFE */ + 0x0000000c, /* EMC_RDV */ + 0x000000c0, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000030, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x00000005, /* EMC_TXSR */ + 0x00000005, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000001, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x000000c7, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00006288, /* EMC_FBIO_CFG5 */ + 0x007800a4, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000, /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0800211c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f108, /* EMC_XM2COMPPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168, /* EMC_XM2QUSEPADCTRL */ + 0x08000000, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000040, /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80000287, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00030003, /* MC_EMEM_ARB_CFG */ + 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ + 0x74830303, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xd8000000, /* EMC_FBIO_SPARE */ + 0xff00ff00, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000000, /* EMC_CFG.PERIODIC_QRST */ + 0x00001221, /* Mode Register 0 */ + 0x00100003, /* Mode Register 1 */ + 0x00200008, /* Mode Register 2 */ + 0x00000001, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 51000, /* SDRAM frequency */ + { + 0x00000002, /* EMC_RC */ + 0x00000008, /* EMC_RFC */ + 0x00000001, /* EMC_RAS */ + 0x00000000, /* EMC_RP */ + 0x00000002, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000000, /* EMC_RD_RCD */ + 0x00000000, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000005, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ + 0x00000007, /* EMC_QSAFE */ + 0x0000000c, /* EMC_RDV */ + 0x00000181, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x00000009, /* EMC_TXSR */ + 0x00000009, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000002, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x0000018e, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00006288, /* EMC_FBIO_CFG5 */ + 0x007800a4, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000, /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0800211c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f108, /* EMC_XM2COMPPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168, /* EMC_XM2QUSEPADCTRL */ + 0x08000000, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000040, /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00010003, /* MC_EMEM_ARB_CFG */ + 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ + 0x73430303, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xd8000000, /* EMC_FBIO_SPARE */ + 0xff00ff00, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000000, /* EMC_CFG.PERIODIC_QRST */ + 0x00001221, /* Mode Register 0 */ + 0x00100003, /* Mode Register 1 */ + 0x00200008, /* Mode Register 2 */ + 0x00000001, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 102000, /* SDRAM frequency */ + { + 0x00000004, /* EMC_RC */ + 0x00000010, /* EMC_RFC */ + 0x00000003, /* EMC_RAS */ + 0x00000001, /* EMC_RP */ + 0x00000002, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000001, /* EMC_RD_RCD */ + 0x00000001, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000005, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ + 0x00000007, /* EMC_QSAFE */ + 0x0000000c, /* EMC_RDV */ + 0x00000303, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x00000012, /* EMC_TXSR */ + 0x00000012, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000004, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x0000031c, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00006288, /* EMC_FBIO_CFG5 */ + 0x007800a4, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000, /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0800211c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f108, /* EMC_XM2COMPPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168, /* EMC_XM2QUSEPADCTRL */ + 0x08000000, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000040, /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000003, /* MC_EMEM_ARB_CFG */ + 0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0403, /* MC_EMEM_ARB_DA_COVERS */ + 0x72830504, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xd8000000, /* EMC_FBIO_SPARE */ + 0xff00ff00, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000000, /* EMC_CFG.PERIODIC_QRST */ + 0x00001221, /* Mode Register 0 */ + 0x00100003, /* Mode Register 1 */ + 0x00200008, /* Mode Register 2 */ + 0x00000001, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 333500, /* SDRAM frequency */ + { + 0x0000000f, /* EMC_RC */ + 0x00000034, /* EMC_RFC */ + 0x0000000a, /* EMC_RAS */ + 0x00000003, /* EMC_RP */ + 0x00000003, /* EMC_R2W */ + 0x00000008, /* EMC_W2R */ + 0x00000002, /* EMC_R2P */ + 0x00000009, /* EMC_W2P */ + 0x00000003, /* EMC_RD_RCD */ + 0x00000003, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000004, /* EMC_WDV */ + 0x00000006, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ + 0x0000000a, /* EMC_QSAFE */ + 0x0000000c, /* EMC_RDV */ + 0x000009e9, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x0000027a, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001, /* EMC_PDEX2WR */ + 0x00000008, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000e, /* EMC_RW2PDEN */ + 0x00000039, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x0000000a, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000a2a, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00007088, /* EMC_FBIO_CFG5 */ + 0x00260084, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00028000, /* EMC_DLL_XFORM_DQS0 */ + 0x00028000, /* EMC_DLL_XFORM_DQS1 */ + 0x00028000, /* EMC_DLL_XFORM_DQS2 */ + 0x00028000, /* EMC_DLL_XFORM_DQS3 */ + 0x00028000, /* EMC_DLL_XFORM_DQS4 */ + 0x00028000, /* EMC_DLL_XFORM_DQS5 */ + 0x00028000, /* EMC_DLL_XFORM_DQS6 */ + 0x00028000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x0004c000, /* EMC_DLL_XFORM_DQ0 */ + 0x0004c000, /* EMC_DLL_XFORM_DQ1 */ + 0x0004c000, /* EMC_DLL_XFORM_DQ2 */ + 0x0004c000, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0800013d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f508, /* EMC_XM2COMPPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8, /* EMC_XM2QUSEPADCTRL */ + 0x08000021, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x014b000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x800014d4, /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a, /* MC_EMEM_ARB_CFG */ + 0xc000003d, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000008, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202, /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0608, /* MC_EMEM_ARB_DA_COVERS */ + 0x70850f09, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xe8000000, /* EMC_FBIO_SPARE */ + 0xff00ff88, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000000, /* EMC_CFG.PERIODIC_QRST */ + 0x00000321, /* Mode Register 0 */ + 0x00100002, /* Mode Register 1 */ + 0x00200000, /* Mode Register 2 */ + 0x00000000, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 667000, /* SDRAM frequency */ + { + 0x0000001f, /* EMC_RC */ + 0x00000069, /* EMC_RFC */ + 0x00000016, /* EMC_RAS */ + 0x00000008, /* EMC_RP */ + 0x00000005, /* EMC_R2W */ + 0x0000000c, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x00000011, /* EMC_W2P */ + 0x00000008, /* EMC_RD_RCD */ + 0x00000008, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000007, /* EMC_WDV */ + 0x0000000b, /* EMC_QUSE */ + 0x00000009, /* EMC_QRST */ + 0x0000000c, /* EMC_QSAFE */ + 0x00000011, /* EMC_RDV */ + 0x00001412, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000504, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x0000000e, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x0000000c, /* EMC_AR2PDEN */ + 0x00000016, /* EMC_RW2PDEN */ + 0x00000072, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000005, /* EMC_TCKE */ + 0x00000015, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000006, /* EMC_TCLKSTABLE */ + 0x00000007, /* EMC_TCLKSTOP */ + 0x00001453, /* EMC_TREFBW */ + 0x0000000c, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00005088, /* EMC_FBIO_CFG5 */ + 0xf00b0191, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000008, /* EMC_DLL_XFORM_DQS0 */ + 0x00000008, /* EMC_DLL_XFORM_DQS1 */ + 0x00000008, /* EMC_DLL_XFORM_DQS2 */ + 0x00000008, /* EMC_DLL_XFORM_DQS3 */ + 0x00000008, /* EMC_DLL_XFORM_DQS4 */ + 0x00000008, /* EMC_DLL_XFORM_DQS5 */ + 0x00000008, /* EMC_DLL_XFORM_DQS6 */ + 0x00000008, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000008, /* EMC_DLL_XFORM_DQ0 */ + 0x00000008, /* EMC_DLL_XFORM_DQ1 */ + 0x00000008, /* EMC_DLL_XFORM_DQ2 */ + 0x00000008, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0600013d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f508, /* EMC_XM2COMPPADCTRL */ + 0x07077404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000000, /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8, /* EMC_XM2QUSEPADCTRL */ + 0x07000021, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x0116000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000014, /* MC_EMEM_ARB_CFG */ + 0xc0000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000010, /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000a, /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202, /* MC_EMEM_ARB_DA_TURNS */ + 0x00140c10, /* MC_EMEM_ARB_DA_COVERS */ + 0x70ea1f11, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xf8000000, /* EMC_FBIO_SPARE */ + 0xff00ff01, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000001, /* EMC_CFG.PERIODIC_QRST */ + 0x00000b71, /* Mode Register 0 */ + 0x00100002, /* Mode Register 1 */ + 0x00200018, /* Mode Register 2 */ + 0x00000000, /* EMC_CFG.DYN_SELF_REF */ + }, +}; + static const u32 pm269_bit_swap_map[32] = { /* DDR bit # SoC bit # */ [0] = 0x1 << 1, @@ -6231,6 +6834,9 @@ int cardhu_emc_init(void) SKU_MEMORY_CARDHU_2GB_1R_HYNIX) tegra_init_emc(cardhu_emc_tables_h5tc2g_a2_2GB1R, ARRAY_SIZE(cardhu_emc_tables_h5tc2g_a2_2GB1R)); + else if (MEMORY_TYPE(board.sku) == SKU_MEMORY_CARDHU_2GB_2R) + tegra_init_emc(cardhu_emc_tables_h5tc2g_a2_2g2r, + ARRAY_SIZE(cardhu_emc_tables_h5tc2g_a2_2g2r)); break; } -- cgit v1.2.3 From 6e32ab70de901e3a30fc269a2758f958c2c40abb Mon Sep 17 00:00:00 2001 From: Vinod Atyam Date: Fri, 17 Aug 2012 14:33:47 +0530 Subject: ARM: tegra: usb_phy: Fix HSIC resume code 1) During remote wakeup resume, no need to keep 25 msec delay after resume bit is cleared. Updated the code now. 2) PSPD bit in HOSTPC register is read only, but bymistake it is getting set in our code. Corrected the code now. 3) During AP resume, no need to set RUN bit 2 times. Corrected the code to do it once. Bug 1028940 Bug 1024592 Change-Id: I872886f4cef6058d3de9d488321aa5b0925fd62a Signed-off-by: Vinod Atyam Reviewed-on: http://git-master/r/124051 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/tegra3_usb_phy.c | 41 ++++++++++++------------------------ 1 file changed, 14 insertions(+), 27 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index b02e9b646284..1020e5d35f89 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -2060,16 +2060,11 @@ static void uhsic_phy_restore_start(struct tegra_usb_phy *phy) /* check whether we wake up from the remote resume */ if (UHSIC_WALK_PTR_VAL & val) { phy->remote_wakeup = true; - pr_info("%s: uhsic remote wakeup detected\n", __func__); } else { - if (!((UHSIC_STROBE_VAL_P0 | UHSIC_DATA_VAL_P0) & val)) { - uhsic_phy_disable_pmc_bus_ctrl(phy); - } else { - DBG("%s(%d): setting pretend connect\n", __func__, __LINE__); - val = readl(base + UHSIC_CMD_CFG0); - val |= UHSIC_PRETEND_CONNECT_DETECT; - writel(val, base + UHSIC_CMD_CFG0); - } + DBG("%s(%d): setting pretend connect\n", __func__, __LINE__); + val = readl(base + UHSIC_CMD_CFG0); + val |= UHSIC_PRETEND_CONNECT_DETECT; + writel(val, base + UHSIC_CMD_CFG0); } } @@ -2096,8 +2091,6 @@ static void uhsic_phy_restore_end(struct tegra_usb_phy *phy) wait_time_us--; } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP)); - /* wait for 25 ms to port resume complete */ - msleep(25); /* disable PMC master control */ uhsic_phy_disable_pmc_bus_ctrl(phy); @@ -2110,19 +2103,19 @@ static void uhsic_phy_restore_end(struct tegra_usb_phy *phy) pr_warn("%s: timeout waiting for SOF\n", __func__); } uhsic_phy_post_resume(phy); + + /* Set RUN bit */ + val = readl(base + USB_USBCMD); + val |= USB_USBCMD_RS; + writel(val, base + USB_USBCMD); + if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS, + USB_USBCMD_RS, 2000)) { + pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__); + return; + } } else { uhsic_phy_disable_pmc_bus_ctrl(phy); } - - /* Set RUN bit */ - val = readl(base + USB_USBCMD); - val |= USB_USBCMD_RS; - writel(val, base + USB_USBCMD); - if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS, - USB_USBCMD_RS, 2000)) { - pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__); - return; - } } static int hsic_rail_enable(struct tegra_usb_phy *phy) @@ -2292,8 +2285,6 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) val = readl(base + HOSTPC1_DEVLC); val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK); val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC); - val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK); - val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED); val &= ~HOSTPC1_DEVLC_STS; writel(val, base + HOSTPC1_DEVLC); @@ -2387,8 +2378,6 @@ int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy) val = readl(base + HOSTPC1_DEVLC); val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK)); val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC); - val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK)); - val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED); writel(val, base + HOSTPC1_DEVLC); val = readl(base + UHSIC_MISC_CFG0); @@ -2428,8 +2417,6 @@ static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy) val = readl(base + HOSTPC1_DEVLC); val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK); val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC); - val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK); - val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED); val &= ~HOSTPC1_DEVLC_STS; writel(val, base + HOSTPC1_DEVLC); /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */ -- cgit v1.2.3 From be0628b0eec72d488503b155d45429c660f37ec9 Mon Sep 17 00:00:00 2001 From: Antti P Miettinen Date: Tue, 26 Jun 2012 16:54:37 +0300 Subject: ARM: tegra: Remove timer workaround Reprogramming running timers may cause timer interrupt state to get out of sync and result in lost timer interrupts. Bug 950482 Change-Id: I83c9d735f9b041e8a57d73ba466f5f9c89ca1b89 Signed-off-by: Antti P Miettinen Reviewed-on: http://git-master/r/111242 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/cpuidle.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index 9d36d0fac5d8..25f63f6c4b2a 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c @@ -137,9 +137,6 @@ static int tegra_idle_enter_lp2(struct cpuidle_device *dev, local_irq_enable(); - /* cpu clockevents may have been reset by powerdown */ - hrtimer_peek_ahead_timers(); - smp_rmb(); /* Update LP2 latency provided no fall back to LP3 */ -- cgit v1.2.3 From 7275366c68e427cb808d0a3aca27fcfe66bf8f3f Mon Sep 17 00:00:00 2001 From: Ray Poudrier Date: Mon, 2 Jul 2012 16:41:32 -0700 Subject: ARM: tegra: kai: update memory timings Extend tick length to 60ns Bug 1001229 Change-Id: I8a96dd08b6d11a196c9b82bec403ab2e4676e2f4 Signed-off-by: Ray Poudrier Reviewed-on: http://git-master/r/113081 (cherry picked from commit 487622aa43568d3f6f9a9f5fc98176e5ffdd6246) Reviewed-on: http://git-master/r/116208 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- arch/arm/mach-tegra/board-kai-memory.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-kai-memory.c b/arch/arm/mach-tegra/board-kai-memory.c index 1f812ece741b..cf5daf6492eb 100644 --- a/arch/arm/mach-tegra/board-kai-memory.c +++ b/arch/arm/mach-tegra/board-kai-memory.c @@ -117,7 +117,7 @@ static const struct tegra_emc_table kai_emc_tables_h5tc4g[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000287, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00020001, /* MC_EMEM_ARB_CFG */ + 0x00030003, /* MC_EMEM_ARB_CFG */ 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -237,7 +237,7 @@ static const struct tegra_emc_table kai_emc_tables_h5tc4g[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00010001, /* MC_EMEM_ARB_CFG */ + 0x00010003, /* MC_EMEM_ARB_CFG */ 0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -357,7 +357,7 @@ static const struct tegra_emc_table kai_emc_tables_h5tc4g[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000001, /* MC_EMEM_ARB_CFG */ + 0x00000003, /* MC_EMEM_ARB_CFG */ 0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -477,7 +477,7 @@ static const struct tegra_emc_table kai_emc_tables_h5tc4g[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000003, /* MC_EMEM_ARB_CFG */ + 0x00000006, /* MC_EMEM_ARB_CFG */ 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -597,8 +597,8 @@ static const struct tegra_emc_table kai_emc_tables_h5tc4g[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800014d4, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000005, /* MC_EMEM_ARB_CFG */ - 0x8000003d, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x0000000a, /* MC_EMEM_ARB_CFG */ + 0xc000003d, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ 0x00000008, /* MC_EMEM_ARB_TIMING_RC */ @@ -717,8 +717,8 @@ static const struct tegra_emc_table kai_emc_tables_h5tc4g[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a, /* MC_EMEM_ARB_CFG */ - 0x80000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000014, /* MC_EMEM_ARB_CFG */ + 0xc0000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ 0x00000010, /* MC_EMEM_ARB_TIMING_RC */ -- cgit v1.2.3 From 71824364492283119d1a18dd179718f85ec810c2 Mon Sep 17 00:00:00 2001 From: krishna kishore Date: Thu, 2 Aug 2012 18:10:08 +0530 Subject: arch: arm: pcie: init TXBA registers Setting default values in TXBA registers to avoid unfair arbitration between downstream reads and completions to upstream reads Bug 1027024 Change-Id: I87763817b7974127f93fa18270b5245a54fc6676 Signed-off-by: krishna kishore Reviewed-on: http://git-master/r/120359 Tested-by: Jay Agarwal Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani --- arch/arm/mach-tegra/pcie.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index c6f0e4bf2bb8..eef215b00018 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -155,6 +155,12 @@ #define RP_VEND_XP 0x00000F00 #define RP_VEND_XP_DL_UP (1 << 30) +#define RP_TXBA1 0x00000E1C +#define RP_TXBA1_CM_OVER_PW_BURST_MASK (0xF << 4) +#define RP_TXBA1_CM_OVER_PW_BURST_INIT_VAL (0x4 << 4) +#define RP_TXBA1_PW_OVER_CM_BURST_MASK (0xF) +#define RP_TXBA1_PW_OVER_CM_BURST_INIT_VAL (0x4) + #define RP_LINK_CONTROL_STATUS 0x00000090 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 @@ -1223,6 +1229,7 @@ static void tegra_pcie_enable_aspm_l1_support(int index) static void tegra_pcie_add_port(int index, u32 offset, u32 reset_reg) { struct tegra_pcie_port *pp; + unsigned int data; pp = tegra_pcie.port + tegra_pcie.num_ports; @@ -1237,6 +1244,18 @@ static void tegra_pcie_add_port(int index, u32 offset, u32 reset_reg) } tegra_pcie_enable_clock_clamp(index); tegra_pcie_enable_aspm_l1_support(index); + + /* + * Initialize TXBA1 register to fix the unfair arbitration + * between downstream reads and completions to upstream reads + */ + data = rp_readl(RP_TXBA1, index); + data &= ~(RP_TXBA1_PW_OVER_CM_BURST_MASK); + data |= RP_TXBA1_PW_OVER_CM_BURST_INIT_VAL; + data &= ~(RP_TXBA1_CM_OVER_PW_BURST_MASK); + data |= RP_TXBA1_CM_OVER_PW_BURST_INIT_VAL; + rp_writel(data, RP_TXBA1, index); + tegra_pcie.num_ports++; pp->index = index; memset(pp->res, 0, sizeof(pp->res)); -- cgit v1.2.3 From e0ed318ccce39543fa821d3cef901111bae556a0 Mon Sep 17 00:00:00 2001 From: Simone Willett Date: Wed, 22 Aug 2012 13:58:14 -0700 Subject: Revert "ARM: tegra: enterprise: update memory timings" This reverts commit 64d7608ed4a0fe0964250ad0423c499841292bf6 Change-Id: I0405128605ed7a858aecb8fb9aaaf80e0e44c4b8 Reviewed-on: http://git-master/r/125322 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-enterprise-memory.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-memory.c b/arch/arm/mach-tegra/board-enterprise-memory.c index 1fc0d3c3fddd..36a8264c2a21 100644 --- a/arch/arm/mach-tegra/board-enterprise-memory.c +++ b/arch/arm/mach-tegra/board-enterprise-memory.c @@ -116,7 +116,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000164, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00050002, /* MC_EMEM_ARB_CFG */ + 0x00050001, /* MC_EMEM_ARB_CFG */ 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -236,7 +236,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800001c2, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00030003, /* MC_EMEM_ARB_CFG */ + 0x00020001, /* MC_EMEM_ARB_CFG */ 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -356,7 +356,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000287, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00010003, /* MC_EMEM_ARB_CFG */ + 0x00010001, /* MC_EMEM_ARB_CFG */ 0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -476,7 +476,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000003, /* MC_EMEM_ARB_CFG */ + 0x00000001, /* MC_EMEM_ARB_CFG */ 0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -596,7 +596,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000006, /* MC_EMEM_ARB_CFG */ + 0x00000003, /* MC_EMEM_ARB_CFG */ 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -716,7 +716,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000ce6, /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000c, /* MC_EMEM_ARB_CFG */ + 0x00000006, /* MC_EMEM_ARB_CFG */ 0xc0000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ -- cgit v1.2.3 From a39320fc45e9657c0d90c97a73fb89d5395cefd3 Mon Sep 17 00:00:00 2001 From: Tuomas Tynkkynen Date: Fri, 17 Aug 2012 11:37:02 +0300 Subject: ARM: tegra: iovmm: Fix spinlock bug if alloc fails iovmm_split_free_block leaves the domain's spinlock unlocked if a memory allocation failed. Unfortunately, all the callers of that function assume that it takes the spinlock. This will then lead to double unlocking of the spinlock. Bug 1035105 Change-Id: Ib4379cad76f053586d6a77b8d0dc9f41af01931a Signed-off-by: Tuomas Tynkkynen Reviewed-on: http://git-master/r/124299 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy --- arch/arm/mach-tegra/iovmm.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/iovmm.c b/arch/arm/mach-tegra/iovmm.c index 86a92aec2d28..488c6a6fc828 100644 --- a/arch/arm/mach-tegra/iovmm.c +++ b/arch/arm/mach-tegra/iovmm.c @@ -255,11 +255,13 @@ static struct tegra_iovmm_block *iovmm_split_free_block( struct tegra_iovmm_block *rem; struct tegra_iovmm_block *b; + spin_unlock(&domain->block_lock); rem = kmem_cache_zalloc(iovmm_cache, GFP_KERNEL); + spin_lock(&domain->block_lock); + if (!rem) return NULL; - spin_lock(&domain->block_lock); p = &domain->free_blocks.rb_node; rem->start = block->start + size; @@ -344,7 +346,6 @@ static struct tegra_iovmm_block *iovmm_alloc_block( simalign = SIMALIGN(best, align); if (DO_SPLIT(simalign)) { iovmm_block_splitting = 1; - spin_unlock(&domain->block_lock); /* Split off misalignment */ b = best; @@ -365,7 +366,6 @@ static struct tegra_iovmm_block *iovmm_alloc_block( if (DO_SPLIT((best->start + best->length) - iovmm_end(best))) { iovmm_block_splitting = 1; - spin_unlock(&domain->block_lock); /* Split off excess */ (void)iovmm_split_free_block(domain, best, size + simalign); @@ -415,7 +415,6 @@ static struct tegra_iovmm_block *iovmm_allocate_vm( /* split the mem before iovm_start. */ if (DO_SPLIT(iovm_start - best->start)) { iovmm_block_splitting = 1; - spin_unlock(&domain->block_lock); best = iovmm_split_free_block(domain, best, (iovm_start - best->start)); } @@ -435,7 +434,6 @@ static struct tegra_iovmm_block *iovmm_allocate_vm( /* split the mem after iovm_start+size. */ if (DO_SPLIT(best->start + best->length - iovmm_end(best))) { iovmm_block_splitting = 1; - spin_unlock(&domain->block_lock); (void)iovmm_split_free_block(domain, best, (iovmm_start(best) - best->start + size)); } -- cgit v1.2.3 From 2e189ac325c9347cbb2411b00154a5dab254cec3 Mon Sep 17 00:00:00 2001 From: Antti P Miettinen Date: Thu, 31 May 2012 12:44:01 +0300 Subject: ARM: Tegra: Omit L2 flush at disable In Tegra kernel L2 is disabled only upon CPU cluster power down, e.g. LP2 entry. Flushing L2 upon every LP2 entry is costly. Since we are always in single core mode upon cluster power down we can safely omit L2 flush upon L2 disable. Change-Id: I27542b11e6133f3192a02440e5b14ea408b860fd Signed-off-by: Antti P Miettinen Reviewed-on: http://git-master/r/105625 Reviewed-by: Krishna Reddy Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid Reviewed-by: Diwakar Tundlam --- arch/arm/mach-tegra/common.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 85eb11f64118..c5401e65426f 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -290,6 +290,20 @@ static inline void tegra_init_cache_tz(bool init) #endif /* CONFIG_TRUSTED_FOUNDATIONS */ #ifdef CONFIG_CACHE_L2X0 +/* + * We define our own outer_disable() to avoid L2 flush upon LP2 entry. + * Since the Tegra kernel will always be in single core mode when + * L2 is being disabled, we can omit the locking. Since we are not + * accessing the spinlock we also avoid the problem of the spinlock + * storage getting out of sync. + */ +static inline void tegra_l2x0_disable(void) +{ + void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; + writel_relaxed(0, p + L2X0_CTRL); + dsb(); +} + void tegra_init_cache(bool init) { #ifdef CONFIG_TRUSTED_FOUNDATIONS @@ -336,6 +350,8 @@ void tegra_init_cache(bool init) aux_ctrl |= 0x7C000001; if (init) { l2x0_init(p, aux_ctrl, 0x8200c3fe); + /* use our outer_disable() routine to avoid flush */ + outer_cache.disable = tegra_l2x0_disable; } else { u32 tmp; -- cgit v1.2.3 From 5510aec770fe9a040b44d72ac9d4e4e0cf44e816 Mon Sep 17 00:00:00 2001 From: Ray Poudrier Date: Tue, 21 Aug 2012 15:09:09 -0700 Subject: ARM: tegra: la: add function to scale LA Add functionality to enable changing of latency allowance settings. This is used for memory tables that may have different tick lengths. Bug 955082 Change-Id: I3055a062846cfdeb992931e691cf687ffb05725c Signed-off-by: Ray Poudrier Reviewed-on: http://git-master/r/124979 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid Reviewed-by: Krishna Reddy --- .../mach-tegra/include/mach/latency_allowance.h | 9 ++++++- arch/arm/mach-tegra/latency_allowance.c | 31 ++++++++++++++++++++++ arch/arm/mach-tegra/tegra3_la_priv.h | 2 +- 3 files changed, 40 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/include/mach/latency_allowance.h b/arch/arm/mach-tegra/include/mach/latency_allowance.h index 5ebc6f03b810..9861834ad9de 100644 --- a/arch/arm/mach-tegra/include/mach/latency_allowance.h +++ b/arch/arm/mach-tegra/include/mach/latency_allowance.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/include/mach/latency_allowance.h * - * Copyright (C) 2011-2012 NVIDIA Corporation. + * Copyright (C) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -107,6 +107,12 @@ static inline void tegra_disable_latency_scaling(enum tegra_la_id id) { return; } + +static inline void tegra_latency_allowance_update_tick_length( + unsigned int new_ns_per_tick) +{ + return; +} #else int tegra_set_latency_allowance(enum tegra_la_id id, unsigned int bandwidth_in_mbps); @@ -117,6 +123,7 @@ int tegra_enable_latency_scaling(enum tegra_la_id id, unsigned int threshold_high); void tegra_disable_latency_scaling(enum tegra_la_id id); +void tegra_latency_allowance_update_tick_length(unsigned int new_ns_per_tick); #endif #endif /* _MACH_TEGRA_LATENCY_ALLOWANCE_H_ */ diff --git a/arch/arm/mach-tegra/latency_allowance.c b/arch/arm/mach-tegra/latency_allowance.c index d481882ce713..86ab179e4646 100644 --- a/arch/arm/mach-tegra/latency_allowance.c +++ b/arch/arm/mach-tegra/latency_allowance.c @@ -257,6 +257,37 @@ void tegra_disable_latency_scaling(enum tegra_la_id id) spin_unlock(&safety_lock); } +void tegra_latency_allowance_update_tick_length(unsigned int new_ns_per_tick) +{ + int i = 0; + int la; + unsigned long reg_read; + unsigned long reg_write; + unsigned long scale_factor = new_ns_per_tick / ns_per_tick; + + if (scale_factor > 1) { + spin_lock(&safety_lock); + ns_per_tick = new_ns_per_tick; + for (i = 0; i < ARRAY_SIZE(la_info_array) - 1; i++) { + reg_read = readl(la_info_array[i].reg_addr); + la = ((reg_read & la_info_array[i].mask) >> + la_info_array[i].shift) / scale_factor; + + reg_write = (reg_read & ~la_info_array[i].mask) | + (la << la_info_array[i].shift); + writel(reg_write, la_info_array[i].reg_addr); + scaling_info[i].la_set = la; + } + spin_unlock(&safety_lock); + + /* Re-scale G2PR, G2SR, G2DR, G2DW with updated ns_per_tick */ + tegra_set_latency_allowance(TEGRA_LA_G2PR, 20); + tegra_set_latency_allowance(TEGRA_LA_G2SR, 20); + tegra_set_latency_allowance(TEGRA_LA_G2DR, 20); + tegra_set_latency_allowance(TEGRA_LA_G2DW, 20); + } +} + static int la_regs_show(struct seq_file *s, void *unused) { unsigned i; diff --git a/arch/arm/mach-tegra/tegra3_la_priv.h b/arch/arm/mach-tegra/tegra3_la_priv.h index 7f3fa7c46931..2a39ea41b6f5 100644 --- a/arch/arm/mach-tegra/tegra3_la_priv.h +++ b/arch/arm/mach-tegra/tegra3_la_priv.h @@ -218,7 +218,7 @@ struct la_scaling_reg_info vi_info[] = { } }; -static const int ns_per_tick = 30; +static int ns_per_tick = 30; /* Tegra3 MC atom size in bytes */ static const int normal_atom_size = 16; #endif -- cgit v1.2.3 From 2b7b55a2a52fc714d0074598bb81bae277e6b1e9 Mon Sep 17 00:00:00 2001 From: Ray Poudrier Date: Tue, 21 Aug 2012 12:23:51 -0700 Subject: ARM:tegra:emc: scale latency allowance by tick len Calculate the tick length of the EMC DFS table and scale the latency allowance settings. Bug 955082 Change-Id: Id7b1504c6854009ba7677c7ddebe0a8f62cbfb7e Signed-off-by: Ray Poudrier Reviewed-on: http://git-master/r/124980 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid Reviewed-by: Krishna Reddy --- arch/arm/mach-tegra/common-t3.c | 15 ++++++++++++-- arch/arm/mach-tegra/tegra3_emc.c | 45 +++++++++++++++++++++++++++++++++++++++- arch/arm/mach-tegra/tegra3_emc.h | 43 +++++++++++++++++++++++++++++++++++++- 3 files changed, 99 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/common-t3.c b/arch/arm/mach-tegra/common-t3.c index 2da656f97c38..76188723b46f 100644 --- a/arch/arm/mach-tegra/common-t3.c +++ b/arch/arm/mach-tegra/common-t3.c @@ -3,7 +3,7 @@ * * Tegra 3 SoC-specific initialization (memory controller, etc.) * - * Copyright (c) 2010-2012, NVIDIA Corporation. + * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -44,6 +44,8 @@ ((MC_EMEM_ARB_TIMING_W2R - MC_EMEM_ARB_CFG) / 4 + 1) #define MC_TIMING_REG_NUM2 \ ((MC_EMEM_ARB_MISC1 - MC_EMEM_ARB_DA_TURNS) / 4 + 1) +#define MC_TIMING_REG_NUM3 \ + ((MC_LATENCY_ALLOWANCE_VI_2 - MC_LATENCY_ALLOWANCE_AFI) / 4 + 1) struct mc_client { const char *name; @@ -59,7 +61,8 @@ static void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE); #ifdef CONFIG_PM_SLEEP -static u32 mc_boot_timing[MC_TIMING_REG_NUM1 + MC_TIMING_REG_NUM2 + 4]; +static u32 mc_boot_timing[MC_TIMING_REG_NUM1 + MC_TIMING_REG_NUM2 + + MC_TIMING_REG_NUM3 + 4]; static void tegra_mc_timing_save(void) { @@ -76,6 +79,10 @@ static void tegra_mc_timing_save(void) *ctx++ = readl((u32)mc + MC_EMEM_ARB_OVERRIDE); *ctx++ = readl((u32)mc + MC_RESERVED_RSV); + for (off = MC_LATENCY_ALLOWANCE_AFI; off <= MC_LATENCY_ALLOWANCE_VI_2; + off += 4) + *ctx++ = readl((u32)mc + off); + *ctx++ = readl((u32)mc + MC_INT_MASK); } @@ -94,6 +101,10 @@ void tegra_mc_timing_restore(void) __raw_writel(*ctx++, (u32)mc + MC_EMEM_ARB_OVERRIDE); __raw_writel(*ctx++, (u32)mc + MC_RESERVED_RSV); + for (off = MC_LATENCY_ALLOWANCE_AFI; off <= MC_LATENCY_ALLOWANCE_VI_2; + off += 4) + __raw_writel(*ctx++, (u32)mc + off); + writel(*ctx++, (u32)mc + MC_INT_MASK); off = readl((u32)mc + MC_INT_MASK); diff --git a/arch/arm/mach-tegra/tegra3_emc.c b/arch/arm/mach-tegra/tegra3_emc.c index 57a673b4df8d..4c06bf91ab1f 100644 --- a/arch/arm/mach-tegra/tegra3_emc.c +++ b/arch/arm/mach-tegra/tegra3_emc.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/tegra3_emc.c * - * Copyright (C) 2012 NVIDIA Corporation + * Copyright (C) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -33,6 +33,7 @@ #include #include +#include #include "clock.h" #include "dvfs.h" @@ -1018,6 +1019,31 @@ static struct notifier_block tegra_emc_resume_nb = { .priority = -1, }; +static int tegra_emc_get_table_ns_per_tick(unsigned int emc_rate, + unsigned int table_tick_len) +{ + unsigned int ns_per_tick = 0; + unsigned int mc_period_10ns = 0; + unsigned int reg; + + reg = mc_readl(MC_EMEM_ARB_MISC0) & MC_EMEM_ARB_MISC0_EMC_SAME_FREQ; + + mc_period_10ns = ((reg ? (NSEC_PER_MSEC * 10) : (20 * NSEC_PER_MSEC)) / + (emc_rate)); + ns_per_tick = ((table_tick_len & MC_EMEM_ARB_CFG_CYCLE_MASK) + * mc_period_10ns) / (10 * + (1 + ((table_tick_len & MC_EMEM_ARB_CFG_EXTRA_TICK_MASK) + >> MC_EMEM_ARB_CFG_EXTRA_TICK_SHIFT))); + + /* round new_ns_per_tick to 30/60 */ + if (ns_per_tick < 45) + ns_per_tick = 30; + else + ns_per_tick = 60; + + return ns_per_tick; +} + void tegra_init_emc(const struct tegra_emc_table *table, int table_size) { int i, mv; @@ -1025,6 +1051,8 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size) bool max_entry = false; unsigned long boot_rate, max_rate; struct clk *cbus = tegra_get_clock_by_name("cbus"); + unsigned int ns_per_tick = 0; + unsigned int cur_ns_per_tick = 0; emc_stats.clkchange_count = 0; spin_lock_init(&emc_stats.spinlock); @@ -1085,6 +1113,19 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size) if (table_rate == max_rate) max_entry = true; + + cur_ns_per_tick = tegra_emc_get_table_ns_per_tick(table_rate, + table[i].burst_regs[MC_EMEM_ARB_CFG_INDEX]); + + if (ns_per_tick == 0) { + ns_per_tick = cur_ns_per_tick; + } else if (ns_per_tick != cur_ns_per_tick) { + pr_err("tegra: invalid EMC DFS table: " + "mismatched DFS tick lengths " + "within table!\n"); + ns_per_tick = 0; + return; + } } /* Validate EMC rate and voltage limits */ @@ -1094,6 +1135,8 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size) return; } + tegra_latency_allowance_update_tick_length(ns_per_tick); + tegra_emc_table = table; adjust_emc_dvfs_table(tegra_emc_table, tegra_emc_table_size); diff --git a/arch/arm/mach-tegra/tegra3_emc.h b/arch/arm/mach-tegra/tegra3_emc.h index 29b4556d749d..43ef636c613f 100644 --- a/arch/arm/mach-tegra/tegra3_emc.h +++ b/arch/arm/mach-tegra/tegra3_emc.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/tegra3_emc.h * - * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -267,6 +267,10 @@ enum { #define MC_EMEM_ADR_CFG 0x54 #define MC_EMEM_ARB_CFG 0x90 +#define MC_EMEM_ARB_CFG_CYCLE_MASK 0x1ff +#define MC_EMEM_ARB_CFG_EXTRA_TICK_SHIFT 16 +#define MC_EMEM_ARB_CFG_EXTRA_TICK_MASK \ + (0x1f << MC_EMEM_ARB_CFG_EXTRA_TICK_SHIFT) #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 #define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_SHIFT 0 #define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK \ @@ -295,6 +299,43 @@ enum { #define MC_EMEM_ARB_OVERRIDE 0xe8 #define MC_EMEM_ARB_OVERRIDE_EACK_MASK (0x3 << 0) #define MC_TIMING_CONTROL 0xfc +#define MC_LATENCY_ALLOWANCE_AFI 0x2e0 +#define MC_LATENCY_ALLOWANCE_AVPC 0x2e4 +#define MC_LATENCY_ALLOWANCE_DC_0 0x2e8 +#define MC_LATENCY_ALLOWANCE_DC_1 0x2ec +#define MC_LATENCY_ALLOWANCE_DC_2 0x2f0 +#define MC_LATENCY_ALLOWANCE_DCB_0 0x2f4 +#define MC_LATENCY_ALLOWANCE_DCB_1 0x2f8 +#define MC_LATENCY_ALLOWANCE_DCB_2 0x2fc +#define MC_LATENCY_ALLOWANCE_EPP_0 0x300 +#define MC_LATENCY_ALLOWANCE_EPP_1 0x304 +#define MC_LATENCY_ALLOWANCE_G2_0 0x308 +#define MC_LATENCY_ALLOWANCE_G2_1 0x30c +#define MC_LATENCY_ALLOWANCE_HC_0 0x310 +#define MC_LATENCY_ALLOWANCE_HC_1 0x314 +#define MC_LATENCY_ALLOWANCE_HDA 0x318 +#define MC_LATENCY_ALLOWANCE_ISP 0x31c +#define MC_LATENCY_ALLOWANCE_MPCORE 0x320 +#define MC_LATENCY_ALLOWANCE_MPCORELP 0x324 +#define MC_LATENCY_ALLOWANCE_MPE_0 0x328 +#define MC_LATENCY_ALLOWANCE_MPE_1 0x32c +#define MC_LATENCY_ALLOWANCE_MPE_2 0x330 +#define MC_LATENCY_ALLOWANCE_NV_0 0x334 +#define MC_LATENCY_ALLOWANCE_NV_1 0x338 +#define MC_LATENCY_ALLOWANCE_NV2_0 0x33c +#define MC_LATENCY_ALLOWANCE_NV2_1 0x340 +#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344 +#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348 +#define MC_LATENCY_ALLOWANCE_PTC 0x34c +#define MC_LATENCY_ALLOWANCE_SATA 0x350 +#define MC_LATENCY_ALLOWANCE_VDE_0 0x354 +#define MC_LATENCY_ALLOWANCE_VDE_1 0x358 +#define MC_LATENCY_ALLOWANCE_VDE_2 0x35c +#define MC_LATENCY_ALLOWANCE_VDE_3 0x360 +#define MC_LATENCY_ALLOWANCE_VI_0 0x364 +#define MC_LATENCY_ALLOWANCE_VI_1 0x368 +#define MC_LATENCY_ALLOWANCE_VI_2 0x36c + #define MC_RESERVED_RSV 0x3fc #endif -- cgit v1.2.3 From d07ff495e37de161764204121324dab6c1e5ff2a Mon Sep 17 00:00:00 2001 From: Krishna Reddy Date: Tue, 21 Aug 2012 18:50:09 -0700 Subject: Revert "arm: tegra: scu: Enable IC and SCU standby" This reverts commit b25193d5c3e2c59169c127d23b59123136cfefa7. This CL is reverted as it causes write perf regression with lmbench(bw_mem) benchmark. Bug 1026077 Change-Id: I9858c88a6e846d2c3629f14c7cc62a7feb4f4528 Signed-off-by: Krishna Reddy Reviewed-on: http://git-master/r/125096 Reviewed-by: Aleksandr Frid --- arch/arm/mach-tegra/headsmp.S | 4 +--- arch/arm/mach-tegra/platsmp.c | 5 +---- 2 files changed, 2 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 63852b99b3d3..59345cfb299d 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -83,9 +83,7 @@ ENTRY(tegra_resume) ldr r1, [r0] orr r1, r1, #1 #if defined(CONFIG_HAVE_ARM_SCU) - orr r1, r1, #(1 << 3) @ Enable SCU speculative line fill. - orr r1, r1, #(1 << 5) @ Enable IC standby. - orr r1, r1, #(1 << 6) @ Enable SCU standby. + orr r1, r1, #(1 << 3) @ Enabled SCU speculative line fill. #endif str r1, [r0] diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index d36b18934acd..b2261b025310 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -299,10 +299,7 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) #if defined(CONFIG_HAVE_ARM_SCU) { - u32 scu_ctrl = __raw_readl(scu_base) | - 1 << 3 | /* Enable speculative line fill*/ - 1 << 5 | /* Enable IC standby */ - 1 << 6; /* Enable SCU standby */ + u32 scu_ctrl = __raw_readl(scu_base) | 1 << 3; if (!(scu_ctrl & 1)) __raw_writel(scu_ctrl, scu_base); } -- cgit v1.2.3 From 59983fe4193541acfd8c7df7bf98139e2ec44d11 Mon Sep 17 00:00:00 2001 From: Krishna Reddy Date: Tue, 21 Aug 2012 18:51:22 -0700 Subject: Revert "arm: tegra: Enable speculative line fill in SCU." This reverts commit 06c880a6086183173c361b4a9d4f8047c6a39769. This CL is reverted as it causes write perf regression with lmbench(bw_mem) benchmark. Bug 1026077 Change-Id: I7ff9ffbfe74e2083aa43cab75b694b1c61987bc3 Signed-off-by: Krishna Reddy Reviewed-on: http://git-master/r/125097 Reviewed-by: Aleksandr Frid --- arch/arm/mach-tegra/headsmp.S | 3 --- arch/arm/mach-tegra/platsmp.c | 8 -------- 2 files changed, 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 59345cfb299d..2fa96381f68f 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -82,9 +82,6 @@ ENTRY(tegra_resume) mov32 r0, TEGRA_ARM_PERIF_BASE ldr r1, [r0] orr r1, r1, #1 -#if defined(CONFIG_HAVE_ARM_SCU) - orr r1, r1, #(1 << 3) @ Enabled SCU speculative line fill. -#endif str r1, [r0] #ifdef CONFIG_TRUSTED_FOUNDATIONS diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index b2261b025310..dbd302414c67 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -296,13 +296,5 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) smp_init_cpus() which also means that it did not initialize the reset handler. Do it now before the secondary CPUs are started. */ tegra_cpu_reset_handler_init(); - -#if defined(CONFIG_HAVE_ARM_SCU) - { - u32 scu_ctrl = __raw_readl(scu_base) | 1 << 3; - if (!(scu_ctrl & 1)) - __raw_writel(scu_ctrl, scu_base); - } -#endif scu_enable(scu_base); } -- cgit v1.2.3 From b536b496165f0de2e854e6297f54371e27233dd2 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 22 Aug 2012 11:14:29 -0700 Subject: ARM: tegra: TAI: Add E1239 support Bug 1002637 Change-Id: I1271f95e8c174422bcb93eed3cc2bd7df8012479 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/123537 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Peterson --- arch/arm/mach-tegra/board-enterprise-panel.c | 112 ++++++- arch/arm/mach-tegra/board-enterprise-pinmux.c | 406 ++++++++++++++++++++++++- arch/arm/mach-tegra/board-enterprise-power.c | 35 ++- arch/arm/mach-tegra/board-enterprise-sensors.c | 164 +++++++--- arch/arm/mach-tegra/board-enterprise.c | 46 ++- arch/arm/mach-tegra/board-enterprise.h | 3 + 6 files changed, 676 insertions(+), 90 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-panel.c b/arch/arm/mach-tegra/board-enterprise-panel.c index 366bf921393d..c27201171e4b 100644 --- a/arch/arm/mach-tegra/board-enterprise-panel.c +++ b/arch/arm/mach-tegra/board-enterprise-panel.c @@ -63,6 +63,8 @@ #define enterprise_lcd_te TEGRA_GPIO_PJ1 +#define enterprise_bl_pwm TEGRA_GPIO_PH3 + #ifdef CONFIG_TEGRA_DC static struct regulator *enterprise_dsi_reg; static bool dsi_regulator_status; @@ -167,6 +169,16 @@ static int enterprise_backlight_notify(struct device *unused, int brightness) static int enterprise_disp1_check_fb(struct device *dev, struct fb_info *info); +static struct platform_pwm_backlight_data external_pwm_disp1_backlight_data = { + .pwm_id = 3, + .max_brightness = 255, + .dft_brightness = 224, + .pwm_period_ns = 1000000, + .notify = enterprise_backlight_notify, + /* Only toggle backlight on fb blank notifications for disp1 */ + .check_fb = enterprise_disp1_check_fb, +}; + #if IS_EXTERNAL_PWM static struct platform_pwm_backlight_data enterprise_disp1_backlight_data = { .pwm_id = 3, @@ -212,10 +224,21 @@ static struct platform_device enterprise_disp1_backlight_device = { }, }; +static struct platform_device external_pwm_disp1_backlight_device = { + .name = "pwm-backlight", + .id = -1, + .dev = { + .platform_data = &external_pwm_disp1_backlight_data, + }, +}; #ifdef CONFIG_TEGRA_DC static int enterprise_hdmi_vddio_enable(void) { int ret; + struct board_info board_info; + + tegra_get_board_info(&board_info); + if (!enterprise_hdmi_vddio) { enterprise_hdmi_vddio = regulator_get(NULL, "hdmi_5v0"); if (IS_ERR_OR_NULL(enterprise_hdmi_vddio)) { @@ -232,16 +255,40 @@ static int enterprise_hdmi_vddio_enable(void) enterprise_hdmi_vddio = NULL; return ret; } + if (board_info.board_id == BOARD_E1239) { + ret = gpio_request(TEGRA_GPIO_PM4, "en_hdmi_buffers"); + if (ret < 0) { + pr_err("%s: gpio_request failed %d\n", __func__, ret); + return ret; + } + + ret = gpio_direction_output(TEGRA_GPIO_PM4, 1); + if (ret < 0) { + pr_err("%s: gpio_direction_ouput failed %d\n", + __func__, ret); + gpio_free(TEGRA_GPIO_PM4); + return ret; + } + } + return ret; } static int enterprise_hdmi_vddio_disable(void) { + struct board_info board_info; + + tegra_get_board_info(&board_info); + if (enterprise_hdmi_vddio) { regulator_disable(enterprise_hdmi_vddio); regulator_put(enterprise_hdmi_vddio); enterprise_hdmi_vddio = NULL; } + if (board_info.board_id == BOARD_E1239) { + gpio_set_value(TEGRA_GPIO_PM4, 0); + gpio_free(TEGRA_GPIO_PM4); + } return 0; } @@ -528,8 +575,10 @@ static int enterprise_dsi_panel_enable(void) if (ret) return ret; + #if DSI_PANEL_RESET - if (board_info.fab >= BOARD_FAB_A03) { + if ((board_info.fab >= BOARD_FAB_A03) || + (board_info.board_id == BOARD_E1239)) { if (enterprise_lcd_reg == NULL) { enterprise_lcd_reg = regulator_get(NULL, "lcd_vddio_en"); if (IS_ERR_OR_NULL(enterprise_lcd_reg)) { @@ -812,6 +861,13 @@ static struct platform_device *enterprise_gfx_devices[] __initdata = { #endif }; +static struct platform_device *external_pwm_gfx_devices[] __initdata = { +#if defined(CONFIG_TEGRA_NVMAP) + &enterprise_nvmap_device, +#endif + &tegra_pwfm3_device, +}; + static struct platform_device *enterprise_bl_devices[] = { &enterprise_disp1_backlight_device, }; @@ -859,14 +915,22 @@ int __init enterprise_panel_init(void) BUILD_BUG_ON(ARRAY_SIZE(enterprise_bl_output_measured_a03) != 256); BUILD_BUG_ON(ARRAY_SIZE(enterprise_bl_output_measured_a02) != 256); - if (board_info.fab >= BOARD_FAB_A03) { + if (board_info.board_id != BOARD_E1239) { + if (board_info.fab >= BOARD_FAB_A03) { #if !(IS_EXTERNAL_PWM) - enterprise_disp1_backlight_data.clk_div = 0x1D; + enterprise_disp1_backlight_data.clk_div = 0x1D; #endif - bl_output = enterprise_bl_output_measured_a03; - } else - bl_output = enterprise_bl_output_measured_a02; - + bl_output = enterprise_bl_output_measured_a03; + } else + bl_output = enterprise_bl_output_measured_a02; + } else { + enterprise_sd_settings.bl_device = + &external_pwm_disp1_backlight_device; + enterprise_bl_devices[0] = + &external_pwm_disp1_backlight_device; + bl_output = + enterprise_bl_output_measured_a03; + } enterprise_dsi.chip_id = tegra_get_chipid(); enterprise_dsi.chip_rev = tegra_get_revision(); @@ -878,13 +942,25 @@ int __init enterprise_panel_init(void) gpio_request(enterprise_hdmi_hpd, "hdmi_hpd"); gpio_direction_input(enterprise_hdmi_hpd); - gpio_request(enterprise_lcd_2d_3d, "lcd_2d_3d"); - gpio_direction_output(enterprise_lcd_2d_3d, 0); - enterprise_stereo_set_mode(enterprise_stereo.mode_2d_3d); + if (board_info.board_id != BOARD_E1239) { + gpio_request(enterprise_lcd_2d_3d, "lcd_2d_3d"); + gpio_direction_output(enterprise_lcd_2d_3d, 0); + enterprise_stereo_set_mode(enterprise_stereo.mode_2d_3d); - gpio_request(enterprise_lcd_swp_pl, "lcd_swp_pl"); - gpio_direction_output(enterprise_lcd_swp_pl, 0); - enterprise_stereo_set_orientation(enterprise_stereo.orientation); + gpio_request(enterprise_lcd_swp_pl, "lcd_swp_pl"); + gpio_direction_output(enterprise_lcd_swp_pl, 0); + enterprise_stereo_set_orientation( + enterprise_stereo.orientation); +#if IS_EXTERNAL_PWM + gpio_request(enterprise_bl_pwm, "bl_pwm"); + gpio_free(enterprise_bl_pwm); +#endif + } else { + /* External pwm is used but do not use IS_EXTERNAL_PWM + compiler switch for TAI */ + gpio_request(enterprise_bl_pwm, "bl_pwm"); + gpio_free(enterprise_bl_pwm); + } #if !(DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE) gpio_request(enterprise_lcd_swp_pl, "lcd_te"); @@ -904,9 +980,13 @@ int __init enterprise_panel_init(void) return err; #endif - err = platform_add_devices(enterprise_gfx_devices, - ARRAY_SIZE(enterprise_gfx_devices)); - + if (board_info.board_id != BOARD_E1239) { + err = platform_add_devices(enterprise_gfx_devices, + ARRAY_SIZE(enterprise_gfx_devices)); + } else { + err = platform_add_devices(external_pwm_gfx_devices, + ARRAY_SIZE(external_pwm_gfx_devices)); + } #if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC) res = nvhost_get_resource_byname(&enterprise_disp1_device, IORESOURCE_MEM, "fbmem"); diff --git a/arch/arm/mach-tegra/board-enterprise-pinmux.c b/arch/arm/mach-tegra/board-enterprise-pinmux.c index 1a19dbf95f4a..71cdd143c88c 100644 --- a/arch/arm/mach-tegra/board-enterprise-pinmux.c +++ b/arch/arm/mach-tegra/board-enterprise-pinmux.c @@ -501,7 +501,9 @@ static __initdata struct tegra_pingroup_config enterprise_pinmux_a02[] = { static struct tegra_gpio_table gpio_table[] = { { .gpio = TEGRA_GPIO_HP_DET, .enable = true }, }; - +static struct tegra_gpio_table tai_gpio_table[] = { + { .gpio = TEGRA_GPIO_CODEC_RST, .enable = true }, +}; struct pin_info_low_power_mode { char name[16]; int gpio_nr; @@ -594,6 +596,354 @@ static __initdata struct pin_info_low_power_mode enterprise_gpio_pins_a03[] = { PIN_GPIO_LPM("SPI1_MISO", TEGRA_GPIO_PX7, 0, 0), PIN_GPIO_LPM("SPI1_SCK", TEGRA_GPIO_PX5, 0, 0), }; +/*******************************TAI pinmux (E1239) ************************/ +static __initdata struct tegra_pingroup_config tai_pinmux_common[] = { + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, PULL_UP, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, PULL_UP, NORMAL, INPUT), + + /* SDMMC4 pinmux */ + DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_RST_N, RSVD1, PULL_DOWN, NORMAL, INPUT), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C3 pinmux */ + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C4 pinmux */ + I2C_PINMUX(DDC_SCL, I2C4, PULL_UP, NORMAL, INPUT, DISABLE, DISABLE), + I2C_PINMUX(DDC_SDA, I2C4, PULL_UP, NORMAL, INPUT, DISABLE, DISABLE), + + /* Power I2C pinmux */ + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + DEFAULT_PINMUX(ULPI_DATA0, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA1, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_CLK, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DIR, ULPI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_NXT, ULPI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_CS0_N, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC0, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D0, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D1, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D7, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D8, DISPLAYA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(LCD_D9, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D13, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC1, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_D1, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_D2, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_D3, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(VI_D5, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_D7, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_MCLK, VI, PULL_UP, NORMAL, INPUT), + + DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU0, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU1, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU2, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU3, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU6, PWM3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD11, PWM3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW0, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW1, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW2, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW3, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW10, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL0, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL3, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL4, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV0, RSVD, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(CLK_32K_OUT, BLINK, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT), + + + DEFAULT_PINMUX(SPI2_CS1_N, INVALID, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + CEC_PINMUX(HDMI_CEC, CEC, NORMAL, TRISTATE, OUTPUT, DEFAULT, DISABLE), + DEFAULT_PINMUX(HDMI_INT, RSVD0, NORMAL, TRISTATE, INPUT), + + /* Gpios */ + /* SDMMC1 CD gpio */ + DEFAULT_PINMUX(GMI_IORDY, RSVD1, PULL_UP, NORMAL, INPUT), + /* SDMMC1 WP gpio */ + DEFAULT_PINMUX(VI_D11, RSVD1, PULL_UP, NORMAL, INPUT), + + /* Touch RESET */ + DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(GMI_AD15, NAND, PULL_UP, TRISTATE, INPUT), + + /* Power rails GPIO */ + DEFAULT_PINMUX(KB_ROW8, KBC, PULL_UP, NORMAL, INPUT), + + VI_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_PCLK, RSVD1, PULL_UP, TRISTATE, INPUT, DISABLE, ENABLE), + VI_PINMUX(VI_HSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + DEFAULT_PINMUX(LCD_PWR0, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D10, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS7_N, NAND_ALT, PULL_UP, TRISTATE, INPUT), + DEFAULT_PINMUX(SPI2_MOSI, SPI6, PULL_UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), +}; + +static __initdata struct tegra_pingroup_config tai_pinmux_a02[] = { + DEFAULT_PINMUX(LCD_PWR2, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_PWR1, DISPLAYA, NORMAL, NORMAL, INPUT), +}; + +static __initdata struct tegra_pingroup_config tai_pinmux_a03[] = { + DEFAULT_PINMUX(LCD_PWR2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR1, DISPLAYA, NORMAL, NORMAL, OUTPUT), +}; + +static __initdata struct tegra_pingroup_config tai_unused_pinmux_common[] = { + DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(CLK2_REQ, DAP, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(CLK3_REQ, DEV3, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(CLK_32K_OUT, BLINK, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB4, VGP4, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB5, VGP5, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB6, VGP6, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD0, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD1, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD2, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD3, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD4, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD5, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD6, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD7, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS0_N, GMI, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS2_N, GMI, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS3_N, GMI, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS6_N, GMI, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CLK, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_DQS, RSVD3, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_RST_N, GMI, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_WAIT, GMI, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_WP_N, GMI, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW6, KBC, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW7, KBC, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW9, KBC, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW11, KBC, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW13, KBC, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW14, KBC, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW15, KBC, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_PCLK, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_WR_N, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_HSYNC, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_VSYNC, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_SCK, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_SDOUT, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_SDIN, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(CRT_HSYNC, CRT, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(CRT_VSYNC, CRT, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC3_DAT6, SDMMC3, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPDIF_OUT, SPDIF, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI2_SCK, SPI2, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI2_MISO, SPI2, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI2_CS0_N, SPI2, PULL_DOWN, TRISTATE, OUTPUT), + + DEFAULT_PINMUX(LCD_D19, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_M1, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD8, PWM0, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD9, PWM1, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD10, PWM2, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD12, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD13, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI, SPI2, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI1_SCK , SPI2, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI1_MISO , INVALID, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI1_CS0_N, SPI1, PULL_DOWN, TRISTATE, OUTPUT), +}; + +static __initdata struct pin_info_low_power_mode +tai_unused_gpio_pins_common[] = { + PIN_GPIO_LPM("CLK2_OUT", TEGRA_GPIO_PW5, 0, 0), + PIN_GPIO_LPM("CLK2_REQ", TEGRA_GPIO_PCC5, 0, 0), + PIN_GPIO_LPM("CLK3_REQ", TEGRA_GPIO_PEE1, 0, 0), + PIN_GPIO_LPM("CLK_32K_OUT", TEGRA_GPIO_PA0, 0, 0), + PIN_GPIO_LPM("GPIO_PBB4", TEGRA_GPIO_PBB4, 0, 0), + PIN_GPIO_LPM("GPIO_PBB5", TEGRA_GPIO_PBB5, 0, 0), + PIN_GPIO_LPM("GPIO_PBB6", TEGRA_GPIO_PBB6, 0, 0), + PIN_GPIO_LPM("GMI_AD0", TEGRA_GPIO_PG0, 0, 0), + PIN_GPIO_LPM("GMI_AD1", TEGRA_GPIO_PG1, 0, 0), + PIN_GPIO_LPM("GMI_AD2", TEGRA_GPIO_PG2, 0, 0), + PIN_GPIO_LPM("GMI_AD3", TEGRA_GPIO_PG3, 0, 0), + PIN_GPIO_LPM("GMI_AD4", TEGRA_GPIO_PG4, 0, 0), + PIN_GPIO_LPM("GMI_AD5", TEGRA_GPIO_PG5, 0, 0), + PIN_GPIO_LPM("GMI_AD6", TEGRA_GPIO_PG6, 0, 0), + PIN_GPIO_LPM("GMI_AD7", TEGRA_GPIO_PG7, 0, 0), + PIN_GPIO_LPM("GMI_CS0_N", TEGRA_GPIO_PJ0, 0, 0), + PIN_GPIO_LPM("GMI_CS2_N", TEGRA_GPIO_PK3, 0, 0), + PIN_GPIO_LPM("GMI_CS3_N", TEGRA_GPIO_PK4, 0, 0), + PIN_GPIO_LPM("GMI_CS6_N", TEGRA_GPIO_PI3, 0, 0), + PIN_GPIO_LPM("GMI_CLK", TEGRA_GPIO_PK1, 0, 0), + PIN_GPIO_LPM("GMI_DQS", TEGRA_GPIO_PI2, 0, 0), + PIN_GPIO_LPM("GMI_RST_N", TEGRA_GPIO_PI4, 0, 0), + PIN_GPIO_LPM("GMI_WAIT", TEGRA_GPIO_PI7, 0, 0), + PIN_GPIO_LPM("GMI_WP_N", TEGRA_GPIO_PC7, 0, 0), + PIN_GPIO_LPM("KB_ROW6", TEGRA_GPIO_PR6, 0, 0), + PIN_GPIO_LPM("KB_ROW7", TEGRA_GPIO_PR7, 0, 0), + PIN_GPIO_LPM("KB_ROW9", TEGRA_GPIO_PS1, 0, 0), + PIN_GPIO_LPM("KB_ROW11", TEGRA_GPIO_PS3, 0, 0), + PIN_GPIO_LPM("KB_ROW13", TEGRA_GPIO_PS5, 0, 0), + PIN_GPIO_LPM("KB_ROW14", TEGRA_GPIO_PS6, 0, 0), + PIN_GPIO_LPM("KB_ROW15", TEGRA_GPIO_PS7, 0, 0), + PIN_GPIO_LPM("LCD_PCLK", TEGRA_GPIO_PB3, 0, 0), + PIN_GPIO_LPM("LCD_WR_N", TEGRA_GPIO_PZ3, 0, 0), + PIN_GPIO_LPM("LCD_HSYNC", TEGRA_GPIO_PJ3, 0, 0), + PIN_GPIO_LPM("LCD_VSYNC", TEGRA_GPIO_PJ4, 0, 0), + PIN_GPIO_LPM("LCD_SCK", TEGRA_GPIO_PZ4, 0, 0), + PIN_GPIO_LPM("LCD_SDOUT", TEGRA_GPIO_PN5, 0, 0), + PIN_GPIO_LPM("LCD_SDIN", TEGRA_GPIO_PZ2, 0, 0), + PIN_GPIO_LPM("CRT_HSYNC", TEGRA_GPIO_PV6, 0, 0), + PIN_GPIO_LPM("CRT_VSYNC", TEGRA_GPIO_PV7, 0, 0), + PIN_GPIO_LPM("SDMMC3_DAT4", TEGRA_GPIO_PD1, 0, 0), + PIN_GPIO_LPM("SDMMC3_DAT5", TEGRA_GPIO_PD0, 0, 0), + PIN_GPIO_LPM("SDMMC3_DAT6", TEGRA_GPIO_PD3, 0, 0), + PIN_GPIO_LPM("SDMMC3_DAT7", TEGRA_GPIO_PD4, 0, 0), + PIN_GPIO_LPM("SPDIF_OUT", TEGRA_GPIO_PK5, 0, 0), + PIN_GPIO_LPM("SPI1_CS0_N", TEGRA_GPIO_PX6, 0, 0), + PIN_GPIO_LPM("SPI2_SCK", TEGRA_GPIO_PX2, 0, 0), + PIN_GPIO_LPM("SPI2_MISO", TEGRA_GPIO_PX1, 0, 0), + PIN_GPIO_LPM("SPI2_CS0_N", TEGRA_GPIO_PX3, 0, 0), + PIN_GPIO_LPM("LCD_D19", TEGRA_GPIO_PM3, 0, 0), + PIN_GPIO_LPM("LCD_M1", TEGRA_GPIO_PW1, 0, 0), + PIN_GPIO_LPM("GMI_AD8", TEGRA_GPIO_PH0, 0, 0), + PIN_GPIO_LPM("GMI_AD9", TEGRA_GPIO_PH1, 0, 0), + PIN_GPIO_LPM("GMI_AD10", TEGRA_GPIO_PH2, 0, 0), + PIN_GPIO_LPM("GMI_AD12", TEGRA_GPIO_PH4, 0, 0), + PIN_GPIO_LPM("GMI_AD13", TEGRA_GPIO_PH5, 0, 0), + PIN_GPIO_LPM("DAP2_FS", TEGRA_GPIO_PA2, 0, 0), + PIN_GPIO_LPM("DAP2_DIN", TEGRA_GPIO_PA4, 0, 0), + PIN_GPIO_LPM("DAP2_DOUT", TEGRA_GPIO_PA5, 0, 0), + PIN_GPIO_LPM("DAP2_SCLK", TEGRA_GPIO_PA3, 0, 0), + PIN_GPIO_LPM("SPI1_MOSI", TEGRA_GPIO_PX4, 0, 0), + PIN_GPIO_LPM("SPI1_SCK", TEGRA_GPIO_PX5, 0, 0), + PIN_GPIO_LPM("SPI1_MISO", TEGRA_GPIO_PX7, 0, 0), + +}; static void enterprise_set_unused_pin_gpio(struct pin_info_low_power_mode *lpm_pin_info, int list_count) @@ -632,27 +982,51 @@ int __init enterprise_pinmux_init(void) struct board_info board_info; tegra_get_board_info(&board_info); - tegra_pinmux_config_table(enterprise_pinmux_common, + if (board_info.board_id != BOARD_E1239) { + tegra_pinmux_config_table(enterprise_pinmux_common, ARRAY_SIZE(enterprise_pinmux_common)); - tegra_drive_pinmux_config_table(enterprise_drive_pinmux, - ARRAY_SIZE(enterprise_drive_pinmux)); - tegra_pinmux_config_table(enterprise_unused_pinmux_common, + tegra_drive_pinmux_config_table(enterprise_drive_pinmux, + ARRAY_SIZE(enterprise_drive_pinmux)); + tegra_pinmux_config_table(enterprise_unused_pinmux_common, ARRAY_SIZE(enterprise_unused_pinmux_common)); - tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table)); - enterprise_set_unused_pin_gpio(enterprise_unused_gpio_pins_common, - ARRAY_SIZE(enterprise_unused_gpio_pins_common)); + tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table)); + enterprise_set_unused_pin_gpio( + enterprise_unused_gpio_pins_common, + ARRAY_SIZE(enterprise_unused_gpio_pins_common)); - if (board_info.fab < BOARD_FAB_A03) { - tegra_pinmux_config_table(enterprise_pinmux_a02, + if (board_info.fab < BOARD_FAB_A03) { + tegra_pinmux_config_table(enterprise_pinmux_a02, ARRAY_SIZE(enterprise_pinmux_a02)); - enterprise_set_unused_pin_gpio(enterprise_unused_gpio_pins_a02, - ARRAY_SIZE(enterprise_unused_gpio_pins_a02)); - } else { - tegra_pinmux_config_table(enterprise_pinmux_a03, + enterprise_set_unused_pin_gpio( + enterprise_unused_gpio_pins_a02, + ARRAY_SIZE(enterprise_unused_gpio_pins_a02)); + } else { + tegra_pinmux_config_table(enterprise_pinmux_a03, ARRAY_SIZE(enterprise_pinmux_a03)); - enterprise_set_unused_pin_gpio(enterprise_gpio_pins_a03, - ARRAY_SIZE(enterprise_gpio_pins_a03)); + enterprise_set_unused_pin_gpio(enterprise_gpio_pins_a03, + ARRAY_SIZE(enterprise_gpio_pins_a03)); + } + } else { + tegra_pinmux_config_table(tai_pinmux_common, + ARRAY_SIZE(tai_pinmux_common)); + if (board_info.fab <= BOARD_FAB_A02) { + tegra_pinmux_config_table(tai_pinmux_a02, + ARRAY_SIZE(tai_pinmux_a02)); + } else { + tegra_pinmux_config_table(tai_pinmux_a03, + ARRAY_SIZE(tai_pinmux_a03)); + } + tegra_drive_pinmux_config_table(enterprise_drive_pinmux, + ARRAY_SIZE(enterprise_drive_pinmux)); + tegra_pinmux_config_table(tai_unused_pinmux_common, + ARRAY_SIZE(tai_unused_pinmux_common)); + + tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table)); + tegra_gpio_config(tai_gpio_table, ARRAY_SIZE(tai_gpio_table)); + enterprise_set_unused_pin_gpio(tai_unused_gpio_pins_common, + ARRAY_SIZE(tai_unused_gpio_pins_common)); + } return 0; diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index f974c49c9f50..7ea2095e6622 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -446,6 +446,10 @@ static struct regulator_consumer_supply fixed_reg_pmu_3v3_en_supply[] = { static struct regulator_consumer_supply fixed_reg_pmu_hdmi_5v0_en_supply[] = { REGULATOR_SUPPLY("hdmi_5v0", NULL), }; +static struct regulator_consumer_supply +fixed_reg_pmu_hdmi_5v0_en_tai_supply[] = { + REGULATOR_SUPPLY("hdmi_5v0", NULL), +}; /* LCD-D16 (GPIO M0) from T30*/ static struct regulator_consumer_supply fixed_reg_vdd_fuse_en_supply[] = { @@ -627,6 +631,9 @@ FIXED_REG(7, vdd_sdmmc3_2v85_en, NULL, FIXED_REG(8, lcd_1v8_en, NULL, TEGRA_GPIO_PB2, true, 1800, 0, 0); +FIXED_REG(9, pmu_hdmi_5v0_en_tai, NULL, + ENT_TPS80031_GPIO_SYSEN, true, 5000, 0, 0); + #define ADD_FIXED_REG(_name) (&fixed_reg_##_name##_dev) static struct platform_device *fixed_regs_devices_a02[] = { ADD_FIXED_REG(pmu_5v15_en), @@ -647,6 +654,14 @@ static struct platform_device *fixed_regs_devices_a03[] = { ADD_FIXED_REG(lcd_1v8_en), }; +static struct platform_device *fixed_regs_devices_tai[] = { + ADD_FIXED_REG(pmu_hdmi_5v0_en_tai), + ADD_FIXED_REG(cam_ldo_2v8_en), + ADD_FIXED_REG(cam_ldo_1v8_en), + ADD_FIXED_REG(vdd_sdmmc3_2v85_en), + ADD_FIXED_REG(lcd_1v8_en), +}; + #define ADD_GPIO_REG(_name) (&gpio_reg_##_name##_dev) static struct platform_device *gpio_regs_devices[] = { ADD_GPIO_REG(sdmmc3_vdd_sel), @@ -660,14 +675,18 @@ static int __init enterprise_fixed_regulator_init(void) tegra_get_board_info(&board_info); - if (board_info.fab < BOARD_FAB_A03) { - fixed_regs_devices = fixed_regs_devices_a02; - nfixreg_devs = ARRAY_SIZE(fixed_regs_devices_a02); + if (board_info.board_id == BOARD_E1239) { + fixed_regs_devices = fixed_regs_devices_tai; + nfixreg_devs = ARRAY_SIZE(fixed_regs_devices_tai); } else { - fixed_regs_devices = fixed_regs_devices_a03; - nfixreg_devs = ARRAY_SIZE(fixed_regs_devices_a03); + if (board_info.fab < BOARD_FAB_A03) { + fixed_regs_devices = fixed_regs_devices_a02; + nfixreg_devs = ARRAY_SIZE(fixed_regs_devices_a02); + } else { + fixed_regs_devices = fixed_regs_devices_a03; + nfixreg_devs = ARRAY_SIZE(fixed_regs_devices_a03); + } } - return platform_add_devices(fixed_regs_devices, nfixreg_devs); } @@ -721,7 +740,8 @@ int __init enterprise_regulator_init(void) battery_gauge_data.battery_present = 0; } - if (board_info.fab < BOARD_FAB_A03) { + if ((board_info.fab < BOARD_FAB_A03) && + (board_info.board_id != BOARD_E1239)) { tps_platform.num_regulator_pdata = ARRAY_SIZE(tps80031_reg_pdata_a02); tps_platform.regulator_pdata = tps80031_reg_pdata_a02; } else { @@ -770,6 +790,7 @@ static void enterprise_init_deep_sleep_mode(void) enterprise_suspend_data.suspend_mode = TEGRA_SUSPEND_LP1; if ((bi.board_id == BOARD_E1205 && (bi.sku & BOARD_SKU_VF_BIT) == 0) || + (bi.board_id == BOARD_E1239 && (bi.sku & BOARD_SKU_VF_BIT) == 0) || (bi.board_id == BOARD_E1197 && (bi.sku & BOARD_SKU_VF_BIT))) enterprise_suspend_data.cpu_timer = 8000; } diff --git a/arch/arm/mach-tegra/board-enterprise-sensors.c b/arch/arm/mach-tegra/board-enterprise-sensors.c index aab409b89ea9..c66d3fbbd1e8 100644 --- a/arch/arm/mach-tegra/board-enterprise-sensors.c +++ b/arch/arm/mach-tegra/board-enterprise-sensors.c @@ -40,16 +40,21 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include "cpu-tegra.h" #include "gpio-names.h" #include "board-enterprise.h" #include "board.h" +#include "clock.h" + +static struct board_info board_info; static int nct_get_temp(void *_data, long *temp) { @@ -283,6 +288,14 @@ struct enterprise_power_rail { static struct enterprise_power_rail ent_vicsi_pwr[NUM_OF_CAM]; +static __initdata struct tegra_clk_init_table tai_front_cam_clk_init_table[] = { + /* name parent rate enabled */ + { "extern3", "pll_p", 24000000, false}, + { "clk_out_3", "extern3", 24000000, false}, + { NULL, NULL, 0, 0}, +}; + + static int enterprise_cam_pwr(enum CAMERA_INDEX cam, bool pwr_on) { struct enterprise_power_rail *reg_cam = &ent_vicsi_pwr[cam]; @@ -357,7 +370,8 @@ static int enterprise_ar0832_ri_power_on(int is_stereo) /* Release Reset */ if (is_stereo) { gpio_set_value(CAM1_RST_L_GPIO, 1); - gpio_set_value(CAM2_RST_L_GPIO, 1); + if (board_info.board_id != BOARD_E1239) + gpio_set_value(CAM2_RST_L_GPIO, 1); } else gpio_set_value(CAM1_RST_L_GPIO, 1); /* @@ -375,11 +389,12 @@ static int enterprise_ar0832_le_power_on(int is_stereo) int ret = 0; pr_info("%s: ++\n", __func__); - ret = enterprise_cam_pwr(CAM_REAR_LEFT, true); - - /* Release Reset */ - gpio_set_value(CAM2_RST_L_GPIO, 1); + if (board_info.board_id != BOARD_E1239) { + ret = enterprise_cam_pwr(CAM_REAR_LEFT, true); + /* Release Reset */ + gpio_set_value(CAM2_RST_L_GPIO, 1); + } /* It takes 2400 EXTCLK for ar0832 to be ready for I2c. EXTCLK is 10 ~ 24MHz. 1 ms should be enough to cover @@ -387,8 +402,10 @@ static int enterprise_ar0832_le_power_on(int is_stereo) */ enterprise_msleep(1); - /* CSI B is shared between Front camera and Rear Left camera */ - gpio_set_value(CAM_CSI_MUX_SEL_GPIO, 1); + if (board_info.board_id != BOARD_E1239) { + /* CSI B is shared between Front camera and Rear Left camera */ + gpio_set_value(CAM_CSI_MUX_SEL_GPIO, 1); + } return ret; } @@ -403,7 +420,8 @@ static int enterprise_ar0832_ri_power_off(int is_stereo) /* Assert Reset */ if (is_stereo) { gpio_set_value(CAM1_RST_L_GPIO, 0); - gpio_set_value(CAM2_RST_L_GPIO, 0); + if (board_info.board_id != BOARD_E1239) + gpio_set_value(CAM2_RST_L_GPIO, 0); } else gpio_set_value(CAM1_RST_L_GPIO, 0); @@ -412,14 +430,15 @@ static int enterprise_ar0832_ri_power_off(int is_stereo) static int enterprise_ar0832_le_power_off(int is_stereo) { - int ret; - - pr_info("%s: ++\n", __func__); - ret = enterprise_cam_pwr(CAM_REAR_LEFT, false); + int ret = 0; - /* Assert Reset */ - gpio_set_value(CAM2_RST_L_GPIO, 0); + if (board_info.board_id != BOARD_E1239) { + pr_info("%s: ++\n", __func__); + ret = enterprise_cam_pwr(CAM_REAR_LEFT, false); + /* Assert Reset */ + gpio_set_value(CAM2_RST_L_GPIO, 0); + } return ret; } @@ -427,10 +446,15 @@ static int enterprise_ov9726_power_on(void) { pr_info("ov9726 power on\n"); - /* switch mipi mux to front camera */ - gpio_set_value(CAM_CSI_MUX_SEL_GPIO, CAM_CSI_MUX_SEL_FRONT); + if (board_info.board_id != BOARD_E1239) { + /* switch mipi mux to front camera */ + gpio_set_value(CAM_CSI_MUX_SEL_GPIO, CAM_CSI_MUX_SEL_FRONT); + } enterprise_cam_pwr(CAM_FRONT, true); + if (board_info.board_id == BOARD_E1239) + clk_enable(tegra_get_clock_by_name("clk_out_3")); + return 0; } @@ -440,6 +464,9 @@ static int enterprise_ov9726_power_off(void) enterprise_cam_pwr(CAM_FRONT, false); + if (board_info.board_id == BOARD_E1239) + clk_disable(tegra_get_clock_by_name("clk_out_3")); + return 0; } @@ -485,7 +512,13 @@ static struct enterprise_cam_gpio enterprise_cam_gpio_data[] = { [5] = TEGRA_CAMERA_GPIO(CAM_FLASH_EN_GPIO, "flash_en", 1), [6] = TEGRA_CAMERA_GPIO(CAM_I2C_MUX_RST_EXP, "cam_i2c_mux_rst", 1), }; - +static struct enterprise_cam_gpio tai_cam_gpio_data[] = { + [0] = TEGRA_CAMERA_GPIO(CAM1_RST_L_GPIO, "cam1_rst_lo", 0), + [1] = TEGRA_CAMERA_GPIO(CAM3_RST_L_GPIO, "cam3_rst_lo", 0), + [2] = TEGRA_CAMERA_GPIO(CAM3_PWDN_GPIO, "cam3_pwdn", 1), + [3] = TEGRA_CAMERA_GPIO(CAM_FLASH_EN_GPIO, "flash_en", 1), + [4] = TEGRA_CAMERA_GPIO(CAM_I2C_MUX_RST_EXP, "cam_i2c_mux_rst", 1), +}; static struct pca954x_platform_mode enterprise_pca954x_modes[] = { { .adap_id = PCA954x_I2C_BUS0, .deselect_on_exit = true, }, { .adap_id = PCA954x_I2C_BUS1, .deselect_on_exit = true, }, @@ -565,49 +598,87 @@ static struct i2c_board_info enterprise_i2c7_boardinfo[] = { .platform_data = &enterprise_ar0832_ri_data, }, }; +static struct i2c_board_info ar0832_i2c2_boardinfo_tai[] = { + { + /* 0x36: alternative slave address */ + I2C_BOARD_INFO("ar0832", 0x36), + .platform_data = &enterprise_ar0832_ri_data, + }, + { + I2C_BOARD_INFO("tps61050", 0x33), + .platform_data = &enterprise_tps61050_pdata, + }, + { + I2C_BOARD_INFO("ov9726", OV9726_I2C_ADDR >> 1), + .platform_data = &enterprise_ov9726_data, + }, +}; static int enterprise_cam_init(void) { int ret; int i; - struct board_info bi; struct board_info cam_bi; bool i2c_mux = false; pr_info("%s:++\n", __func__); memset(ent_vicsi_pwr, 0, sizeof(ent_vicsi_pwr)); - for (i = 0; i < ARRAY_SIZE(enterprise_cam_gpio_data); i++) { - ret = gpio_request(enterprise_cam_gpio_data[i].gpio, - enterprise_cam_gpio_data[i].label); - if (ret < 0) { - pr_err("%s: gpio_request failed for gpio #%d\n", - __func__, i); - goto fail_free_gpio; - } - gpio_direction_output(enterprise_cam_gpio_data[i].gpio, - enterprise_cam_gpio_data[i].value); - gpio_export(enterprise_cam_gpio_data[i].gpio, false); - } - tegra_get_board_info(&bi); tegra_get_camera_board_info(&cam_bi); - if (bi.board_id == BOARD_E1205) { - if (bi.fab == BOARD_FAB_A00 || bi.fab == BOARD_FAB_A01) + if (board_info.board_id == BOARD_E1239) { + for (i = 0; i < ARRAY_SIZE(tai_cam_gpio_data); i++) { + ret = gpio_request(tai_cam_gpio_data[i].gpio, + tai_cam_gpio_data[i].label); + if (ret < 0) { + pr_err("%s: gpio_request failed for gpio #%d\n", + __func__, i); + goto fail_free_gpio; + } + gpio_direction_output(tai_cam_gpio_data[i].gpio, + tai_cam_gpio_data[i].value); + gpio_export(tai_cam_gpio_data[i].gpio, false); + } + + tegra_clk_init_from_table(tai_front_cam_clk_init_table); + + } else { + for (i = 0; i < ARRAY_SIZE(enterprise_cam_gpio_data); i++) { + ret = gpio_request(enterprise_cam_gpio_data[i].gpio, + enterprise_cam_gpio_data[i].label); + if (ret < 0) { + pr_err("%s: gpio_request failed for gpio #%d\n", + __func__, i); + goto fail_free_gpio; + } + gpio_direction_output(enterprise_cam_gpio_data[i].gpio, + enterprise_cam_gpio_data[i].value); + gpio_export(enterprise_cam_gpio_data[i].gpio, false); + } + } + + if (board_info.board_id == BOARD_E1205) { + if (board_info.fab == BOARD_FAB_A00 || + board_info.fab == BOARD_FAB_A01) i2c_mux = false; - else if (bi.fab == BOARD_FAB_A02) + else if (board_info.fab == BOARD_FAB_A02) i2c_mux = true; - } else if (bi.board_id == BOARD_E1197) { + } else if (board_info.board_id == BOARD_E1197) { if (cam_bi.fab == BOARD_FAB_A00) i2c_mux = false; else if (cam_bi.fab == BOARD_FAB_A01) i2c_mux = true; } - if (!i2c_mux) - i2c_register_board_info(2, ar0832_i2c2_boardinfo, - ARRAY_SIZE(ar0832_i2c2_boardinfo)); - else { + if (!i2c_mux) { + if (board_info.board_id == BOARD_E1239) { + i2c_register_board_info(2, ar0832_i2c2_boardinfo_tai, + ARRAY_SIZE(ar0832_i2c2_boardinfo)); + } else { + i2c_register_board_info(2, ar0832_i2c2_boardinfo, + ARRAY_SIZE(ar0832_i2c2_boardinfo)); + } + } else { i2c_register_board_info(2, enterprise_i2c2_boardinfo, ARRAY_SIZE(enterprise_i2c2_boardinfo)); /* @@ -623,8 +694,14 @@ static int enterprise_cam_init(void) fail_free_gpio: pr_err("%s enterprise_cam_init failed!\n", __func__); - while (i--) - gpio_free(enterprise_cam_gpio_data[i].gpio); + if (board_info.board_id == BOARD_E1239) { + while (i--) + gpio_free(tai_cam_gpio_data[i].gpio); + + } else { + while (i--) + gpio_free(enterprise_cam_gpio_data[i].gpio); + } return ret; } @@ -657,9 +734,12 @@ int __init enterprise_sensors_init(void) { int ret; + tegra_get_board_info(&board_info); + enterprise_isl_init(); enterprise_nct1008_init(); - mpuirq_init(); + if (board_info.board_id != BOARD_E1239) + mpuirq_init(); #if ENTERPRISE_INA230_ENABLED enterprise_ina230_init(); #endif diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c index 0a3024f62dab..498f8a176991 100644 --- a/arch/arm/mach-tegra/board-enterprise.c +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -875,18 +875,31 @@ static void enterprise_audio_init(void) tegra_get_board_info(&board_info); - if (board_info.board_id == BOARD_E1197) - enterprise_audio_pdata.i2s_param[HIFI_CODEC].audio_port_id = 1; - else if (board_info.fab == BOARD_FAB_A04) { - enterprise_audio_pdata.i2s_param[BASEBAND].audio_port_id = 4; + if (board_info.board_id == BOARD_E1239) { + enterprise_audio_aic326x_pdata.i2s_param[BASEBAND]. + audio_port_id = 4; + enterprise_audio_aic326x_pdata.i2s_param[BASEBAND]. + i2s_mode = TEGRA_DAIFMT_I2S; + enterprise_audio_aic326x_pdata.i2s_param[BASEBAND]. + channels = 2; platform_device_register(&tegra_i2s_device4); } else { - enterprise_audio_pdata.i2s_param[BASEBAND].audio_port_id = 2; - platform_device_register(&tegra_i2s_device2); - } + if (board_info.board_id == BOARD_E1197) + enterprise_audio_pdata.i2s_param[HIFI_CODEC]. + audio_port_id = 1; + else if (board_info.fab == BOARD_FAB_A04) { + enterprise_audio_pdata.i2s_param[BASEBAND]. + audio_port_id = 4; + platform_device_register(&tegra_i2s_device4); + } else { + enterprise_audio_pdata.i2s_param[BASEBAND]. + audio_port_id = 2; + platform_device_register(&tegra_i2s_device2); + } + } platform_add_devices(enterprise_audio_devices, - ARRAY_SIZE(enterprise_audio_devices)); + ARRAY_SIZE(enterprise_audio_devices)); } @@ -953,8 +966,12 @@ static struct platform_device tegra_baseband_m7400_device = { static void enterprise_baseband_init(void) { + struct board_info board_info; + int modem_id = tegra_get_modem_id(); + tegra_get_board_info(&board_info); + switch (modem_id) { case TEGRA_BB_PH450: /* PH450 ULPI */ enterprise_modem_init(); @@ -967,7 +984,13 @@ static void enterprise_baseband_init(void) &tegra_usb_hsic_host_register; tegra_baseband_power_data.hsic_unregister = &tegra_usb_hsic_host_unregister; - + if ((board_info.board_id == BOARD_E1239) && + (board_info.fab <= BOARD_FAB_A02)) { + tegra_baseband_power_data.modem. + xmm.ipc_hsic_active = BB_GPIO_LCD_PWR2; + tegra_baseband_power_data.modem. + xmm.ipc_hsic_sus_req = BB_GPIO_LCD_PWR1; + } platform_device_register(&tegra_baseband_power_device); platform_device_register(&tegra_baseband_power2_device); break; @@ -989,6 +1012,8 @@ static void enterprise_nfc_init(void) tegra_get_board_info(&bi); if (bi.board_id == BOARD_E1205 && bi.fab >= BOARD_FAB_A03) { nfc_pdata.firm_gpio = TEGRA_GPIO_PX7; + } else if (bi.board_id == BOARD_E1239) { + nfc_pdata.firm_gpio = TEGRA_GPIO_PN6; } } @@ -1009,6 +1034,9 @@ static void __init tegra_enterprise_init(void) enterprise_i2c_init(); enterprise_uart_init(); enterprise_usb_init(); + if (board_info.board_id == BOARD_E1239) + enterprise_bt_rfkill_pdata[0].shutdown_gpio = TEGRA_GPIO_PF4; + platform_add_devices(enterprise_devices, ARRAY_SIZE(enterprise_devices)); tegra_ram_console_debug_init(); enterprise_regulator_init(); diff --git a/arch/arm/mach-tegra/board-enterprise.h b/arch/arm/mach-tegra/board-enterprise.h index 3c6d149abdff..b77c3cae7346 100644 --- a/arch/arm/mach-tegra/board-enterprise.h +++ b/arch/arm/mach-tegra/board-enterprise.h @@ -28,6 +28,7 @@ /* Processor Board ID */ #define BOARD_E1205 0x0C05 #define BOARD_E1197 0x0B61 +#define BOARD_E1239 0x0C27 #define SKU_BATTERY_SUPPORT 0x1 /* Board Fab version */ @@ -113,6 +114,7 @@ void enterprise_bpc_mgmt_init(void); /* Audio-related GPIOs */ #define TEGRA_GPIO_HP_DET TEGRA_GPIO_PW3 +#define TEGRA_GPIO_CODEC_RST TEGRA_GPIO_PX0 /* Baseband GPIO addresses */ @@ -159,6 +161,7 @@ enum tegra_bb_type { }; /* Indicate the pwm of backlight, DC pwm or external pwm3. */ +/* External pwm is used for TAI (E1239) but do not set this compiler switch */ #define IS_EXTERNAL_PWM 0 #endif /*_MACH_TEGRA_BOARD_ENTERPRISE_H */ -- cgit v1.2.3 From 812e6d344d35d7ef6df9ccbeed5f6a65c53e7977 Mon Sep 17 00:00:00 2001 From: Jay Agarwal Date: Thu, 16 Aug 2012 18:08:12 +0530 Subject: arm: tegra: pcie: WAR to avoid hang on PCIe device Setting DFPCI_RSPPASSPW bit in AFI_CONFIGURATION register to avoid instant hang on CPU read/write while gpu transfers are in progress. Bug 1034443 Change-Id: I40c99588753b8b2cb2d418b54c6ac73f7b8ddc13 Signed-off-by: Jay Agarwal Reviewed-on: http://git-master/r/124037 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/pcie.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index eef215b00018..04d3a5db3f7e 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -105,6 +105,7 @@ #define AFI_CONFIGURATION 0xac #define AFI_CONFIGURATION_EN_FPCI (1 << 0) +#define AFI_CONFIGURATION_DFPCI_RSPPASSPW (1 << 2) #define AFI_FPCI_ERROR_MASKS 0xb0 @@ -876,8 +877,11 @@ static void tegra_pcie_enable_controller(void) /* Take the PCIe interface module out of reset */ tegra_periph_reset_deassert(tegra_pcie.pcie_xclk); + /* WAR avoid hang on CPU read/write while gpu transfers in progress */ + val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_DFPCI_RSPPASSPW; + /* Finally enable PCIe */ - val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI; + val |= AFI_CONFIGURATION_EN_FPCI; afi_writel(val, AFI_CONFIGURATION); val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR | -- cgit v1.2.3 From 22c39b2a2302932c58ebe78e7c9315c07d84e6ab Mon Sep 17 00:00:00 2001 From: Manoj Gangwal Date: Wed, 22 Aug 2012 19:41:25 +0530 Subject: arm: tegra: config: Enable TI TLV320AIC326X codec Enable TI TLV320AIC326X audio codec configuration. Bug 1034241 Change-Id: I5997c365f6ae3fde12e40f3a157421b655bb054e Signed-off-by: Manoj Gangwal Reviewed-on: http://git-master/r/125261 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/configs/tegra3_android_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/tegra3_android_defconfig b/arch/arm/configs/tegra3_android_defconfig index fa637e81128b..6f3f056d4cb9 100644 --- a/arch/arm/configs/tegra3_android_defconfig +++ b/arch/arm/configs/tegra3_android_defconfig @@ -392,6 +392,8 @@ CONFIG_SND_SOC_TEGRA_MAX98088=y CONFIG_SND_SOC_TEGRA_TLV320AIC326X=y CONFIG_SND_SOC_TEGRA_RT5639=y CONFIG_SND_SOC_TEGRA_RT5640=y +CONFIG_SND_SOC_TLV320AIC326X=y +CONFIG_AIC3262_CODEC=y CONFIG_HID_SONY=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_DEVICEFS=y -- cgit v1.2.3 From ebc38db61f1d6407c761beea4b48252a613ed6a6 Mon Sep 17 00:00:00 2001 From: Manoj Gangwal Date: Wed, 22 Aug 2012 20:02:19 +0530 Subject: arm: tegra: E1239: Add TI aic326x support 1) Add latest TI aic326x codec driver support 2) Dmic support for TAI Bug 1034241 Change-Id: I8db5223fd203a4e8f93f159a9c654486831f08a1 Signed-off-by: Manoj Gangwal Reviewed-on: http://git-master/r/125265 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-enterprise.c | 45 ++++++++++++++++++++++++++++++++-- arch/arm/mach-tegra/board-enterprise.h | 7 +++++- 2 files changed, 49 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c index 498f8a176991..88c824761ebe 100644 --- a/arch/arm/mach-tegra/board-enterprise.c +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -38,6 +38,8 @@ #include #include #include +#include +#include #include #include @@ -210,6 +212,44 @@ static __initdata struct tegra_clk_init_table enterprise_clk_i2s4_table[] = { { NULL, NULL, 0, 0}, }; +static struct aic3262_gpio_setup aic3262_gpio[] = { + /* GPIO 1*/ + { + .used = 1, + .in = 0, + .value = AIC3262_GPIO1_FUNC_INT1_OUTPUT , + }, + /* GPIO 2*/ + { + .used = 1, + .in = 0, + .value = AIC3262_GPIO2_FUNC_ADC_MOD_CLK_OUTPUT, + }, + /* GPIO 1 */ + { + .used = 0, + }, + {// GPI2 + .used = 1, + .in = 1, + .in_reg = AIC3262_DMIC_INPUT_CNTL, + .in_reg_bitmask = AIC3262_DMIC_CONFIGURE_MASK, + .in_reg_shift = AIC3262_DMIC_CONFIGURE_SHIFT, + .value = AIC3262_DMIC_GPI2_LEFT_GPI2_RIGHT, + }, + {// GPO1 + .used = 0, + .value = AIC3262_GPO1_FUNC_DISABLED, + }, +}; + +static struct aic3262_pdata aic3262_codec_pdata = { + .gpio_irq = 1, + .gpio = aic3262_gpio, + .naudint_irq = TEGRA_GPIO_HP_DET, + .irq_base = AIC3262_CODEC_IRQ_BASE, +}; + static struct tegra_i2c_platform_data enterprise_i2c1_platform_data = { .adapter_nr = 0, .bus_count = 1, @@ -364,8 +404,9 @@ static struct i2c_board_info __initdata max98088_board_info = { }; static struct i2c_board_info __initdata enterprise_codec_aic326x_info = { - I2C_BOARD_INFO("aic3262-codec", 0x18), - .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_HP_DET), + I2C_BOARD_INFO("tlv320aic3262", 0x18), + .platform_data = &aic3262_codec_pdata, + .irq = TEGRA_GPIO_HP_DET, }; static struct i2c_board_info __initdata nfc_board_info = { diff --git a/arch/arm/mach-tegra/board-enterprise.h b/arch/arm/mach-tegra/board-enterprise.h index b77c3cae7346..e9bda707fed2 100644 --- a/arch/arm/mach-tegra/board-enterprise.h +++ b/arch/arm/mach-tegra/board-enterprise.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/board-enterprise.h * - * Copyright (c) 2011, NVIDIA Corporation. + * Copyright (c) 2012, NVIDIA Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -94,6 +94,11 @@ void enterprise_bpc_mgmt_init(void); #define ENT_TPS80031_IRQ_BASE TEGRA_NR_IRQS #define ENT_TPS80031_IRQ_END (ENT_TPS80031_IRQ_BASE + TPS80031_INT_NR) +/* AIC326X IRQs */ +/* Assuming TPS is the PMIC on Ent */ +#define AIC3262_CODEC_IRQ_BASE ENT_TPS80031_IRQ_END +#define AIC3262_CODEC_IRQ_END (AIC3262_CODEC_IRQ_BASE + 6) + /*****************Camera GPIOs ******************/ #define CAM_CSI_MUX_SEL_GPIO TEGRA_GPIO_PM3 #define CAM_CSI_MUX_SEL_REAR 1 -- cgit v1.2.3 From d3e0f5babd4ead87fd7172bd9d5681c54ca86242 Mon Sep 17 00:00:00 2001 From: Manoj Gangwal Date: Mon, 27 Aug 2012 20:14:03 +0530 Subject: arm: tegra: E1239: Fix LP0 audio stop issue Fix audio stop issue after resuming from lp0. Bug 1039326 Change-Id: Ieb586b614ffecc9d149213fbfd3cbb3198088725 Signed-off-by: Manoj Gangwal Reviewed-on: http://git-master/r/127562 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/board-enterprise.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c index 88c824761ebe..f3808a3b48fb 100644 --- a/arch/arm/mach-tegra/board-enterprise.c +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -245,9 +245,10 @@ static struct aic3262_gpio_setup aic3262_gpio[] = { static struct aic3262_pdata aic3262_codec_pdata = { .gpio_irq = 1, + .gpio_reset = TEGRA_GPIO_CODEC_RST, .gpio = aic3262_gpio, - .naudint_irq = TEGRA_GPIO_HP_DET, - .irq_base = AIC3262_CODEC_IRQ_BASE, + .naudint_irq = TEGRA_GPIO_HP_DET, + .irq_base = AIC3262_CODEC_IRQ_BASE, }; static struct tegra_i2c_platform_data enterprise_i2c1_platform_data = { -- cgit v1.2.3 From 794066c1c027693fa4ae96b51fa9aa4f9a9ba002 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 27 Aug 2012 12:22:07 -0700 Subject: arm: tegra: tai: correct gpio for voice call Bug 1031990 Change-Id: I9410bc0347544701a753287713f9537710e7533f Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/127620 Reviewed-by: Scott Peterson Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Michael Hsu Tested-by: Michael Hsu --- arch/arm/mach-tegra/board-enterprise-pinmux.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-pinmux.c b/arch/arm/mach-tegra/board-enterprise-pinmux.c index 71cdd143c88c..8a1a7194878e 100644 --- a/arch/arm/mach-tegra/board-enterprise-pinmux.c +++ b/arch/arm/mach-tegra/board-enterprise-pinmux.c @@ -727,8 +727,8 @@ static __initdata struct tegra_pingroup_config tai_pinmux_common[] = { DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PCC1, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB0, I2S4, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT), -- cgit v1.2.3 From a4e44614a5bae9e714ac99c43a6085194edb3c21 Mon Sep 17 00:00:00 2001 From: Kirill Artamonov Date: Tue, 21 Aug 2012 15:02:22 +0300 Subject: ARM: cache-l2x0: fix L2 maintenance for R3P1_50 Do flush and clear by set/way instead of by-way by enabling errata 727915 for pl310 revision R3P1_50. By-way maintenance doesn't work with enabled lp2_in_idle on Tegra3 platform using R3P1_50 revision of pl310. Debug register access causes hang when CONFIG_TRUSTED_FOUNDATIONS is defined. Don't access those regeisters if CONFIG_TRUSTED_FOUNDATIONS is defined. bug 983964 Signed-off-by: Kirill Artamonov Change-Id: I76a3a9ef9dbcf86140ee26752202bf25542144e6 Reviewed-on: http://git-master/r/125153 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy Reviewed-by: Antti Miettinen Tested-by: Antti Miettinen GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen Reviewed-by: Peter De Schrijver --- arch/arm/include/asm/hardware/cache-l2x0.h | 1 + arch/arm/mm/cache-l2x0.c | 7 ++++--- 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index fd04f24055fd..22ec488494da 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -79,6 +79,7 @@ #define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30 #define REV_PL310_R2P0 4 +#define REV_PL310_R3P1_50 7 #ifndef __ASSEMBLY__ extern void l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 0336d47c5dd4..972c7bd08a83 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -83,7 +83,8 @@ static inline void l2x0_inv_line(unsigned long addr) writel_relaxed(addr, base + L2X0_INV_LINE_PA); } -#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) +#if !defined(CONFIG_TRUSTED_FOUNDATIONS) && \ + (defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)) #define debug_writel(val) outer_cache.set_debug(val) @@ -161,7 +162,7 @@ static void l2x0_flush_all(void) unsigned long flags; #ifdef CONFIG_PL310_ERRATA_727915 - if (is_pl310_rev(REV_PL310_R2P0)) { + if (is_pl310_rev(REV_PL310_R2P0) || is_pl310_rev(REV_PL310_R3P1_50)) { l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_INV_LINE_IDX); return; } @@ -178,7 +179,7 @@ static void l2x0_clean_all(void) unsigned long flags; #ifdef CONFIG_PL310_ERRATA_727915 - if (is_pl310_rev(REV_PL310_R2P0)) { + if (is_pl310_rev(REV_PL310_R2P0) || is_pl310_rev(REV_PL310_R3P1_50)) { l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_LINE_IDX); return; } -- cgit v1.2.3 From 9b55075dfad2224545aef164f63869453face3fd Mon Sep 17 00:00:00 2001 From: Kirill Artamonov Date: Tue, 21 Aug 2012 15:02:22 +0300 Subject: ARM: tegra: enable errata 727915 for Tegra3 By-way maintenance doesn't reliably work with enabled lp2_in_idle on Tegra3 platform which uses R3P1_50 revision of pl310. Enable errata 727915 for Tegra3 to avoid system hang. Change-Id: Ia296c1d5b35b8f28353c15d1e4622686bc7d3beb Signed-off-by: Kirill Artamonov Reviewed-on: http://git-master/r/127225 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Juha Tukkinen --- arch/arm/mach-tegra/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index f4f4d58452ed..e90ff587cc44 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -67,6 +67,7 @@ config ARCH_TEGRA_3x_SOC select CPA select ARCH_HAS_SUSPEND_PAGETABLE select NVMAP_CACHE_MAINT_BY_SET_WAYS + select PL310_ERRATA_727915 help Support for NVIDIA Tegra 3 family of SoCs, based upon the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller -- cgit v1.2.3 From e3d92859c4351847a98e48746fb19d12fac16c6d Mon Sep 17 00:00:00 2001 From: Bob Johnston Date: Thu, 16 Aug 2012 10:52:14 -0400 Subject: E1853 BRINGUP Linux Snor: Micron Support Expanding NOR functionality to work with ADMUX and Burst mode for Micron Support in E1853. Bug 989919 Bug 966833 - Adding fields for picking MUX vs NONMUX and picking Async, Paging, Burst mode for reads - Added run time decision between them - 1853 specific settings for Async NOR - 1852 specific settings for NOR - 1853 NOR timings changed Reviewed-on: http://git-master/r/122286 (cherry picked from commit a242e7194c7de559d22fe5b275a8782086f10e50) Change-Id: I79de1d52d4c7199c83b380c2fa6d8cae6b35f09d Signed-off-by: Bob Johnston Reviewed-on: http://git-master/r/124946 Tested-by: Bob Johnston Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sumeet Gupta Reviewed-by: Varun Wadekar --- arch/arm/mach-tegra/board-e1853.c | 30 ++++++++++++++++++++++++++++++ arch/arm/mach-tegra/board-p1852.c | 8 ++++++-- 2 files changed, 36 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-e1853.c b/arch/arm/mach-tegra/board-e1853.c index cec5667fb95b..3b6d2bfc3d4c 100644 --- a/arch/arm/mach-tegra/board-e1853.c +++ b/arch/arm/mach-tegra/board-e1853.c @@ -355,6 +355,35 @@ static void e1853_usb_init(void) platform_device_register(&tegra_ehci3_device); } +static struct tegra_nor_platform_data e1853_nor_data = { + .flash = { + .map_name = "cfi_probe", + .width = 2, + }, + .chip_parms = { + .MuxMode = NorMuxMode_ADMux, + .BurstLength = NorBurstLength_CntBurst, + .ReadMode = NorReadMode_Async, + .ReadyActive = NorReadyActive_BeforeData, + /* FIXME: Need to use characterized value */ + .timing_default = { + .timing0 = 0xA0A05585, + .timing1 = 0x200A0406, + }, + .timing_read = { + .timing0 = 0xA0A05585, + .timing1 = 0x00050406, + }, + }, +}; + +static void e1853_nor_init(void) +{ + tegra_nor_device.resource[2].end = TEGRA_NOR_FLASH_BASE + SZ_64M - 1; + tegra_nor_device.dev.platform_data = &e1853_nor_data; + platform_device_register(&tegra_nor_device); +} + static void __init tegra_e1853_init(void) { tegra_init_board_info(); @@ -368,6 +397,7 @@ static void __init tegra_e1853_init(void) e1853_spi_init(); platform_add_devices(e1853_devices, ARRAY_SIZE(e1853_devices)); e1853_panel_init(); + e1853_nor_init(); e1853_pcie_init(); } diff --git a/arch/arm/mach-tegra/board-p1852.c b/arch/arm/mach-tegra/board-p1852.c index aefc21774a7d..4ff3eaf47899 100644 --- a/arch/arm/mach-tegra/board-p1852.c +++ b/arch/arm/mach-tegra/board-p1852.c @@ -1,6 +1,4 @@ /* - * arch/arm/mach-tegra/board-p1852.c - * * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -15,6 +13,8 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . * + * arch/arm/mach-tegra/board-p1852.c + * */ #include @@ -606,6 +606,10 @@ static struct tegra_nor_platform_data p1852_nor_data = { .width = 2, }, .chip_parms = { + .MuxMode = NorMuxMode_ADNonMux, + .ReadMode = NorReadMode_Page, + .PageLength = NorPageLength_8Word, + .ReadyActive = NorReadyActive_WithData, /* FIXME: Need to use characterized value */ .timing_default = { .timing0 = 0x30300263, -- cgit v1.2.3 From 6bc9afa39a1d2a0b2c909fb019ca49d848d96d63 Mon Sep 17 00:00:00 2001 From: Dongfang Shi Date: Thu, 9 Aug 2012 12:22:27 -0700 Subject: arm: tegra: p1852: set FPDLink latch clock edge Make parallel data strobed on rising clock edge For SKU2 MODS get correct CRC. Bug 995623 Change-Id: I70f4b87e781821cf4ff8370c17b79f5bea7dc55c Signed-off-by: Dongfang Shi Reviewed-on: http://git-master/r/121824 (cherry-pick from 5200d0f10b936e00dbc2a946eed8c2e48b039943) Reviewed-on: http://git-master/r/122537 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bob Johnston Reviewed-by: Nitin Kumbhar Reviewed-by: Varun Wadekar --- arch/arm/mach-tegra/board-p1852-panel.c | 190 ++++++++++++++++++-------------- 1 file changed, 106 insertions(+), 84 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-p1852-panel.c b/arch/arm/mach-tegra/board-p1852-panel.c index 970133d8a78e..8ca533175ea1 100644 --- a/arch/arm/mach-tegra/board-p1852-panel.c +++ b/arch/arm/mach-tegra/board-p1852-panel.c @@ -39,6 +39,15 @@ #define P1852_LVDS_SER1_ADDR 0xd #define P1852_LVDS_SER2_ADDR 0xc +#define LVDS_SER_REG_CONFIG_1 0x4 +#define LVDS_SER_REG_CONFIG_1_BKWD_OVERRIDE 3 +#define LVDS_SER_REG_CONFIG_1_BKWD 2 + +#define LVDS_SER_REG_DATA_PATH_CTRL 0x12 +#define LVDS_SER_REG_DATA_PATH_CTRL_PASS_RGB 6 + +#define LVDS_SER_REG_CONFIG_0 0x3 +#define LVDS_SER_REG_CONFIG_0_TRFB 0 /* RGB panel requires no special enable/disable */ static int p1852_panel_enable(void) @@ -51,15 +60,98 @@ static int p1852_panel_disable(void) return 0; } +static int ser_i2c_read(struct i2c_client *client, + u8 reg_addr, u8 *pval) +{ + struct i2c_msg msg[] = { + { + .addr = client->addr, + .flags = 0, + .len = 1, + .buf = ®_addr, + }, + { + .addr = client->addr, + .flags = I2C_M_RD, + .len = 1, + .buf = pval, + }, + }; + + return i2c_transfer(client->adapter, msg, 2); +} + +static int ser_i2c_write(struct i2c_client *client, + u8 reg_addr, u8 val) +{ + u8 buffer[] = {reg_addr, val}; + struct i2c_msg msg[] = { + { + .addr = client->addr, + .flags = 0, + .len = 2, + .buf = buffer, + }, + }; + + return i2c_transfer(client->adapter, msg, 1); +} + +static int lvds_ser_init(struct i2c_client *client, + bool is_fpdlinkII, + bool support_hdcp, + bool clk_rise_edge) +{ + u8 val; + int err = 0; + + /* intentional call make register & bus ready */ + ser_i2c_read(client, LVDS_SER_REG_CONFIG_1, &val); + + if (is_fpdlinkII) { + err = ser_i2c_read(client, LVDS_SER_REG_CONFIG_1, &val); + if (err < 0) + return err; + + val |= (1 << LVDS_SER_REG_CONFIG_1_BKWD_OVERRIDE); + val |= (1 << LVDS_SER_REG_CONFIG_1_BKWD); + + err = ser_i2c_write(client, LVDS_SER_REG_CONFIG_1, val); + if (err < 0) + return err; + } + else if (!support_hdcp) { + err = ser_i2c_read(client, LVDS_SER_REG_DATA_PATH_CTRL, &val); + if (err < 0) + return err; + + val |= (1 << LVDS_SER_REG_DATA_PATH_CTRL_PASS_RGB); + + err = ser_i2c_write(client, LVDS_SER_REG_DATA_PATH_CTRL, val); + if (err < 0) + return err; + } + + if (clk_rise_edge) { + err = ser_i2c_read(client, LVDS_SER_REG_CONFIG_0, &val); + if (err < 0) + return err; + + val |= (1 << LVDS_SER_REG_CONFIG_0_TRFB); + + err = ser_i2c_write(client, LVDS_SER_REG_CONFIG_0, val); + } + + return (err < 0 ? err : 0); +} + /* enable primary LVDS */ static int p1852_lvds_enable(void) { struct i2c_adapter *adapter; struct i2c_board_info info = {{0}}; static struct i2c_client *client; - struct i2c_msg msg[2]; - u8 cmd_buf[] = {0x4, 0}; - int status=-1; + int err = -1; /* Turn on serializer chip */ gpio_set_value(P1852_LVDS_ENA1, 1); @@ -76,47 +168,13 @@ static int p1852_lvds_enable(void) if (!client) pr_warning("%s: client is null\n", __func__); else { - msg[0].addr = P1852_LVDS_SER1_ADDR; - msg[0].flags = 0; - msg[0].len = 1; - msg[0].buf = &cmd_buf[0]; - - status = i2c_transfer(client->adapter, msg, 1); - /* ignore first write status */ - - msg[0].addr = P1852_LVDS_SER1_ADDR; - msg[0].flags = 0; - msg[0].len = 1; - msg[0].buf = &cmd_buf[0]; - - msg[1].addr = P1852_LVDS_SER1_ADDR; - msg[1].flags = I2C_M_RD; - msg[1].len = 1; - msg[1].buf = &cmd_buf[1]; - - status = i2c_transfer(client->adapter, msg, 2); - if (status < 0) { - pr_warning("%s: i2c failed, addr=0x%x, reg=%d, ret=%d\n", - __func__, P1852_LVDS_SER1_ADDR, cmd_buf[0], status); - } - else { - cmd_buf[1] |= (1 << 2); - cmd_buf[1] |= (1 << 3); - - msg[0].addr = P1852_LVDS_SER1_ADDR; - msg[0].flags = 0; - msg[0].len = 2; - msg[0].buf = &cmd_buf[0]; - - status = i2c_transfer(client->adapter, msg, 1); - if (status < 0) { - pr_warning("%s: i2c err, addr=0x%x, reg=%d, ret=%d\n", - __func__, P1852_LVDS_SER1_ADDR, cmd_buf[0], status); - } - } + err = lvds_ser_init(client, + true, /* is_fpdlinkII*/ + false, /* support_hdcp */ + true); /* clk_rise_edge */ } } - return (status<0 ? status : 0); + return err; } /* Disable primary LVDS */ @@ -134,9 +192,7 @@ static int p1852_lvds2_enable(void) struct i2c_adapter *adapter; struct i2c_board_info info = {{0}}; static struct i2c_client *client; - struct i2c_msg msg[2]; - u8 cmd_buf[] = {0x4, 0}; - int status=-1; + int err = -1; /* Enable HDMI HPD */ /* need nothing here */ @@ -159,47 +215,13 @@ static int p1852_lvds2_enable(void) if (!client) pr_warning("%s: client is null\n", __func__); else { - msg[0].addr = P1852_LVDS_SER2_ADDR; - msg[0].flags = 0; - msg[0].len = 1; - msg[0].buf = &cmd_buf[0]; - - status = i2c_transfer(client->adapter, msg, 1); - /* ignore first write status */ - - msg[0].addr = P1852_LVDS_SER2_ADDR; - msg[0].flags = 0; - msg[0].len = 1; - msg[0].buf = &cmd_buf[0]; - - msg[1].addr = P1852_LVDS_SER2_ADDR; - msg[1].flags = I2C_M_RD; - msg[1].len = 1; - msg[1].buf = &cmd_buf[1]; - - status = i2c_transfer(client->adapter, msg, 2); - if (status < 0) { - pr_warning("%s: i2c failed, addr=0x%x, reg=%d, ret=%d\n", - __func__, P1852_LVDS_SER2_ADDR, cmd_buf[0], status); - } - else { - cmd_buf[1] |= (1 << 2); - cmd_buf[1] |= (1 << 3); - - msg[0].addr = P1852_LVDS_SER2_ADDR; - msg[0].flags = 0; - msg[0].len = 2; - msg[0].buf = &cmd_buf[0]; - - status = i2c_transfer(client->adapter, msg, 1); - if (status < 0) { - pr_warning("%s: i2c err, addr=0x%x, reg=%d, ret=%d\n", - __func__, P1852_LVDS_SER2_ADDR, cmd_buf[0], status); - } - } + err = lvds_ser_init(client, + true, /* is_fpdlinkII*/ + false, /* support_hdcp */ + true); /* clk_rise_edge */ } } - return (status<0 ? status : 0); + return err; } /* Disable secondary LVDS */ -- cgit v1.2.3 From 2b7077e02ee6cd9d8326cb0ef2cb6a721bfc01a6 Mon Sep 17 00:00:00 2001 From: Christopher Freeman Date: Fri, 24 Aug 2012 14:04:29 -0700 Subject: video: tegra: cardhu: Default bpp from hardware This patch adds: 1. A kernel config option that hints to DC driver to use the current value of the color depth register as the default for initializing the FB driver. 2. Checks to see if DC is enabled before reading off the color depth register in tegra_dc_probe. Change-Id: I852cc1328fcf42f33052f46b86d753e691744329 Signed-off-by: Christopher Freeman Reviewed-on: http://git-master/r/127297 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/Kconfig | 9 +++++++++ arch/arm/mach-tegra/board-cardhu-panel.c | 8 ++++++++ 2 files changed, 17 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index e90ff587cc44..b9627372564f 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -578,3 +578,12 @@ config TEGRA_SKIN_THROTTLE Enable throttling to control the temperature of the skin/case of the device. endif + +config TEGRA_DC_USE_HW_BPP + bool "Default Bits Per Pixel value from tegra DC hardware" + depends on TEGRA_DC + default n + help + Programs platform data to inform DC driver to use current + hardware value for bits per pixel setting. Useful for + preserving and displaying framebuffer content from bootloader. diff --git a/arch/arm/mach-tegra/board-cardhu-panel.c b/arch/arm/mach-tegra/board-cardhu-panel.c index 530fcfc4ba09..d7101af55712 100644 --- a/arch/arm/mach-tegra/board-cardhu-panel.c +++ b/arch/arm/mach-tegra/board-cardhu-panel.c @@ -678,7 +678,11 @@ static struct tegra_fb_data cardhu_fb_data = { .win = 0, .xres = 1366, .yres = 768, +#ifdef CONFIG_TEGRA_DC_USE_HW_BPP + .bits_per_pixel = -1, +#else .bits_per_pixel = 32, +#endif .flags = TEGRA_FB_FLIP_ON_PROBE, }; @@ -686,7 +690,11 @@ static struct tegra_fb_data cardhu_hdmi_fb_data = { .win = 0, .xres = 640, .yres = 480, +#ifdef CONFIG_TEGRA_DC_USE_HW_BPP + .bits_per_pixel = -1, +#else .bits_per_pixel = 32, +#endif .flags = TEGRA_FB_FLIP_ON_PROBE, }; -- cgit v1.2.3 From fb1ba1236a57894c13b92d0497a9dd23d02f6ed9 Mon Sep 17 00:00:00 2001 From: Simone Willett Date: Wed, 22 Aug 2012 13:58:52 -0700 Subject: Revert "Revert "ARM: tegra: enterprise: update memory timings"" This reverts commit 0405128605ed7a858aecb8fb9aaaf80e0e44c4b8 Change-Id: I3a0ee9b0079b884d53c43323e21b472a40c31bb7 Reviewed-on: http://git-master/r/125323 Reviewed-by: Simone Willett Tested-by: Simone Willett Reviewed-by: Raymond Poudrier --- arch/arm/mach-tegra/board-enterprise-memory.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-memory.c b/arch/arm/mach-tegra/board-enterprise-memory.c index 36a8264c2a21..1fc0d3c3fddd 100644 --- a/arch/arm/mach-tegra/board-enterprise-memory.c +++ b/arch/arm/mach-tegra/board-enterprise-memory.c @@ -116,7 +116,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000164, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00050001, /* MC_EMEM_ARB_CFG */ + 0x00050002, /* MC_EMEM_ARB_CFG */ 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -236,7 +236,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800001c2, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00020001, /* MC_EMEM_ARB_CFG */ + 0x00030003, /* MC_EMEM_ARB_CFG */ 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -356,7 +356,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000287, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00010001, /* MC_EMEM_ARB_CFG */ + 0x00010003, /* MC_EMEM_ARB_CFG */ 0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -476,7 +476,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000001, /* MC_EMEM_ARB_CFG */ + 0x00000003, /* MC_EMEM_ARB_CFG */ 0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -596,7 +596,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000003, /* MC_EMEM_ARB_CFG */ + 0x00000006, /* MC_EMEM_ARB_CFG */ 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ @@ -716,7 +716,7 @@ static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000ce6, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000006, /* MC_EMEM_ARB_CFG */ + 0x0000000c, /* MC_EMEM_ARB_CFG */ 0xc0000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ -- cgit v1.2.3 From fee255cde01510e139d02b87473786271d1081ae Mon Sep 17 00:00:00 2001 From: Karthik Ramakrishnan Date: Mon, 13 Aug 2012 19:09:16 -0700 Subject: arm: tegra: Set Core to 0.95V in LP1 When the device prepares for LP1, the Core voltage is set to the highest value(1.2V for Enterprise and Kai, and 1.3V for AP37 and Cardhu). This is to set for some of the driver suspend along the sequence need a higher emc frequency and thus a higher Core voltage. Since the sequence of drivers suspend depends on the sequence of their registration in the table, which in turn is platform-dependent, there is no right place in the LP1 entry path where the Core voltage can be set to a lower voltage. Hence, the Core voltage remains high in LP1 resulting in higher power. Thus, the only safe location where the Core voltage can be lowered is once all the drivers are suspended and the DRAM is set in self-refresh, at the final point just before the system is suspended in the IRAM code. This location at the assembly code ensures that no other module will be running and thus that nothing will require a higher core voltage. The Core is set to the lowest possible value since nothing requires it. It is then restored to the highest voltage as soon as the LP1 resume code is started so that all drivers are resumed safely. At the execution point in IRAM during LP1 suspend path, even the I2C clocks are gated. They must be reset first and then the I2C transaction is performed. An I2C transaction involves 4 bytes of data, to send the slave address, the Core voltage register address and 2 bytes of data which has the value to set the voltage(the second byte is not required for this transaction). Once these registers are set, the I2C transaction is performed by setting the I2C transaction register to 0xA02. After sending the I2C transaction, we wait for about 250us to check the status of the transaction and if not updated, wait for more time to check again. If after 2ms and the transaction fails to register, the transaction is aborted and the device is allowed to enter at high voltage. Since the failure rate of I2C transaction is very low at this point in execution where there will be no conflicts in the bus, it is okay to have Core high for some of the LP1 cycles. However, it is unacceptable for the I2C transaction to fail on the way from LP1 resume since the device cannot come up with a lower Core voltage. In this case, the transaction is retried again and again till it is successful. There is no way but to keep trying as the device would fail to resume with Core at 0.95V. Each platform(or each PMU) has different values for the I2C transaction ie. slave address, Core voltage register and the value to set the voltage. For the device in IRAM, it cannot access anything in SDRAM memory, these values needs to be pushed to IRAM memory before the device starts execution in IRAM. This is done during initialization of suspend code when it picks values from the board files and copies it to IRAM part of code, before the whole memory is copied to IRAM. This new feature is controlled by a KConfig variable TEGRA_LP1_950 which should be enabled once the board file of the device is updated with the right values. The device hangs when it does not have the right values for the I2C transaction. With this change in Core, LP1 power is reduced by 12mW in Enterprise, 20mW in AP37 and about 24mW in Kai. Bug 1035684 Change-Id: I4318c66fd70ab227ef0786d6a13286e020e4541d Signed-off-by: Karthik Ramakrishnan (cherry picked from commit ab476f287376fd0ae51a9f298659f5eba19f0296) Reviewed-on: http://git-master/r/124779 Reviewed-by: Lokesh Pathak Tested-by: Lokesh Pathak --- arch/arm/mach-tegra/Kconfig | 7 ++ arch/arm/mach-tegra/pm.c | 15 +++++ arch/arm/mach-tegra/pm.h | 8 +++ arch/arm/mach-tegra/sleep-t3.S | 150 ++++++++++++++++++++++++++++++++++++++++- arch/arm/mach-tegra/sleep.h | 40 +++++++++++ 5 files changed, 219 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index b9627372564f..422ad20bb094 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -577,6 +577,13 @@ config TEGRA_SKIN_THROTTLE help Enable throttling to control the temperature of the skin/case of the device. + +config TEGRA_LP1_950 + bool "LP1 low core voltage" + default n + depends on ARCH_TEGRA_3x_SOC + help + Enable support for LP1 Core voltage to set to lowest endif config TEGRA_DC_USE_HW_BPP diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index d251e57626aa..2cdfdfe6f43d 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -1186,6 +1186,21 @@ out: plat->suspend_mode = TEGRA_SUSPEND_LP2; } +#ifdef CONFIG_TEGRA_LP1_950 + if (pdata->lp1_lowvolt_support) { + u32 lp1_core_lowvolt, lp1_core_highvolt; + memcpy(tegra_lp1_register_pmuslave_addr(), &pdata->pmuslave_addr, 4); + memcpy(tegra_lp1_register_i2c_base_addr(), &pdata->i2c_base_addr, 4); + + lp1_core_lowvolt = 0; + lp1_core_lowvolt = (pdata->lp1_core_volt_low << 8) | pdata->core_reg_addr; + memcpy(tegra_lp1_register_core_lowvolt(), &lp1_core_lowvolt, 4); + + lp1_core_highvolt = 0; + lp1_core_highvolt = (pdata->lp1_core_volt_high << 8) | pdata->core_reg_addr; + memcpy(tegra_lp1_register_core_highvolt(), &lp1_core_highvolt, 4); + } +#endif /* !!!FIXME!!! THIS IS TEGRA2 ONLY */ /* Initialize scratch registers used for CPU LP2 synchronization */ writel(0, pmc + PMC_SCRATCH37); diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index b78e9b1abc00..5ea2b7f843a2 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -65,6 +65,14 @@ struct tegra_suspend_platform_data { /* lp_state = 0 for LP0 state, 1 for LP1 state, 2 for LP2 state */ void (*board_resume)(int lp_state, enum resume_stage stg); unsigned int cpu_resume_boost; /* CPU frequency resume boost in kHz */ +#ifdef CONFIG_TEGRA_LP1_950 + bool lp1_lowvolt_support; + unsigned int i2c_base_addr; + unsigned int pmuslave_addr; + unsigned int core_reg_addr; + unsigned int lp1_core_volt_low; + unsigned int lp1_core_volt_high; +#endif }; /* clears io dpd settings before kernel code */ diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S index 23e96c605b96..4ee73d581a08 100644 --- a/arch/arm/mach-tegra/sleep-t3.S +++ b/arch/arm/mach-tegra/sleep-t3.S @@ -95,6 +95,16 @@ #define PMC_PLLM_WB0_OVERRIDE 0x1dc #define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4 +#define CLK_RESET_CLK_ENB_H_SET 0x328 +#define CLK_RESET_CLK_ENB_H_CLR 0x32c +#define CLK_RESET_CLK_RST_DEV_H_SET 0x308 +#define CLK_RESET_CLK_RST_DEV_H_CLR 0x30c + +#define I2C_CNFG 0x0 +#define I2C_ADDR0 0x4 +#define I2C_DATA1 0xc +#define I2C_DATA2 0x10 +#define I2C_STATUS 0x1c #define MSELECT_CLKM (0x3 << 30) @@ -348,6 +358,66 @@ ENTRY(tegra3_lp1_reset) mov32 r4, ((1<<28) | (8)) @ burst policy is PLLX str r4, [r0, #CLK_RESET_CCLK_BURST] +#ifdef CONFIG_TEGRA_LP1_950 +lp1_voltset: + /* Restore the Core voltage to high on LP1 resume */ + /* Reset(Enable/Disable) the DVC-I2C Controller*/ + mov r1, #(1 << 15) + str r1, [r0, #CLK_RESET_CLK_RST_DEV_H_SET] + + /* Wait for 2us */ + mov32 r7, TEGRA_TMRUS_BASE + wait_for_us r1, r7, r9 + add r1, r1, #2 + wait_until r1, r7, r9 + + mov r1, #(1 << 15) + str r1, [r0, #CLK_RESET_CLK_RST_DEV_H_CLR] + + /* Enable the DVC-I2C Controller */ + mov r1, #(1 << 15) + str r1, [r0, #CLK_RESET_CLK_ENB_H_SET] + + + /* Same I2C transaction protocol as suspend */ + ldr r1, lp1_register_pmuslave_addr + cmp r1, #0 + beq lp1_voltskip_resume + + ldr r4, lp1_register_i2c_base_addr + str r1, [r4, #I2C_ADDR0] + + mov32 r1, 0x2 + str r1, [r4, #I2C_CNFG] + + ldr r1, lp1_register_core_highvolt + str r1, [r4, #I2C_DATA1] + + mov32 r1, 0 + str r1, [r4, #I2C_DATA2] + + mov32 r1, 0xA02 + str r1, [r4, #I2C_CNFG] + + wait_for_us r1, r7, r9 + mov32 r3, 0x7D0 /* Wait for 2ms and try transaction again */ + add r0, r1, r3 +loop_i2c_status_resume: + add r1, r1, #0xFA /* Check status every 250us */ + wait_until r1, r7, r9 + cmp r0, r1 + beq lp1_voltset + + ldr r3, [r4, #I2C_STATUS] + cmp r3, #0 + bne loop_i2c_status_resume + +lp1_voltskip_resume: + /* Disable the DVC-I2C Controller */ + mov r0, #(1 << 15) + str r0, [r5, #CLK_RESET_CLK_ENB_H_CLR] +#endif + #if defined (CONFIG_CACHE_L2X0) /* power up L2 */ ldr r0, [r2, #PMC_PWRGATE_STATUS] @@ -492,6 +562,21 @@ tegra3_sdram_pad_address: tegra3_sdram_pad_size: .word tegra3_sdram_pad_address - tegra3_sdram_pad_save +#ifdef CONFIG_TEGRA_LP1_950 + .globl lp1_register_pmuslave_addr + .globl lp1_register_i2c_base_addr + .globl lp1_register_core_lowvolt + .globl lp1_register_core_highvolt +lp1_register_pmuslave_addr: + .word 0 +lp1_register_i2c_base_addr: + .word 0 +lp1_register_core_lowvolt: + .word 0 +lp1_register_core_highvolt: + .word 0 +#endif + /* * tegra3_tear_down_core * @@ -526,9 +611,72 @@ tegra3_cpu_clk32k: str r0, [r4, #PMC_PLLM_WB0_OVERRIDE] mov pc, lr +lp1_clocks_prepare: + /* Prepare to set the Core to the lowest voltage if supported. + * Start by setting the I2C clocks to make the I2C transfer */ +#ifdef CONFIG_TEGRA_LP1_950 + /* Set up the PWR I2C GPIOs with the right masks*/ + + /* Reset(Set/Clr) the DVC-I2C Controller*/ + mov r0, #(1 << 15) + str r0, [r5, #CLK_RESET_CLK_RST_DEV_H_SET] + + /* Wait for 2us */ + wait_for_us r1, r7, r9 + mov32 r0, 0x7D0 + add r1, r1, r0 + wait_until r1, r7, r9 + + mov r0, #(1 << 15) + str r0, [r5, #CLK_RESET_CLK_RST_DEV_H_CLR] + + /* Enable the DVC-I2C Controller */ + mov r0, #(1 << 15) + str r0, [r5, #CLK_RESET_CLK_ENB_H_SET] + + /* I2C transfer protocol: + * 4 packets: Slaveaddr + WriteConfigure + Data1 + Data2 */ + ldr r0, lp1_register_pmuslave_addr + cmp r0, #0 + beq lp1_volt_skip + ldr r1, lp1_register_i2c_base_addr + str r0, [r1, #I2C_ADDR0] + + mov32 r0, 0x2 + str r0, [r1, #I2C_CNFG] + + ldr r0, lp1_register_core_lowvolt + str r0, [r1, #I2C_DATA1] + + mov32 r0, 0 + str r0, [r1, #I2C_DATA2] + + /* Send I2C transaction */ + mov32 r0, 0xA02 + str r0, [r1, #I2C_CNFG] + + /* Check the transaction status before proceeding */ + wait_for_us r2, r7, r9 + mov32 r3, 0x7D0 /* Wait for 2ms for I2C transaction */ + add r3, r2, r3 +loop_i2c_status_suspend: + add r2, r2, #0xFA /* Check status every 250us */ + cmp r3, r2 + beq lp1_volt_skip /* Waited for 2ms, I2C transaction didn't take place */ + wait_until r2, r7, r9 + + ldr r0, [r1, #I2C_STATUS] + cmp r0, #0 + bne loop_i2c_status_suspend +lp1_volt_skip: + + /* Disable the DVC-I2C Controller */ + mov r0, #(1 << 15) + str r0, [r5, #CLK_RESET_CLK_ENB_H_CLR] + +#endif /* start by jumping to clkm to safely disable PLLs, then jump * to clks */ -lp1_clocks_prepare: mov r0, #(1 << 28) str r0, [r5, #CLK_RESET_SCLK_BURST] str r0, [r5, #CLK_RESET_CCLK_BURST] diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index c57399985ecd..48b2bb8cfdb2 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -223,6 +223,10 @@ void tegra2_sleep_wfi(unsigned long v2p); #else extern unsigned int tegra3_iram_start; extern unsigned int tegra3_iram_end; +extern unsigned int lp1_register_pmuslave_addr; +extern unsigned int lp1_register_i2c_base_addr; +extern unsigned int lp1_register_core_lowvolt; +extern unsigned int lp1_register_core_highvolt; void tegra3_sleep_core(unsigned long v2p); void tegra3_sleep_cpu_secondary(unsigned long v2p); void tegra3_hotplug_shutdown(void); @@ -245,5 +249,41 @@ static inline void *tegra_iram_end(void) return &tegra3_iram_end; #endif } + +static inline void *tegra_lp1_register_pmuslave_addr(void) +{ +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + return NULL; +#else + return &lp1_register_pmuslave_addr; +#endif +} + +static inline void *tegra_lp1_register_i2c_base_addr(void) +{ +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + return NULL; +#else + return &lp1_register_i2c_base_addr; +#endif +} + +static inline void *tegra_lp1_register_core_lowvolt(void) +{ +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + return NULL; +#else + return &lp1_register_core_lowvolt; +#endif +} + +static inline void *tegra_lp1_register_core_highvolt(void) +{ +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + return NULL; +#else + return &lp1_register_core_highvolt; +#endif +} #endif #endif -- cgit v1.2.3 From a495f9b4003aa646c2a85713239a12f317c98892 Mon Sep 17 00:00:00 2001 From: Karthik Ramakrishnan Date: Fri, 10 Aug 2012 17:24:20 -0700 Subject: arm: tegra: Board files settings for LP1 0.95V CoreV Set the register values for each of the board files to keep the Core voltage to 0.95V in LP1. This change is only for those platforms where LP1 is supported. Enterprise and Kai are the main platforms for this change. There is no support for Cardhu for LP1 and so is left blank and the feature will be skipped for Cardhu platforms, except for AP37. AP37 with a PM269 board needs this change and so Cardhu board file is updated with the values specific to AP37. This change is part of the feature to set VCore to 0.95V Refer to http://git-master/r/124135 for more details Bug 1035684 Change-Id: I6d1d984b0e7968b441cebbc37705c25647a4a85a Signed-off-by: Karthik Ramakrishnan (cherry picked from commit b46921e475bd95e729896a6763bc94df1e03ee4a) Reviewed-on: http://git-master/r/124780 Reviewed-by: Lokesh Pathak Tested-by: Lokesh Pathak --- arch/arm/mach-tegra/board-cardhu-power.c | 21 +++++++++++++++++++++ arch/arm/mach-tegra/board-enterprise-power.c | 8 ++++++++ arch/arm/mach-tegra/board-kai-power.c | 8 ++++++++ 3 files changed, 37 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-power.c b/arch/arm/mach-tegra/board-cardhu-power.c index 4f96c5cc5d05..e76cbc458914 100644 --- a/arch/arm/mach-tegra/board-cardhu-power.c +++ b/arch/arm/mach-tegra/board-cardhu-power.c @@ -1134,15 +1134,25 @@ static struct tegra_suspend_platform_data cardhu_suspend_data = { .cpu_lp2_min_residency = 2000, .board_suspend = cardhu_board_suspend, .board_resume = cardhu_board_resume, +#ifdef CONFIG_TEGRA_LP1_950 + .lp1_lowvolt_support = false, + .i2c_base_addr = 0, + .pmuslave_addr = 0, + .core_reg_addr = 0, + .lp1_core_volt_low = 0, + .lp1_core_volt_high = 0, +#endif }; int __init cardhu_suspend_init(void) { struct board_info board_info; struct board_info pmu_board_info; + struct board_info display_board_info; tegra_get_board_info(&board_info); tegra_get_pmu_board_info(&pmu_board_info); + tegra_get_display_board_info(&display_board_info); /* For PMU Fab A03, A04 and A05 make core_pwr_req to high */ if ((pmu_board_info.fab == BOARD_FAB_A03) || @@ -1170,6 +1180,17 @@ int __init cardhu_suspend_init(void) tegra_disable_wake_source(TEGRA_WAKE_USB1_VBUS); break; case BOARD_PM269: +#ifdef CONFIG_TEGRA_LP1_950 + /* AP37 board supports the LP1_950mV feature */ + if (is_display_board_dsi(display_board_info.board_id)) { + cardhu_suspend_data.lp1_lowvolt_support = true; + cardhu_suspend_data.i2c_base_addr = TEGRA_I2C5_BASE; + cardhu_suspend_data.pmuslave_addr = 0xC0; + cardhu_suspend_data.core_reg_addr = 0x03; + cardhu_suspend_data.lp1_core_volt_low = 0x2D; + cardhu_suspend_data.lp1_core_volt_high = 0x50; + } +#endif case BOARD_PM305: case BOARD_PM311: break; diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index 7ea2095e6622..b7fd3654f1da 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -779,6 +779,14 @@ static struct tegra_suspend_platform_data enterprise_suspend_data = { .sysclkreq_high = true, .board_suspend = enterprise_board_suspend, .board_resume = enterprise_board_resume, +#ifdef CONFIG_TEGRA_LP1_950 + .lp1_lowvolt_support = true, + .i2c_base_addr = TEGRA_I2C5_BASE, + .pmuslave_addr = 0x24, + .core_reg_addr = 0x5B, + .lp1_core_volt_low = 0x1D, + .lp1_core_volt_high = 0x33, +#endif }; static void enterprise_init_deep_sleep_mode(void) diff --git a/arch/arm/mach-tegra/board-kai-power.c b/arch/arm/mach-tegra/board-kai-power.c index 6c66f1d2bbe9..027d97458dd3 100644 --- a/arch/arm/mach-tegra/board-kai-power.c +++ b/arch/arm/mach-tegra/board-kai-power.c @@ -614,6 +614,14 @@ static struct tegra_suspend_platform_data kai_suspend_data = { .cpu_lp2_min_residency = 2000, .board_suspend = kai_board_suspend, .board_resume = kai_board_resume, +#ifdef CONFIG_TEGRA_LP1_950 + .lp1_lowvolt_support = true, + .i2c_base_addr = TEGRA_I2C5_BASE, + .pmuslave_addr = 0x78, + .core_reg_addr = 0x17, + .lp1_core_volt_low = 0x0C, + .lp1_core_volt_high = 0x20, +#endif }; int __init kai_suspend_init(void) -- cgit v1.2.3 From 9c153df4f3b2ef23622ae3c1807f1e207cefd49b Mon Sep 17 00:00:00 2001 From: Karthik Ramakrishnan Date: Fri, 10 Aug 2012 17:33:20 -0700 Subject: arm: tegra: Enable LP1_950 config Enable LP1 Core voltage settings to 950mV The feature is added in the below change. Refer to http://git-master/r/#change,124135 for more details. Bug 1035684 Change-Id: I922efff17797f4666fd6ed069a8523c164445842 Signed-off-by: Karthik Ramakrishnan (cherry picked from commit 0f5d34db547ca6bfb9c0bae0b0048f58ba71c833) Reviewed-on: http://git-master/r/124781 Reviewed-by: Lokesh Pathak Tested-by: Lokesh Pathak --- arch/arm/configs/tegra3_android_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/tegra3_android_defconfig b/arch/arm/configs/tegra3_android_defconfig index 6f3f056d4cb9..39a511f377e1 100644 --- a/arch/arm/configs/tegra3_android_defconfig +++ b/arch/arm/configs/tegra3_android_defconfig @@ -40,6 +40,7 @@ CONFIG_TEGRA_USB_MODEM_POWER=y CONFIG_TEGRA_BB_XMM_POWER=y CONFIG_TEGRA_BB_XMM_POWER2=m CONFIG_TEGRA_PLLM_RESTRICTED=y +CONFIG_TEGRA_LP1_950=y CONFIG_ARM_ERRATA_742230=y CONFIG_ARM_ERRATA_743622=y CONFIG_ARM_ERRATA_751472=y -- cgit v1.2.3 From b9b3cf7d4369dffac20ae9cfa0f0426feeb98490 Mon Sep 17 00:00:00 2001 From: Wen Yi Date: Wed, 8 Aug 2012 11:36:04 -0700 Subject: arm: cardhu: correct EMEM_ARB_CFG in emc dfs table The memory frequencies 266.5mhz and 437mhz have incorrect EMEM_ARB_CFG set in emc table of Samsung part. That resulted in emc scaling completely disabled and emc runs at 533mhz all time. The settings have been corrected to 0x00000008 and 0x0000000D. Bug 1030392 Bug 1039060 Reviewed-on: http://git-master/r/122163 (cherry picked from commit f691268c138b9ed31b3867b049e64c121ecb188e) Change-Id: I13f89c19af5391743aeba348f4a3ca4a73307bdf Signed-off-by: Wen Yi Reviewed-on: http://git-master/r/127429 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Raymond Poudrier Reviewed-by: Bharat Nihalani Tested-by: Sanjay Singh Rawat --- arch/arm/mach-tegra/board-cardhu-memory.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-memory.c b/arch/arm/mach-tegra/board-cardhu-memory.c index 33a66053ee45..305899f664e4 100644 --- a/arch/arm/mach-tegra/board-cardhu-memory.c +++ b/arch/arm/mach-tegra/board-cardhu-memory.c @@ -4794,7 +4794,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000dff, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000006, /* MC_EMEM_ARB_CFG */ + 0x0000000d, /* MC_EMEM_ARB_CFG */ 0xc000004f, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ -- cgit v1.2.3 From fdf01c32a988868681c25259b002c421a2183bf7 Mon Sep 17 00:00:00 2001 From: Wen Yi Date: Mon, 27 Aug 2012 14:44:13 +0530 Subject: arm: cardhu: change parameters for emc 266.5mhz The EmcTclkStable is set to 0x00000004 and McEmemArbOutStandingReq is set to 0xc0000030 Bug 1030392 Bug 1039060 Reviewed-on: http://git-master/r/122302 (cherry picked from commit a3a1d1797e310d61204256af8be995f9396c22e7) Change-Id: Ic65334a6573582ae99d05a8f6f8290096755827e Signed-off-by: Wen Yi Reviewed-on: http://git-master/r/127458 Reviewed-by: Lokesh Pathak Tested-by: Lokesh Pathak --- arch/arm/mach-tegra/board-cardhu-memory.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-memory.c b/arch/arm/mach-tegra/board-cardhu-memory.c index 305899f664e4..4ec8839c44f6 100644 --- a/arch/arm/mach-tegra/board-cardhu-memory.c +++ b/arch/arm/mach-tegra/board-cardhu-memory.c @@ -4619,7 +4619,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = { 0x00000004, /* EMC_TCKE */ 0x0000000e, /* EMC_TFAW */ 0x00000006, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ + 0x00000004, /* EMC_TCLKSTABLE */ 0x00000002, /* EMC_TCLKSTOP */ 0x00000455, /* EMC_TREFBW */ 0x00000000, /* EMC_QUSE_EXTRA */ @@ -4674,8 +4674,8 @@ static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = { 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800008ee, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000004, /* MC_EMEM_ARB_CFG */ - 0x80000030, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000008, /* MC_EMEM_ARB_CFG */ + 0xc0000030, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ 0x00000008, /* MC_EMEM_ARB_TIMING_RC */ -- cgit v1.2.3 From cd9aa0af4b0e5e2e1e1cb50fb009c7d945206bec Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 28 Aug 2012 15:12:14 -0700 Subject: arm: tegra: config: Add Tai Bug 1002637 Change-Id: I33d38ab3a5395f85564ef9a3282db152b4d79113 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/127974 Reviewed-by: Lokesh Pathak Tested-by: Lokesh Pathak --- arch/arm/configs/tegra3_android_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/tegra3_android_defconfig b/arch/arm/configs/tegra3_android_defconfig index 39a511f377e1..c738192e967d 100644 --- a/arch/arm/configs/tegra3_android_defconfig +++ b/arch/arm/configs/tegra3_android_defconfig @@ -28,6 +28,7 @@ CONFIG_ARCH_TEGRA_3x_SOC=y CONFIG_TEGRA_PCI=y CONFIG_MACH_CARDHU=y CONFIG_MACH_TEGRA_ENTERPRISE=y +CONFIG_MACH_TAI=y CONFIG_MACH_KAI=y CONFIG_TEGRA_PWM=y CONFIG_TEGRA_EMC_SCALING_ENABLE=y -- cgit v1.2.3 From 5be4f2338b61cb876d6917b5f5e5fb275eaefc8b Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 28 Aug 2012 15:20:57 -0700 Subject: ARM: tegra: tai: Add tai machine num http://www.arm.linux.org.uk/developer/machines/list.php?id=4311 Bug 1002637 Change-Id: Id52214c1780294e4e4a6607b954c05e9be950fdd Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/127978 Reviewed-by: Lokesh Pathak Tested-by: Lokesh Pathak --- arch/arm/mach-tegra/Kconfig | 6 ++++++ arch/arm/tools/mach-types | 3 ++- 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 422ad20bb094..617f08bd54bd 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -203,6 +203,12 @@ config MACH_TEGRA_ENTERPRISE help Support for NVIDIA Enterprise development platform +config MACH_TAI + bool "Tai board" + depends on MACH_TEGRA_ENTERPRISE + help + Support for NVIDIA Tai development platform + config MACH_KAI bool "Kai board" depends on ARCH_TEGRA_3x_SOC diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index e15301d86c68..978683edfead 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -1115,6 +1115,7 @@ ubisys_p9d_evp MACH_UBISYS_P9D_EVP UBISYS_P9D_EVP 3493 atdgp318 MACH_ATDGP318 ATDGP318 3494 tegra_enterprise MACH_TEGRA_ENTERPRISE TEGRA_ENTERPRISE 3512 p1852 MACH_P1852 P1852 3651 -kai MACH_KAI KAI 3897 +kai MACH_KAI KAI 3897 p852 MACH_P852 P852 3667 e1853 MACH_E1853 E1853 4241 +tai MACH_TAI TAI 4311 -- cgit v1.2.3 From 6bf311e63071e172c56f3e18475ad06c63cb8d30 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 28 Aug 2012 16:10:58 -0700 Subject: arm: tegra: tai: keep smps4 ON Bug 1029431 Change-Id: I79ba7e363feeaec86912445ce005ea65a3960718 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/127994 Reviewed-by: Lokesh Pathak Tested-by: Lokesh Pathak --- arch/arm/mach-tegra/board-enterprise-power.c | 39 ++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index b7fd3654f1da..c154841eba93 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -140,6 +140,13 @@ static struct regulator_consumer_supply tps80031_smps4_supply_a03[] = { REGULATOR_SUPPLY("vddf_core_emmc", NULL), }; +static struct regulator_consumer_supply tps80031_smps4_supply_tai[] = { + REGULATOR_SUPPLY("vddio_sdmmc_2v85", NULL), + REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL), + REGULATOR_SUPPLY("vdd_ddr_rx", NULL), + REGULATOR_SUPPLY("vddf_core_emmc", NULL), +}; + static struct regulator_consumer_supply tps80031_vana_supply_a02[] = { REGULATOR_SUPPLY("unused_vana", NULL), }; @@ -272,6 +279,7 @@ TPS_PDATA_INIT(SMPS2, smps2, common, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ TPS_PDATA_INIT(SMPS3, smps3, common, 600, 2100, 0, 1, 0, 0, -1, 0, 0, 0, 0, 0); TPS_PDATA_INIT(SMPS4, smps4, a02, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); TPS_PDATA_INIT(SMPS4, smps4, a03, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(SMPS4, smps4, tai, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); TPS_PDATA_INIT(LDO1, ldo1, a02, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, 0, 0); TPS_PDATA_INIT(LDO1, ldo1, a03, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); TPS_PDATA_INIT(LDO2, ldo2, common, 1000, 1000, 0, 1, 1, 1, -1, 0, 0, 0, 0, 0); @@ -372,6 +380,25 @@ static struct tps80031_regulator_platform_data *tps80031_reg_pdata_a03[] = { TPS_REG_PDATA(vana, a03), }; +static struct tps80031_regulator_platform_data *tps80031_reg_pdata_tai[] = { + TPS_REG_PDATA(vio, a03), + TPS_REG_PDATA(smps1, common), + TPS_REG_PDATA(smps2, common), + TPS_REG_PDATA(smps3, common), + TPS_REG_PDATA(ldo2, common), + TPS_REG_PDATA(ldo3, common), + TPS_REG_PDATA(ldo5, common), + TPS_REG_PDATA(vbus, common), + TPS_REG_PDATA(smps4, tai), + TPS_REG_PDATA(ldo1, a03), + TPS_REG_PDATA(ldo4, a03), + TPS_REG_PDATA(ldo6, a03), + TPS_REG_PDATA(ldo7, a03), + TPS_REG_PDATA(ldoln, a03), + TPS_REG_PDATA(ldousb, a03), + TPS_REG_PDATA(vana, a03), +}; + static struct tps80031_clk32k_init_data clk32k_idata[] = { { .clk32k_nr = TPS80031_CLOCK32K_G, @@ -745,8 +772,16 @@ int __init enterprise_regulator_init(void) tps_platform.num_regulator_pdata = ARRAY_SIZE(tps80031_reg_pdata_a02); tps_platform.regulator_pdata = tps80031_reg_pdata_a02; } else { - tps_platform.num_regulator_pdata = ARRAY_SIZE(tps80031_reg_pdata_a03); - tps_platform.regulator_pdata = tps80031_reg_pdata_a03; + if (machine_is_tai()) { + tps_platform.num_regulator_pdata = + ARRAY_SIZE(tps80031_reg_pdata_tai); + tps_platform.regulator_pdata = + tps80031_reg_pdata_tai; + } else { + tps_platform.num_regulator_pdata = + ARRAY_SIZE(tps80031_reg_pdata_a03); + tps_platform.regulator_pdata = tps80031_reg_pdata_a03; + } tps_platform.pupd_init_data = pupd_idata; tps_platform.pupd_init_data_size = ARRAY_SIZE(pupd_idata); tps_platform.gpio_init_data = gpio_idata_a03; -- cgit v1.2.3 From 29b248c4f6171b08dc84eda893b1bfffaaeb5cc4 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 29 Aug 2012 15:19:04 +0530 Subject: i2c: tegra: rename fast clock and div clock Rename fast clock to "fast-clk" and div clock to "div-clk" in driver and clock table to have aligned with mainline as: This is based on change: --------- commit f16e6e77a105ec53496f0d8343895da342917873 Author: Laxman Dewangan i2c: tegra: pass proper name for getting clock --------- Change-Id: Ie9a1972a18e2e60ac7c84c4509860cf72405ef16 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/128150 --- arch/arm/mach-tegra/tegra2_clocks.c | 16 ++++++++-------- arch/arm/mach-tegra/tegra3_clocks.c | 20 ++++++++++---------- 2 files changed, 18 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index fa88b11552d9..08359fcc0d31 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -2460,14 +2460,14 @@ struct clk tegra_list_periph_clks[] = { PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 0x31E, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 0x31E, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */ - PERIPH_CLK("i2c1", "tegra-i2c.0", "i2c-div", 12, 0x124, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("i2c2", "tegra-i2c.1", "i2c-div", 54, 0x198, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("i2c3", "tegra-i2c.2", "i2c-div", 67, 0x1b8, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("dvc", "tegra-i2c.3", "i2c-div", 47, 0x128, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("i2c1-fast", "tegra-i2c.0", "i2c-fast", 0, 0, 0x31E, 108000000, mux_pllp_out3, PERIPH_NO_ENB), - PERIPH_CLK("i2c2-fast", "tegra-i2c.1", "i2c-fast", 0, 0, 0x31E, 108000000, mux_pllp_out3, PERIPH_NO_ENB), - PERIPH_CLK("i2c3-fast", "tegra-i2c.2", "i2c-fast", 0, 0, 0x31E, 108000000, mux_pllp_out3, PERIPH_NO_ENB), - PERIPH_CLK("dvc-fast", "tegra-i2c.3", "i2c-fast", 0, 0, 0x31E, 108000000, mux_pllp_out3, PERIPH_NO_ENB), + PERIPH_CLK("i2c1", "tegra-i2c.0", "div-clk", 12, 0x124, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16 | PERIPH_ON_APB), + PERIPH_CLK("i2c2", "tegra-i2c.1", "div-clk", 54, 0x198, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16 | PERIPH_ON_APB), + PERIPH_CLK("i2c3", "tegra-i2c.2", "div-clk", 67, 0x1b8, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16 | PERIPH_ON_APB), + PERIPH_CLK("dvc", "tegra-i2c.3", "div-clk", 47, 0x128, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16 | PERIPH_ON_APB), + PERIPH_CLK("i2c1-fast", "tegra-i2c.0", "fast-clk", 0, 0, 0x31E, 108000000, mux_pllp_out3, PERIPH_NO_ENB), + PERIPH_CLK("i2c2-fast", "tegra-i2c.1", "fast-clk", 0, 0, 0x31E, 108000000, mux_pllp_out3, PERIPH_NO_ENB), + PERIPH_CLK("i2c3-fast", "tegra-i2c.2", "fast-clk", 0, 0, 0x31E, 108000000, mux_pllp_out3, PERIPH_NO_ENB), + PERIPH_CLK("dvc-fast", "tegra-i2c.3", "fast-clk", 0, 0, 0x31E, 108000000, mux_pllp_out3, PERIPH_NO_ENB), PERIPH_CLK("uarta", "tegra_uart.0", NULL, 6, 0x178, 0x31E, 600000000, mux_pllp_pllc_pllm_clkm, MUX | PERIPH_ON_APB), PERIPH_CLK("uartb", "tegra_uart.1", NULL, 7, 0x17c, 0x31E, 600000000, mux_pllp_pllc_pllm_clkm, MUX | PERIPH_ON_APB), PERIPH_CLK("uartc", "tegra_uart.2", NULL, 55, 0x1a0, 0x31E, 600000000, mux_pllp_pllc_pllm_clkm, MUX | PERIPH_ON_APB), diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 9793c7ab052b..0bc60869a3d0 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -4349,16 +4349,16 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */ - PERIPH_CLK("i2c1", "tegra-i2c.0", "i2c-div", 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("i2c2", "tegra-i2c.1", "i2c-div", 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("i2c3", "tegra-i2c.2", "i2c-div", 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("i2c4", "tegra-i2c.3", "i2c-div", 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("i2c5", "tegra-i2c.4", "i2c-div", 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("i2c1-fast", "tegra-i2c.0", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), - PERIPH_CLK("i2c2-fast", "tegra-i2c.1", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), - PERIPH_CLK("i2c3-fast", "tegra-i2c.2", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), - PERIPH_CLK("i2c4-fast", "tegra-i2c.3", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), - PERIPH_CLK("i2c5-fast", "tegra-i2c.4", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), + PERIPH_CLK("i2c1", "tegra-i2c.0", "div-clk", 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), + PERIPH_CLK("i2c2", "tegra-i2c.1", "div-clk", 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), + PERIPH_CLK("i2c3", "tegra-i2c.2", "div-clk", 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), + PERIPH_CLK("i2c4", "tegra-i2c.3", "div-clk", 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), + PERIPH_CLK("i2c5", "tegra-i2c.4", "div-clk", 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), + PERIPH_CLK("i2c1-fast", "tegra-i2c.0", "fast-clk", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), + PERIPH_CLK("i2c2-fast", "tegra-i2c.1", "fast-clk", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), + PERIPH_CLK("i2c3-fast", "tegra-i2c.2", "fast-clk", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), + PERIPH_CLK("i2c4-fast", "tegra-i2c.3", "fast-clk", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), + PERIPH_CLK("i2c5-fast", "tegra-i2c.4", "fast-clk", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), PERIPH_CLK("uarta", "tegra_uart.0", NULL, 6, 0x178, 900000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), PERIPH_CLK("uartb", "tegra_uart.1", NULL, 7, 0x17c, 900000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), PERIPH_CLK("uartc", "tegra_uart.2", NULL, 55, 0x1a0, 900000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), -- cgit v1.2.3 From f04a298e90fee39e8bcc74cbee0ef4e2645ed6da Mon Sep 17 00:00:00 2001 From: Nikesh Oswal Date: Tue, 28 Aug 2012 19:51:04 +0530 Subject: enterprise pinmux: set the pinmux for audio ports Bug: 1039342 Reviewed-on: http://git-master/r/127868 (cherry picked from commit 92f2d2099e3411dfa1966e8ead58dc5654f3124c) Change-Id: Ibe7dd39a06170766ec043ccbf18df0078ee9e7cb Signed-off-by: Nikesh Oswal Reviewed-on: http://git-master/r/128508 Reviewed-by: Niranjan Wartikar Reviewed-by: Scott Peterson --- arch/arm/mach-tegra/board-enterprise-pinmux.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-pinmux.c b/arch/arm/mach-tegra/board-enterprise-pinmux.c index 8a1a7194878e..efbdeb337e15 100644 --- a/arch/arm/mach-tegra/board-enterprise-pinmux.c +++ b/arch/arm/mach-tegra/board-enterprise-pinmux.c @@ -258,8 +258,8 @@ static __initdata struct tegra_pingroup_config enterprise_pinmux_a03[] = { DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GPIO_PV3, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), DEFAULT_PINMUX(LCD_PWR1, DISPLAYA, NORMAL, TRISTATE, OUTPUT), DEFAULT_PINMUX(LCD_PWR2, DISPLAYA, NORMAL, TRISTATE, INPUT), @@ -307,10 +307,10 @@ static __initdata struct tegra_pingroup_config enterprise_pinmux_a03[] = { DEFAULT_PINMUX(GPIO_PU4, PWM1, PULL_DOWN, TRISTATE, OUTPUT), DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, TRISTATE, INPUT), DEFAULT_PINMUX(GPIO_PU6, PWM3, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, TRISTATE, INPUT), DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, TRISTATE, INPUT), @@ -326,14 +326,14 @@ static __initdata struct tegra_pingroup_config enterprise_pinmux_a03[] = { DEFAULT_PINMUX(KB_COL3, KBC, PULL_DOWN, TRISTATE, OUTPUT), DEFAULT_PINMUX(GPIO_PV0, RSVD, PULL_UP, TRISTATE, INPUT), DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, TRISTATE, INPUT), DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(SPI1_MOSI, SPI1, PULL_DOWN, TRISTATE, OUTPUT), DEFAULT_PINMUX(SPI1_SCK, SPI1, PULL_DOWN, TRISTATE, OUTPUT), -- cgit v1.2.3 From f0a2ca55641520d9a1d86a50e59c202d175c4635 Mon Sep 17 00:00:00 2001 From: Rakesh Iyer Date: Tue, 21 Aug 2012 18:25:17 -0700 Subject: video: tegra: dc: support for vblank sync Add wait for vsync support for one-shot panels. The code supports extension of this feature to other panels. Bug 1033411. Change-Id: Ie4d6cb45e5de81083458169ccdfa33230235ed72 Signed-off-by: Rakesh Iyer Reviewed-on: http://git-master/r/128927 Reviewed-by: Mrutyunjay Sawant Tested-by: Mrutyunjay Sawant --- arch/arm/mach-tegra/include/mach/dc.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/include/mach/dc.h b/arch/arm/mach-tegra/include/mach/dc.h index 3483fe91ce66..d7aaed0bdcdc 100644 --- a/arch/arm/mach-tegra/include/mach/dc.h +++ b/arch/arm/mach-tegra/include/mach/dc.h @@ -24,6 +24,7 @@ #include #include +#include #include #define TEGRA_MAX_DC 2 @@ -368,6 +369,8 @@ struct tegra_dc_out { u8 *out_sel_configs; unsigned n_out_sel_configs; + bool user_needs_vblank; + struct completion user_vblank_comp; int (*enable)(void); int (*postpoweron)(void); @@ -525,6 +528,8 @@ bool tegra_dc_get_connected(struct tegra_dc *); bool tegra_dc_hpd(struct tegra_dc *dc); +void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank); +int tegra_dc_wait_for_vsync(struct tegra_dc *dc); void tegra_dc_blank(struct tegra_dc *dc); void tegra_dc_enable(struct tegra_dc *dc); -- cgit v1.2.3 From 616ade39df296b2c60d8ce74c719bc560f78f598 Mon Sep 17 00:00:00 2001 From: Chandrakanth Gorantla Date: Mon, 27 Aug 2012 10:29:44 +0530 Subject: ARM: tegra: cardhu: set I2S as slave mode enable slave mode for cardhu platform. BUG 998682 Change-Id: Iad330677154af417e0848059536581bcabdd98bc Signed-off-by: Chandrakanth Gorantla Reviewed-on: http://git-master/r/128734 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Scott Peterson --- arch/arm/mach-tegra/board-cardhu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c index 9fa78c502747..d2b996009165 100644 --- a/arch/arm/mach-tegra/board-cardhu.c +++ b/arch/arm/mach-tegra/board-cardhu.c @@ -733,7 +733,7 @@ static struct tegra_asoc_platform_data cardhu_audio_wm8903_pdata = { .gpio_ext_mic_en = -1, .i2s_param[HIFI_CODEC] = { .audio_port_id = 0, - .is_i2s_master = 1, + .is_i2s_master = 0, .i2s_mode = TEGRA_DAIFMT_I2S, }, .i2s_param[BASEBAND] = { -- cgit v1.2.3 From 5c13235fdd38404b3b785aa5c2d7e6f51e4bfb53 Mon Sep 17 00:00:00 2001 From: Sang-Hun Lee Date: Fri, 17 Aug 2012 16:54:05 -0700 Subject: ARM: tegra: kai: adjust ov2710 power sequence Update the power sequence to match the specification Bug 1031318 Reviewed-on: http://git-master/r/124496 (cherry picked from commit d2b1e1ddb2e65482eb15698b925471daf573a7ba) Change-Id: I837cafb494571816ee6ef25ea8159fc0de9fb2f5 Signed-off-by: Sang-Hun Lee Reviewed-on: http://git-master/r/128945 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani --- arch/arm/mach-tegra/board-kai-sensors.c | 40 ++++++++++++++++----------------- 1 file changed, 20 insertions(+), 20 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-kai-sensors.c b/arch/arm/mach-tegra/board-kai-sensors.c index 29d1bea2e8a7..048c39c9759f 100644 --- a/arch/arm/mach-tegra/board-kai-sensors.c +++ b/arch/arm/mach-tegra/board-kai-sensors.c @@ -179,8 +179,15 @@ static int kai_camera_init(void) static int kai_ov2710_power_on(void) { - gpio_direction_output(CAM2_POWER_DWN_GPIO, 0); - mdelay(10); + if (kai_1v8_cam3 == NULL) { + kai_1v8_cam3 = regulator_get(NULL, "vdd_1v8_cam3"); + if (WARN_ON(IS_ERR(kai_1v8_cam3))) { + pr_err("%s: couldn't get regulator vdd_1v8_cam3: %d\n", + __func__, (int)PTR_ERR(kai_1v8_cam3)); + goto reg_get_vdd_1v8_cam3_fail; + } + } + regulator_enable(kai_1v8_cam3); if (kai_vdd_cam3 == NULL) { kai_vdd_cam3 = regulator_get(NULL, "vdd_cam3"); @@ -191,43 +198,36 @@ static int kai_ov2710_power_on(void) } } regulator_enable(kai_vdd_cam3); - - if (kai_1v8_cam3 == NULL) { - kai_1v8_cam3 = regulator_get(NULL, "vdd_1v8_cam3"); - if (WARN_ON(IS_ERR(kai_1v8_cam3))) { - pr_err("%s: couldn't get regulator vdd_1v8_cam3: %d\n", - __func__, (int)PTR_ERR(kai_1v8_cam3)); - goto reg_get_vdd_1v8_cam3_fail; - } - } - regulator_enable(kai_1v8_cam3); mdelay(5); + gpio_direction_output(CAM2_POWER_DWN_GPIO, 0); + mdelay(10); + gpio_direction_output(CAM2_RST_GPIO, 1); mdelay(10); return 0; -reg_get_vdd_1v8_cam3_fail: - kai_1v8_cam3 = NULL; - regulator_put(kai_vdd_cam3); - reg_get_vdd_cam3_fail: kai_vdd_cam3 = NULL; + regulator_put(kai_1v8_cam3); + +reg_get_vdd_1v8_cam3_fail: + kai_1v8_cam3 = NULL; return -ENODEV; } static int kai_ov2710_power_off(void) { - gpio_direction_output(CAM2_POWER_DWN_GPIO, 1); - gpio_direction_output(CAM2_RST_GPIO, 0); - if (kai_1v8_cam3) - regulator_disable(kai_1v8_cam3); + gpio_direction_output(CAM2_POWER_DWN_GPIO, 1); + if (kai_vdd_cam3) regulator_disable(kai_vdd_cam3); + if (kai_1v8_cam3) + regulator_disable(kai_1v8_cam3); return 0; } -- cgit v1.2.3 From 65ce999d1b22b01f6a2e6b3516be47e83d6d2584 Mon Sep 17 00:00:00 2001 From: Rakesh Bodla Date: Tue, 4 Sep 2012 11:43:44 +0530 Subject: arm: tegra: phy: enable wakeup event for usb phy If usb device already connected, should disable WKCN in USB2D_PORTSC1, and enable WKDS in USB2D_PORTSC1, during utmi phy power off. All the wakeup resource should be cleared after the event happened. Bug 1020021 Bug 1028429 Change-Id: I807ca76d4392318adf6adb808cb2bf290cd0d60c Signed-off-by: Rakesh Bodla Reviewed-on: http://git-master/r/128547 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty --- arch/arm/mach-tegra/tegra2_usb_phy.c | 17 +++++++++++++--- arch/arm/mach-tegra/tegra3_usb_phy.c | 38 ++++++++++++++++++++++++++---------- 2 files changed, 42 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra2_usb_phy.c b/arch/arm/mach-tegra/tegra2_usb_phy.c index 892e3ba8ec71..0292ebb75083 100644 --- a/arch/arm/mach-tegra/tegra2_usb_phy.c +++ b/arch/arm/mach-tegra/tegra2_usb_phy.c @@ -613,13 +613,19 @@ static int utmi_phy_irq(struct tegra_usb_phy *phy) val &= ~USB_PHY_CLK_VALID_INT_ENB | USB_PHY_CLK_VALID_INT_STS; writel(val , (base + USB_SUSP_CTRL)); - pr_info("%s: usb device plugged-in\n", __func__); + val = readl(base + USB_USBSTS); if (!(val & USB_USBSTS_PCI)) return IRQ_NONE; + val = readl(base + USB_PORTSC); - val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS); + if (val & USB_PORTSC_CCS) + val &= ~USB_PORTSC_WKCN; + else + val &= ~USB_PORTSC_WKDS; + val &= ~USB_PORTSC_RWC_BITS; writel(val , (base + USB_PORTSC)); + } else if (!phy->phy_clk_on) { return IRQ_NONE; } @@ -710,8 +716,12 @@ static int utmi_phy_power_off(struct tegra_usb_phy *phy) enable_hotplug = (val & USB_ID_STATUS) ? false : true; } if (enable_hotplug) { + /* Enable wakeup event of device plug-in/plug-out */ val = readl(base + USB_PORTSC); - val |= USB_PORTSC_WKCN; + if (val & USB_PORTSC_CCS) + val |= USB_PORTSC_WKDS; + else + val |= USB_PORTSC_WKCN; writel(val, base + USB_PORTSC); val = readl(base + USB_SUSP_CTRL); @@ -726,6 +736,7 @@ static int utmi_phy_power_off(struct tegra_usb_phy *phy) } } + /* Disable PHY clock */ if (phy->inst == 2) { val = readl(base + USB_PORTSC); val |= USB_PORTSC_PHCD; diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index 1020e5d35f89..66637f29b19c 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -1246,15 +1246,26 @@ static int utmi_phy_irq(struct tegra_usb_phy *phy) val &= ~USB_PHY_CLK_VALID_INT_ENB | USB_PHY_CLK_VALID_INT_STS; writel(val , (base + USB_SUSP_CTRL)); - pr_info("%s: usb device plugged-in\n", __func__); - val = readl(base + USB_USBSTS); - if (!(val & USB_USBSTS_PCI)) { - irq_status = IRQ_NONE; - goto exit; + + /* In case of remote wakeup PHY clock will not up + immediately, so should not access any controller + register but normal plug-in/plug-out should be + executed */ + if (!remote_wakeup) { + val = readl(base + USB_USBSTS); + if (!(val & USB_USBSTS_PCI)) { + irq_status = IRQ_NONE; + goto exit; + } + + val = readl(base + USB_PORTSC); + if (val & USB_PORTSC_CCS) + val &= ~USB_PORTSC_WKCN; + else + val &= ~USB_PORTSC_WKDS; + val &= ~USB_PORTSC_RWC_BITS; + writel(val , (base + USB_PORTSC)); } - val = readl(base + USB_PORTSC); - val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS); - writel(val , (base + USB_PORTSC)); } else if (!phy->phy_clk_on) { if (remote_wakeup) irq_status = IRQ_HANDLED; @@ -1476,8 +1487,12 @@ static int utmi_phy_power_off(struct tegra_usb_phy *phy) enable_hotplug = (val & USB_ID_STATUS) ? false : true; } if (enable_hotplug) { + /* Enable wakeup event of device plug-in/plug-out */ val = readl(base + USB_PORTSC); - val |= USB_PORTSC_WKCN; + if (val & USB_PORTSC_CCS) + val |= USB_PORTSC_WKDS; + else + val |= USB_PORTSC_WKCN; writel(val, base + USB_PORTSC); val = readl(base + USB_SUSP_CTRL); @@ -1491,6 +1506,7 @@ static int utmi_phy_power_off(struct tegra_usb_phy *phy) } } + /* Disable PHY clock */ val = readl(base + HOSTPC1_DEVLC); val |= HOSTPC1_DEVLC_PHCD; writel(val, base + HOSTPC1_DEVLC); @@ -1679,7 +1695,9 @@ static void utmi_phy_restore_end(struct tegra_usb_phy *phy) val = readl(base + USB_PORTSC); udelay(1); if (wait_time_us == 0) { - PHY_DBG("%s PMC REMOTE WAKEUP FPR timeout val = 0x%x instance = %d\n", __func__, val, phy->inst); + PHY_DBG("%s PMC REMOTE WAKEUP FPR timeout" + "val = 0x%lx instance = %d\n", + __func__, val, phy->inst); utmip_phy_disable_pmc_bus_ctrl(phy); utmi_phy_post_resume(phy); return; -- cgit v1.2.3 From e9db5831001626ab6ed6edfdb5641072780926a7 Mon Sep 17 00:00:00 2001 From: Kerwin Wan Date: Wed, 4 Jul 2012 16:20:24 +0800 Subject: arm: tegra: kai: update memory timings bug 947148 Change-Id: Icc9711e44375dee9346cbe2cb8af090286a244a2 Signed-off-by: Kerwin Wan Reviewed-on: http://git-master/r/126834 (cherry picked from commit 90ec2d7e47927723f8c088c178bb560828fac622) Reviewed-on: http://git-master/r/129571 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani Reviewed-by: Jon Mayo --- arch/arm/mach-tegra/board-kai-memory.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-kai-memory.c b/arch/arm/mach-tegra/board-kai-memory.c index cf5daf6492eb..07d6405c7016 100644 --- a/arch/arm/mach-tegra/board-kai-memory.c +++ b/arch/arm/mach-tegra/board-kai-memory.c @@ -118,7 +118,7 @@ static const struct tegra_emc_table kai_emc_tables_h5tc4g[] = { 0x00000000, /* EMC_CTT_DURATION */ 0x80000287, /* EMC_DYN_SELF_REF_CONTROL */ 0x00030003, /* MC_EMEM_ARB_CFG */ - 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ @@ -238,7 +238,7 @@ static const struct tegra_emc_table kai_emc_tables_h5tc4g[] = { 0x00000000, /* EMC_CTT_DURATION */ 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ 0x00010003, /* MC_EMEM_ARB_CFG */ - 0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ @@ -358,7 +358,7 @@ static const struct tegra_emc_table kai_emc_tables_h5tc4g[] = { 0x00000000, /* EMC_CTT_DURATION */ 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ 0x00000003, /* MC_EMEM_ARB_CFG */ - 0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ -- cgit v1.2.3 From 6315861867aae8b64d04a46b05248c33b7d613db Mon Sep 17 00:00:00 2001 From: Rakesh Goyal Date: Sun, 26 Aug 2012 00:04:33 +0530 Subject: ARM: tegra: tai: fix gpio number for nfc and bluetooth NFC use GPIO4 for download firmware BT_RST is required to make bluetooth on/off Bug 1002637 Change-Id: Ic49a3fe606de618dfafdf0bc35b6a6fc1ac12cdd Signed-off-by: Rakesh Goyal Reviewed-on: http://git-master/r/128612 Reviewed-by: Rakesh Kumar Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani --- arch/arm/mach-tegra/board-enterprise.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c index f3808a3b48fb..51db725d0223 100644 --- a/arch/arm/mach-tegra/board-enterprise.c +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -1055,7 +1055,7 @@ static void enterprise_nfc_init(void) if (bi.board_id == BOARD_E1205 && bi.fab >= BOARD_FAB_A03) { nfc_pdata.firm_gpio = TEGRA_GPIO_PX7; } else if (bi.board_id == BOARD_E1239) { - nfc_pdata.firm_gpio = TEGRA_GPIO_PN6; + nfc_pdata.firm_gpio = TEGRA_GPIO_PD2; } } @@ -1077,7 +1077,7 @@ static void __init tegra_enterprise_init(void) enterprise_uart_init(); enterprise_usb_init(); if (board_info.board_id == BOARD_E1239) - enterprise_bt_rfkill_pdata[0].shutdown_gpio = TEGRA_GPIO_PF4; + enterprise_bt_rfkill_pdata[0].reset_gpio = TEGRA_GPIO_PF4; platform_add_devices(enterprise_devices, ARRAY_SIZE(enterprise_devices)); tegra_ram_console_debug_init(); -- cgit v1.2.3 From 32b8cc820fc9f3709c23e6b383825d6cdb0a6085 Mon Sep 17 00:00:00 2001 From: Rakesh Goyal Date: Tue, 28 Aug 2012 22:16:08 +0530 Subject: ARM: tegra: enterprise: enable wl18xx wireless module support Bug 990784 Change-Id: I173df3f7244e7d0b40ae5aad98c72885ff42fdab Signed-off-by: Rakesh Goyal Reviewed-on: http://git-master/r/129103 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Rakesh Kumar Reviewed-by: Bharat Nihalani --- arch/arm/mach-tegra/board-enterprise-sdhci.c | 44 ++++++++++++++--- arch/arm/mach-tegra/board-enterprise.c | 73 +++++++++++++++++++++++++--- arch/arm/mach-tegra/board-enterprise.h | 2 + arch/arm/mach-tegra/board.h | 4 +- 4 files changed, 107 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-enterprise-sdhci.c b/arch/arm/mach-tegra/board-enterprise-sdhci.c index 8032f8105bed..a003ae9cbd8e 100644 --- a/arch/arm/mach-tegra/board-enterprise-sdhci.c +++ b/arch/arm/mach-tegra/board-enterprise-sdhci.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -52,6 +53,14 @@ static struct wifi_platform_data enterprise_wifi_control = { .set_carddetect = enterprise_wifi_set_carddetect, }; +static struct wl12xx_platform_data enterprise_wl12xx_wlan_data __initdata = { + .irq = TEGRA_GPIO_TO_IRQ(ENTERPRISE_WLAN_WOW), + .board_ref_clock = WL12XX_REFCLOCK_26, + .board_tcxo_clock = 1, + .set_power = enterprise_wifi_power, + .set_carddetect = enterprise_wifi_set_carddetect, +}; + static struct resource wifi_resource[] = { [0] = { .name = "bcm4329_wlan_irq", @@ -61,7 +70,7 @@ static struct resource wifi_resource[] = { }, }; -static struct platform_device enterprise_wifi_device = { +static struct platform_device enterprise_brcm_wifi_device = { .name = "bcm4329_wlan", .id = 1, .num_resources = 1, @@ -238,10 +247,22 @@ static int enterprise_wifi_power(int on) tegra_io_dpd_disable(sd_dpd); mutex_unlock(&sd_dpd->delay_lock); } - gpio_set_value(ENTERPRISE_WLAN_PWR, on); - mdelay(100); - gpio_set_value(ENTERPRISE_WLAN_RST, on); - mdelay(200); + + if (on) { + gpio_set_value(ENTERPRISE_WLAN_RST, 1); + mdelay(100); + gpio_set_value(ENTERPRISE_WLAN_RST, 0); + mdelay(100); + gpio_set_value(ENTERPRISE_WLAN_RST, 1); + mdelay(100); + gpio_set_value(ENTERPRISE_WLAN_PWR, 1); + mdelay(200); + } else { + gpio_set_value(ENTERPRISE_WLAN_RST, 0); + mdelay(100); + gpio_set_value(ENTERPRISE_WLAN_PWR, 0); + } + if (sd_dpd) { mutex_lock(&sd_dpd->delay_lock); tegra_io_dpd_enable(sd_dpd); @@ -295,7 +316,11 @@ static int __init enterprise_wifi_init(void) if (rc) pr_err("WLAN_WOW gpio direction configuration failed:%d\n", rc); - platform_device_register(&enterprise_wifi_device); + if (tegra_get_commchip_id() == COMMCHIP_TI_WL18XX) + wl12xx_set_platform_data(&enterprise_wl12xx_wlan_data); + else + platform_device_register(&enterprise_brcm_wifi_device); + return 0; } @@ -306,6 +331,13 @@ int __init enterprise_sdhci_init(void) tegra_sdhci_platform_data2.cd_gpio = ENTERPRISE_SD_CD; platform_device_register(&tegra_sdhci_device2); + /* TI wifi module does not use emdedded sdio */ + if (tegra_get_commchip_id() == COMMCHIP_TI_WL18XX) { +#ifdef CONFIG_MMC_EMBEDDED_SDIO + tegra_sdhci_platform_data0.mmc_data.embedded_sdio = NULL; +#endif + } + platform_device_register(&tegra_sdhci_device0); enterprise_wifi_init(); return 0; diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c index 51db725d0223..25f737f75338 100644 --- a/arch/arm/mach-tegra/board-enterprise.c +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -42,6 +42,8 @@ #include #include +#include +#include #include #include @@ -124,6 +126,32 @@ static struct tegra_thermal_data thermal_data = { #endif }; +/* wl128x BT, FM, GPS connectivity chip */ +struct ti_st_plat_data enterprise_wilink_pdata = { + .nshutdown_gpio = TEGRA_GPIO_PE6, + .dev_name = BLUETOOTH_UART_DEV_NAME, + .flow_cntrl = 1, + .baud_rate = 3000000, +}; + +static struct platform_device wl128x_device = { + .name = "kim", + .id = -1, + .dev.platform_data = &enterprise_wilink_pdata, +}; + +static struct platform_device btwilink_device = { + .name = "btwilink", + .id = -1, +}; + +static noinline void __init enterprise_bt_st(void) +{ + pr_info("enterprise_bt_st"); + + platform_device_register(&wl128x_device); + platform_device_register(&btwilink_device); +} static struct rfkill_gpio_platform_data enterprise_bt_rfkill_pdata[] = { { .name = "bt_rfkill", @@ -140,8 +168,21 @@ static struct platform_device enterprise_bt_rfkill_device = { .platform_data = &enterprise_bt_rfkill_pdata, }, }; - -static struct resource enterprise_bluesleep_resources[] = { +static struct resource enterprise_ti_bluesleep_resources[] = { + [0] = { + .name = "gpio_host_wake", + .start = TEGRA_GPIO_PS2, + .end = TEGRA_GPIO_PS2, + .flags = IORESOURCE_IO, + }, + [1] = { + .name = "host_wake", + .start = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PS2), + .end = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PS2), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, + }, +}; +static struct resource enterprise_brcm_bluesleep_resources[] = { [0] = { .name = "gpio_host_wake", .start = TEGRA_GPIO_PS2, @@ -162,16 +203,30 @@ static struct resource enterprise_bluesleep_resources[] = { }, }; -static struct platform_device enterprise_bluesleep_device = { +static struct platform_device enterprise_ti_bluesleep_device = { .name = "bluesleep", .id = -1, - .num_resources = ARRAY_SIZE(enterprise_bluesleep_resources), - .resource = enterprise_bluesleep_resources, + .num_resources = ARRAY_SIZE(enterprise_ti_bluesleep_resources), + .resource = enterprise_ti_bluesleep_resources, }; +static struct platform_device enterprise_brcm_bluesleep_device = { + .name = "bluesleep", + .id = -1, + .num_resources = ARRAY_SIZE(enterprise_brcm_bluesleep_resources), + .resource = enterprise_brcm_bluesleep_resources, +}; +static void __init enterprise_bt_rfkill(void) +{ + platform_device_register(&enterprise_bt_rfkill_device); + return; +} static void __init enterprise_setup_bluesleep(void) { - platform_device_register(&enterprise_bluesleep_device); + if (tegra_get_commchip_id() == COMMCHIP_TI_WL18XX) + platform_device_register(&enterprise_ti_bluesleep_device); + else + platform_device_register(&enterprise_brcm_bluesleep_device); return; } @@ -634,7 +689,6 @@ static struct platform_device *enterprise_devices[] __initdata = { &tegra_avp_device, #endif &tegra_camera, - &enterprise_bt_rfkill_device, &tegra_spi_device4, &tegra_hda_device, #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE) @@ -1078,7 +1132,6 @@ static void __init tegra_enterprise_init(void) enterprise_usb_init(); if (board_info.board_id == BOARD_E1239) enterprise_bt_rfkill_pdata[0].reset_gpio = TEGRA_GPIO_PF4; - platform_add_devices(enterprise_devices, ARRAY_SIZE(enterprise_devices)); tegra_ram_console_debug_init(); enterprise_regulator_init(); @@ -1093,6 +1146,10 @@ static void __init tegra_enterprise_init(void) enterprise_audio_init(); enterprise_baseband_init(); enterprise_panel_init(); + if (tegra_get_commchip_id() == COMMCHIP_TI_WL18XX) + enterprise_bt_st(); + else + enterprise_bt_rfkill(); enterprise_setup_bluesleep(); enterprise_emc_init(); enterprise_sensors_init(); diff --git a/arch/arm/mach-tegra/board-enterprise.h b/arch/arm/mach-tegra/board-enterprise.h index e9bda707fed2..ae488dfb4618 100644 --- a/arch/arm/mach-tegra/board-enterprise.h +++ b/arch/arm/mach-tegra/board-enterprise.h @@ -121,6 +121,8 @@ void enterprise_bpc_mgmt_init(void); #define TEGRA_GPIO_HP_DET TEGRA_GPIO_PW3 #define TEGRA_GPIO_CODEC_RST TEGRA_GPIO_PX0 +/* UART port which is used by bluetooth*/ +#define BLUETOOTH_UART_DEV_NAME "/dev/ttyHS2" /* Baseband GPIO addresses */ #define GPIO_BB_RESET TEGRA_GPIO_PE1 diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index 7c081fad642a..85d02d501b63 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -72,9 +72,9 @@ #define COMMCHIP_UNKNOWN 0 #define COMMCHIP_NOCHIP 1 #define COMMCHIP_BROADCOM_BCM4329 2 -#define COMMCHIP BROADCOM_BCM4330 3 +#define COMMCHIP_BROADCOM_BCM4330 3 #define COMMCHIP_MARVELL_SD8797 4 - +#define COMMCHIP_TI_WL18XX 5 struct memory_accessor; -- cgit v1.2.3 From 3bdf9371b4e75e3dc9612360ab55924587714155 Mon Sep 17 00:00:00 2001 From: Chris Johnson Date: Fri, 24 Aug 2012 17:27:58 -0700 Subject: arm: tegra: secureos: disable L2 as part of sleep CPU SMC This is an alternate way to have the L2 disabled available with later TL secureos versions. In this version, the sleep CPU SMC which is the last one issued before entering LP2 on CPU0, will also disable the L2 without a flush of the secureos workspace. Change-Id: I61c3caade6cb6f922b9d9f9ca0739bc6ae4e78cd Signed-off-by: Hyung Taek Ryoo Reviewed-on: http://git-master/r/128951 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: James Zhao Reviewed-by: Yu-Huan Hsu --- arch/arm/mach-tegra/common.c | 25 +++++++++++-------------- arch/arm/mach-tegra/pm.c | 10 ++++++++++ 2 files changed, 21 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index c5401e65426f..8364589e1ff6 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -227,8 +227,6 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { }; #ifdef CONFIG_TRUSTED_FOUNDATIONS -#define CACHE_LINE_SIZE 32 - static inline void tegra_l2x0_disable_tz(void) { static u32 l2x0_way_mask; @@ -244,20 +242,19 @@ static inline void tegra_l2x0_disable_tz(void) l2x0_way_mask = (1 << ways) - 1; } #ifdef CONFIG_ARCH_TEGRA_2x_SOC - /* flush all ways on disable */ + /* flush all ways on any disable */ tegra_generic_smc_uncached(0xFFFFF100, 0x00000002, l2x0_way_mask); #elif defined(CONFIG_ARCH_TEGRA_3x_SOC) - if (tegra_is_cpu_in_lp2(0)) { - register unsigned long sp asm ("sp"); - - /* flush only the stack, if entering LP2 */ - __cpuc_flush_dcache_area((void *)sp, (CACHE_LINE_SIZE * 2)); - outer_flush_range(__pa(sp), __pa(sp) + (CACHE_LINE_SIZE * 2)); - - /* pass zero arg, so secureos flushes only its workspace */ - tegra_generic_smc_uncached(0xFFFFF100, 0x00000002, 0x0); - } else { - /* flush all ways on disable, if entering LP0/LP1 */ + if (tegra_is_cpu_in_lp2(0) == false) { + /* + * If entering LP0/LP1, ask secureos to fully flush and + * disable the L2. + * + * If entering LP2, L2 disable is handled by the secureos + * as part of the tegra_sleep_cpu() SMC. This SMC indicates + * no more secureos tasks will be scheduled, allowing it + * to optimize out L2 flushes on its side. + */ tegra_generic_smc_uncached(0xFFFFF100, 0x00000002, l2x0_way_mask); } diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 2cdfdfe6f43d..b20b51245d50 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -579,6 +579,16 @@ static void tegra_sleep_core(enum tegra_suspend_mode mode, static inline void tegra_sleep_cpu(unsigned long v2p) { #ifdef CONFIG_TRUSTED_FOUNDATIONS + if (tegra_is_cpu_in_lp2(0)) { + struct thread_info *thread; + + /* flush thread state (sleep SMC will also disable L2) */ + thread = current_thread_info(); + BUG_ON(!thread); + + __cpuc_flush_dcache_area(thread, THREAD_SIZE); + outer_flush_range(__pa(thread), __pa(thread) + THREAD_SIZE); + } tegra_generic_smc_uncached(0xFFFFFFFC, 0xFFFFFFE4, (TEGRA_RESET_HANDLER_BASE + tegra_cpu_reset_handler_offset)); -- cgit v1.2.3 From e96e462aee43ed8699f5cd64728c389e92ef402e Mon Sep 17 00:00:00 2001 From: Vinayak Pane Date: Thu, 23 Aug 2012 19:48:12 -0700 Subject: arm: tegra: xmm: add post_resume phy callback phy post_resume is called when usb port+hub is resumed, check if modem has finished resume by then. Notify modem about post resume by setting bb_wake to low. Modify check for CP initiated wakeup to read current modem state (ap_wake). Bug 1034420 Change-Id: Ie9a3aa581bd7660183464e3fc2554ceb055b69b2 Signed-off-by: Vinayak Pane Reviewed-on: http://git-master/r/129533 Reviewed-by: Simone Willett Tested-by: Simone Willett --- arch/arm/mach-tegra/baseband-xmm-power.c | 92 +++++++++++++++++--------------- arch/arm/mach-tegra/board-enterprise.c | 10 +++- 2 files changed, 57 insertions(+), 45 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/baseband-xmm-power.c b/arch/arm/mach-tegra/baseband-xmm-power.c index 5a7cecde526b..59e0779047b9 100644 --- a/arch/arm/mach-tegra/baseband-xmm-power.c +++ b/arch/arm/mach-tegra/baseband-xmm-power.c @@ -92,6 +92,7 @@ static int power_onoff; static int reenable_autosuspend; static bool wakeup_pending; static bool modem_sleep_flag; +static bool modem_acked_resume; static spinlock_t xmm_lock; static DEFINE_MUTEX(xmm_onoff_mutex); static bool system_suspending; @@ -259,6 +260,7 @@ static int xmm_power_on(struct platform_device *device) /* reset the state machine */ baseband_xmm_set_power_status(BBXMM_PS_INIT); modem_sleep_flag = false; + modem_acked_resume = true; pr_debug("%s wake_st(%d) modem version %lu\n", __func__, ipc_ap_wake_state, modem_ver); @@ -466,41 +468,37 @@ static void xmm_power_l2_resume(void) modem_sleep_flag = false; wakeup_pending = false; - if (cp_initiated_l2tol0) { - cp_initiated_l2tol0 = false; - queue_work(workqueue, &l2_resume_work); - spin_unlock_irqrestore(&xmm_lock, flags); - pr_info("CP L2->L0\n"); - } else { - /* set the slave wakeup request */ - value = gpio_get_value(pdata->modem.xmm.ipc_ap_wake); + value = gpio_get_value(pdata->modem.xmm.ipc_ap_wake); + if (value) { + /* set the slave wakeup request - bb_wake high */ + drv->hostwake = 0; + gpio_set_value(pdata->modem.xmm.ipc_bb_wake, 1); spin_unlock_irqrestore(&xmm_lock, flags); - if (value) { - pr_info("AP/CP L2->L0\n"); - drv->hostwake = 0; - /* wake bb */ - gpio_set_value(pdata->modem.xmm.ipc_bb_wake, 1); + pr_info("AP L2->L0\n"); retry: - /* wait for cp */ - pr_debug("waiting for host wakeup from CP...\n"); - ret = wait_event_interruptible_timeout(drv->bb_wait, + /* wait for cp */ + pr_debug("waiting for host wakeup from CP...\n"); + ret = wait_event_interruptible_timeout(drv->bb_wait, drv->hostwake == 1, msecs_to_jiffies(delay)); - if (ret == 0) { + if (ret == 0) { + pr_info("!!AP L2->L0 Failed\n"); + return; + } + if (ret == -ERESTARTSYS) { + if (rcount >= 5) { pr_info("!!AP L2->L0 Failed\n"); return; } - if (ret == -ERESTARTSYS) { - if (rcount >= 5) { - pr_info("!!AP L2->L0 Failed\n"); - return; - } - pr_debug("%s: caught signal\n", __func__); - rcount++; - goto retry; - } - pr_debug("Get gpio host wakeup low <-\n"); - } else - pr_info("CP already ready\n"); + pr_debug("%s: caught signal\n", __func__); + rcount++; + goto retry; + } + pr_debug("Get gpio host wakeup low <-\n"); + } else { + cp_initiated_l2tol0 = false; + queue_work(workqueue, &l2_resume_work); + spin_unlock_irqrestore(&xmm_lock, flags); + pr_info("CP L2->L0\n"); } } @@ -521,16 +519,12 @@ void baseband_xmm_set_power_status(unsigned int status) spin_lock_irqsave(&xmm_lock, flags); switch (status) { case BBXMM_PS_L0: - if (modem_sleep_flag) { - /* We dont have L3 state now, should be handled from L2 - * xmm_power_driver_handle_resume(data); - */ - } baseband_xmm_powerstate = status; if (!wake_lock_active(&wakelock)) wake_lock_timeout(&wakelock, HZ*2); + + /* pull hsic_active high for enumeration */ value = gpio_get_value(data->modem.xmm.ipc_hsic_active); - pr_debug("before L0 ipc_hsic_active=%d\n", value); if (!value) { pr_debug("L0 gpio set ipc_hsic_active=1 ->\n"); gpio_set_value(data->modem.xmm.ipc_hsic_active, 1); @@ -539,19 +533,31 @@ void baseband_xmm_set_power_status(unsigned int status) modem_power_on = false; baseband_modem_power_on(data); } + + /* cp acknowledgment for ap L2->L0 wake */ + if (!modem_acked_resume) + pr_err("%s: CP didn't ack usb-resume\n", __func__); + value = gpio_get_value(data->modem.xmm.ipc_bb_wake); + if (value) { + /* clear the slave wakeup request */ + gpio_set_value(data->modem.xmm.ipc_bb_wake, 0); + pr_debug("gpio bb_wake done low\n"); + } break; case BBXMM_PS_L2: - baseband_xmm_powerstate = status; + modem_acked_resume = false; if (wakeup_pending) { spin_unlock_irqrestore(&xmm_lock, flags); pr_debug("%s: wakeup pending\n", __func__); xmm_power_l2_resume(); spin_lock_irqsave(&xmm_lock, flags); + break; } else { if (wake_lock_active(&wakelock)) wake_unlock(&wakelock); modem_sleep_flag = true; } + baseband_xmm_powerstate = status; break; case BBXMM_PS_L2TOL0: pr_debug("L2TOL0\n"); @@ -588,7 +594,6 @@ irqreturn_t xmm_power_ipc_ap_wake_irq(int value) spin_lock(&xmm_lock); /* AP L2 to L0 wakeup */ - pr_debug("received wakeup ap l2->l0\n"); drv->hostwake = 1; wake_up_interruptible(&drv->bb_wait); @@ -621,26 +626,24 @@ irqreturn_t xmm_power_ipc_ap_wake_irq(int value) spin_unlock(&xmm_lock); } else { pr_debug("%s - rising\n", __func__); + spin_lock(&xmm_lock); + modem_acked_resume = true; value = gpio_get_value(data->modem.xmm.ipc_hsic_active); if (!value) { pr_info("host active low: ignore request\n"); ipc_ap_wake_state = IPC_AP_WAKE_H; + spin_unlock(&xmm_lock); return IRQ_HANDLED; } - value = gpio_get_value(data->modem.xmm.ipc_bb_wake); - if (value) { - /* Clear the slave wakeup request */ - gpio_set_value(data->modem.xmm.ipc_bb_wake, 0); - pr_debug("gpio slave wakeup done ->\n"); - } + if (reenable_autosuspend && usbdev) { reenable_autosuspend = false; queue_work(workqueue, &autopm_resume_work); } modem_sleep_flag = false; - baseband_xmm_set_power_status(BBXMM_PS_L0); /* save gpio state */ ipc_ap_wake_state = IPC_AP_WAKE_H; + spin_unlock(&xmm_lock); } return IRQ_HANDLED; } @@ -774,6 +777,7 @@ static void xmm_power_work_func(struct work_struct *work) pr_debug("BBXMM_WORK_INIT_FLASH_PM_STEP1\n"); pr_debug("%s: ipc_hsic_active -> 0\n", __func__); gpio_set_value(pdata->modem.xmm.ipc_hsic_active, 0); + modem_acked_resume = true; /* reset / power on sequence */ xmm_power_reset_on(pdata); /* set power status as on */ diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c index 25f737f75338..a85c2dccd1a3 100644 --- a/arch/arm/mach-tegra/board-enterprise.c +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -799,6 +799,14 @@ static void enterprise_usb_hsic_preresume(void) #endif } +static void enterprise_usb_hsic_post_resume(void) +{ + pr_debug("%s\n", __func__); +#ifdef CONFIG_TEGRA_BB_XMM_POWER + baseband_xmm_set_power_status(BBXMM_PS_L0); +#endif +} + static void enterprise_usb_hsic_phy_power(void) { pr_debug("%s\n", __func__); @@ -819,7 +827,7 @@ static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = { .post_suspend = enterprise_usb_hsic_postsupend, .pre_resume = enterprise_usb_hsic_preresume, .port_power = enterprise_usb_hsic_phy_power, - .post_phy_on = enterprise_usb_hsic_phy_power, + .post_resume = enterprise_usb_hsic_post_resume, .post_phy_off = enterprise_usb_hsic_post_phy_off, }; -- cgit v1.2.3 From c56d1413ee5fb5ae24f36e9e7b8e578f3d91db15 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Fri, 24 Aug 2012 12:36:47 +0000 Subject: ARM: 7467/1: mutex: use generic xchg-based implementation for ARMv6+ The open-coded mutex implementation for ARMv6+ cores suffers from a severe lack of barriers, so in the uncontended case we don't actually protect any accesses performed during the critical section. Furthermore, the code is largely a duplication of the ARMv6+ atomic_dec code but optimised to remove a branch instruction, as the mutex fastpath was previously inlined. Now that this is executed out-of-line, we can reuse the atomic access code for the locking (in fact, we use the xchg code as this produces shorter critical sections). This patch uses the generic xchg based implementation for mutexes on ARMv6+, which introduces barriers to the lock/unlock operations and also has the benefit of removing a fair amount of inline assembly code. Change-Id: I58e3ca4d2740a834d30b54fc35742fa2df7792ad Cc: : 0bce9c46: mutex: Place lock in contended... Cc: Acked-by: Arnd Bergmann Acked-by: Nicolas Pitre Reported-by: Shan Kang Signed-off-by: Will Deacon Signed-off-by: Russell King Reviewed-on: http://git-master/r/130940 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani Tested-by: Bharat Nihalani --- arch/arm/include/asm/mutex.h | 119 ++----------------------------------------- 1 file changed, 4 insertions(+), 115 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/mutex.h b/arch/arm/include/asm/mutex.h index 93226cf23ae0..b1479fd04a95 100644 --- a/arch/arm/include/asm/mutex.h +++ b/arch/arm/include/asm/mutex.h @@ -7,121 +7,10 @@ */ #ifndef _ASM_MUTEX_H #define _ASM_MUTEX_H - -#if __LINUX_ARM_ARCH__ < 6 -/* On pre-ARMv6 hardware the swp based implementation is the most efficient. */ -# include -#else - /* - * Attempting to lock a mutex on ARMv6+ can be done with a bastardized - * atomic decrement (it is not a reliable atomic decrement but it satisfies - * the defined semantics for our purpose, while being smaller and faster - * than a real atomic decrement or atomic swap. The idea is to attempt - * decrementing the lock value only once. If once decremented it isn't zero, - * or if its store-back fails due to a dispute on the exclusive store, we - * simply bail out immediately through the slow path where the lock will be - * reattempted until it succeeds. + * On pre-ARMv6 hardware this results in a swp-based implementation, + * which is the most efficient. For ARMv6+, we emit a pair of exclusive + * accesses instead. */ -static inline void -__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *)) -{ - int __ex_flag, __res; - - __asm__ ( - - "ldrex %0, [%2] \n\t" - "sub %0, %0, #1 \n\t" - "strex %1, %0, [%2] " - - : "=&r" (__res), "=&r" (__ex_flag) - : "r" (&(count)->counter) - : "cc","memory" ); - - __res |= __ex_flag; - if (unlikely(__res != 0)) - fail_fn(count); -} - -static inline int -__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *)) -{ - int __ex_flag, __res; - - __asm__ ( - - "ldrex %0, [%2] \n\t" - "sub %0, %0, #1 \n\t" - "strex %1, %0, [%2] " - - : "=&r" (__res), "=&r" (__ex_flag) - : "r" (&(count)->counter) - : "cc","memory" ); - - __res |= __ex_flag; - if (unlikely(__res != 0)) - __res = fail_fn(count); - return __res; -} - -/* - * Same trick is used for the unlock fast path. However the original value, - * rather than the result, is used to test for success in order to have - * better generated assembly. - */ -static inline void -__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *)) -{ - int __ex_flag, __res, __orig; - - __asm__ ( - - "ldrex %0, [%3] \n\t" - "add %1, %0, #1 \n\t" - "strex %2, %1, [%3] " - - : "=&r" (__orig), "=&r" (__res), "=&r" (__ex_flag) - : "r" (&(count)->counter) - : "cc","memory" ); - - __orig |= __ex_flag; - if (unlikely(__orig != 0)) - fail_fn(count); -} - -/* - * If the unlock was done on a contended lock, or if the unlock simply fails - * then the mutex remains locked. - */ -#define __mutex_slowpath_needs_to_unlock() 1 - -/* - * For __mutex_fastpath_trylock we use another construct which could be - * described as a "single value cmpxchg". - * - * This provides the needed trylock semantics like cmpxchg would, but it is - * lighter and less generic than a true cmpxchg implementation. - */ -static inline int -__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *)) -{ - int __ex_flag, __res, __orig; - - __asm__ ( - - "1: ldrex %0, [%3] \n\t" - "subs %1, %0, #1 \n\t" - "strexeq %2, %1, [%3] \n\t" - "movlt %0, #0 \n\t" - "cmpeq %2, #0 \n\t" - "bgt 1b " - - : "=&r" (__orig), "=&r" (__res), "=&r" (__ex_flag) - : "r" (&count->counter) - : "cc", "memory" ); - - return __orig; -} - -#endif +#include #endif -- cgit v1.2.3 From 75bdd482816eba85414a71b86535fa87db336aa3 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Mon, 13 Aug 2012 17:38:48 +0000 Subject: ARM: mutex: use generic atomic_dec-based implementation for ARMv6+ Commit a76d7bd96d65 ("ARM: 7467/1: mutex: use generic xchg-based implementation for ARMv6+") removed the barrier-less, ARM-specific mutex implementation in favour of the generic xchg-based code. Since then, a bug was uncovered in the xchg code when running on SMP platforms, due to interactions between the locking paths and the MUTEX_SPIN_ON_OWNER code. This was fixed in 0bce9c46bf3b ("mutex: place lock in contended state after fastpath_lock failure"), however, the atomic_dec-based mutex algorithm is now marginally more efficient for ARM (~0.5% improvement in hackbench scores on dual A15). This patch moves ARMv6+ platforms to the atomic_dec-based mutex code. Change-Id: I8f64e98ccb61cc1cb9cb68ee15e55d8a792792f5 Cc: Nicolas Pitre Signed-off-by: Will Deacon Acked-by: Nicolas Pitre Reviewed-on: http://git-master/r/130941 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani Tested-by: Bharat Nihalani --- arch/arm/include/asm/mutex.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/mutex.h b/arch/arm/include/asm/mutex.h index b1479fd04a95..6e813d93a736 100644 --- a/arch/arm/include/asm/mutex.h +++ b/arch/arm/include/asm/mutex.h @@ -9,8 +9,13 @@ #define _ASM_MUTEX_H /* * On pre-ARMv6 hardware this results in a swp-based implementation, - * which is the most efficient. For ARMv6+, we emit a pair of exclusive - * accesses instead. + * which is the most efficient. For ARMv6+, we have exclusive memory + * accessors and use atomic_dec to avoid the extra xchg operations + * on the locking slowpaths. */ +#if __LINUX_ARM_ARCH__ < 6 #include +#else +#include +#endif #endif -- cgit v1.2.3 From 678708d95daa7d29ad5f49944f1b5385e3f27401 Mon Sep 17 00:00:00 2001 From: Jihoon Bang Date: Tue, 19 Jun 2012 16:12:00 -0700 Subject: WAR: gr3d: limit 3d clock when camera is on As WAR, limit 3d clock frequency and emc clock frequency when camera is on and chip is AP37. 3d clock is set to 361MHz and 437MHz is requested for emc clock with this change. This change allows 3d to request 1.1V in Core instead of 1.3V in AP37. Bug 1001262 Bug 1019309 Change-Id: I9f46f93d8da0fcf5afe05839177bf0d6e43a5840 Signed-off-by: Jihoon Bang Reviewed-on: http://git-master/r/130945 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani Tested-by: Bharat Nihalani --- arch/arm/mach-tegra/board-cardhu.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c index d2b996009165..e0b84ae06976 100644 --- a/arch/arm/mach-tegra/board-cardhu.c +++ b/arch/arm/mach-tegra/board-cardhu.c @@ -45,6 +45,7 @@ #include #include #include +#include #include #include @@ -628,11 +629,28 @@ static void __init cardhu_uart_init(void) ARRAY_SIZE(cardhu_uart_devices)); } +static struct tegra_camera_platform_data tegra_camera_pdata = { + .limit_3d_emc_clk = false, +}; + static struct platform_device tegra_camera = { .name = "tegra_camera", + .dev = { + .platform_data = &tegra_camera_pdata, + }, .id = -1, }; +static void tegra_camera_init(void) +{ + /* For AP37 platform, limit 3d and emc freq when camera is ON */ + if (TEGRA_REVISION_A03 == tegra_get_revision() && + 0xA0 == tegra_sku_id()) + tegra_camera_pdata.limit_3d_emc_clk = true; + else + tegra_camera_pdata.limit_3d_emc_clk = false; +} + static struct platform_device *cardhu_spi_devices[] __initdata = { &tegra_spi_device4, }; @@ -1422,6 +1440,7 @@ static void __init tegra_cardhu_init(void) cardhu_edp_init(); #endif cardhu_uart_init(); + tegra_camera_init(); platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices)); tegra_ram_console_debug_init(); tegra_io_dpd_init(); -- cgit v1.2.3 From b3595d04747d71e494bc0dbc64175d9645d193ad Mon Sep 17 00:00:00 2001 From: Sumit Bhattacharya Date: Tue, 11 Sep 2012 21:02:58 +0530 Subject: Revert "ARM: tegra: cardhu: set I2S as slave mode" This reverts commit 616ade39df296b2c60d8ce74c719bc560f78f598. Bug 1046372 Change-Id: I1e8554f773e6af459f50658b683eafb2b0160f64 Signed-off-by: Sumit Bhattacharya Reviewed-on: http://git-master/r/131458 Reviewed-by: Varun Colbert Tested-by: Varun Colbert --- arch/arm/mach-tegra/board-cardhu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c index e0b84ae06976..7c3c81c8821a 100644 --- a/arch/arm/mach-tegra/board-cardhu.c +++ b/arch/arm/mach-tegra/board-cardhu.c @@ -751,7 +751,7 @@ static struct tegra_asoc_platform_data cardhu_audio_wm8903_pdata = { .gpio_ext_mic_en = -1, .i2s_param[HIFI_CODEC] = { .audio_port_id = 0, - .is_i2s_master = 0, + .is_i2s_master = 1, .i2s_mode = TEGRA_DAIFMT_I2S, }, .i2s_param[BASEBAND] = { -- cgit v1.2.3 From 441a643006ba7368494a13a44223ef85cc041c78 Mon Sep 17 00:00:00 2001 From: Petlozu Pravareshwar Date: Wed, 12 Sep 2012 15:12:36 +0530 Subject: arm: tegra: usb_phy: set vbus_reg to NULL Setting vbus_reg to NULL if regulator get fails. Bug 1047065 Change-Id: I574f58d46f226d70034a4f363103fd9763482292 Signed-off-by: Petlozu Pravareshwar Reviewed-on: http://git-master/r/131759 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty --- arch/arm/mach-tegra/usb_phy.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c index 9288144a1e11..2a7364c12753 100644 --- a/arch/arm/mach-tegra/usb_phy.c +++ b/arch/arm/mach-tegra/usb_phy.c @@ -315,6 +315,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct platform_device *pdev) instance : %d\n", PTR_ERR(phy->vbus_reg), phy->inst); err = PTR_ERR(phy->vbus_reg); + phy->vbus_reg = NULL; goto fail_init; } } else { -- cgit v1.2.3 From 4c12e7369dcd7789ff2477279e28a792dca2eac7 Mon Sep 17 00:00:00 2001 From: Wen Yi Date: Tue, 21 Aug 2012 17:04:48 -0700 Subject: arm: tegra: raise cpu floor when display is on When device is idle and display is on, the minimal cpu frequency can drop to 51mhz. Since it takes several tens of millisecond to ramp up cpu freq, the delay impact negatively the performance of low latency CPU bound tasks. Given the power savings of several milliwatts running cpu at 51mhz comparing to 102mhz or 204 mhz at idle, the idle cpu freq is hence raised to 102mhz for smart panel device and 204mhz for dump panel devices. Bug 1036216 Change-Id: Ifb0ed88d4c5fcf5b637d09c587322cec72b8a08d Signed-off-by: Wen Yi (cherry picked from commit c8465feffcd0cf2401bbd6c6f535955dd68bda55) Reviewed-on: http://git-master/r/132479 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ujjaval Patel Reviewed-by: Bharat Nihalani --- arch/arm/mach-tegra/board-cardhu-power.c | 2 ++ arch/arm/mach-tegra/board-enterprise-power.c | 1 + arch/arm/mach-tegra/pm.c | 9 ++++++--- arch/arm/mach-tegra/pm.h | 11 +++++++++++ 4 files changed, 20 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu-power.c b/arch/arm/mach-tegra/board-cardhu-power.c index e76cbc458914..677b38347514 100644 --- a/arch/arm/mach-tegra/board-cardhu-power.c +++ b/arch/arm/mach-tegra/board-cardhu-power.c @@ -1191,6 +1191,8 @@ int __init cardhu_suspend_init(void) cardhu_suspend_data.lp1_core_volt_high = 0x50; } #endif + if (is_display_board_dsi(display_board_info.board_id)) + cardhu_suspend_data.cpu_wake_freq = CPU_WAKE_FREQ_LOW; case BOARD_PM305: case BOARD_PM311: break; diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index c154841eba93..3475452adc5a 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -822,6 +822,7 @@ static struct tegra_suspend_platform_data enterprise_suspend_data = { .lp1_core_volt_low = 0x1D, .lp1_core_volt_high = 0x33, #endif + .cpu_wake_freq = CPU_WAKE_FREQ_LOW, }; static void enterprise_init_deep_sleep_mode(void) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index b20b51245d50..88dd501689af 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -178,7 +178,6 @@ struct suspend_context tegra_sctx; #define MC_SECURITY_SIZE 0x70 #define MC_SECURITY_CFG2 0x7c -#define AWAKE_CPU_FREQ_MIN 51000 static struct pm_qos_request_list awake_cpu_freq_req; struct dvfs_rail *tegra_cpu_rail; @@ -1105,13 +1104,17 @@ void __init tegra_init_suspend(struct tegra_suspend_platform_data *plat) u32 reg; u32 mode; + if (plat->cpu_wake_freq == 0) + plat->cpu_wake_freq = CPU_WAKE_FREQ_HIGH; + tegra_cpu_rail = tegra_dvfs_get_rail_by_name("vdd_cpu"); tegra_core_rail = tegra_dvfs_get_rail_by_name("vdd_core"); pm_qos_add_request(&awake_cpu_freq_req, PM_QOS_CPU_FREQ_MIN, - AWAKE_CPU_FREQ_MIN); + plat->cpu_wake_freq); tegra_pclk = clk_get_sys(NULL, "pclk"); BUG_ON(IS_ERR(tegra_pclk)); + pdata = plat; (void)reg; (void)mode; @@ -1383,7 +1386,7 @@ static void pm_late_resume(struct early_suspend *h) { if (clk_wake) clk_enable(clk_wake); - pm_qos_update_request(&awake_cpu_freq_req, (s32)AWAKE_CPU_FREQ_MIN); + pm_qos_update_request(&awake_cpu_freq_req, (s32)pdata->cpu_wake_freq); } static struct early_suspend pm_early_suspender = { diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 5ea2b7f843a2..401c0aaf061f 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -33,6 +33,16 @@ #define PMC_SCRATCH1 0x54 #define PMC_SCRATCH4 0x60 +/* The following two constants are for setting the CPU freq + * floor when display is on. 204000Khz is for tablet and + * 102000KHz is for phones. The reason for different values + * for tablet and phone is due to phones usually have smart + * displays that requires less CPU activity for refreshing + * the screen + */ + +#define CPU_WAKE_FREQ_HIGH 204000 +#define CPU_WAKE_FREQ_LOW 102000 enum tegra_suspend_mode { TEGRA_SUSPEND_NONE = 0, TEGRA_SUSPEND_LP2, /* CPU voltage off */ @@ -73,6 +83,7 @@ struct tegra_suspend_platform_data { unsigned int lp1_core_volt_low; unsigned int lp1_core_volt_high; #endif + int cpu_wake_freq; }; /* clears io dpd settings before kernel code */ -- cgit v1.2.3 From a17f13d2678106114e447dc22aefff5f6aba5e9e Mon Sep 17 00:00:00 2001 From: Matt Pedro Date: Sun, 30 Sep 2012 18:49:22 -0400 Subject: ARM: tegra: Fix missing functions in gpio header Fix the missing tegra_gpio enable/disable function defitintions. Change-Id: I82ed085bd67486d5e9c383a8c26243e2c1edf670 Signed-off-by: Matt Pedro Reviewed-on: http://git-master/r/140026 Reviewed-by: Automatic_Commit_Validation_User --- arch/arm/mach-tegra/include/mach/gpio.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/include/mach/gpio.h b/arch/arm/mach-tegra/include/mach/gpio.h index 031179a3259d..b7357ab0c4dd 100644 --- a/arch/arm/mach-tegra/include/mach/gpio.h +++ b/arch/arm/mach-tegra/include/mach/gpio.h @@ -71,6 +71,8 @@ struct tegra_gpio_table { }; void tegra_gpio_config(struct tegra_gpio_table *table, int num); +void tegra_gpio_enable(int gpio); +void tegra_gpio_disable(int gpio); int tegra_gpio_resume_init(void); void tegra_gpio_init_configure(unsigned gpio, bool is_input, int value); void tegra_gpio_set_tristate(int gpio, enum tegra_tristate ts); -- cgit v1.2.3 From dca35e304167aac14110b877cafa68a93d3f0a32 Mon Sep 17 00:00:00 2001 From: Matt Pedro Date: Sun, 30 Sep 2012 21:27:12 -0400 Subject: ARM: tegra: fix-up definition by adding 'static' Fix up the definition of the tegra_gpio enable/disable. Change-Id: Id71242690efa3e5994a4b70089826f2b87997ece Signed-off-by: Matt Pedro Reviewed-on: http://git-master/r/140036 Reviewed-by: Automatic_Commit_Validation_User --- arch/arm/mach-tegra/include/mach/gpio.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/include/mach/gpio.h b/arch/arm/mach-tegra/include/mach/gpio.h index b7357ab0c4dd..aa0495fc6327 100644 --- a/arch/arm/mach-tegra/include/mach/gpio.h +++ b/arch/arm/mach-tegra/include/mach/gpio.h @@ -71,8 +71,8 @@ struct tegra_gpio_table { }; void tegra_gpio_config(struct tegra_gpio_table *table, int num); -void tegra_gpio_enable(int gpio); -void tegra_gpio_disable(int gpio); +static void tegra_gpio_enable(int gpio); +static void tegra_gpio_disable(int gpio); int tegra_gpio_resume_init(void); void tegra_gpio_init_configure(unsigned gpio, bool is_input, int value); void tegra_gpio_set_tristate(int gpio, enum tegra_tristate ts); -- cgit v1.2.3 From f87537ce06430905a822ff16e75cb51aacac50ee Mon Sep 17 00:00:00 2001 From: Matt Pedro Date: Mon, 1 Oct 2012 11:44:42 -0400 Subject: ARM: tegra: fix-up tegra_gpio enable/diablse defs Clean-up the definition of the tegra_gpio enable/disable so that it compares to the l4t r16 rel. Change-Id: Ia8584ada1e2a728d2784d6d57c72ed4b0ee01cf1 Signed-off-by: Matt Pedro Reviewed-on: http://git-master/r/140648 Reviewed-by: Automatic_Commit_Validation_User --- arch/arm/mach-tegra/include/mach/gpio.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/include/mach/gpio.h b/arch/arm/mach-tegra/include/mach/gpio.h index aa0495fc6327..b7357ab0c4dd 100644 --- a/arch/arm/mach-tegra/include/mach/gpio.h +++ b/arch/arm/mach-tegra/include/mach/gpio.h @@ -71,8 +71,8 @@ struct tegra_gpio_table { }; void tegra_gpio_config(struct tegra_gpio_table *table, int num); -static void tegra_gpio_enable(int gpio); -static void tegra_gpio_disable(int gpio); +void tegra_gpio_enable(int gpio); +void tegra_gpio_disable(int gpio); int tegra_gpio_resume_init(void); void tegra_gpio_init_configure(unsigned gpio, bool is_input, int value); void tegra_gpio_set_tristate(int gpio, enum tegra_tristate ts); -- cgit v1.2.3 From ad99dcd0cf6a0984d5a6102c986bde247a096df6 Mon Sep 17 00:00:00 2001 From: Shashank Sharma Date: Tue, 7 Aug 2012 12:15:06 +0530 Subject: arm: tegra: cardhu: Reserve 16MB on RAM for HDMI Reserve 16MB for HDMI maximum possible resolution (1920x1080) at 32 bpp and double buffering. Change-Id: Id719a875b805723758485f970ab9e2f1a28ed19b Signed-off-by: Shashank Sharma Reviewed-on: http://git-master/r/121562 (cherry picked from commit d376bc491a460353124adc0f2be8612add0d8e76) Reviewed-on: http://git-master/r/140032 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro Tested-by: Matthew Pedro Reviewed-by: Winnie Hsu --- arch/arm/mach-tegra/board-cardhu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c index 7c3c81c8821a..e14e6b25d644 100644 --- a/arch/arm/mach-tegra/board-cardhu.c +++ b/arch/arm/mach-tegra/board-cardhu.c @@ -1472,8 +1472,8 @@ static void __init tegra_cardhu_init(void) static void __init tegra_cardhu_reserve(void) { #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) - /* support 1920X1200 with 24bpp */ - tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M); + /* Support 1920X1080 32bpp,double buffered on HDMI*/ + tegra_reserve(0, SZ_8M + SZ_1M, SZ_16M); #else tegra_reserve(SZ_128M, SZ_8M, SZ_8M); #endif -- cgit v1.2.3 From 442fa75f3eee2b2650623201ce8e52ae0a5a96d3 Mon Sep 17 00:00:00 2001 From: Mursalin Akon Date: Fri, 7 Sep 2012 11:30:32 -0700 Subject: config: use CFG80211 for bcmdhd CFG80211 is needed for WFD. So, use CFG80211, instead of, WEXT in bcmdhd driver. Bug 1029792 Bug 1029733 Change-Id: I81d99a821429f3be8400355faa5bee14904c0944 Signed-off-by: Mursalin Akon Reviewed-on: http://git-master/r/141630 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Matthew Pedro GVS: Gerrit_Virtual_Submit --- arch/arm/configs/tegra3_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/configs/tegra3_defconfig b/arch/arm/configs/tegra3_defconfig index 95ca04c1832a..82cb7b2501cb 100644 --- a/arch/arm/configs/tegra3_defconfig +++ b/arch/arm/configs/tegra3_defconfig @@ -184,6 +184,8 @@ CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_LL=y CONFIG_BT_BLUESLEEP=y CONFIG_CFG80211=y +CONFIG_LIB80211=m +CONFIG_MAC80211=m CONFIG_RFKILL=y CONFIG_CAIF=y CONFIG_NFC=y @@ -230,7 +232,7 @@ CONFIG_BCM4329_WIFI_CONTROL_FUNC=y CONFIG_BCMDHD=m CONFIG_BCMDHD_FW_DIR="/lib/firmware" CONFIG_BCMDHD_NVRAM_DIR="/lib/firmware" -CONFIG_BCMDHD_WEXT=y +CONFIG_BCMDHD_CFG80211=y CONFIG_BCMDHD_WIFI_CONTROL_FUNC=y CONFIG_BCMDHD_HW_OOB=y CONFIG_USB_CATC=y -- cgit v1.2.3 From 49eac6c2664809abd41c0b0b368ab093bcf5a783 Mon Sep 17 00:00:00 2001 From: Mursalin Akon Date: Tue, 11 Sep 2012 14:50:03 -0700 Subject: enabling P2P for bcmdhd driver Bug 1029792 Change-Id: I8ee7190ccd50863f6f0f1aa216035afbae57ebcf Signed-off-by: Mursalin Akon Reviewed-on: http://git-master/r/141631 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Matthew Pedro GVS: Gerrit_Virtual_Submit --- arch/arm/configs/tegra3_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/tegra3_defconfig b/arch/arm/configs/tegra3_defconfig index 82cb7b2501cb..41c39818ee70 100644 --- a/arch/arm/configs/tegra3_defconfig +++ b/arch/arm/configs/tegra3_defconfig @@ -232,6 +232,7 @@ CONFIG_BCM4329_WIFI_CONTROL_FUNC=y CONFIG_BCMDHD=m CONFIG_BCMDHD_FW_DIR="/lib/firmware" CONFIG_BCMDHD_NVRAM_DIR="/lib/firmware" +CONFIG_DHD_ENABLE_P2P=y CONFIG_BCMDHD_CFG80211=y CONFIG_BCMDHD_WIFI_CONTROL_FUNC=y CONFIG_BCMDHD_HW_OOB=y -- cgit v1.2.3 From 1a2a5beb5de03cb58e4a37fa72193a8e662e9b22 Mon Sep 17 00:00:00 2001 From: Preetham Chandru R Date: Fri, 5 Oct 2012 18:25:50 +0530 Subject: ARM: tegra: ventana: disable usb1 vbus gpio disable the usb1 vbus gpio in kernel and not depend on bootloader to disable the vbus initially. Currently, the kernel enables and disables the vbus when the otg is configured to host mode, but when the system boots with no cable connected the kernel relies on the bootloader to turn the vbus off. This CL removes that dependency. Bug 1047048 Signed-off-by: Preetham Chandru R Reviewed-on: http://git-master/r/#change,141970 (cherry picked from commit c3461995dd156968d766ec05879fd1097221ceb8) Change-Id: I96c1f4b97a2cafdfd498b591647200d26298a43b Reviewed-on: http://git-master/r/142839 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kiran Adduri GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro --- arch/arm/mach-tegra/board-ventana-pinmux.c | 1 + arch/arm/mach-tegra/board-ventana.h | 3 +++ 2 files changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-ventana-pinmux.c b/arch/arm/mach-tegra/board-ventana-pinmux.c index eb371384ed4c..43b4b75878a2 100644 --- a/arch/arm/mach-tegra/board-ventana-pinmux.c +++ b/arch/arm/mach-tegra/board-ventana-pinmux.c @@ -181,6 +181,7 @@ static struct tegra_gpio_table gpio_table[] = { { .gpio = TEGRA_GPIO_HP_DET, .enable = true }, { .gpio = TEGRA_GPIO_INT_MIC_EN, .enable = true }, { .gpio = TEGRA_GPIO_EXT_MIC_EN, .enable = true }, + { .gpio = TEGRA_GPIO_USB1_VBUS, .enable = false }, }; int __init ventana_pinmux_init(void) diff --git a/arch/arm/mach-tegra/board-ventana.h b/arch/arm/mach-tegra/board-ventana.h index b8d8040d187b..8ebf4c9b3c4a 100644 --- a/arch/arm/mach-tegra/board-ventana.h +++ b/arch/arm/mach-tegra/board-ventana.h @@ -87,6 +87,9 @@ int ventana_cam_fixed_voltage_regulator_init(void); #define TEGRA_GPIO_INT_MIC_EN TEGRA_GPIO_PX0 #define TEGRA_GPIO_EXT_MIC_EN TEGRA_GPIO_PX1 +/* Usb1 vbus GPIO */ +#define TEGRA_GPIO_USB1_VBUS TEGRA_GPIO_PD0 + /* AC detect GPIO */ #define AC_PRESENT_GPIO TEGRA_GPIO_PV3 -- cgit v1.2.3 From b0935d3914c6a01349eaacce08d28620e7b78f6f Mon Sep 17 00:00:00 2001 From: Preetham Chandru R Date: Wed, 10 Oct 2012 15:37:28 +0530 Subject: ARM: tegra: rename fuse driver The fuse driver registers parameters and thus create a /sys/module/fuse directory which collides with the fuse filesystem driver. Rename fuse.c to tegra-fuse.c to fix this. Bug 1058350 Change-Id: I5201bc43fcb44df8181085322bc40d1f6e99bf93 Signed-off-by: Marc Dietrich Signed-off-by: Preetham Chandru R Reviewed-on: http://git-master/r/143206 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Stephen Warren GVS: Gerrit_Virtual_Submit Reviewed-by: Dan Willemsen Reviewed-by: Matthew Pedro --- arch/arm/mach-tegra/Makefile | 2 +- arch/arm/mach-tegra/fuse.c | 461 --------------------------------------- arch/arm/mach-tegra/tegra_fuse.c | 461 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 462 insertions(+), 462 deletions(-) delete mode 100644 arch/arm/mach-tegra/fuse.c create mode 100644 arch/arm/mach-tegra/tegra_fuse.c (limited to 'arch') diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 3aa3e32848f8..85e1964a2284 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -39,7 +39,7 @@ AFLAGS_sleep.o :=-Wa,-march=armv7-a$(plus_sec) obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-t2.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-t3.o -obj-y += fuse.o +obj-y += tegra_fuse.o obj-y += kfuse.o obj-y += csi.o obj-$(CONFIG_TEGRA_SILICON_PLATFORM) += tegra_odm_fuses.o diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c deleted file mode 100644 index bb7c242ef47e..000000000000 --- a/arch/arm/mach-tegra/fuse.c +++ /dev/null @@ -1,461 +0,0 @@ -/* - * arch/arm/mach-tegra/fuse.c - * - * Copyright (C) 2010 Google, Inc. - * Copyright (C) 2010-2012 NVIDIA Corp. - * - * Author: - * Colin Cross - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "fuse.h" -#include "apbio.h" - -#define FUSE_SKU_INFO 0x110 -#if defined(CONFIG_ARCH_TEGRA_2x_SOC) -#define FUSE_UID_LOW 0x108 -#define FUSE_UID_HIGH 0x10c -#define FUSE_SPARE_BIT 0x200 -#else -#define FUSE_VENDOR_CODE 0x200 -#define FUSE_VENDOR_CODE_MASK 0xf -#define FUSE_FAB_CODE 0x204 -#define FUSE_FAB_CODE_MASK 0x3f -#define FUSE_LOT_CODE_0 0x208 -#define FUSE_LOT_CODE_1 0x20c -#define FUSE_WAFER_ID 0x210 -#define FUSE_WAFER_ID_MASK 0x3f -#define FUSE_X_COORDINATE 0x214 -#define FUSE_X_COORDINATE_MASK 0x1ff -#define FUSE_Y_COORDINATE 0x218 -#define FUSE_Y_COORDINATE_MASK 0x1ff -#define FUSE_GPU_INFO 0x390 -#define FUSE_GPU_INFO_MASK (1<<2) -#define FUSE_SPARE_BIT 0x244 -/* fuse registers used in public fuse data read API */ -#define FUSE_TEST_PROGRAM_REVISION_0 0x128 -/* fuse spare bits are used to get Tj-ADT values */ -#define FUSE_SPARE_BIT_0_0 0x244 -#define NUM_TSENSOR_SPARE_BITS 28 -/* tsensor calibration register */ -#define FUSE_TSENSOR_CALIB_0 0x198 - -#endif - -#define TEGRA_AGE_0_6 0x2cc /*Spare bit 34*/ -#define TEGRA_AGE_1_6 0x308 /*Spare bit 49*/ -#define TEGRA_AGE_0_5 0x2c8 /*Spare bit 33*/ -#define TEGRA_AGE_1_5 0x304 /*Spare bit 48*/ -#define TEGRA_AGE_0_4 0x2c4 /*Spare bit 32*/ -#define TEGRA_AGE_1_4 0x300 /*Spare bit 47*/ -#define TEGRA_AGE_0_3 0x2c0 /*Spare bit 31*/ -#define TEGRA_AGE_1_3 0x2fc /*Spare bit 46*/ -#define TEGRA_AGE_0_2 0x2bc /*Spare bit 30*/ -#define TEGRA_AGE_1_2 0x2f8 /*Spare bit 45*/ -#define TEGRA_AGE_0_1 0x2b8 /*Spare bit 29*/ -#define TEGRA_AGE_1_1 0x2f4 /*Spare bit 44*/ -#define TEGRA_AGE_0_0 0x2b4 /*Spare bit 28*/ -#define TEGRA_AGE_1_0 0x2f0 /*Spare bit 43*/ - -struct tegra_id { - enum tegra_chipid chipid; - unsigned int major, minor, netlist, patch; - enum tegra_revision revision; - char *priv; -}; - -static struct tegra_id tegra_id; - -static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { - [TEGRA_REVISION_UNKNOWN] = "unknown", - [TEGRA_REVISION_A01] = "A01", - [TEGRA_REVISION_A02] = "A02", - [TEGRA_REVISION_A03] = "A03", - [TEGRA_REVISION_A03p] = "A03 prime", - [TEGRA_REVISION_A04] = "A04", - [TEGRA_REVISION_A04p] = "A04 prime", -}; - -u32 tegra_fuse_readl(unsigned long offset) -{ - return tegra_apb_readl(TEGRA_FUSE_BASE + offset); -} - -void tegra_fuse_writel(u32 value, unsigned long offset) -{ - tegra_apb_writel(value, TEGRA_FUSE_BASE + offset); -} - -static inline bool get_spare_fuse(int bit) -{ - return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4); -} - -const char *tegra_get_revision_name(void) -{ - return tegra_revision_name[tegra_get_revision()]; -} - -void tegra_init_fuse(void) -{ - u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48)); - reg |= 1 << 28; - writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48)); - tegra_init_speedo_data(); - - pr_info("Tegra Revision: %s " - "SKU: 0x%x CPU Process: %d Core Process: %d\n", - tegra_get_revision_name(), tegra_sku_id(), - tegra_cpu_process_id(), tegra_core_process_id()); -} - -#ifdef CONFIG_ARCH_TEGRA_2x_SOC -int tegra_fuse_get_revision(u32 *rev) -{ - return -ENOENT; -} -EXPORT_SYMBOL(tegra_fuse_get_revision); - -int tegra_fuse_get_tsensor_calibration_data(u32 *calib) -{ - return -ENOENT; -} -EXPORT_SYMBOL(tegra_fuse_get_tsensor_calibration_data); - -int tegra_fuse_get_tsensor_spare_bits(u32 *spare_bits) -{ - return -ENOENT; -} -EXPORT_SYMBOL(tegra_fuse_get_tsensor_spare_bits); - -#else - -int tegra_fuse_get_revision(u32 *rev) -{ - /* fuse revision */ - *rev = tegra_fuse_readl(FUSE_TEST_PROGRAM_REVISION_0); - return 0; -} -EXPORT_SYMBOL(tegra_fuse_get_revision); - -int tegra_fuse_get_tsensor_calibration_data(u32 *calib) -{ - /* tsensor calibration fuse */ - *calib = tegra_fuse_readl(FUSE_TSENSOR_CALIB_0); - return 0; -} -EXPORT_SYMBOL(tegra_fuse_get_tsensor_calibration_data); - -int tegra_fuse_get_tsensor_spare_bits(u32 *spare_bits) -{ - u32 value; - int i; - - BUG_ON(NUM_TSENSOR_SPARE_BITS > (sizeof(u32) * 8)); - if (!spare_bits) - return -ENOMEM; - *spare_bits = 0; - /* spare bits 0-27 */ - for (i = 0; i < NUM_TSENSOR_SPARE_BITS; i++) { - value = tegra_fuse_readl(FUSE_SPARE_BIT_0_0 + - (i << 2)); - if (value) - *spare_bits |= BIT(i); - } - return 0; -} -EXPORT_SYMBOL(tegra_fuse_get_tsensor_spare_bits); -#endif - -#define TEGRA_READ_AGE_BIT(n, bit, age) {\ - bit = tegra_fuse_readl(TEGRA_AGE_0_##n);\ - bit |= tegra_fuse_readl(TEGRA_AGE_1_##n);\ - bit = bit << n;\ - age |= bit;\ -} - -int tegra_get_age(void) -{ - int linear_age, age_bit; - linear_age = age_bit = 0; - - TEGRA_READ_AGE_BIT(6, age_bit, linear_age); - TEGRA_READ_AGE_BIT(5, age_bit, linear_age); - TEGRA_READ_AGE_BIT(4, age_bit, linear_age); - TEGRA_READ_AGE_BIT(3, age_bit, linear_age); - TEGRA_READ_AGE_BIT(2, age_bit, linear_age); - TEGRA_READ_AGE_BIT(1, age_bit, linear_age); - TEGRA_READ_AGE_BIT(0, age_bit, linear_age); - - /*Default Aug, 2012*/ - if (linear_age <= 0) - linear_age = 8; - - pr_info("TEGRA: Linear age: %d\n", linear_age); - - return linear_age; -} - -unsigned long long tegra_chip_uid(void) -{ -#if defined(CONFIG_ARCH_TEGRA_2x_SOC) - unsigned long long lo, hi; - - lo = tegra_fuse_readl(FUSE_UID_LOW); - hi = tegra_fuse_readl(FUSE_UID_HIGH); - return (hi << 32ull) | lo; -#else - u64 uid = 0ull; - u32 reg; - u32 cid; - u32 vendor; - u32 fab; - u32 lot; - u32 wafer; - u32 x; - u32 y; - u32 i; - - /* This used to be so much easier in prior chips. Unfortunately, there - is no one-stop shopping for the unique id anymore. It must be - constructed from various bits of information burned into the fuses - during the manufacturing process. The 64-bit unique id is formed - by concatenating several bit fields. The notation used for the - various fields is with the UID composed - thusly: - - - - Where: - - Field Bits Position Data - ------- ---- -------- ---------------------------------------- - CID 4 60 Chip id (encoded as zero for T30) - VENDOR 4 56 Vendor code - FAB 6 50 FAB code - LOT 26 24 Lot code (5-digit base-36-coded-decimal, - re-encoded to 26 bits binary) - WAFER 6 18 Wafer id - X 9 9 Wafer X-coordinate - Y 9 0 Wafer Y-coordinate - ------- ---- - Total 64 - */ - - /* Get the chip id and encode each chip variant as a unique value. */ - reg = readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + 0x804)); - reg = (reg & 0xFF00) >> 8; - - switch (reg) { - case TEGRA_CHIPID_TEGRA3: - cid = 0; - break; - - default: - BUG(); - break; - } - - vendor = tegra_fuse_readl(FUSE_VENDOR_CODE) & FUSE_VENDOR_CODE_MASK; - fab = tegra_fuse_readl(FUSE_FAB_CODE) & FUSE_FAB_CODE_MASK; - - /* Lot code must be re-encoded from a 5 digit base-36 'BCD' number - to a binary number. */ - lot = 0; - reg = tegra_fuse_readl(FUSE_LOT_CODE_0) << 2; - - for (i = 0; i < 5; ++i) { - u32 digit = (reg & 0xFC000000) >> 26; - BUG_ON(digit >= 36); - lot *= 36; - lot += digit; - reg <<= 6; - } - - wafer = tegra_fuse_readl(FUSE_WAFER_ID) & FUSE_WAFER_ID_MASK; - x = tegra_fuse_readl(FUSE_X_COORDINATE) & FUSE_X_COORDINATE_MASK; - y = tegra_fuse_readl(FUSE_Y_COORDINATE) & FUSE_Y_COORDINATE_MASK; - - uid = ((unsigned long long)cid << 60ull) - | ((unsigned long long)vendor << 56ull) - | ((unsigned long long)fab << 50ull) - | ((unsigned long long)lot << 24ull) - | ((unsigned long long)wafer << 18ull) - | ((unsigned long long)x << 9ull) - | ((unsigned long long)y << 0ull); - return uid; -#endif -} - -unsigned int tegra_spare_fuse(int bit) -{ - BUG_ON(bit < 0 || bit > 61); - return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4); -} - -int tegra_sku_id(void) -{ - static int sku_id = -1; - if (sku_id == -1) { - u32 reg = tegra_fuse_readl(FUSE_SKU_INFO); - sku_id = reg & 0xFF; - } - return sku_id; -} - -int tegra_gpu_register_sets(void) -{ -#ifdef CONFIG_ARCH_TEGRA_HAS_DUAL_3D - u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + FUSE_GPU_INFO)); - if (reg & FUSE_GPU_INFO_MASK) - return 1; - else - return 2; -#else - return 1; -#endif -} - -struct chip_revision { - enum tegra_chipid chipid; - unsigned int major; - unsigned int minor; - char prime; - enum tegra_revision revision; -}; - -#define CHIP_REVISION(id, m, n, p, rev) { \ - .chipid = TEGRA_CHIPID_##id, \ - .major = m, \ - .minor = n, \ - .prime = p, \ - .revision = TEGRA_REVISION_##rev } - -static struct chip_revision tegra_chip_revisions[] = { - CHIP_REVISION(TEGRA2, 1, 2, 0, A02), - CHIP_REVISION(TEGRA2, 1, 3, 0, A03), - CHIP_REVISION(TEGRA2, 1, 3, 'p', A03p), - CHIP_REVISION(TEGRA2, 1, 4, 0, A04), - CHIP_REVISION(TEGRA2, 1, 4, 'p', A04p), - CHIP_REVISION(TEGRA3, 1, 1, 0, A01), - CHIP_REVISION(TEGRA3, 1, 2, 0, A02), - CHIP_REVISION(TEGRA3, 1, 3, 0, A03), -}; - -static enum tegra_revision tegra_decode_revision(const struct tegra_id *id) -{ - enum tegra_revision revision = TEGRA_REVISION_UNKNOWN; - -#if defined(CONFIG_TEGRA_SILICON_PLATFORM) - int i ; - char prime; - - if (id->priv == NULL) - prime = 0; - else - prime = *(id->priv); - - for (i = 0; i < ARRAY_SIZE(tegra_chip_revisions); i++) { - if ((id->chipid != tegra_chip_revisions[i].chipid) || - (id->minor != tegra_chip_revisions[i].minor) || - (id->major != tegra_chip_revisions[i].major) || - (prime != tegra_chip_revisions[i].prime)) - continue; - - revision = tegra_chip_revisions[i].revision; - break; - } -#endif - - return revision; -} - -static void tegra_set_tegraid(u32 chipid, - u32 major, u32 minor, - u32 nlist, u32 patch, const char *priv) -{ - tegra_id.chipid = (enum tegra_chipid) chipid; - tegra_id.major = major; - tegra_id.minor = minor; - tegra_id.netlist = nlist; - tegra_id.patch = patch; - tegra_id.priv = (char *)priv; - tegra_id.revision = tegra_decode_revision(&tegra_id); -} - -static void tegra_get_tegraid_from_hw(void) -{ - void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804; - void __iomem *netlist = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x860; - u32 cid = readl(chip_id); - u32 nlist = readl(netlist); - char *priv = NULL; - -#ifdef CONFIG_ARCH_TEGRA_2x_SOC - if (get_spare_fuse(18) || get_spare_fuse(19)) - priv = "p"; -#endif - tegra_set_tegraid((cid >> 8) & 0xff, - (cid >> 4) & 0xf, - (cid >> 16) & 0xf, - (nlist >> 0) & 0xffff, - (nlist >> 16) & 0xffff, - priv); -} - -enum tegra_chipid tegra_get_chipid(void) -{ - if (tegra_id.chipid == TEGRA_CHIPID_UNKNOWN) - tegra_get_tegraid_from_hw(); - - return tegra_id.chipid; -} - -enum tegra_revision tegra_get_revision(void) -{ - if (tegra_id.chipid == TEGRA_CHIPID_UNKNOWN) - tegra_get_tegraid_from_hw(); - - return tegra_id.revision; -} - -static int get_chip_id(char *val, const struct kernel_param *kp) -{ - return param_get_uint(val, kp); -} - -static int get_revision(char *val, const struct kernel_param *kp) -{ - return param_get_uint(val, kp); -} - -static struct kernel_param_ops tegra_chip_id_ops = { - .get = get_chip_id, -}; - -static struct kernel_param_ops tegra_revision_ops = { - .get = get_revision, -}; - -module_param_cb(tegra_chip_id, &tegra_chip_id_ops, &tegra_id.chipid, 0444); -module_param_cb(tegra_chip_rev, &tegra_revision_ops, &tegra_id.revision, 0444); diff --git a/arch/arm/mach-tegra/tegra_fuse.c b/arch/arm/mach-tegra/tegra_fuse.c new file mode 100644 index 000000000000..11328c4cada3 --- /dev/null +++ b/arch/arm/mach-tegra/tegra_fuse.c @@ -0,0 +1,461 @@ +/* + * arch/arm/mach-tegra/tegra_fuse.c + * + * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2010-2012 NVIDIA Corp. + * + * Author: + * Colin Cross + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "fuse.h" +#include "apbio.h" + +#define FUSE_SKU_INFO 0x110 +#if defined(CONFIG_ARCH_TEGRA_2x_SOC) +#define FUSE_UID_LOW 0x108 +#define FUSE_UID_HIGH 0x10c +#define FUSE_SPARE_BIT 0x200 +#else +#define FUSE_VENDOR_CODE 0x200 +#define FUSE_VENDOR_CODE_MASK 0xf +#define FUSE_FAB_CODE 0x204 +#define FUSE_FAB_CODE_MASK 0x3f +#define FUSE_LOT_CODE_0 0x208 +#define FUSE_LOT_CODE_1 0x20c +#define FUSE_WAFER_ID 0x210 +#define FUSE_WAFER_ID_MASK 0x3f +#define FUSE_X_COORDINATE 0x214 +#define FUSE_X_COORDINATE_MASK 0x1ff +#define FUSE_Y_COORDINATE 0x218 +#define FUSE_Y_COORDINATE_MASK 0x1ff +#define FUSE_GPU_INFO 0x390 +#define FUSE_GPU_INFO_MASK (1<<2) +#define FUSE_SPARE_BIT 0x244 +/* fuse registers used in public fuse data read API */ +#define FUSE_TEST_PROGRAM_REVISION_0 0x128 +/* fuse spare bits are used to get Tj-ADT values */ +#define FUSE_SPARE_BIT_0_0 0x244 +#define NUM_TSENSOR_SPARE_BITS 28 +/* tsensor calibration register */ +#define FUSE_TSENSOR_CALIB_0 0x198 + +#endif + +#define TEGRA_AGE_0_6 0x2cc /*Spare bit 34*/ +#define TEGRA_AGE_1_6 0x308 /*Spare bit 49*/ +#define TEGRA_AGE_0_5 0x2c8 /*Spare bit 33*/ +#define TEGRA_AGE_1_5 0x304 /*Spare bit 48*/ +#define TEGRA_AGE_0_4 0x2c4 /*Spare bit 32*/ +#define TEGRA_AGE_1_4 0x300 /*Spare bit 47*/ +#define TEGRA_AGE_0_3 0x2c0 /*Spare bit 31*/ +#define TEGRA_AGE_1_3 0x2fc /*Spare bit 46*/ +#define TEGRA_AGE_0_2 0x2bc /*Spare bit 30*/ +#define TEGRA_AGE_1_2 0x2f8 /*Spare bit 45*/ +#define TEGRA_AGE_0_1 0x2b8 /*Spare bit 29*/ +#define TEGRA_AGE_1_1 0x2f4 /*Spare bit 44*/ +#define TEGRA_AGE_0_0 0x2b4 /*Spare bit 28*/ +#define TEGRA_AGE_1_0 0x2f0 /*Spare bit 43*/ + +struct tegra_id { + enum tegra_chipid chipid; + unsigned int major, minor, netlist, patch; + enum tegra_revision revision; + char *priv; +}; + +static struct tegra_id tegra_id; + +static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { + [TEGRA_REVISION_UNKNOWN] = "unknown", + [TEGRA_REVISION_A01] = "A01", + [TEGRA_REVISION_A02] = "A02", + [TEGRA_REVISION_A03] = "A03", + [TEGRA_REVISION_A03p] = "A03 prime", + [TEGRA_REVISION_A04] = "A04", + [TEGRA_REVISION_A04p] = "A04 prime", +}; + +u32 tegra_fuse_readl(unsigned long offset) +{ + return tegra_apb_readl(TEGRA_FUSE_BASE + offset); +} + +void tegra_fuse_writel(u32 value, unsigned long offset) +{ + tegra_apb_writel(value, TEGRA_FUSE_BASE + offset); +} + +static inline bool get_spare_fuse(int bit) +{ + return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4); +} + +const char *tegra_get_revision_name(void) +{ + return tegra_revision_name[tegra_get_revision()]; +} + +void tegra_init_fuse(void) +{ + u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48)); + reg |= 1 << 28; + writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48)); + tegra_init_speedo_data(); + + pr_info("Tegra Revision: %s " + "SKU: 0x%x CPU Process: %d Core Process: %d\n", + tegra_get_revision_name(), tegra_sku_id(), + tegra_cpu_process_id(), tegra_core_process_id()); +} + +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +int tegra_fuse_get_revision(u32 *rev) +{ + return -ENOENT; +} +EXPORT_SYMBOL(tegra_fuse_get_revision); + +int tegra_fuse_get_tsensor_calibration_data(u32 *calib) +{ + return -ENOENT; +} +EXPORT_SYMBOL(tegra_fuse_get_tsensor_calibration_data); + +int tegra_fuse_get_tsensor_spare_bits(u32 *spare_bits) +{ + return -ENOENT; +} +EXPORT_SYMBOL(tegra_fuse_get_tsensor_spare_bits); + +#else + +int tegra_fuse_get_revision(u32 *rev) +{ + /* fuse revision */ + *rev = tegra_fuse_readl(FUSE_TEST_PROGRAM_REVISION_0); + return 0; +} +EXPORT_SYMBOL(tegra_fuse_get_revision); + +int tegra_fuse_get_tsensor_calibration_data(u32 *calib) +{ + /* tsensor calibration fuse */ + *calib = tegra_fuse_readl(FUSE_TSENSOR_CALIB_0); + return 0; +} +EXPORT_SYMBOL(tegra_fuse_get_tsensor_calibration_data); + +int tegra_fuse_get_tsensor_spare_bits(u32 *spare_bits) +{ + u32 value; + int i; + + BUG_ON(NUM_TSENSOR_SPARE_BITS > (sizeof(u32) * 8)); + if (!spare_bits) + return -ENOMEM; + *spare_bits = 0; + /* spare bits 0-27 */ + for (i = 0; i < NUM_TSENSOR_SPARE_BITS; i++) { + value = tegra_fuse_readl(FUSE_SPARE_BIT_0_0 + + (i << 2)); + if (value) + *spare_bits |= BIT(i); + } + return 0; +} +EXPORT_SYMBOL(tegra_fuse_get_tsensor_spare_bits); +#endif + +#define TEGRA_READ_AGE_BIT(n, bit, age) {\ + bit = tegra_fuse_readl(TEGRA_AGE_0_##n);\ + bit |= tegra_fuse_readl(TEGRA_AGE_1_##n);\ + bit = bit << n;\ + age |= bit;\ +} + +int tegra_get_age(void) +{ + int linear_age, age_bit; + linear_age = age_bit = 0; + + TEGRA_READ_AGE_BIT(6, age_bit, linear_age); + TEGRA_READ_AGE_BIT(5, age_bit, linear_age); + TEGRA_READ_AGE_BIT(4, age_bit, linear_age); + TEGRA_READ_AGE_BIT(3, age_bit, linear_age); + TEGRA_READ_AGE_BIT(2, age_bit, linear_age); + TEGRA_READ_AGE_BIT(1, age_bit, linear_age); + TEGRA_READ_AGE_BIT(0, age_bit, linear_age); + + /*Default Aug, 2012*/ + if (linear_age <= 0) + linear_age = 8; + + pr_info("TEGRA: Linear age: %d\n", linear_age); + + return linear_age; +} + +unsigned long long tegra_chip_uid(void) +{ +#if defined(CONFIG_ARCH_TEGRA_2x_SOC) + unsigned long long lo, hi; + + lo = tegra_fuse_readl(FUSE_UID_LOW); + hi = tegra_fuse_readl(FUSE_UID_HIGH); + return (hi << 32ull) | lo; +#else + u64 uid = 0ull; + u32 reg; + u32 cid; + u32 vendor; + u32 fab; + u32 lot; + u32 wafer; + u32 x; + u32 y; + u32 i; + + /* This used to be so much easier in prior chips. Unfortunately, there + is no one-stop shopping for the unique id anymore. It must be + constructed from various bits of information burned into the fuses + during the manufacturing process. The 64-bit unique id is formed + by concatenating several bit fields. The notation used for the + various fields is with the UID composed + thusly: + + + + Where: + + Field Bits Position Data + ------- ---- -------- ---------------------------------------- + CID 4 60 Chip id (encoded as zero for T30) + VENDOR 4 56 Vendor code + FAB 6 50 FAB code + LOT 26 24 Lot code (5-digit base-36-coded-decimal, + re-encoded to 26 bits binary) + WAFER 6 18 Wafer id + X 9 9 Wafer X-coordinate + Y 9 0 Wafer Y-coordinate + ------- ---- + Total 64 + */ + + /* Get the chip id and encode each chip variant as a unique value. */ + reg = readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + 0x804)); + reg = (reg & 0xFF00) >> 8; + + switch (reg) { + case TEGRA_CHIPID_TEGRA3: + cid = 0; + break; + + default: + BUG(); + break; + } + + vendor = tegra_fuse_readl(FUSE_VENDOR_CODE) & FUSE_VENDOR_CODE_MASK; + fab = tegra_fuse_readl(FUSE_FAB_CODE) & FUSE_FAB_CODE_MASK; + + /* Lot code must be re-encoded from a 5 digit base-36 'BCD' number + to a binary number. */ + lot = 0; + reg = tegra_fuse_readl(FUSE_LOT_CODE_0) << 2; + + for (i = 0; i < 5; ++i) { + u32 digit = (reg & 0xFC000000) >> 26; + BUG_ON(digit >= 36); + lot *= 36; + lot += digit; + reg <<= 6; + } + + wafer = tegra_fuse_readl(FUSE_WAFER_ID) & FUSE_WAFER_ID_MASK; + x = tegra_fuse_readl(FUSE_X_COORDINATE) & FUSE_X_COORDINATE_MASK; + y = tegra_fuse_readl(FUSE_Y_COORDINATE) & FUSE_Y_COORDINATE_MASK; + + uid = ((unsigned long long)cid << 60ull) + | ((unsigned long long)vendor << 56ull) + | ((unsigned long long)fab << 50ull) + | ((unsigned long long)lot << 24ull) + | ((unsigned long long)wafer << 18ull) + | ((unsigned long long)x << 9ull) + | ((unsigned long long)y << 0ull); + return uid; +#endif +} + +unsigned int tegra_spare_fuse(int bit) +{ + BUG_ON(bit < 0 || bit > 61); + return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4); +} + +int tegra_sku_id(void) +{ + static int sku_id = -1; + if (sku_id == -1) { + u32 reg = tegra_fuse_readl(FUSE_SKU_INFO); + sku_id = reg & 0xFF; + } + return sku_id; +} + +int tegra_gpu_register_sets(void) +{ +#ifdef CONFIG_ARCH_TEGRA_HAS_DUAL_3D + u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + FUSE_GPU_INFO)); + if (reg & FUSE_GPU_INFO_MASK) + return 1; + else + return 2; +#else + return 1; +#endif +} + +struct chip_revision { + enum tegra_chipid chipid; + unsigned int major; + unsigned int minor; + char prime; + enum tegra_revision revision; +}; + +#define CHIP_REVISION(id, m, n, p, rev) { \ + .chipid = TEGRA_CHIPID_##id, \ + .major = m, \ + .minor = n, \ + .prime = p, \ + .revision = TEGRA_REVISION_##rev } + +static struct chip_revision tegra_chip_revisions[] = { + CHIP_REVISION(TEGRA2, 1, 2, 0, A02), + CHIP_REVISION(TEGRA2, 1, 3, 0, A03), + CHIP_REVISION(TEGRA2, 1, 3, 'p', A03p), + CHIP_REVISION(TEGRA2, 1, 4, 0, A04), + CHIP_REVISION(TEGRA2, 1, 4, 'p', A04p), + CHIP_REVISION(TEGRA3, 1, 1, 0, A01), + CHIP_REVISION(TEGRA3, 1, 2, 0, A02), + CHIP_REVISION(TEGRA3, 1, 3, 0, A03), +}; + +static enum tegra_revision tegra_decode_revision(const struct tegra_id *id) +{ + enum tegra_revision revision = TEGRA_REVISION_UNKNOWN; + +#if defined(CONFIG_TEGRA_SILICON_PLATFORM) + int i ; + char prime; + + if (id->priv == NULL) + prime = 0; + else + prime = *(id->priv); + + for (i = 0; i < ARRAY_SIZE(tegra_chip_revisions); i++) { + if ((id->chipid != tegra_chip_revisions[i].chipid) || + (id->minor != tegra_chip_revisions[i].minor) || + (id->major != tegra_chip_revisions[i].major) || + (prime != tegra_chip_revisions[i].prime)) + continue; + + revision = tegra_chip_revisions[i].revision; + break; + } +#endif + + return revision; +} + +static void tegra_set_tegraid(u32 chipid, + u32 major, u32 minor, + u32 nlist, u32 patch, const char *priv) +{ + tegra_id.chipid = (enum tegra_chipid) chipid; + tegra_id.major = major; + tegra_id.minor = minor; + tegra_id.netlist = nlist; + tegra_id.patch = patch; + tegra_id.priv = (char *)priv; + tegra_id.revision = tegra_decode_revision(&tegra_id); +} + +static void tegra_get_tegraid_from_hw(void) +{ + void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804; + void __iomem *netlist = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x860; + u32 cid = readl(chip_id); + u32 nlist = readl(netlist); + char *priv = NULL; + +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + if (get_spare_fuse(18) || get_spare_fuse(19)) + priv = "p"; +#endif + tegra_set_tegraid((cid >> 8) & 0xff, + (cid >> 4) & 0xf, + (cid >> 16) & 0xf, + (nlist >> 0) & 0xffff, + (nlist >> 16) & 0xffff, + priv); +} + +enum tegra_chipid tegra_get_chipid(void) +{ + if (tegra_id.chipid == TEGRA_CHIPID_UNKNOWN) + tegra_get_tegraid_from_hw(); + + return tegra_id.chipid; +} + +enum tegra_revision tegra_get_revision(void) +{ + if (tegra_id.chipid == TEGRA_CHIPID_UNKNOWN) + tegra_get_tegraid_from_hw(); + + return tegra_id.revision; +} + +static int get_chip_id(char *val, const struct kernel_param *kp) +{ + return param_get_uint(val, kp); +} + +static int get_revision(char *val, const struct kernel_param *kp) +{ + return param_get_uint(val, kp); +} + +static struct kernel_param_ops tegra_chip_id_ops = { + .get = get_chip_id, +}; + +static struct kernel_param_ops tegra_revision_ops = { + .get = get_revision, +}; + +module_param_cb(tegra_chip_id, &tegra_chip_id_ops, &tegra_id.chipid, 0444); +module_param_cb(tegra_chip_rev, &tegra_revision_ops, &tegra_id.revision, 0444); -- cgit v1.2.3 From c4a5c51e493a8d4154c15c95d2bd93b348090892 Mon Sep 17 00:00:00 2001 From: Preetham Chandru R Date: Thu, 1 Nov 2012 19:18:40 +0530 Subject: arm : tegra2 : do not power off the phy in suspend Since there is no PMC available in tegra2 we will not be able to get any remote wakeup events. Hence do not power of the phy during usb suspend. Bug 1166740 Change-Id: I882066a283af2e574b111da3472eb3f8f8a9d6eb Signed-off-by: Preetham Chandru R Reviewed-on: http://git-master/r/160593 Reviewed-by: Rakesh Bodla Reviewed-by: Venu Byravarasu Reviewed-by: Venkat Moganty Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit --- arch/arm/mach-tegra/board-ventana.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board-ventana.c b/arch/arm/mach-tegra/board-ventana.c index e897275e4433..500118114b39 100644 --- a/arch/arm/mach-tegra/board-ventana.c +++ b/arch/arm/mach-tegra/board-ventana.c @@ -502,7 +502,7 @@ static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = { .vbus_reg = NULL, .hot_plug = true, .remote_wakeup_supported = false, - .power_off_on_suspend = true, + .power_off_on_suspend = false, }, .u_cfg.utmi = { .hssync_start_delay = 9, @@ -562,7 +562,7 @@ static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = { .vbus_reg = NULL, .hot_plug = true, .remote_wakeup_supported = false, - .power_off_on_suspend = true, + .power_off_on_suspend = false, }, .u_cfg.utmi = { .hssync_start_delay = 9, -- cgit v1.2.3