From 52c99bda04d8bb1fb390821695b0f9efc1e1db44 Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 04:57:01 -0300 Subject: V4L/DVB (7862): Add mxl5505s driver for MaxiLinear 5505 chipsets Initial check-in of the original driver to establish history. Signed-off-by: Chia-Ling Lu Developer Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 4989 ++++++++++++++++++++++++++++++++ 1 file changed, 4989 insertions(+) create mode 100644 drivers/media/common/tuners/mxl5005s.c (limited to 'drivers/media/common/tuners/mxl5005s.c') diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c new file mode 100644 index 000000000000..a32475fa1472 --- /dev/null +++ b/drivers/media/common/tuners/mxl5005s.c @@ -0,0 +1,4989 @@ +/* + * For the Realtek RTL chip RTL2831U + * Realtek Release Date: 2008-03-14, ver 080314 + * Realtek version RTL2831 Linux driver version 080314 + * ver 080314 + * + * for linux kernel version 2.6.21.4 - 2.6.22-14 + * support MXL5005s and MT2060 tuners (support tuner auto-detecting) + * support two IR types -- RC5 and NEC + * + * Known boards with Realtek RTL chip RTL2821U + * Freecom USB stick 14aa:0160 (version 4) + * Conceptronic CTVDIGRCU + * + * Copyright (c) 2008 Realtek + * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * This code is placed under the terms of the GNU General Public License + * + * Released by Realtek under GPLv2. + * Thanks to Realtek for a lot of support we received ! + * + * Revision: 080314 - original version + */ + + +/** + +@file + +@brief MxL5005S tuner module definition + +One can manipulate MxL5005S tuner through MxL5005S module. +MxL5005S module is derived from tuner module. + +*/ + + +#include "tuner_mxl5005s.h" +#include "tuner_demod_io.h" + + + + + + +/** + +@defgroup MXL5005S_TUNER_MODULE MxL5005S tuner module + +MxL5005S tuner module is drived from tuner base module. + +@see TUNER_BASE_MODULE + +*/ + + + + + +/** + +@defgroup MXL5005S_MODULE_BUILDER MxL5005S module builder +@ingroup MXL5005S_TUNER_MODULE + +One should call MxL5005S module builder before using MxL5005S module. + +*/ +/// @{ + + + + + +/** + +@brief MxL5005S tuner module builder + +Use BuildMxl5005sModule() to build MxL5005S module, set all module function pointers with the corresponding functions, +and initialize module private variables. + + +@param [in] ppTuner Pointer to MxL5005S tuner module pointer +@param [in] pTunerModuleMemory Pointer to an allocated tuner module memory +@param [in] pMxl5005sExtraModuleMemory Pointer to an allocated MxL5005S extra module memory +@param [in] pI2cBridgeModuleMemory Pointer to an allocated I2C bridge module memory +@param [in] DeviceAddr MxL5005S I2C device address +@param [in] CrystalFreqHz MxL5005S crystal frequency in Hz + + +@note \n + -# One should call BuildMxl5005sModule() to build MxL5005S module before using it. + +*/ +void +BuildMxl5005sModule( + TUNER_MODULE **ppTuner, + TUNER_MODULE *pTunerModuleMemory, + MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory, + BASE_INTERFACE_MODULE *pBaseInterfaceModuleMemory, + I2C_BRIDGE_MODULE *pI2cBridgeModuleMemory, + unsigned char DeviceAddr, + int StandardMode + ) +{ + MXL5005S_EXTRA_MODULE *pExtra; + + int MxlModMode; + int MxlIfMode; + unsigned long MxlBandwitdh; + unsigned long MxlIfFreqHz; + unsigned long MxlCrystalFreqHz; + int MxlAgcMode; + unsigned short MxlTop; + unsigned short MxlIfOutputLoad; + int MxlClockOut; + int MxlDivOut; + int MxlCapSel; + int MxlRssiOnOff; + unsigned char MxlStandard; + unsigned char MxlTfType; + + + + // Set tuner module pointer, tuner extra module pointer, and I2C bridge module pointer. + *ppTuner = pTunerModuleMemory; + (*ppTuner)->pExtra = pMxl5005sExtraModuleMemory; + (*ppTuner)->pBaseInterface = pBaseInterfaceModuleMemory; + (*ppTuner)->pI2cBridge = pI2cBridgeModuleMemory; + + // Get tuner extra module pointer. + pExtra = (MXL5005S_EXTRA_MODULE *)(*ppTuner)->pExtra; + + + // Set I2C bridge tuner arguments. + mxl5005s_SetI2cBridgeModuleTunerArg(*ppTuner); + + + // Set tuner module manipulating function pointers. + (*ppTuner)->SetDeviceAddr = mxl5005s_SetDeviceAddr; + + (*ppTuner)->GetTunerType = mxl5005s_GetTunerType; + (*ppTuner)->GetDeviceAddr = mxl5005s_GetDeviceAddr; + + (*ppTuner)->Initialize = mxl5005s_Initialize; + (*ppTuner)->SetRfFreqHz = mxl5005s_SetRfFreqHz; + (*ppTuner)->GetRfFreqHz = mxl5005s_GetRfFreqHz; + + + // Set tuner extra module manipulating function pointers. + pExtra->SetRegsWithTable = mxl5005s_SetRegsWithTable; + pExtra->SetRegMaskBits = mxl5005s_SetRegMaskBits; + pExtra->SetSpectrumMode = mxl5005s_SetSpectrumMode; + pExtra->SetBandwidthHz = mxl5005s_SetBandwidthHz; + + + // Initialize tuner parameter setting status. + (*ppTuner)->IsDeviceAddrSet = NO; + (*ppTuner)->IsRfFreqHzSet = NO; + + + // Set MxL5005S parameters. + MxlModMode = MXL_DIGITAL_MODE; + MxlIfMode = MXL_ZERO_IF; + MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; + MxlIfFreqHz = IF_FREQ_4570000HZ; + MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; + MxlAgcMode = MXL_SINGLE_AGC; + MxlTop = MXL5005S_TOP_25P2; + MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; + MxlClockOut = MXL_CLOCK_OUT_DISABLE; + MxlDivOut = MXL_DIV_OUT_4; + MxlCapSel = MXL_CAP_SEL_ENABLE; + MxlRssiOnOff = MXL_RSSI_ENABLE; + MxlTfType = MXL_TF_C_H; + + + // Set MxL5005S parameters according to standard mode + switch(StandardMode) + { + default: + case MXL5005S_STANDARD_DVBT: MxlStandard = MXL_DVBT; break; + case MXL5005S_STANDARD_ATSC: MxlStandard = MXL_ATSC; break; + } + + + // Set MxL5005S extra module. + pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; + + MXL5005_TunerConfig(&pExtra->MxlDefinedTunerStructure, (unsigned char)MxlModMode, (unsigned char)MxlIfMode, + MxlBandwitdh, MxlIfFreqHz, MxlCrystalFreqHz, (unsigned char)MxlAgcMode, MxlTop, MxlIfOutputLoad, + (unsigned char)MxlClockOut, (unsigned char)MxlDivOut, (unsigned char)MxlCapSel, (unsigned char)MxlRssiOnOff, + MxlStandard, MxlTfType); + + + + // Note: Need to set all module arguments before using module functions. + + + // Set tuner type. + (*ppTuner)->TunerType = TUNER_TYPE_MXL5005S; + + // Set tuner I2C device address. + (*ppTuner)->SetDeviceAddr(*ppTuner, DeviceAddr); + + + return; +} + + + + + +/// @} + + + + + +/** + +@defgroup MXL5005S_MANIPULATING_FUNCTIONS MxL5005S manipulating functions derived from tuner base module +@ingroup MXL5005S_TUNER_MODULE + +One can use the MxL5005S tuner module manipulating interface implemented by MxL5005S manipulating functions to +manipulate MxL5005S tuner. + +*/ +/// @{ + + + + + +/** + +@brief Set MxL5005S tuner I2C device address. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_SET_DEVICE_ADDR() function pointer with mxl5005s_SetDeviceAddr(). + +@see TUNER_FP_SET_DEVICE_ADDR + +*/ +void +mxl5005s_SetDeviceAddr( + TUNER_MODULE *pTuner, + unsigned char DeviceAddr + ) +{ + // Set tuner I2C device address. + pTuner->DeviceAddr = DeviceAddr; + pTuner->IsDeviceAddrSet = YES; + + + return; +} + + + + + +/** + +@brief Get MxL5005S tuner type. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_GET_TUNER_TYPE() function pointer with mxl5005s_GetTunerType(). + +@see TUNER_FP_GET_TUNER_TYPE + +*/ +void +mxl5005s_GetTunerType( + TUNER_MODULE *pTuner, + int *pTunerType + ) +{ + // Get tuner type from tuner module. + *pTunerType = pTuner->TunerType; + + + return; +} + + + + + +/** + +@brief Get MxL5005S tuner I2C device address. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_GET_DEVICE_ADDR() function pointer with mxl5005s_GetDeviceAddr(). + +@see TUNER_FP_GET_DEVICE_ADDR + +*/ +int +mxl5005s_GetDeviceAddr( + TUNER_MODULE *pTuner, + unsigned char *pDeviceAddr + ) +{ + // Get tuner I2C device address from tuner module. + if(pTuner->IsDeviceAddrSet != YES) + goto error_status_get_tuner_i2c_device_addr; + + *pDeviceAddr = pTuner->DeviceAddr; + + + return FUNCTION_SUCCESS; + + +error_status_get_tuner_i2c_device_addr: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Initialize MxL5005S tuner. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_INITIALIZE() function pointer with mxl5005s_Initialize(). + +@see TUNER_FP_INITIALIZE + +*/ +int +mxl5005s_Initialize( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner + ) +{ + MXL5005S_EXTRA_MODULE *pExtra; + + unsigned char AgcMasterByte; + unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + int TableLen; + + + + // Get tuner extra module. + pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; + + + // Get AGC master byte + AgcMasterByte = pExtra->AgcMasterByte; + + + // Initialize MxL5005S tuner according to MxL5005S tuner example code. + + // Tuner initialization stage 0 + MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); + AddrTable[0] = MASTER_CONTROL_ADDR; + ByteTable[0] |= AgcMasterByte; + + if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + // Tuner initialization stage 1 + MXL_GetInitRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen); + + if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Set MxL5005S tuner RF frequency in Hz. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_SET_RF_FREQ_HZ() function pointer with mxl5005s_SetRfFreqHz(). + +@see TUNER_FP_SET_RF_FREQ_HZ + +*/ +int +mxl5005s_SetRfFreqHz( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned long RfFreqHz + ) +{ + MXL5005S_EXTRA_MODULE *pExtra; + BASE_INTERFACE_MODULE *pBaseInterface; + + unsigned char AgcMasterByte; + unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + int TableLen; + + unsigned long IfDivval; + unsigned char MasterControlByte; + + + + // Get tuner extra module and base interface module. + pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; + pBaseInterface = pTuner->pBaseInterface; + + + // Get AGC master byte + AgcMasterByte = pExtra->AgcMasterByte; + + + // Set MxL5005S tuner RF frequency according to MxL5005S tuner example code. + + // Tuner RF frequency setting stage 0 + MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ; + AddrTable[0] = MASTER_CONTROL_ADDR; + ByteTable[0] |= AgcMasterByte; + + if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + // Tuner RF frequency setting stage 1 + MXL_TuneRF(&pExtra->MxlDefinedTunerStructure, RfFreqHz); + + MXL_ControlRead(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, &IfDivval); + + MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 0); + MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_EXTPOWERUP, 1); + MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, 8); + + MXL_GetCHRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ; + + MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; + AddrTable[TableLen] = MASTER_CONTROL_ADDR ; + ByteTable[TableLen] = MasterControlByte | AgcMasterByte; + TableLen += 1; + + if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + // Wait 30 ms. + pBaseInterface->WaitMs(pBaseInterface, 30); + + + // Tuner RF frequency setting stage 2 + MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 1) ; + MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, IfDivval) ; + MXL_GetCHRegister_ZeroIF(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ; + + MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; + AddrTable[TableLen] = MASTER_CONTROL_ADDR ; + ByteTable[TableLen] = MasterControlByte | AgcMasterByte ; + TableLen += 1; + + if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + // Set tuner RF frequency parameter. + pTuner->RfFreqHz = RfFreqHz; + pTuner->IsRfFreqHzSet = YES; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Get MxL5005S tuner RF frequency in Hz. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_GET_RF_FREQ_HZ() function pointer with mxl5005s_GetRfFreqHz(). + +@see TUNER_FP_GET_RF_FREQ_HZ + +*/ +int +mxl5005s_GetRfFreqHz( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned long *pRfFreqHz + ) +{ + // Get tuner RF frequency in Hz from tuner module. + if(pTuner->IsRfFreqHzSet != YES) + goto error_status_get_tuner_rf_frequency; + + *pRfFreqHz = pTuner->RfFreqHz; + + + return FUNCTION_SUCCESS; + + +error_status_get_tuner_rf_frequency: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Set MxL5005S tuner registers with table. + +*/ +/* +int +mxl5005s_SetRegsWithTable( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned char *pAddrTable, + unsigned char *pByteTable, + int TableLen + ) +{ + BASE_INTERFACE_MODULE *pBaseInterface; + I2C_BRIDGE_MODULE *pI2cBridge; + unsigned char WritingByteNumMax; + + int i; + unsigned char WritingBuffer[I2C_BUFFER_LEN]; + unsigned char WritingIndex; + + + + // Get base interface, I2C bridge, and maximum writing byte number. + pBaseInterface = pTuner->pBaseInterface; + pI2cBridge = pTuner->pI2cBridge; + WritingByteNumMax = pBaseInterface->I2cWritingByteNumMax; + + + // Set registers with table. + // Note: 1. The I2C format of MxL5005S is described as follows: + // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * n + stop_bit + // ... + // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * m + latch_byte + stop_bit + // 2. The latch_byte is 0xfe. + // 3. The following writing byte separating scheme takes latch_byte as two byte data. + for(i = 0, WritingIndex = 0; i < TableLen; i++) + { + // Put register address and register byte value into writing buffer. + WritingBuffer[WritingIndex] = pAddrTable[i]; + WritingBuffer[WritingIndex + 1] = pByteTable[i]; + WritingIndex += 2; + + // If writing buffer is full, send the I2C writing command with writing buffer. + if(WritingIndex > (WritingByteNumMax - 2)) + { + if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + WritingIndex = 0; + } + } + + + // Send the last I2C writing command with writing buffer and latch byte. + WritingBuffer[WritingIndex] = MXL5005S_LATCH_BYTE; + WritingIndex += 1; + + if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} +*/ + + +int +mxl5005s_SetRegsWithTable( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned char *pAddrTable, + unsigned char *pByteTable, + int TableLen + ) +{ + int i; + u8 end_two_bytes_buf[]={ 0 , 0 }; + u8 tuner_addr=0x00; + + pTuner->GetDeviceAddr(pTuner , &tuner_addr); + + for( i = 0 ; i < TableLen - 1 ; i++) + { + if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , &pByteTable[i] , 1 ) ) + return FUNCTION_ERROR; + } + + end_two_bytes_buf[0] = pByteTable[i]; + end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE; + + if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , end_two_bytes_buf , 2 ) ) + return FUNCTION_ERROR; + + return FUNCTION_SUCCESS; +} + + + + + +/** + +@brief Set MxL5005S tuner register bits. + +*/ +int +mxl5005s_SetRegMaskBits( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned char RegAddr, + unsigned char Msb, + unsigned char Lsb, + const unsigned char WritingValue + ) +{ + MXL5005S_EXTRA_MODULE *pExtra; + + int i; + + unsigned char Mask; + unsigned char Shift; + + unsigned char RegByte; + + + + // Get tuner extra module. + pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; + + + // Generate mask and shift according to MSB and LSB. + Mask = 0; + for(i = Lsb; i < (unsigned char)(Msb + 1); i++) + Mask |= 0x1 << i; + + Shift = Lsb; + + + // Get tuner register byte according to register adddress. + MXL_RegRead(&pExtra->MxlDefinedTunerStructure, RegAddr, &RegByte); + + + // Reserve register byte unmask bit with mask and inlay writing value into it. + RegByte &= ~Mask; + RegByte |= (WritingValue << Shift) & Mask; + + + // Update tuner register byte table. + MXL_RegWrite(&pExtra->MxlDefinedTunerStructure, RegAddr, RegByte); + + + // Write tuner register byte with writing byte. + if(pExtra->SetRegsWithTable( dib, pTuner, &RegAddr, &RegByte, LEN_1_BYTE) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Set MxL5005S tuner spectrum mode. + +*/ +int +mxl5005s_SetSpectrumMode( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + int SpectrumMode + ) +{ + static const unsigned char BbIqswapTable[SPECTRUM_MODE_NUM] = + { + // BB_IQSWAP + 0, // Normal spectrum + 1, // Inverse spectrum + }; + + + MXL5005S_EXTRA_MODULE *pExtra; + + + + // Get tuner extra module. + pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; + + + // Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode. + if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_IQSWAP_ADDR, MXL5005S_BB_IQSWAP_MSB, + MXL5005S_BB_IQSWAP_LSB, BbIqswapTable[SpectrumMode]) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Set MxL5005S tuner bandwidth in Hz. + +*/ +int +mxl5005s_SetBandwidthHz( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned long BandwidthHz + ) +{ + MXL5005S_EXTRA_MODULE *pExtra; + + unsigned char BbDlpfBandsel; + + + + // Get tuner extra module. + pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; + + + // Set BB_DLPF_BANDSEL according to bandwidth. + switch(BandwidthHz) + { + default: + case MXL5005S_BANDWIDTH_6MHZ: BbDlpfBandsel = 3; break; + case MXL5005S_BANDWIDTH_7MHZ: BbDlpfBandsel = 2; break; + case MXL5005S_BANDWIDTH_8MHZ: BbDlpfBandsel = 0; break; + } + + if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_DLPF_BANDSEL_ADDR, MXL5005S_BB_DLPF_BANDSEL_MSB, + MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} + + + + + +/// @} + + + + + +/** + +@defgroup MXL5005S_DEPENDENCE MxL5005S dependence +@ingroup MXL5005S_TUNER_MODULE + +MxL5005S dependence is the related functions for MxL5005S tuner module interface. +One should not use MxL5005S dependence directly. + +*/ +/// @{ + + + + + +/** + +@brief Set I2C bridge module tuner arguments. + +MxL5005S builder will use mxl5005s_SetI2cBridgeModuleTunerArg() to set I2C bridge module tuner arguments. + + +@param [in] pTuner The tuner module pointer + + +@see BuildMxl5005sModule() + +*/ +void +mxl5005s_SetI2cBridgeModuleTunerArg( + TUNER_MODULE *pTuner + ) +{ + I2C_BRIDGE_MODULE *pI2cBridge; + + + + // Get I2C bridge module. + pI2cBridge = pTuner->pI2cBridge; + + // Set I2C bridge module tuner arguments. + pI2cBridge->pTunerDeviceAddr = &pTuner->DeviceAddr; + + + return; +} + + + + + +/// @} + + + + + + + + + + + + + + + + + + + + + + + +// The following context is source code provided by MaxLinear. + + + + + +// MaxLinear source code - MXL5005_Initialize.cpp + + + +//#ifdef _MXL_HEADER +//#include "stdafx.h" +//#endif +//#include "MXL5005_c.h" + +_u16 MXL5005_RegisterInit (Tuner_struct * Tuner) +{ + Tuner->TunerRegs_Num = TUNER_REGS_NUM ; +// Tuner->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; + + Tuner->TunerRegs[0].Reg_Num = 9 ; + Tuner->TunerRegs[0].Reg_Val = 0x40 ; + + Tuner->TunerRegs[1].Reg_Num = 11 ; + Tuner->TunerRegs[1].Reg_Val = 0x19 ; + + Tuner->TunerRegs[2].Reg_Num = 12 ; + Tuner->TunerRegs[2].Reg_Val = 0x60 ; + + Tuner->TunerRegs[3].Reg_Num = 13 ; + Tuner->TunerRegs[3].Reg_Val = 0x00 ; + + Tuner->TunerRegs[4].Reg_Num = 14 ; + Tuner->TunerRegs[4].Reg_Val = 0x00 ; + + Tuner->TunerRegs[5].Reg_Num = 15 ; + Tuner->TunerRegs[5].Reg_Val = 0xC0 ; + + Tuner->TunerRegs[6].Reg_Num = 16 ; + Tuner->TunerRegs[6].Reg_Val = 0x00 ; + + Tuner->TunerRegs[7].Reg_Num = 17 ; + Tuner->TunerRegs[7].Reg_Val = 0x00 ; + + Tuner->TunerRegs[8].Reg_Num = 18 ; + Tuner->TunerRegs[8].Reg_Val = 0x00 ; + + Tuner->TunerRegs[9].Reg_Num = 19 ; + Tuner->TunerRegs[9].Reg_Val = 0x34 ; + + Tuner->TunerRegs[10].Reg_Num = 21 ; + Tuner->TunerRegs[10].Reg_Val = 0x00 ; + + Tuner->TunerRegs[11].Reg_Num = 22 ; + Tuner->TunerRegs[11].Reg_Val = 0x6B ; + + Tuner->TunerRegs[12].Reg_Num = 23 ; + Tuner->TunerRegs[12].Reg_Val = 0x35 ; + + Tuner->TunerRegs[13].Reg_Num = 24 ; + Tuner->TunerRegs[13].Reg_Val = 0x70 ; + + Tuner->TunerRegs[14].Reg_Num = 25 ; + Tuner->TunerRegs[14].Reg_Val = 0x3E ; + + Tuner->TunerRegs[15].Reg_Num = 26 ; + Tuner->TunerRegs[15].Reg_Val = 0x82 ; + + Tuner->TunerRegs[16].Reg_Num = 31 ; + Tuner->TunerRegs[16].Reg_Val = 0x00 ; + + Tuner->TunerRegs[17].Reg_Num = 32 ; + Tuner->TunerRegs[17].Reg_Val = 0x40 ; + + Tuner->TunerRegs[18].Reg_Num = 33 ; + Tuner->TunerRegs[18].Reg_Val = 0x53 ; + + Tuner->TunerRegs[19].Reg_Num = 34 ; + Tuner->TunerRegs[19].Reg_Val = 0x81 ; + + Tuner->TunerRegs[20].Reg_Num = 35 ; + Tuner->TunerRegs[20].Reg_Val = 0xC9 ; + + Tuner->TunerRegs[21].Reg_Num = 36 ; + Tuner->TunerRegs[21].Reg_Val = 0x01 ; + + Tuner->TunerRegs[22].Reg_Num = 37 ; + Tuner->TunerRegs[22].Reg_Val = 0x00 ; + + Tuner->TunerRegs[23].Reg_Num = 41 ; + Tuner->TunerRegs[23].Reg_Val = 0x00 ; + + Tuner->TunerRegs[24].Reg_Num = 42 ; + Tuner->TunerRegs[24].Reg_Val = 0xF8 ; + + Tuner->TunerRegs[25].Reg_Num = 43 ; + Tuner->TunerRegs[25].Reg_Val = 0x43 ; + + Tuner->TunerRegs[26].Reg_Num = 44 ; + Tuner->TunerRegs[26].Reg_Val = 0x20 ; + + Tuner->TunerRegs[27].Reg_Num = 45 ; + Tuner->TunerRegs[27].Reg_Val = 0x80 ; + + Tuner->TunerRegs[28].Reg_Num = 46 ; + Tuner->TunerRegs[28].Reg_Val = 0x88 ; + + Tuner->TunerRegs[29].Reg_Num = 47 ; + Tuner->TunerRegs[29].Reg_Val = 0x86 ; + + Tuner->TunerRegs[30].Reg_Num = 48 ; + Tuner->TunerRegs[30].Reg_Val = 0x00 ; + + Tuner->TunerRegs[31].Reg_Num = 49 ; + Tuner->TunerRegs[31].Reg_Val = 0x00 ; + + Tuner->TunerRegs[32].Reg_Num = 53 ; + Tuner->TunerRegs[32].Reg_Val = 0x94 ; + + Tuner->TunerRegs[33].Reg_Num = 54 ; + Tuner->TunerRegs[33].Reg_Val = 0xFA ; + + Tuner->TunerRegs[34].Reg_Num = 55 ; + Tuner->TunerRegs[34].Reg_Val = 0x92 ; + + Tuner->TunerRegs[35].Reg_Num = 56 ; + Tuner->TunerRegs[35].Reg_Val = 0x80 ; + + Tuner->TunerRegs[36].Reg_Num = 57 ; + Tuner->TunerRegs[36].Reg_Val = 0x41 ; + + Tuner->TunerRegs[37].Reg_Num = 58 ; + Tuner->TunerRegs[37].Reg_Val = 0xDB ; + + Tuner->TunerRegs[38].Reg_Num = 59 ; + Tuner->TunerRegs[38].Reg_Val = 0x00 ; + + Tuner->TunerRegs[39].Reg_Num = 60 ; + Tuner->TunerRegs[39].Reg_Val = 0x00 ; + + Tuner->TunerRegs[40].Reg_Num = 61 ; + Tuner->TunerRegs[40].Reg_Val = 0x00 ; + + Tuner->TunerRegs[41].Reg_Num = 62 ; + Tuner->TunerRegs[41].Reg_Val = 0x00 ; + + Tuner->TunerRegs[42].Reg_Num = 65 ; + Tuner->TunerRegs[42].Reg_Val = 0xF8 ; + + Tuner->TunerRegs[43].Reg_Num = 66 ; + Tuner->TunerRegs[43].Reg_Val = 0xE4 ; + + Tuner->TunerRegs[44].Reg_Num = 67 ; + Tuner->TunerRegs[44].Reg_Val = 0x90 ; + + Tuner->TunerRegs[45].Reg_Num = 68 ; + Tuner->TunerRegs[45].Reg_Val = 0xC0 ; + + Tuner->TunerRegs[46].Reg_Num = 69 ; + Tuner->TunerRegs[46].Reg_Val = 0x01 ; + + Tuner->TunerRegs[47].Reg_Num = 70 ; + Tuner->TunerRegs[47].Reg_Val = 0x50 ; + + Tuner->TunerRegs[48].Reg_Num = 71 ; + Tuner->TunerRegs[48].Reg_Val = 0x06 ; + + Tuner->TunerRegs[49].Reg_Num = 72 ; + Tuner->TunerRegs[49].Reg_Val = 0x00 ; + + Tuner->TunerRegs[50].Reg_Num = 73 ; + Tuner->TunerRegs[50].Reg_Val = 0x20 ; + + Tuner->TunerRegs[51].Reg_Num = 76 ; + Tuner->TunerRegs[51].Reg_Val = 0xBB ; + + Tuner->TunerRegs[52].Reg_Num = 77 ; + Tuner->TunerRegs[52].Reg_Val = 0x13 ; + + Tuner->TunerRegs[53].Reg_Num = 81 ; + Tuner->TunerRegs[53].Reg_Val = 0x04 ; + + Tuner->TunerRegs[54].Reg_Num = 82 ; + Tuner->TunerRegs[54].Reg_Val = 0x75 ; + + Tuner->TunerRegs[55].Reg_Num = 83 ; + Tuner->TunerRegs[55].Reg_Val = 0x00 ; + + Tuner->TunerRegs[56].Reg_Num = 84 ; + Tuner->TunerRegs[56].Reg_Val = 0x00 ; + + Tuner->TunerRegs[57].Reg_Num = 85 ; + Tuner->TunerRegs[57].Reg_Val = 0x00 ; + + Tuner->TunerRegs[58].Reg_Num = 91 ; + Tuner->TunerRegs[58].Reg_Val = 0x70 ; + + Tuner->TunerRegs[59].Reg_Num = 92 ; + Tuner->TunerRegs[59].Reg_Val = 0x00 ; + + Tuner->TunerRegs[60].Reg_Num = 93 ; + Tuner->TunerRegs[60].Reg_Val = 0x00 ; + + Tuner->TunerRegs[61].Reg_Num = 94 ; + Tuner->TunerRegs[61].Reg_Val = 0x00 ; + + Tuner->TunerRegs[62].Reg_Num = 95 ; + Tuner->TunerRegs[62].Reg_Val = 0x0C ; + + Tuner->TunerRegs[63].Reg_Num = 96 ; + Tuner->TunerRegs[63].Reg_Val = 0x00 ; + + Tuner->TunerRegs[64].Reg_Num = 97 ; + Tuner->TunerRegs[64].Reg_Val = 0x00 ; + + Tuner->TunerRegs[65].Reg_Num = 98 ; + Tuner->TunerRegs[65].Reg_Val = 0xE2 ; + + Tuner->TunerRegs[66].Reg_Num = 99 ; + Tuner->TunerRegs[66].Reg_Val = 0x00 ; + + Tuner->TunerRegs[67].Reg_Num = 100 ; + Tuner->TunerRegs[67].Reg_Val = 0x00 ; + + Tuner->TunerRegs[68].Reg_Num = 101 ; + Tuner->TunerRegs[68].Reg_Val = 0x12 ; + + Tuner->TunerRegs[69].Reg_Num = 102 ; + Tuner->TunerRegs[69].Reg_Val = 0x80 ; + + Tuner->TunerRegs[70].Reg_Num = 103 ; + Tuner->TunerRegs[70].Reg_Val = 0x32 ; + + Tuner->TunerRegs[71].Reg_Num = 104 ; + Tuner->TunerRegs[71].Reg_Val = 0xB4 ; + + Tuner->TunerRegs[72].Reg_Num = 105 ; + Tuner->TunerRegs[72].Reg_Val = 0x60 ; + + Tuner->TunerRegs[73].Reg_Num = 106 ; + Tuner->TunerRegs[73].Reg_Val = 0x83 ; + + Tuner->TunerRegs[74].Reg_Num = 107 ; + Tuner->TunerRegs[74].Reg_Val = 0x84 ; + + Tuner->TunerRegs[75].Reg_Num = 108 ; + Tuner->TunerRegs[75].Reg_Val = 0x9C ; + + Tuner->TunerRegs[76].Reg_Num = 109 ; + Tuner->TunerRegs[76].Reg_Val = 0x02 ; + + Tuner->TunerRegs[77].Reg_Num = 110 ; + Tuner->TunerRegs[77].Reg_Val = 0x81 ; + + Tuner->TunerRegs[78].Reg_Num = 111 ; + Tuner->TunerRegs[78].Reg_Val = 0xC0 ; + + Tuner->TunerRegs[79].Reg_Num = 112 ; + Tuner->TunerRegs[79].Reg_Val = 0x10 ; + + Tuner->TunerRegs[80].Reg_Num = 131 ; + Tuner->TunerRegs[80].Reg_Val = 0x8A ; + + Tuner->TunerRegs[81].Reg_Num = 132 ; + Tuner->TunerRegs[81].Reg_Val = 0x10 ; + + Tuner->TunerRegs[82].Reg_Num = 133 ; + Tuner->TunerRegs[82].Reg_Val = 0x24 ; + + Tuner->TunerRegs[83].Reg_Num = 134 ; + Tuner->TunerRegs[83].Reg_Val = 0x00 ; + + Tuner->TunerRegs[84].Reg_Num = 135 ; + Tuner->TunerRegs[84].Reg_Val = 0x00 ; + + Tuner->TunerRegs[85].Reg_Num = 136 ; + Tuner->TunerRegs[85].Reg_Val = 0x7E ; + + Tuner->TunerRegs[86].Reg_Num = 137 ; + Tuner->TunerRegs[86].Reg_Val = 0x40 ; + + Tuner->TunerRegs[87].Reg_Num = 138 ; + Tuner->TunerRegs[87].Reg_Val = 0x38 ; + + Tuner->TunerRegs[88].Reg_Num = 146 ; + Tuner->TunerRegs[88].Reg_Val = 0xF6 ; + + Tuner->TunerRegs[89].Reg_Num = 147 ; + Tuner->TunerRegs[89].Reg_Val = 0x1A ; + + Tuner->TunerRegs[90].Reg_Num = 148 ; + Tuner->TunerRegs[90].Reg_Val = 0x62 ; + + Tuner->TunerRegs[91].Reg_Num = 149 ; + Tuner->TunerRegs[91].Reg_Val = 0x33 ; + + Tuner->TunerRegs[92].Reg_Num = 150 ; + Tuner->TunerRegs[92].Reg_Val = 0x80 ; + + Tuner->TunerRegs[93].Reg_Num = 156 ; + Tuner->TunerRegs[93].Reg_Val = 0x56 ; + + Tuner->TunerRegs[94].Reg_Num = 157 ; + Tuner->TunerRegs[94].Reg_Val = 0x17 ; + + Tuner->TunerRegs[95].Reg_Num = 158 ; + Tuner->TunerRegs[95].Reg_Val = 0xA9 ; + + Tuner->TunerRegs[96].Reg_Num = 159 ; + Tuner->TunerRegs[96].Reg_Val = 0x00 ; + + Tuner->TunerRegs[97].Reg_Num = 160 ; + Tuner->TunerRegs[97].Reg_Val = 0x00 ; + + Tuner->TunerRegs[98].Reg_Num = 161 ; + Tuner->TunerRegs[98].Reg_Val = 0x00 ; + + Tuner->TunerRegs[99].Reg_Num = 162 ; + Tuner->TunerRegs[99].Reg_Val = 0x40 ; + + Tuner->TunerRegs[100].Reg_Num = 166 ; + Tuner->TunerRegs[100].Reg_Val = 0xAE ; + + Tuner->TunerRegs[101].Reg_Num = 167 ; + Tuner->TunerRegs[101].Reg_Val = 0x1B ; + + Tuner->TunerRegs[102].Reg_Num = 168 ; + Tuner->TunerRegs[102].Reg_Val = 0xF2 ; + + Tuner->TunerRegs[103].Reg_Num = 195 ; + Tuner->TunerRegs[103].Reg_Val = 0x00 ; + + return 0 ; +} + +_u16 MXL5005_ControlInit (Tuner_struct *Tuner) +{ + Tuner->Init_Ctrl_Num = INITCTRL_NUM ; + + Tuner->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; + Tuner->Init_Ctrl[0].size = 1 ; + Tuner->Init_Ctrl[0].addr[0] = 73; + Tuner->Init_Ctrl[0].bit[0] = 7; + Tuner->Init_Ctrl[0].val[0] = 0; + + Tuner->Init_Ctrl[1].Ctrl_Num = BB_MODE ; + Tuner->Init_Ctrl[1].size = 1 ; + Tuner->Init_Ctrl[1].addr[0] = 53; + Tuner->Init_Ctrl[1].bit[0] = 2; + Tuner->Init_Ctrl[1].val[0] = 1; + + Tuner->Init_Ctrl[2].Ctrl_Num = BB_BUF ; + Tuner->Init_Ctrl[2].size = 2 ; + Tuner->Init_Ctrl[2].addr[0] = 53; + Tuner->Init_Ctrl[2].bit[0] = 1; + Tuner->Init_Ctrl[2].val[0] = 0; + Tuner->Init_Ctrl[2].addr[1] = 57; + Tuner->Init_Ctrl[2].bit[1] = 0; + Tuner->Init_Ctrl[2].val[1] = 1; + + Tuner->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ; + Tuner->Init_Ctrl[3].size = 1 ; + Tuner->Init_Ctrl[3].addr[0] = 53; + Tuner->Init_Ctrl[3].bit[0] = 0; + Tuner->Init_Ctrl[3].val[0] = 0; + + Tuner->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ; + Tuner->Init_Ctrl[4].size = 3 ; + Tuner->Init_Ctrl[4].addr[0] = 53; + Tuner->Init_Ctrl[4].bit[0] = 5; + Tuner->Init_Ctrl[4].val[0] = 0; + Tuner->Init_Ctrl[4].addr[1] = 53; + Tuner->Init_Ctrl[4].bit[1] = 6; + Tuner->Init_Ctrl[4].val[1] = 0; + Tuner->Init_Ctrl[4].addr[2] = 53; + Tuner->Init_Ctrl[4].bit[2] = 7; + Tuner->Init_Ctrl[4].val[2] = 1; + + Tuner->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ; + Tuner->Init_Ctrl[5].size = 1 ; + Tuner->Init_Ctrl[5].addr[0] = 59; + Tuner->Init_Ctrl[5].bit[0] = 0; + Tuner->Init_Ctrl[5].val[0] = 0; + + Tuner->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ; + Tuner->Init_Ctrl[6].size = 2 ; + Tuner->Init_Ctrl[6].addr[0] = 53; + Tuner->Init_Ctrl[6].bit[0] = 3; + Tuner->Init_Ctrl[6].val[0] = 0; + Tuner->Init_Ctrl[6].addr[1] = 53; + Tuner->Init_Ctrl[6].bit[1] = 4; + Tuner->Init_Ctrl[6].val[1] = 1; + + Tuner->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ; + Tuner->Init_Ctrl[7].size = 4 ; + Tuner->Init_Ctrl[7].addr[0] = 22; + Tuner->Init_Ctrl[7].bit[0] = 4; + Tuner->Init_Ctrl[7].val[0] = 0; + Tuner->Init_Ctrl[7].addr[1] = 22; + Tuner->Init_Ctrl[7].bit[1] = 5; + Tuner->Init_Ctrl[7].val[1] = 1; + Tuner->Init_Ctrl[7].addr[2] = 22; + Tuner->Init_Ctrl[7].bit[2] = 6; + Tuner->Init_Ctrl[7].val[2] = 1; + Tuner->Init_Ctrl[7].addr[3] = 22; + Tuner->Init_Ctrl[7].bit[3] = 7; + Tuner->Init_Ctrl[7].val[3] = 0; + + Tuner->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ; + Tuner->Init_Ctrl[8].size = 1 ; + Tuner->Init_Ctrl[8].addr[0] = 22; + Tuner->Init_Ctrl[8].bit[0] = 2; + Tuner->Init_Ctrl[8].val[0] = 0; + + Tuner->Init_Ctrl[9].Ctrl_Num = AGC_IF ; + Tuner->Init_Ctrl[9].size = 4 ; + Tuner->Init_Ctrl[9].addr[0] = 76; + Tuner->Init_Ctrl[9].bit[0] = 0; + Tuner->Init_Ctrl[9].val[0] = 1; + Tuner->Init_Ctrl[9].addr[1] = 76; + Tuner->Init_Ctrl[9].bit[1] = 1; + Tuner->Init_Ctrl[9].val[1] = 1; + Tuner->Init_Ctrl[9].addr[2] = 76; + Tuner->Init_Ctrl[9].bit[2] = 2; + Tuner->Init_Ctrl[9].val[2] = 0; + Tuner->Init_Ctrl[9].addr[3] = 76; + Tuner->Init_Ctrl[9].bit[3] = 3; + Tuner->Init_Ctrl[9].val[3] = 1; + + Tuner->Init_Ctrl[10].Ctrl_Num = AGC_RF ; + Tuner->Init_Ctrl[10].size = 4 ; + Tuner->Init_Ctrl[10].addr[0] = 76; + Tuner->Init_Ctrl[10].bit[0] = 4; + Tuner->Init_Ctrl[10].val[0] = 1; + Tuner->Init_Ctrl[10].addr[1] = 76; + Tuner->Init_Ctrl[10].bit[1] = 5; + Tuner->Init_Ctrl[10].val[1] = 1; + Tuner->Init_Ctrl[10].addr[2] = 76; + Tuner->Init_Ctrl[10].bit[2] = 6; + Tuner->Init_Ctrl[10].val[2] = 0; + Tuner->Init_Ctrl[10].addr[3] = 76; + Tuner->Init_Ctrl[10].bit[3] = 7; + Tuner->Init_Ctrl[10].val[3] = 1; + + Tuner->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ; + Tuner->Init_Ctrl[11].size = 5 ; + Tuner->Init_Ctrl[11].addr[0] = 43; + Tuner->Init_Ctrl[11].bit[0] = 3; + Tuner->Init_Ctrl[11].val[0] = 0; + Tuner->Init_Ctrl[11].addr[1] = 43; + Tuner->Init_Ctrl[11].bit[1] = 4; + Tuner->Init_Ctrl[11].val[1] = 0; + Tuner->Init_Ctrl[11].addr[2] = 43; + Tuner->Init_Ctrl[11].bit[2] = 5; + Tuner->Init_Ctrl[11].val[2] = 0; + Tuner->Init_Ctrl[11].addr[3] = 43; + Tuner->Init_Ctrl[11].bit[3] = 6; + Tuner->Init_Ctrl[11].val[3] = 1; + Tuner->Init_Ctrl[11].addr[4] = 43; + Tuner->Init_Ctrl[11].bit[4] = 7; + Tuner->Init_Ctrl[11].val[4] = 0; + + Tuner->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ; + Tuner->Init_Ctrl[12].size = 6 ; + Tuner->Init_Ctrl[12].addr[0] = 44; + Tuner->Init_Ctrl[12].bit[0] = 2; + Tuner->Init_Ctrl[12].val[0] = 0; + Tuner->Init_Ctrl[12].addr[1] = 44; + Tuner->Init_Ctrl[12].bit[1] = 3; + Tuner->Init_Ctrl[12].val[1] = 0; + Tuner->Init_Ctrl[12].addr[2] = 44; + Tuner->Init_Ctrl[12].bit[2] = 4; + Tuner->Init_Ctrl[12].val[2] = 0; + Tuner->Init_Ctrl[12].addr[3] = 44; + Tuner->Init_Ctrl[12].bit[3] = 5; + Tuner->Init_Ctrl[12].val[3] = 1; + Tuner->Init_Ctrl[12].addr[4] = 44; + Tuner->Init_Ctrl[12].bit[4] = 6; + Tuner->Init_Ctrl[12].val[4] = 0; + Tuner->Init_Ctrl[12].addr[5] = 44; + Tuner->Init_Ctrl[12].bit[5] = 7; + Tuner->Init_Ctrl[12].val[5] = 0; + + Tuner->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ; + Tuner->Init_Ctrl[13].size = 7 ; + Tuner->Init_Ctrl[13].addr[0] = 11; + Tuner->Init_Ctrl[13].bit[0] = 0; + Tuner->Init_Ctrl[13].val[0] = 1; + Tuner->Init_Ctrl[13].addr[1] = 11; + Tuner->Init_Ctrl[13].bit[1] = 1; + Tuner->Init_Ctrl[13].val[1] = 0; + Tuner->Init_Ctrl[13].addr[2] = 11; + Tuner->Init_Ctrl[13].bit[2] = 2; + Tuner->Init_Ctrl[13].val[2] = 0; + Tuner->Init_Ctrl[13].addr[3] = 11; + Tuner->Init_Ctrl[13].bit[3] = 3; + Tuner->Init_Ctrl[13].val[3] = 1; + Tuner->Init_Ctrl[13].addr[4] = 11; + Tuner->Init_Ctrl[13].bit[4] = 4; + Tuner->Init_Ctrl[13].val[4] = 1; + Tuner->Init_Ctrl[13].addr[5] = 11; + Tuner->Init_Ctrl[13].bit[5] = 5; + Tuner->Init_Ctrl[13].val[5] = 0; + Tuner->Init_Ctrl[13].addr[6] = 11; + Tuner->Init_Ctrl[13].bit[6] = 6; + Tuner->Init_Ctrl[13].val[6] = 0; + + Tuner->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ; + Tuner->Init_Ctrl[14].size = 16 ; + Tuner->Init_Ctrl[14].addr[0] = 13; + Tuner->Init_Ctrl[14].bit[0] = 0; + Tuner->Init_Ctrl[14].val[0] = 0; + Tuner->Init_Ctrl[14].addr[1] = 13; + Tuner->Init_Ctrl[14].bit[1] = 1; + Tuner->Init_Ctrl[14].val[1] = 0; + Tuner->Init_Ctrl[14].addr[2] = 13; + Tuner->Init_Ctrl[14].bit[2] = 2; + Tuner->Init_Ctrl[14].val[2] = 0; + Tuner->Init_Ctrl[14].addr[3] = 13; + Tuner->Init_Ctrl[14].bit[3] = 3; + Tuner->Init_Ctrl[14].val[3] = 0; + Tuner->Init_Ctrl[14].addr[4] = 13; + Tuner->Init_Ctrl[14].bit[4] = 4; + Tuner->Init_Ctrl[14].val[4] = 0; + Tuner->Init_Ctrl[14].addr[5] = 13; + Tuner->Init_Ctrl[14].bit[5] = 5; + Tuner->Init_Ctrl[14].val[5] = 0; + Tuner->Init_Ctrl[14].addr[6] = 13; + Tuner->Init_Ctrl[14].bit[6] = 6; + Tuner->Init_Ctrl[14].val[6] = 0; + Tuner->Init_Ctrl[14].addr[7] = 13; + Tuner->Init_Ctrl[14].bit[7] = 7; + Tuner->Init_Ctrl[14].val[7] = 0; + Tuner->Init_Ctrl[14].addr[8] = 12; + Tuner->Init_Ctrl[14].bit[8] = 0; + Tuner->Init_Ctrl[14].val[8] = 0; + Tuner->Init_Ctrl[14].addr[9] = 12; + Tuner->Init_Ctrl[14].bit[9] = 1; + Tuner->Init_Ctrl[14].val[9] = 0; + Tuner->Init_Ctrl[14].addr[10] = 12; + Tuner->Init_Ctrl[14].bit[10] = 2; + Tuner->Init_Ctrl[14].val[10] = 0; + Tuner->Init_Ctrl[14].addr[11] = 12; + Tuner->Init_Ctrl[14].bit[11] = 3; + Tuner->Init_Ctrl[14].val[11] = 0; + Tuner->Init_Ctrl[14].addr[12] = 12; + Tuner->Init_Ctrl[14].bit[12] = 4; + Tuner->Init_Ctrl[14].val[12] = 0; + Tuner->Init_Ctrl[14].addr[13] = 12; + Tuner->Init_Ctrl[14].bit[13] = 5; + Tuner->Init_Ctrl[14].val[13] = 1; + Tuner->Init_Ctrl[14].addr[14] = 12; + Tuner->Init_Ctrl[14].bit[14] = 6; + Tuner->Init_Ctrl[14].val[14] = 1; + Tuner->Init_Ctrl[14].addr[15] = 12; + Tuner->Init_Ctrl[14].bit[15] = 7; + Tuner->Init_Ctrl[14].val[15] = 0; + + Tuner->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ; + Tuner->Init_Ctrl[15].size = 3 ; + Tuner->Init_Ctrl[15].addr[0] = 147; + Tuner->Init_Ctrl[15].bit[0] = 2; + Tuner->Init_Ctrl[15].val[0] = 0; + Tuner->Init_Ctrl[15].addr[1] = 147; + Tuner->Init_Ctrl[15].bit[1] = 3; + Tuner->Init_Ctrl[15].val[1] = 1; + Tuner->Init_Ctrl[15].addr[2] = 147; + Tuner->Init_Ctrl[15].bit[2] = 4; + Tuner->Init_Ctrl[15].val[2] = 1; + + Tuner->Init_Ctrl[16].Ctrl_Num = I_DRIVER ; + Tuner->Init_Ctrl[16].size = 2 ; + Tuner->Init_Ctrl[16].addr[0] = 147; + Tuner->Init_Ctrl[16].bit[0] = 0; + Tuner->Init_Ctrl[16].val[0] = 0; + Tuner->Init_Ctrl[16].addr[1] = 147; + Tuner->Init_Ctrl[16].bit[1] = 1; + Tuner->Init_Ctrl[16].val[1] = 1; + + Tuner->Init_Ctrl[17].Ctrl_Num = EN_AAF ; + Tuner->Init_Ctrl[17].size = 1 ; + Tuner->Init_Ctrl[17].addr[0] = 147; + Tuner->Init_Ctrl[17].bit[0] = 7; + Tuner->Init_Ctrl[17].val[0] = 0; + + Tuner->Init_Ctrl[18].Ctrl_Num = EN_3P ; + Tuner->Init_Ctrl[18].size = 1 ; + Tuner->Init_Ctrl[18].addr[0] = 147; + Tuner->Init_Ctrl[18].bit[0] = 6; + Tuner->Init_Ctrl[18].val[0] = 0; + + Tuner->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ; + Tuner->Init_Ctrl[19].size = 1 ; + Tuner->Init_Ctrl[19].addr[0] = 156; + Tuner->Init_Ctrl[19].bit[0] = 0; + Tuner->Init_Ctrl[19].val[0] = 0; + + Tuner->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ; + Tuner->Init_Ctrl[20].size = 1 ; + Tuner->Init_Ctrl[20].addr[0] = 147; + Tuner->Init_Ctrl[20].bit[0] = 5; + Tuner->Init_Ctrl[20].val[0] = 0; + + Tuner->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ; + Tuner->Init_Ctrl[21].size = 1 ; + Tuner->Init_Ctrl[21].addr[0] = 137; + Tuner->Init_Ctrl[21].bit[0] = 4; + Tuner->Init_Ctrl[21].val[0] = 0; + + Tuner->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ; + Tuner->Init_Ctrl[22].size = 1 ; + Tuner->Init_Ctrl[22].addr[0] = 137; + Tuner->Init_Ctrl[22].bit[0] = 7; + Tuner->Init_Ctrl[22].val[0] = 0; + + Tuner->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ; + Tuner->Init_Ctrl[23].size = 1 ; + Tuner->Init_Ctrl[23].addr[0] = 91; + Tuner->Init_Ctrl[23].bit[0] = 5; + Tuner->Init_Ctrl[23].val[0] = 1; + + Tuner->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ; + Tuner->Init_Ctrl[24].size = 1 ; + Tuner->Init_Ctrl[24].addr[0] = 43; + Tuner->Init_Ctrl[24].bit[0] = 0; + Tuner->Init_Ctrl[24].val[0] = 1; + + Tuner->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ; + Tuner->Init_Ctrl[25].size = 2 ; + Tuner->Init_Ctrl[25].addr[0] = 22; + Tuner->Init_Ctrl[25].bit[0] = 0; + Tuner->Init_Ctrl[25].val[0] = 1; + Tuner->Init_Ctrl[25].addr[1] = 22; + Tuner->Init_Ctrl[25].bit[1] = 1; + Tuner->Init_Ctrl[25].val[1] = 1; + + Tuner->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ; + Tuner->Init_Ctrl[26].size = 1 ; + Tuner->Init_Ctrl[26].addr[0] = 134; + Tuner->Init_Ctrl[26].bit[0] = 2; + Tuner->Init_Ctrl[26].val[0] = 0; + + Tuner->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ; + Tuner->Init_Ctrl[27].size = 1 ; + Tuner->Init_Ctrl[27].addr[0] = 137; + Tuner->Init_Ctrl[27].bit[0] = 3; + Tuner->Init_Ctrl[27].val[0] = 0; + + Tuner->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ; + Tuner->Init_Ctrl[28].size = 1 ; + Tuner->Init_Ctrl[28].addr[0] = 77; + Tuner->Init_Ctrl[28].bit[0] = 7; + Tuner->Init_Ctrl[28].val[0] = 0; + + Tuner->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ; + Tuner->Init_Ctrl[29].size = 1 ; + Tuner->Init_Ctrl[29].addr[0] = 166; + Tuner->Init_Ctrl[29].bit[0] = 7; + Tuner->Init_Ctrl[29].val[0] = 1; + + Tuner->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ; + Tuner->Init_Ctrl[30].size = 3 ; + Tuner->Init_Ctrl[30].addr[0] = 166; + Tuner->Init_Ctrl[30].bit[0] = 0; + Tuner->Init_Ctrl[30].val[0] = 0; + Tuner->Init_Ctrl[30].addr[1] = 166; + Tuner->Init_Ctrl[30].bit[1] = 1; + Tuner->Init_Ctrl[30].val[1] = 1; + Tuner->Init_Ctrl[30].addr[2] = 166; + Tuner->Init_Ctrl[30].bit[2] = 2; + Tuner->Init_Ctrl[30].val[2] = 1; + + Tuner->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ; + Tuner->Init_Ctrl[31].size = 3 ; + Tuner->Init_Ctrl[31].addr[0] = 166; + Tuner->Init_Ctrl[31].bit[0] = 3; + Tuner->Init_Ctrl[31].val[0] = 1; + Tuner->Init_Ctrl[31].addr[1] = 166; + Tuner->Init_Ctrl[31].bit[1] = 4; + Tuner->Init_Ctrl[31].val[1] = 0; + Tuner->Init_Ctrl[31].addr[2] = 166; + Tuner->Init_Ctrl[31].bit[2] = 5; + Tuner->Init_Ctrl[31].val[2] = 1; + + Tuner->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ; + Tuner->Init_Ctrl[32].size = 3 ; + Tuner->Init_Ctrl[32].addr[0] = 167; + Tuner->Init_Ctrl[32].bit[0] = 0; + Tuner->Init_Ctrl[32].val[0] = 1; + Tuner->Init_Ctrl[32].addr[1] = 167; + Tuner->Init_Ctrl[32].bit[1] = 1; + Tuner->Init_Ctrl[32].val[1] = 1; + Tuner->Init_Ctrl[32].addr[2] = 167; + Tuner->Init_Ctrl[32].bit[2] = 2; + Tuner->Init_Ctrl[32].val[2] = 0; + + Tuner->Init_Ctrl[33].Ctrl_Num = RFA_FLR ; + Tuner->Init_Ctrl[33].size = 4 ; + Tuner->Init_Ctrl[33].addr[0] = 168; + Tuner->Init_Ctrl[33].bit[0] = 0; + Tuner->Init_Ctrl[33].val[0] = 0; + Tuner->Init_Ctrl[33].addr[1] = 168; + Tuner->Init_Ctrl[33].bit[1] = 1; + Tuner->Init_Ctrl[33].val[1] = 1; + Tuner->Init_Ctrl[33].addr[2] = 168; + Tuner->Init_Ctrl[33].bit[2] = 2; + Tuner->Init_Ctrl[33].val[2] = 0; + Tuner->Init_Ctrl[33].addr[3] = 168; + Tuner->Init_Ctrl[33].bit[3] = 3; + Tuner->Init_Ctrl[33].val[3] = 0; + + Tuner->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ; + Tuner->Init_Ctrl[34].size = 4 ; + Tuner->Init_Ctrl[34].addr[0] = 168; + Tuner->Init_Ctrl[34].bit[0] = 4; + Tuner->Init_Ctrl[34].val[0] = 1; + Tuner->Init_Ctrl[34].addr[1] = 168; + Tuner->Init_Ctrl[34].bit[1] = 5; + Tuner->Init_Ctrl[34].val[1] = 1; + Tuner->Init_Ctrl[34].addr[2] = 168; + Tuner->Init_Ctrl[34].bit[2] = 6; + Tuner->Init_Ctrl[34].val[2] = 1; + Tuner->Init_Ctrl[34].addr[3] = 168; + Tuner->Init_Ctrl[34].bit[3] = 7; + Tuner->Init_Ctrl[34].val[3] = 1; + + Tuner->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ; + Tuner->Init_Ctrl[35].size = 1 ; + Tuner->Init_Ctrl[35].addr[0] = 135; + Tuner->Init_Ctrl[35].bit[0] = 0; + Tuner->Init_Ctrl[35].val[0] = 0; + + Tuner->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ; + Tuner->Init_Ctrl[36].size = 1 ; + Tuner->Init_Ctrl[36].addr[0] = 56; + Tuner->Init_Ctrl[36].bit[0] = 3; + Tuner->Init_Ctrl[36].val[0] = 0; + + Tuner->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ; + Tuner->Init_Ctrl[37].size = 7 ; + Tuner->Init_Ctrl[37].addr[0] = 59; + Tuner->Init_Ctrl[37].bit[0] = 1; + Tuner->Init_Ctrl[37].val[0] = 0; + Tuner->Init_Ctrl[37].addr[1] = 59; + Tuner->Init_Ctrl[37].bit[1] = 2; + Tuner->Init_Ctrl[37].val[1] = 0; + Tuner->Init_Ctrl[37].addr[2] = 59; + Tuner->Init_Ctrl[37].bit[2] = 3; + Tuner->Init_Ctrl[37].val[2] = 0; + Tuner->Init_Ctrl[37].addr[3] = 59; + Tuner->Init_Ctrl[37].bit[3] = 4; + Tuner->Init_Ctrl[37].val[3] = 0; + Tuner->Init_Ctrl[37].addr[4] = 59; + Tuner->Init_Ctrl[37].bit[4] = 5; + Tuner->Init_Ctrl[37].val[4] = 0; + Tuner->Init_Ctrl[37].addr[5] = 59; + Tuner->Init_Ctrl[37].bit[5] = 6; + Tuner->Init_Ctrl[37].val[5] = 0; + Tuner->Init_Ctrl[37].addr[6] = 59; + Tuner->Init_Ctrl[37].bit[6] = 7; + Tuner->Init_Ctrl[37].val[6] = 0; + + Tuner->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ; + Tuner->Init_Ctrl[38].size = 6 ; + Tuner->Init_Ctrl[38].addr[0] = 32; + Tuner->Init_Ctrl[38].bit[0] = 2; + Tuner->Init_Ctrl[38].val[0] = 0; + Tuner->Init_Ctrl[38].addr[1] = 32; + Tuner->Init_Ctrl[38].bit[1] = 3; + Tuner->Init_Ctrl[38].val[1] = 0; + Tuner->Init_Ctrl[38].addr[2] = 32; + Tuner->Init_Ctrl[38].bit[2] = 4; + Tuner->Init_Ctrl[38].val[2] = 0; + Tuner->Init_Ctrl[38].addr[3] = 32; + Tuner->Init_Ctrl[38].bit[3] = 5; + Tuner->Init_Ctrl[38].val[3] = 0; + Tuner->Init_Ctrl[38].addr[4] = 32; + Tuner->Init_Ctrl[38].bit[4] = 6; + Tuner->Init_Ctrl[38].val[4] = 1; + Tuner->Init_Ctrl[38].addr[5] = 32; + Tuner->Init_Ctrl[38].bit[5] = 7; + Tuner->Init_Ctrl[38].val[5] = 0; + + Tuner->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ; + Tuner->Init_Ctrl[39].size = 1 ; + Tuner->Init_Ctrl[39].addr[0] = 25; + Tuner->Init_Ctrl[39].bit[0] = 3; + Tuner->Init_Ctrl[39].val[0] = 1; + + + Tuner->CH_Ctrl_Num = CHCTRL_NUM ; + + Tuner->CH_Ctrl[0].Ctrl_Num = DN_POLY ; + Tuner->CH_Ctrl[0].size = 2 ; + Tuner->CH_Ctrl[0].addr[0] = 68; + Tuner->CH_Ctrl[0].bit[0] = 6; + Tuner->CH_Ctrl[0].val[0] = 1; + Tuner->CH_Ctrl[0].addr[1] = 68; + Tuner->CH_Ctrl[0].bit[1] = 7; + Tuner->CH_Ctrl[0].val[1] = 1; + + Tuner->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ; + Tuner->CH_Ctrl[1].size = 2 ; + Tuner->CH_Ctrl[1].addr[0] = 70; + Tuner->CH_Ctrl[1].bit[0] = 6; + Tuner->CH_Ctrl[1].val[0] = 1; + Tuner->CH_Ctrl[1].addr[1] = 70; + Tuner->CH_Ctrl[1].bit[1] = 7; + Tuner->CH_Ctrl[1].val[1] = 0; + + Tuner->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ; + Tuner->CH_Ctrl[2].size = 9 ; + Tuner->CH_Ctrl[2].addr[0] = 69; + Tuner->CH_Ctrl[2].bit[0] = 5; + Tuner->CH_Ctrl[2].val[0] = 0; + Tuner->CH_Ctrl[2].addr[1] = 69; + Tuner->CH_Ctrl[2].bit[1] = 6; + Tuner->CH_Ctrl[2].val[1] = 0; + Tuner->CH_Ctrl[2].addr[2] = 69; + Tuner->CH_Ctrl[2].bit[2] = 7; + Tuner->CH_Ctrl[2].val[2] = 0; + Tuner->CH_Ctrl[2].addr[3] = 68; + Tuner->CH_Ctrl[2].bit[3] = 0; + Tuner->CH_Ctrl[2].val[3] = 0; + Tuner->CH_Ctrl[2].addr[4] = 68; + Tuner->CH_Ctrl[2].bit[4] = 1; + Tuner->CH_Ctrl[2].val[4] = 0; + Tuner->CH_Ctrl[2].addr[5] = 68; + Tuner->CH_Ctrl[2].bit[5] = 2; + Tuner->CH_Ctrl[2].val[5] = 0; + Tuner->CH_Ctrl[2].addr[6] = 68; + Tuner->CH_Ctrl[2].bit[6] = 3; + Tuner->CH_Ctrl[2].val[6] = 0; + Tuner->CH_Ctrl[2].addr[7] = 68; + Tuner->CH_Ctrl[2].bit[7] = 4; + Tuner->CH_Ctrl[2].val[7] = 0; + Tuner->CH_Ctrl[2].addr[8] = 68; + Tuner->CH_Ctrl[2].bit[8] = 5; + Tuner->CH_Ctrl[2].val[8] = 0; + + Tuner->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ; + Tuner->CH_Ctrl[3].size = 1 ; + Tuner->CH_Ctrl[3].addr[0] = 70; + Tuner->CH_Ctrl[3].bit[0] = 5; + Tuner->CH_Ctrl[3].val[0] = 0; + + Tuner->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ; + Tuner->CH_Ctrl[4].size = 3 ; + Tuner->CH_Ctrl[4].addr[0] = 73; + Tuner->CH_Ctrl[4].bit[0] = 4; + Tuner->CH_Ctrl[4].val[0] = 0; + Tuner->CH_Ctrl[4].addr[1] = 73; + Tuner->CH_Ctrl[4].bit[1] = 5; + Tuner->CH_Ctrl[4].val[1] = 1; + Tuner->CH_Ctrl[4].addr[2] = 73; + Tuner->CH_Ctrl[4].bit[2] = 6; + Tuner->CH_Ctrl[4].val[2] = 0; + + Tuner->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ; + Tuner->CH_Ctrl[5].size = 4 ; + Tuner->CH_Ctrl[5].addr[0] = 70; + Tuner->CH_Ctrl[5].bit[0] = 0; + Tuner->CH_Ctrl[5].val[0] = 0; + Tuner->CH_Ctrl[5].addr[1] = 70; + Tuner->CH_Ctrl[5].bit[1] = 1; + Tuner->CH_Ctrl[5].val[1] = 0; + Tuner->CH_Ctrl[5].addr[2] = 70; + Tuner->CH_Ctrl[5].bit[2] = 2; + Tuner->CH_Ctrl[5].val[2] = 0; + Tuner->CH_Ctrl[5].addr[3] = 70; + Tuner->CH_Ctrl[5].bit[3] = 3; + Tuner->CH_Ctrl[5].val[3] = 0; + + Tuner->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ; + Tuner->CH_Ctrl[6].size = 1 ; + Tuner->CH_Ctrl[6].addr[0] = 70; + Tuner->CH_Ctrl[6].bit[0] = 4; + Tuner->CH_Ctrl[6].val[0] = 1; + + Tuner->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ; + Tuner->CH_Ctrl[7].size = 1 ; + Tuner->CH_Ctrl[7].addr[0] = 111; + Tuner->CH_Ctrl[7].bit[0] = 4; + Tuner->CH_Ctrl[7].val[0] = 0; + + Tuner->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ; + Tuner->CH_Ctrl[8].size = 1 ; + Tuner->CH_Ctrl[8].addr[0] = 111; + Tuner->CH_Ctrl[8].bit[0] = 7; + Tuner->CH_Ctrl[8].val[0] = 1; + + Tuner->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ; + Tuner->CH_Ctrl[9].size = 1 ; + Tuner->CH_Ctrl[9].addr[0] = 111; + Tuner->CH_Ctrl[9].bit[0] = 6; + Tuner->CH_Ctrl[9].val[0] = 1; + + Tuner->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ; + Tuner->CH_Ctrl[10].size = 1 ; + Tuner->CH_Ctrl[10].addr[0] = 111; + Tuner->CH_Ctrl[10].bit[0] = 5; + Tuner->CH_Ctrl[10].val[0] = 0; + + Tuner->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ; + Tuner->CH_Ctrl[11].size = 2 ; + Tuner->CH_Ctrl[11].addr[0] = 110; + Tuner->CH_Ctrl[11].bit[0] = 0; + Tuner->CH_Ctrl[11].val[0] = 1; + Tuner->CH_Ctrl[11].addr[1] = 110; + Tuner->CH_Ctrl[11].bit[1] = 1; + Tuner->CH_Ctrl[11].val[1] = 0; + + Tuner->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ; + Tuner->CH_Ctrl[12].size = 3 ; + Tuner->CH_Ctrl[12].addr[0] = 69; + Tuner->CH_Ctrl[12].bit[0] = 2; + Tuner->CH_Ctrl[12].val[0] = 0; + Tuner->CH_Ctrl[12].addr[1] = 69; + Tuner->CH_Ctrl[12].bit[1] = 3; + Tuner->CH_Ctrl[12].val[1] = 0; + Tuner->CH_Ctrl[12].addr[2] = 69; + Tuner->CH_Ctrl[12].bit[2] = 4; + Tuner->CH_Ctrl[12].val[2] = 0; + + Tuner->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ; + Tuner->CH_Ctrl[13].size = 6 ; + Tuner->CH_Ctrl[13].addr[0] = 110; + Tuner->CH_Ctrl[13].bit[0] = 2; + Tuner->CH_Ctrl[13].val[0] = 0; + Tuner->CH_Ctrl[13].addr[1] = 110; + Tuner->CH_Ctrl[13].bit[1] = 3; + Tuner->CH_Ctrl[13].val[1] = 0; + Tuner->CH_Ctrl[13].addr[2] = 110; + Tuner->CH_Ctrl[13].bit[2] = 4; + Tuner->CH_Ctrl[13].val[2] = 0; + Tuner->CH_Ctrl[13].addr[3] = 110; + Tuner->CH_Ctrl[13].bit[3] = 5; + Tuner->CH_Ctrl[13].val[3] = 0; + Tuner->CH_Ctrl[13].addr[4] = 110; + Tuner->CH_Ctrl[13].bit[4] = 6; + Tuner->CH_Ctrl[13].val[4] = 0; + Tuner->CH_Ctrl[13].addr[5] = 110; + Tuner->CH_Ctrl[13].bit[5] = 7; + Tuner->CH_Ctrl[13].val[5] = 1; + + Tuner->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ; + Tuner->CH_Ctrl[14].size = 7 ; + Tuner->CH_Ctrl[14].addr[0] = 14; + Tuner->CH_Ctrl[14].bit[0] = 0; + Tuner->CH_Ctrl[14].val[0] = 0; + Tuner->CH_Ctrl[14].addr[1] = 14; + Tuner->CH_Ctrl[14].bit[1] = 1; + Tuner->CH_Ctrl[14].val[1] = 0; + Tuner->CH_Ctrl[14].addr[2] = 14; + Tuner->CH_Ctrl[14].bit[2] = 2; + Tuner->CH_Ctrl[14].val[2] = 0; + Tuner->CH_Ctrl[14].addr[3] = 14; + Tuner->CH_Ctrl[14].bit[3] = 3; + Tuner->CH_Ctrl[14].val[3] = 0; + Tuner->CH_Ctrl[14].addr[4] = 14; + Tuner->CH_Ctrl[14].bit[4] = 4; + Tuner->CH_Ctrl[14].val[4] = 0; + Tuner->CH_Ctrl[14].addr[5] = 14; + Tuner->CH_Ctrl[14].bit[5] = 5; + Tuner->CH_Ctrl[14].val[5] = 0; + Tuner->CH_Ctrl[14].addr[6] = 14; + Tuner->CH_Ctrl[14].bit[6] = 6; + Tuner->CH_Ctrl[14].val[6] = 0; + + Tuner->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ; + Tuner->CH_Ctrl[15].size = 18 ; + Tuner->CH_Ctrl[15].addr[0] = 17; + Tuner->CH_Ctrl[15].bit[0] = 6; + Tuner->CH_Ctrl[15].val[0] = 0; + Tuner->CH_Ctrl[15].addr[1] = 17; + Tuner->CH_Ctrl[15].bit[1] = 7; + Tuner->CH_Ctrl[15].val[1] = 0; + Tuner->CH_Ctrl[15].addr[2] = 16; + Tuner->CH_Ctrl[15].bit[2] = 0; + Tuner->CH_Ctrl[15].val[2] = 0; + Tuner->CH_Ctrl[15].addr[3] = 16; + Tuner->CH_Ctrl[15].bit[3] = 1; + Tuner->CH_Ctrl[15].val[3] = 0; + Tuner->CH_Ctrl[15].addr[4] = 16; + Tuner->CH_Ctrl[15].bit[4] = 2; + Tuner->CH_Ctrl[15].val[4] = 0; + Tuner->CH_Ctrl[15].addr[5] = 16; + Tuner->CH_Ctrl[15].bit[5] = 3; + Tuner->CH_Ctrl[15].val[5] = 0; + Tuner->CH_Ctrl[15].addr[6] = 16; + Tuner->CH_Ctrl[15].bit[6] = 4; + Tuner->CH_Ctrl[15].val[6] = 0; + Tuner->CH_Ctrl[15].addr[7] = 16; + Tuner->CH_Ctrl[15].bit[7] = 5; + Tuner->CH_Ctrl[15].val[7] = 0; + Tuner->CH_Ctrl[15].addr[8] = 16; + Tuner->CH_Ctrl[15].bit[8] = 6; + Tuner->CH_Ctrl[15].val[8] = 0; + Tuner->CH_Ctrl[15].addr[9] = 16; + Tuner->CH_Ctrl[15].bit[9] = 7; + Tuner->CH_Ctrl[15].val[9] = 0; + Tuner->CH_Ctrl[15].addr[10] = 15; + Tuner->CH_Ctrl[15].bit[10] = 0; + Tuner->CH_Ctrl[15].val[10] = 0; + Tuner->CH_Ctrl[15].addr[11] = 15; + Tuner->CH_Ctrl[15].bit[11] = 1; + Tuner->CH_Ctrl[15].val[11] = 0; + Tuner->CH_Ctrl[15].addr[12] = 15; + Tuner->CH_Ctrl[15].bit[12] = 2; + Tuner->CH_Ctrl[15].val[12] = 0; + Tuner->CH_Ctrl[15].addr[13] = 15; + Tuner->CH_Ctrl[15].bit[13] = 3; + Tuner->CH_Ctrl[15].val[13] = 0; + Tuner->CH_Ctrl[15].addr[14] = 15; + Tuner->CH_Ctrl[15].bit[14] = 4; + Tuner->CH_Ctrl[15].val[14] = 0; + Tuner->CH_Ctrl[15].addr[15] = 15; + Tuner->CH_Ctrl[15].bit[15] = 5; + Tuner->CH_Ctrl[15].val[15] = 0; + Tuner->CH_Ctrl[15].addr[16] = 15; + Tuner->CH_Ctrl[15].bit[16] = 6; + Tuner->CH_Ctrl[15].val[16] = 1; + Tuner->CH_Ctrl[15].addr[17] = 15; + Tuner->CH_Ctrl[15].bit[17] = 7; + Tuner->CH_Ctrl[15].val[17] = 1; + + Tuner->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ; + Tuner->CH_Ctrl[16].size = 5 ; + Tuner->CH_Ctrl[16].addr[0] = 112; + Tuner->CH_Ctrl[16].bit[0] = 0; + Tuner->CH_Ctrl[16].val[0] = 0; + Tuner->CH_Ctrl[16].addr[1] = 112; + Tuner->CH_Ctrl[16].bit[1] = 1; + Tuner->CH_Ctrl[16].val[1] = 0; + Tuner->CH_Ctrl[16].addr[2] = 112; + Tuner->CH_Ctrl[16].bit[2] = 2; + Tuner->CH_Ctrl[16].val[2] = 0; + Tuner->CH_Ctrl[16].addr[3] = 112; + Tuner->CH_Ctrl[16].bit[3] = 3; + Tuner->CH_Ctrl[16].val[3] = 0; + Tuner->CH_Ctrl[16].addr[4] = 112; + Tuner->CH_Ctrl[16].bit[4] = 4; + Tuner->CH_Ctrl[16].val[4] = 1; + + Tuner->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ; + Tuner->CH_Ctrl[17].size = 1 ; + Tuner->CH_Ctrl[17].addr[0] = 14; + Tuner->CH_Ctrl[17].bit[0] = 7; + Tuner->CH_Ctrl[17].val[0] = 0; + + Tuner->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ; + Tuner->CH_Ctrl[18].size = 4 ; + Tuner->CH_Ctrl[18].addr[0] = 107; + Tuner->CH_Ctrl[18].bit[0] = 3; + Tuner->CH_Ctrl[18].val[0] = 0; + Tuner->CH_Ctrl[18].addr[1] = 107; + Tuner->CH_Ctrl[18].bit[1] = 4; + Tuner->CH_Ctrl[18].val[1] = 0; + Tuner->CH_Ctrl[18].addr[2] = 107; + Tuner->CH_Ctrl[18].bit[2] = 5; + Tuner->CH_Ctrl[18].val[2] = 0; + Tuner->CH_Ctrl[18].addr[3] = 107; + Tuner->CH_Ctrl[18].bit[3] = 6; + Tuner->CH_Ctrl[18].val[3] = 0; + + Tuner->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ; + Tuner->CH_Ctrl[19].size = 3 ; + Tuner->CH_Ctrl[19].addr[0] = 107; + Tuner->CH_Ctrl[19].bit[0] = 7; + Tuner->CH_Ctrl[19].val[0] = 1; + Tuner->CH_Ctrl[19].addr[1] = 106; + Tuner->CH_Ctrl[19].bit[1] = 0; + Tuner->CH_Ctrl[19].val[1] = 1; + Tuner->CH_Ctrl[19].addr[2] = 106; + Tuner->CH_Ctrl[19].bit[2] = 1; + Tuner->CH_Ctrl[19].val[2] = 1; + + Tuner->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ; + Tuner->CH_Ctrl[20].size = 11 ; + Tuner->CH_Ctrl[20].addr[0] = 109; + Tuner->CH_Ctrl[20].bit[0] = 2; + Tuner->CH_Ctrl[20].val[0] = 0; + Tuner->CH_Ctrl[20].addr[1] = 109; + Tuner->CH_Ctrl[20].bit[1] = 3; + Tuner->CH_Ctrl[20].val[1] = 0; + Tuner->CH_Ctrl[20].addr[2] = 109; + Tuner->CH_Ctrl[20].bit[2] = 4; + Tuner->CH_Ctrl[20].val[2] = 0; + Tuner->CH_Ctrl[20].addr[3] = 109; + Tuner->CH_Ctrl[20].bit[3] = 5; + Tuner->CH_Ctrl[20].val[3] = 0; + Tuner->CH_Ctrl[20].addr[4] = 109; + Tuner->CH_Ctrl[20].bit[4] = 6; + Tuner->CH_Ctrl[20].val[4] = 0; + Tuner->CH_Ctrl[20].addr[5] = 109; + Tuner->CH_Ctrl[20].bit[5] = 7; + Tuner->CH_Ctrl[20].val[5] = 0; + Tuner->CH_Ctrl[20].addr[6] = 108; + Tuner->CH_Ctrl[20].bit[6] = 0; + Tuner->CH_Ctrl[20].val[6] = 0; + Tuner->CH_Ctrl[20].addr[7] = 108; + Tuner->CH_Ctrl[20].bit[7] = 1; + Tuner->CH_Ctrl[20].val[7] = 0; + Tuner->CH_Ctrl[20].addr[8] = 108; + Tuner->CH_Ctrl[20].bit[8] = 2; + Tuner->CH_Ctrl[20].val[8] = 1; + Tuner->CH_Ctrl[20].addr[9] = 108; + Tuner->CH_Ctrl[20].bit[9] = 3; + Tuner->CH_Ctrl[20].val[9] = 1; + Tuner->CH_Ctrl[20].addr[10] = 108; + Tuner->CH_Ctrl[20].bit[10] = 4; + Tuner->CH_Ctrl[20].val[10] = 1; + + Tuner->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ; + Tuner->CH_Ctrl[21].size = 6 ; + Tuner->CH_Ctrl[21].addr[0] = 106; + Tuner->CH_Ctrl[21].bit[0] = 2; + Tuner->CH_Ctrl[21].val[0] = 0; + Tuner->CH_Ctrl[21].addr[1] = 106; + Tuner->CH_Ctrl[21].bit[1] = 3; + Tuner->CH_Ctrl[21].val[1] = 0; + Tuner->CH_Ctrl[21].addr[2] = 106; + Tuner->CH_Ctrl[21].bit[2] = 4; + Tuner->CH_Ctrl[21].val[2] = 0; + Tuner->CH_Ctrl[21].addr[3] = 106; + Tuner->CH_Ctrl[21].bit[3] = 5; + Tuner->CH_Ctrl[21].val[3] = 0; + Tuner->CH_Ctrl[21].addr[4] = 106; + Tuner->CH_Ctrl[21].bit[4] = 6; + Tuner->CH_Ctrl[21].val[4] = 0; + Tuner->CH_Ctrl[21].addr[5] = 106; + Tuner->CH_Ctrl[21].bit[5] = 7; + Tuner->CH_Ctrl[21].val[5] = 1; + + Tuner->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ; + Tuner->CH_Ctrl[22].size = 1 ; + Tuner->CH_Ctrl[22].addr[0] = 138; + Tuner->CH_Ctrl[22].bit[0] = 4; + Tuner->CH_Ctrl[22].val[0] = 1; + + Tuner->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ; + Tuner->CH_Ctrl[23].size = 1 ; + Tuner->CH_Ctrl[23].addr[0] = 17; + Tuner->CH_Ctrl[23].bit[0] = 5; + Tuner->CH_Ctrl[23].val[0] = 0; + + Tuner->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ; + Tuner->CH_Ctrl[24].size = 1 ; + Tuner->CH_Ctrl[24].addr[0] = 111; + Tuner->CH_Ctrl[24].bit[0] = 3; + Tuner->CH_Ctrl[24].val[0] = 0; + + Tuner->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ; + Tuner->CH_Ctrl[25].size = 1 ; + Tuner->CH_Ctrl[25].addr[0] = 112; + Tuner->CH_Ctrl[25].bit[0] = 7; + Tuner->CH_Ctrl[25].val[0] = 0; + + Tuner->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ; + Tuner->CH_Ctrl[26].size = 1 ; + Tuner->CH_Ctrl[26].addr[0] = 136; + Tuner->CH_Ctrl[26].bit[0] = 7; + Tuner->CH_Ctrl[26].val[0] = 0; + + Tuner->CH_Ctrl[27].Ctrl_Num = GPIO_4B ; + Tuner->CH_Ctrl[27].size = 1 ; + Tuner->CH_Ctrl[27].addr[0] = 149; + Tuner->CH_Ctrl[27].bit[0] = 7; + Tuner->CH_Ctrl[27].val[0] = 0; + + Tuner->CH_Ctrl[28].Ctrl_Num = GPIO_3B ; + Tuner->CH_Ctrl[28].size = 1 ; + Tuner->CH_Ctrl[28].addr[0] = 149; + Tuner->CH_Ctrl[28].bit[0] = 6; + Tuner->CH_Ctrl[28].val[0] = 0; + + Tuner->CH_Ctrl[29].Ctrl_Num = GPIO_4 ; + Tuner->CH_Ctrl[29].size = 1 ; + Tuner->CH_Ctrl[29].addr[0] = 149; + Tuner->CH_Ctrl[29].bit[0] = 5; + Tuner->CH_Ctrl[29].val[0] = 1; + + Tuner->CH_Ctrl[30].Ctrl_Num = GPIO_3 ; + Tuner->CH_Ctrl[30].size = 1 ; + Tuner->CH_Ctrl[30].addr[0] = 149; + Tuner->CH_Ctrl[30].bit[0] = 4; + Tuner->CH_Ctrl[30].val[0] = 1; + + Tuner->CH_Ctrl[31].Ctrl_Num = GPIO_1B ; + Tuner->CH_Ctrl[31].size = 1 ; + Tuner->CH_Ctrl[31].addr[0] = 149; + Tuner->CH_Ctrl[31].bit[0] = 3; + Tuner->CH_Ctrl[31].val[0] = 0; + + Tuner->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ; + Tuner->CH_Ctrl[32].size = 1 ; + Tuner->CH_Ctrl[32].addr[0] = 93; + Tuner->CH_Ctrl[32].bit[0] = 1; + Tuner->CH_Ctrl[32].val[0] = 0; + + Tuner->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ; + Tuner->CH_Ctrl[33].size = 1 ; + Tuner->CH_Ctrl[33].addr[0] = 93; + Tuner->CH_Ctrl[33].bit[0] = 0; + Tuner->CH_Ctrl[33].val[0] = 0; + + Tuner->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ; + Tuner->CH_Ctrl[34].size = 6 ; + Tuner->CH_Ctrl[34].addr[0] = 92; + Tuner->CH_Ctrl[34].bit[0] = 2; + Tuner->CH_Ctrl[34].val[0] = 0; + Tuner->CH_Ctrl[34].addr[1] = 92; + Tuner->CH_Ctrl[34].bit[1] = 3; + Tuner->CH_Ctrl[34].val[1] = 0; + Tuner->CH_Ctrl[34].addr[2] = 92; + Tuner->CH_Ctrl[34].bit[2] = 4; + Tuner->CH_Ctrl[34].val[2] = 0; + Tuner->CH_Ctrl[34].addr[3] = 92; + Tuner->CH_Ctrl[34].bit[3] = 5; + Tuner->CH_Ctrl[34].val[3] = 0; + Tuner->CH_Ctrl[34].addr[4] = 92; + Tuner->CH_Ctrl[34].bit[4] = 6; + Tuner->CH_Ctrl[34].val[4] = 0; + Tuner->CH_Ctrl[34].addr[5] = 92; + Tuner->CH_Ctrl[34].bit[5] = 7; + Tuner->CH_Ctrl[34].val[5] = 0; + + Tuner->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ; + Tuner->CH_Ctrl[35].size = 6 ; + Tuner->CH_Ctrl[35].addr[0] = 93; + Tuner->CH_Ctrl[35].bit[0] = 2; + Tuner->CH_Ctrl[35].val[0] = 0; + Tuner->CH_Ctrl[35].addr[1] = 93; + Tuner->CH_Ctrl[35].bit[1] = 3; + Tuner->CH_Ctrl[35].val[1] = 0; + Tuner->CH_Ctrl[35].addr[2] = 93; + Tuner->CH_Ctrl[35].bit[2] = 4; + Tuner->CH_Ctrl[35].val[2] = 0; + Tuner->CH_Ctrl[35].addr[3] = 93; + Tuner->CH_Ctrl[35].bit[3] = 5; + Tuner->CH_Ctrl[35].val[3] = 0; + Tuner->CH_Ctrl[35].addr[4] = 93; + Tuner->CH_Ctrl[35].bit[4] = 6; + Tuner->CH_Ctrl[35].val[4] = 0; + Tuner->CH_Ctrl[35].addr[5] = 93; + Tuner->CH_Ctrl[35].bit[5] = 7; + Tuner->CH_Ctrl[35].val[5] = 0; + +#ifdef _MXL_PRODUCTION + Tuner->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ; + Tuner->CH_Ctrl[36].size = 1 ; + Tuner->CH_Ctrl[36].addr[0] = 109; + Tuner->CH_Ctrl[36].bit[0] = 1; + Tuner->CH_Ctrl[36].val[0] = 1; + + Tuner->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ; + Tuner->CH_Ctrl[37].size = 2 ; + Tuner->CH_Ctrl[37].addr[0] = 112; + Tuner->CH_Ctrl[37].bit[0] = 5; + Tuner->CH_Ctrl[37].val[0] = 0; + Tuner->CH_Ctrl[37].addr[1] = 112; + Tuner->CH_Ctrl[37].bit[1] = 6; + Tuner->CH_Ctrl[37].val[1] = 0; + + Tuner->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ; + Tuner->CH_Ctrl[38].size = 1 ; + Tuner->CH_Ctrl[38].addr[0] = 65; + Tuner->CH_Ctrl[38].bit[0] = 1; + Tuner->CH_Ctrl[38].val[0] = 0; +#endif + + return 0 ; +} + + + + + + + + + + + + + + + +// MaxLinear source code - MXL5005_c.cpp + + + +// MXL5005.cpp : Defines the initialization routines for the DLL. +// 2.6.12 + + +//#ifdef _MXL_HEADER +//#include "stdafx.h" +//#endif +//#include "MXL5005_c.h" + + +void InitTunerControls(Tuner_struct *Tuner) +{ + MXL5005_RegisterInit(Tuner) ; + MXL5005_ControlInit(Tuner) ; +#ifdef _MXL_INTERNAL + MXL5005_MXLControlInit(Tuner) ; +#endif +} + + + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_ConfigTuner // +// // +// Description: Configure MXL5005Tuner structure for desired // +// Channel Bandwidth/Channel Frequency // +// // +// // +// Functions used: // +// MXL_SynthIFLO_Calc // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// Mode: Tuner Mode (Analog/Digital) // +// IF_Mode: IF Mode ( Zero/Low ) // +// Bandwidth: Filter Channel Bandwidth (in Hz) // +// IF_out: Desired IF out Frequency (in Hz) // +// Fxtal: Crystal Frerquency (in Hz) // +// TOP: 0: Dual AGC; Value: take over point // +// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // +// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // +// DIV_OUT: 0: Div-1; 1: Div-4 // +// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // +// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL5005_TunerConfig(Tuner_struct *Tuner, + _u8 Mode, // 0: Analog Mode ; 1: Digital Mode + _u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF + _u32 Bandwidth, // filter channel bandwidth (6, 7, 8) + _u32 IF_out, // Desired IF Out Frequency + _u32 Fxtal, // XTAL Frequency + _u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 + _u16 TOP, // 0: Dual AGC; Value: take over point + _u16 IF_OUT_LOAD, // IF Out Load Resistor (200 / 300 Ohms) + _u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out + _u8 DIV_OUT, // 0: Div-1; 1: Div-4 + _u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable + _u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI + _u8 Mod_Type, // Modulation Type; + // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable + _u8 TF_Type // Tracking Filter + // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H + ) +{ + _u16 status = 0 ; + + Tuner->Mode = Mode ; + Tuner->IF_Mode = IF_mode ; + Tuner->Chan_Bandwidth = Bandwidth ; + Tuner->IF_OUT = IF_out ; + Tuner->Fxtal = Fxtal ; + Tuner->AGC_Mode = AGC_Mode ; + Tuner->TOP = TOP ; + Tuner->IF_OUT_LOAD = IF_OUT_LOAD ; + Tuner->CLOCK_OUT = CLOCK_OUT ; + Tuner->DIV_OUT = DIV_OUT ; + Tuner->CAPSELECT = CAPSELECT ; + Tuner->EN_RSSI = EN_RSSI ; + Tuner->Mod_Type = Mod_Type ; + Tuner->TF_Type = TF_Type ; + + + + // + // Initialize all the controls and registers + // + InitTunerControls (Tuner) ; + // + // Synthesizer LO frequency calculation + // + MXL_SynthIFLO_Calc( Tuner ) ; + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_SynthIFLO_Calc // +// // +// Description: Calculate Internal IF-LO Frequency // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +void MXL_SynthIFLO_Calc(Tuner_struct *Tuner) +{ + if (Tuner->Mode == 1) // Digital Mode + { + Tuner->IF_LO = Tuner->IF_OUT ; + } + else // Analog Mode + { + if(Tuner->IF_Mode == 0) // Analog Zero IF mode + { + Tuner->IF_LO = Tuner->IF_OUT + 400000 ; + } + else // Analog Low IF mode + { + Tuner->IF_LO = Tuner->IF_OUT + Tuner->Chan_Bandwidth/2 ; + } + } +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_SynthRFTGLO_Calc // +// // +// Description: Calculate Internal RF-LO frequency and // +// internal Tone-Gen(TG)-LO frequency // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) +{ + if (Tuner->Mode == 1) // Digital Mode + { + //remove 20.48MHz setting for 2.6.10 + Tuner->RF_LO = Tuner->RF_IN ; + Tuner->TG_LO = Tuner->RF_IN - 750000 ; //change for 2.6.6 + } + else // Analog Mode + { + if(Tuner->IF_Mode == 0) // Analog Zero IF mode + { + Tuner->RF_LO = Tuner->RF_IN - 400000 ; + Tuner->TG_LO = Tuner->RF_IN - 1750000 ; + } + else // Analog Low IF mode + { + Tuner->RF_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth/2 ; + Tuner->TG_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth + 500000 ; + } + } +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_OverwriteICDefault // +// // +// Description: Overwrite the Default Register Setting // +// // +// // +// Functions used: // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) +{ + _u16 status = 0 ; + + status += MXL_ControlWrite(Tuner, OVERRIDE_1, 1) ; + status += MXL_ControlWrite(Tuner, OVERRIDE_2, 1) ; + status += MXL_ControlWrite(Tuner, OVERRIDE_3, 1) ; + status += MXL_ControlWrite(Tuner, OVERRIDE_4, 1) ; + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_BlockInit // +// // +// Description: Tuner Initialization as a function of 'User Settings' // +// * User settings in Tuner strcuture must be assigned // +// first // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// Tuner_struct: structure defined at higher level // +// // +// Inputs: // +// Tuner : Tuner structure defined at higher level // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_BlockInit( Tuner_struct *Tuner ) +{ + _u16 status = 0 ; + + status += MXL_OverwriteICDefault(Tuner) ; + + // + // Downconverter Control + // Dig Ana + status += MXL_ControlWrite(Tuner, DN_IQTN_AMP_CUT, Tuner->Mode ? 1 : 0) ; + + // + // Filter Control + // Dig Ana + status += MXL_ControlWrite(Tuner, BB_MODE, Tuner->Mode ? 0 : 1) ; + status += MXL_ControlWrite(Tuner, BB_BUF, Tuner->Mode ? 3 : 2) ; + status += MXL_ControlWrite(Tuner, BB_BUF_OA, Tuner->Mode ? 1 : 0) ; + + status += MXL_ControlWrite(Tuner, BB_IQSWAP, Tuner->Mode ? 0 : 1) ; + status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 0) ; + + // Initialize Low-Pass Filter + if (Tuner->Mode) { // Digital Mode + switch (Tuner->Chan_Bandwidth) { + case 8000000: + status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 0) ; + break ; + case 7000000: + status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 2) ; + break ; + case 6000000: + status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 3) ; + break ; + } + } else { // Analog Mode + switch (Tuner->Chan_Bandwidth) { + case 8000000: // Low Zero + status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 0 : 3)) ; + break ; + case 7000000: + status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 1 : 4)) ; + break ; + case 6000000: + status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 2 : 5)) ; + break ; + } + } + + // + // Charge Pump Control + // Dig Ana + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, Tuner->Mode ? 5 : 8) ; + status += MXL_ControlWrite(Tuner, RFSYN_EN_CHP_HIGAIN, Tuner->Mode ? 1 : 1) ; + status += MXL_ControlWrite(Tuner, EN_CHP_LIN_B, Tuner->Mode ? 0 : 0) ; + + // + // AGC TOP Control + // + if (Tuner->AGC_Mode == 0) // Dual AGC + { + status += MXL_ControlWrite(Tuner, AGC_IF, 15) ; + status += MXL_ControlWrite(Tuner, AGC_RF, 15) ; + } + else // Single AGC Mode Dig Ana + status += MXL_ControlWrite(Tuner, AGC_RF, Tuner->Mode? 15 : 12) ; + + + if (Tuner->TOP == 55) // TOP == 5.5 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x0) ; + + if (Tuner->TOP == 72) // TOP == 7.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x1) ; + + if (Tuner->TOP == 92) // TOP == 9.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x2) ; + + if (Tuner->TOP == 110) // TOP == 11.0 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x3) ; + + if (Tuner->TOP == 129) // TOP == 12.9 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x4) ; + + if (Tuner->TOP == 147) // TOP == 14.7 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x5) ; + + if (Tuner->TOP == 168) // TOP == 16.8 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x6) ; + + if (Tuner->TOP == 194) // TOP == 19.4 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x7) ; + + if (Tuner->TOP == 212) // TOP == 21.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x9) ; + + if (Tuner->TOP == 232) // TOP == 23.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xA) ; + + if (Tuner->TOP == 252) // TOP == 25.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xB) ; + + if (Tuner->TOP == 271) // TOP == 27.1 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xC) ; + + if (Tuner->TOP == 292) // TOP == 29.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xD) ; + + if (Tuner->TOP == 317) // TOP == 31.7 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xE) ; + + if (Tuner->TOP == 349) // TOP == 34.9 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xF) ; + + // + // IF Synthesizer Control + // + status += MXL_IFSynthInit( Tuner ) ; + + // + // IF UpConverter Control + if (Tuner->IF_OUT_LOAD == 200) + { + status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 6) ; + status += MXL_ControlWrite(Tuner, I_DRIVER, 2) ; + } + if (Tuner->IF_OUT_LOAD == 300) + { + status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 4) ; + status += MXL_ControlWrite(Tuner, I_DRIVER, 1) ; + } + + // + // Anti-Alias Filtering Control + // + // initialise Anti-Aliasing Filter + if (Tuner->Mode) {// Digital Mode + if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 6280000UL) { + status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; + status += MXL_ControlWrite(Tuner, EN_3P, 1) ; + status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; + status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; + } + if ((Tuner->IF_OUT == 36125000UL) || (Tuner->IF_OUT == 36150000UL)) { + status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; + status += MXL_ControlWrite(Tuner, EN_3P, 1) ; + status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; + status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ; + } + if (Tuner->IF_OUT > 36150000UL) { + status += MXL_ControlWrite(Tuner, EN_AAF, 0) ; + status += MXL_ControlWrite(Tuner, EN_3P, 1) ; + status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; + status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ; + } + } else { // Analog Mode + if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 5000000UL) + { + status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; + status += MXL_ControlWrite(Tuner, EN_3P, 1) ; + status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; + status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; + } + if (Tuner->IF_OUT > 5000000UL) + { + status += MXL_ControlWrite(Tuner, EN_AAF, 0) ; + status += MXL_ControlWrite(Tuner, EN_3P, 0) ; + status += MXL_ControlWrite(Tuner, EN_AUX_3P, 0) ; + status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; + } + } + + // + // Demod Clock Out + // + if (Tuner->CLOCK_OUT) + status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 1) ; + else + status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 0) ; + + if (Tuner->DIV_OUT == 1) + status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 1) ; + if (Tuner->DIV_OUT == 0) + status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 0) ; + + // + // Crystal Control + // + if (Tuner->CAPSELECT) + status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 1) ; + else + status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 0) ; + + if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) + status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 1) ; + if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL) + status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 0) ; + + if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL) + status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 3) ; + if (Tuner->Fxtal > 22000000UL && Tuner->Fxtal <= 32000000UL) + status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 0) ; + + // + // Misc Controls + // + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog LowIF mode + status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 0); + else + status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 1); + +// status += MXL_ControlRead(Tuner, IF_DIVVAL, &IF_DIVVAL_Val) ; + + // Set TG_R_DIV + status += MXL_ControlWrite(Tuner, TG_R_DIV, MXL_Ceiling(Tuner->Fxtal, 1000000)) ; + + // + // Apply Default value to BB_INITSTATE_DLPF_TUNE + // + + + + // + // RSSI Control + // + if(Tuner->EN_RSSI) + { + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 3) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; + // TOP point + status += MXL_ControlWrite(Tuner, RFA_FLR, 0) ; + status += MXL_ControlWrite(Tuner, RFA_CEIL, 12) ; + } + + // + // Modulation type bit settings + // Override the control values preset + // + if (Tuner->Mod_Type == MXL_DVBT) // DVB-T Mode + { + Tuner->AGC_Mode = 1 ; // Single AGC Mode + + // Enable RSSI + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; + // TOP point + status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ; + status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ; + if (Tuner->IF_OUT <= 6280000UL) // Low IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; + else // High IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + + } + if (Tuner->Mod_Type == MXL_ATSC) // ATSC Mode + { + Tuner->AGC_Mode = 1 ; // Single AGC Mode + + // Enable RSSI + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 4) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; + // TOP point + status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ; + status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ; + + status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ; // Low Zero + if (Tuner->IF_OUT <= 6280000UL) // Low IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; + else // High IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + } + if (Tuner->Mod_Type == MXL_QAM) // QAM Mode + { + Tuner->Mode = MXL_DIGITAL_MODE; + + //Tuner->AGC_Mode = 1 ; // Single AGC Mode + + // Disable RSSI //change here for v2.6.5 + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; + + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; //change here for v2.6.5 + + if (Tuner->IF_OUT <= 6280000UL) // Low IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; + else // High IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + } + if (Tuner->Mod_Type == MXL_ANALOG_CABLE) // Analog Cable Mode + { + //Tuner->Mode = MXL_DIGITAL_MODE ; + Tuner->AGC_Mode = 1 ; // Single AGC Mode + + // Disable RSSI + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + + status += MXL_ControlWrite(Tuner, AGC_IF, 1) ; //change for 2.6.3 + status += MXL_ControlWrite(Tuner, AGC_RF, 15) ; + + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + } + + if (Tuner->Mod_Type == MXL_ANALOG_OTA) //Analog OTA Terrestrial mode add for 2.6.7 + { + //Tuner->Mode = MXL_ANALOG_MODE; + + // Enable RSSI + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; + + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; + + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + } + + // RSSI disable + if(Tuner->EN_RSSI==0) + { + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + } + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_IFSynthInit // +// // +// Description: Tuner IF Synthesizer related register initialization // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// Tuner_struct: structure defined at higher level // +// // +// Inputs: // +// Tuner : Tuner structure defined at higher level // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_IFSynthInit( Tuner_struct * Tuner ) +{ + _u16 status = 0 ; + // Declare Local Variables + _u32 Fref = 0 ; + _u32 Kdbl, intModVal ; + _u32 fracModVal ; + Kdbl = 2 ; + + if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) + Kdbl = 2 ; + if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL) + Kdbl = 1 ; + + // + // IF Synthesizer Control + // + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF mode + { + if (Tuner->IF_LO == 41000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 328000000UL ; + } + if (Tuner->IF_LO == 47000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 376000000UL ; + } + if (Tuner->IF_LO == 54000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 324000000UL ; + } + if (Tuner->IF_LO == 60000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 39250000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 314000000UL ; + } + if (Tuner->IF_LO == 39650000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 317200000UL ; + } + if (Tuner->IF_LO == 40150000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 321200000UL ; + } + if (Tuner->IF_LO == 40650000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 325200000UL ; + } + } + + if (Tuner->Mode || (Tuner->Mode == 0 && Tuner->IF_Mode == 0)) + { + if (Tuner->IF_LO == 57000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 342000000UL ; + } + if (Tuner->IF_LO == 44000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 352000000UL ; + } + if (Tuner->IF_LO == 43750000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 350000000UL ; + } + if (Tuner->IF_LO == 36650000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 366500000UL ; + } + if (Tuner->IF_LO == 36150000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 361500000UL ; + } + if (Tuner->IF_LO == 36000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 35250000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 352500000UL ; + } + if (Tuner->IF_LO == 34750000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 347500000UL ; + } + if (Tuner->IF_LO == 6280000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 376800000UL ; + } + if (Tuner->IF_LO == 5000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 4500000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 4570000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 365600000UL ; + } + if (Tuner->IF_LO == 4000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 57400000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 344400000UL ; + } + if (Tuner->IF_LO == 44400000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 355200000UL ; + } + if (Tuner->IF_LO == 44150000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 353200000UL ; + } + if (Tuner->IF_LO == 37050000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 370500000UL ; + } + if (Tuner->IF_LO == 36550000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 365500000UL ; + } + if (Tuner->IF_LO == 36125000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 361250000UL ; + } + if (Tuner->IF_LO == 6000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 5400000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 324000000UL ; + } + if (Tuner->IF_LO == 5380000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 322800000UL ; + } + if (Tuner->IF_LO == 5200000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 374400000UL ; + } + if (Tuner->IF_LO == 4900000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 352800000UL ; + } + if (Tuner->IF_LO == 4400000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 352000000UL ; + } + if (Tuner->IF_LO == 4063000UL) //add for 2.6.8 + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 365670000UL ; + } + } + // CHCAL_INT_MOD_IF + // CHCAL_FRAC_MOD_IF + intModVal = Fref / (Tuner->Fxtal * Kdbl/2) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_IF, intModVal ) ; + + fracModVal = (2<<15)*(Fref/1000 - (Tuner->Fxtal/1000 * Kdbl/2) * intModVal); + fracModVal = fracModVal / ((Tuner->Fxtal * Kdbl/2)/1000) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_IF, fracModVal) ; + + + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_GetXtalInt // +// // +// Description: return the Crystal Integration Value for // +// TG_VCO_BIAS calculation // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// Crystal Frequency Value in Hz // +// // +// Outputs: // +// Calculated Crystal Frequency Integration Value // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +_u32 MXL_GetXtalInt(_u32 Xtal_Freq) +{ + if ((Xtal_Freq % 1000000) == 0) + return (Xtal_Freq / 10000) ; + else + return (((Xtal_Freq / 1000000) + 1)*100) ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL5005_TuneRF // +// // +// Description: Set control names to tune to requested RF_IN frequency // +// // +// Globals: // +// None // +// // +// Functions used: // +// MXL_SynthRFTGLO_Calc // +// MXL5005_ControlWrite // +// MXL_GetXtalInt // +// // +// Inputs: // +// Tuner : Tuner structure defined at higher level // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// 1 : Unsuccessful // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) +{ + // Declare Local Variables + _u16 status = 0 ; + _u32 divider_val, E3, E4, E5, E5A ; + _u32 Fmax, Fmin, FmaxBin, FminBin ; + _u32 Kdbl_RF = 2; + _u32 tg_divval ; + _u32 tg_lo ; + _u32 Xtal_Int ; + + _u32 Fref_TG; + _u32 Fvco; +// _u32 temp; + + + Xtal_Int = MXL_GetXtalInt(Tuner->Fxtal ) ; + + Tuner->RF_IN = RF_Freq ; + + MXL_SynthRFTGLO_Calc( Tuner ) ; + + if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL) + Kdbl_RF = 2 ; + if (Tuner->Fxtal > 22000000 && Tuner->Fxtal <= 32000000) + Kdbl_RF = 1 ; + + // + // Downconverter Controls + // + // Look-Up Table Implementation for: + // DN_POLY + // DN_RFGAIN + // DN_CAP_RFLPF + // DN_EN_VHFUHFBAR + // DN_GAIN_ADJUST + // Change the boundary reference from RF_IN to RF_LO + if (Tuner->RF_LO < 40000000UL) { + return -1; + } + if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 2) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 423) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ; + } + if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 222) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ; + } + if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 147) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ; + } + if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 9) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ; + } + if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + } + if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 650000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 1) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + } + if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 900000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 2) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + } + if (Tuner->RF_LO > 900000000UL) { + return -1; + } + // DN_IQTNBUF_AMP + // DN_IQTNGNBFBIAS_BST + if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 400000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 400000000UL && Tuner->RF_LO <= 450000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 450000000UL && Tuner->RF_LO <= 500000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 500000000UL && Tuner->RF_LO <= 550000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 550000000UL && Tuner->RF_LO <= 600000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 600000000UL && Tuner->RF_LO <= 650000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 700000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 700000000UL && Tuner->RF_LO <= 750000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 750000000UL && Tuner->RF_LO <= 800000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 800000000UL && Tuner->RF_LO <= 850000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ; + } + if (Tuner->RF_LO > 850000000UL && Tuner->RF_LO <= 900000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ; + } + + // + // Set RF Synth and LO Path Control + // + // Look-Up table implementation for: + // RFSYN_EN_OUTMUX + // RFSYN_SEL_VCO_OUT + // RFSYN_SEL_VCO_HI + // RFSYN_SEL_DIVM + // RFSYN_RF_DIV_BIAS + // DN_SEL_FREQ + // + // Set divider_val, Fmax, Fmix to use in Equations + FminBin = 28000000UL ; + FmaxBin = 42500000UL ; + if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + divider_val = 64 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 42500000UL ; + FmaxBin = 56000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + divider_val = 64 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 56000000UL ; + FmaxBin = 85000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + divider_val = 32 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 85000000UL ; + FmaxBin = 112000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + divider_val = 32 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 112000000UL ; + FmaxBin = 170000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ; + divider_val = 16 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 170000000UL ; + FmaxBin = 225000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ; + divider_val = 16 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 225000000UL ; + FmaxBin = 300000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 4) ; + divider_val = 8 ; + Fmax = 340000000UL ; + Fmin = FminBin ; + } + FminBin = 300000000UL ; + FmaxBin = 340000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + divider_val = 8 ; + Fmax = FmaxBin ; + Fmin = 225000000UL ; + } + FminBin = 340000000UL ; + FmaxBin = 450000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 2) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + divider_val = 8 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 450000000UL ; + FmaxBin = 680000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + divider_val = 4 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 680000000UL ; + FmaxBin = 900000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + divider_val = 4 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + + // CHCAL_INT_MOD_RF + // CHCAL_FRAC_MOD_RF + // RFSYN_LPF_R + // CHCAL_EN_INT_RF + + // Equation E3 + // RFSYN_VCO_BIAS + E3 = (((Fmax-Tuner->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, E3) ; + + // Equation E4 + // CHCAL_INT_MOD_RF + E4 = (Tuner->RF_LO*divider_val/1000)/(2*Tuner->Fxtal*Kdbl_RF/1000) ; + MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, E4) ; + + // Equation E5 + // CHCAL_FRAC_MOD_RF + // CHCAL_EN_INT_RF + E5 = ((2<<17)*(Tuner->RF_LO/10000*divider_val - (E4*(2*Tuner->Fxtal*Kdbl_RF)/10000)))/(2*Tuner->Fxtal*Kdbl_RF/10000) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ; + + // Equation E5A + // RFSYN_LPF_R + E5A = (((Fmax - Tuner->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; + status += MXL_ControlWrite(Tuner, RFSYN_LPF_R, E5A) ; + + // Euqation E5B + // CHCAL_EN_INIT_RF + status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0)); + //if (E5 == 0) + // status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, 1); + //else + // status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ; + + // + // Set TG Synth + // + // Look-Up table implementation for: + // TG_LO_DIVVAL + // TG_LO_SELVAL + // + // Set divider_val, Fmax, Fmix to use in Equations + if (Tuner->TG_LO < 33000000UL) { + return -1; + } + FminBin = 33000000UL ; + FmaxBin = 50000000UL ; + if (Tuner->TG_LO >= FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x6) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ; + divider_val = 36 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 50000000UL ; + FmaxBin = 67000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x1) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ; + divider_val = 24 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 67000000UL ; + FmaxBin = 100000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0xC) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + divider_val = 18 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 100000000UL ; + FmaxBin = 150000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + divider_val = 12 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 150000000UL ; + FmaxBin = 200000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + divider_val = 8 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 200000000UL ; + FmaxBin = 300000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ; + divider_val = 6 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 300000000UL ; + FmaxBin = 400000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ; + divider_val = 4 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 400000000UL ; + FmaxBin = 600000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ; + divider_val = 3 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 600000000UL ; + FmaxBin = 900000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ; + divider_val = 2 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + + // TG_DIV_VAL + tg_divval = (Tuner->TG_LO*divider_val/100000) + *(MXL_Ceiling(Tuner->Fxtal,1000000) * 100) / (Tuner->Fxtal/1000) ; + status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval) ; + + if (Tuner->TG_LO > 600000000UL) + status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval + 1 ) ; + + Fmax = 1800000000UL ; + Fmin = 1200000000UL ; + + + + // to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4 + Fref_TG = (Tuner->Fxtal/1000)/ MXL_Ceiling(Tuner->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000 + + Fvco = (Tuner->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10 + + tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8; + + //below equation is same as above but much harder to debug. + //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((Tuner->TG_LO/10000)*divider_val*(Tuner->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ; + + + status += MXL_ControlWrite(Tuner, TG_VCO_BIAS , tg_lo) ; + + + + //add for 2.6.5 + //Special setting for QAM + if(Tuner ->Mod_Type == MXL_QAM) + { + if(Tuner->RF_IN < 680000000) + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; + else + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 2) ; + } + + + //remove 20.48MHz setting for 2.6.10 + + // + // Off Chip Tracking Filter Control + // + if (Tuner->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; + + status += MXL_SetGPIO(Tuner, 3, 1) ; // turn off Bank 1 + status += MXL_SetGPIO(Tuner, 1, 1) ; // turn off Bank 2 + status += MXL_SetGPIO(Tuner, 4, 1) ; // turn off Bank 3 + } + + if (Tuner->TF_Type == MXL_TF_C) // Tracking Filter type C + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; + status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000) + { + + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 29) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 16) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 7) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only + { + status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000) + { + + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_D) // Tracking Filter type D + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + + + if (Tuner->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 + { + status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + + if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) // if UHF and terrestrial => Turn off Tracking Filter + { + // Turn off all the banks + status += MXL_SetGPIO(Tuner, 3, 1) ; + status += MXL_SetGPIO(Tuner, 1, 1) ; + status += MXL_SetGPIO(Tuner, 4, 1) ; + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; + + status += MXL_ControlWrite(Tuner, AGC_IF, 10) ; + } + + else // if VHF or cable => Turn on Tracking Filter + { + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 140000000) + { + + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + } + if (Tuner->RF_IN >= 140000000 && Tuner->RF_IN < 240000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + } + if (Tuner->RF_IN >= 240000000 && Tuner->RF_IN < 340000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + } + if (Tuner->RF_IN >= 340000000 && Tuner->RF_IN < 430000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + } + if (Tuner->RF_IN >= 430000000 && Tuner->RF_IN < 470000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + } + if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 570000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + } + if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 620000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Offq + } + if (Tuner->RF_IN >= 620000000 && Tuner->RF_IN < 760000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + } + + if (Tuner->TF_Type == MXL_TF_E) // Tracking Filter type E + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_F) // Tracking Filter type F + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 160000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 160000000 && Tuner->RF_IN < 210000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 210000000 && Tuner->RF_IN < 300000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 300000000 && Tuner->RF_IN < 390000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 390000000 && Tuner->RF_IN < 515000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 515000000 && Tuner->RF_IN < 650000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 650000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 50000000 && Tuner->RF_IN < 190000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 190000000 && Tuner->RF_IN < 280000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 350000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 470000000) //modified for 2.6.11 + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN < 820000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 820000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) //if UHF and terrestrial=> Turn off Tracking Filter + { + // Turn off all the banks + status += MXL_SetGPIO(Tuner, 3, 1) ; + status += MXL_SetGPIO(Tuner, 1, 1) ; + status += MXL_SetGPIO(Tuner, 4, 1) ; + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; + + //2.6.12 + //Turn on RSSI + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; + + + //status += MXL_ControlWrite(Tuner, AGC_IF, 10) ; //doesn't matter since RSSI is turn on + + //following parameter is from analog OTA mode, can be change to seek better performance + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; + } + + else //if VHF or Cable => Turn on Tracking Filter + { + //2.6.12 + //Turn off RSSI + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; + + //change back from above condition + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ; + + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + } + return status ; +} + +_u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val) +{ + _u16 status = 0 ; + + if (GPIO_Num == 1) + status += MXL_ControlWrite(Tuner, GPIO_1B, GPIO_Val ? 0 : 1) ; + // GPIO2 is not available + if (GPIO_Num == 3) + { + if (GPIO_Val == 1) { + status += MXL_ControlWrite(Tuner, GPIO_3, 0) ; + status += MXL_ControlWrite(Tuner, GPIO_3B, 0) ; + } + if (GPIO_Val == 0) { + status += MXL_ControlWrite(Tuner, GPIO_3, 1) ; + status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ; + } + if (GPIO_Val == 3) { // tri-state + status += MXL_ControlWrite(Tuner, GPIO_3, 0) ; + status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ; + } + } + if (GPIO_Num == 4) + { + if (GPIO_Val == 1) { + status += MXL_ControlWrite(Tuner, GPIO_4, 0) ; + status += MXL_ControlWrite(Tuner, GPIO_4B, 0) ; + } + if (GPIO_Val == 0) { + status += MXL_ControlWrite(Tuner, GPIO_4, 1) ; + status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ; + } + if (GPIO_Val == 3) { // tri-state + status += MXL_ControlWrite(Tuner, GPIO_4, 0) ; + status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ; + } + } + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_ControlWrite // +// // +// Description: Update control name value // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// MXL_ControlWrite( Tuner, controlName, value, Group ) // +// // +// Inputs: // +// Tuner : Tuner structure // +// ControlName : Control name to be updated // +// value : Value to be written // +// // +// Outputs: // +// Tuner : Tuner structure defined at higher level // +// // +// Return: // +// 0 : Successful write // +// >0 : Value exceed maximum allowed for control number // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value) +{ + _u16 status = 0 ; + // Will write ALL Matching Control Name + status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 1 ) ; // Write Matching INIT Control + status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 2 ) ; // Write Matching CH Control +#ifdef _MXL_INTERNAL + status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 3 ) ; // Write Matching MXL Control +#endif + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_ControlWrite // +// // +// Description: Update control name value // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// strcmp // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// ControlName : Control Name // +// value : Value Assigned to Control Name // +// controlGroup : Control Register Group // +// // +// Outputs: // +// NONE // +// // +// Return: // +// 0 : Successful write // +// 1 : Value exceed maximum allowed for control name // +// 2 : Control name not found // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u16 controlGroup) +{ + _u16 i, j, k ; + _u32 highLimit ; + _u32 ctrlVal ; + + if( controlGroup == 1) // Initial Control + { + for (i=0; iInit_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) + { // find the control Name + highLimit = 1 << Tuner->Init_Ctrl[i].size ; + if ( value < highLimit) + { + for( j=0; jInit_Ctrl[i].size; j++) + { + Tuner->Init_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + // change the register map accordingly + MXL_RegWriteBit( Tuner, (_u8)(Tuner->Init_Ctrl[i].addr[j]), + (_u8)(Tuner->Init_Ctrl[i].bit[j]), + (_u8)((value>>j) & 0x01) ) ; + } + ctrlVal = 0 ; + for(k=0; kInit_Ctrl[i].size; k++) + { + ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ; + } + } + else + { + return -1 ; + } + } + } + } + if ( controlGroup == 2) // Chan change Control + { + for (i=0; iCH_Ctrl_Num; i++) + { + if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) + { // find the control Name + highLimit = 1 << Tuner->CH_Ctrl[i].size ; + if ( value < highLimit) + { + for( j=0; jCH_Ctrl[i].size; j++) + { + Tuner->CH_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + // change the register map accordingly + MXL_RegWriteBit( Tuner, (_u8)(Tuner->CH_Ctrl[i].addr[j]), + (_u8)(Tuner->CH_Ctrl[i].bit[j]), + (_u8)((value>>j) & 0x01) ) ; + } + ctrlVal = 0 ; + for(k=0; kCH_Ctrl[i].size; k++) + { + ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ; + } + } + else + { + return -1 ; + } + } + } + } +#ifdef _MXL_INTERNAL + if ( controlGroup == 3) // Maxlinear Control + { + for (i=0; iMXL_Ctrl_Num; i++) + { + if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) + { // find the control Name + highLimit = (1 << Tuner->MXL_Ctrl[i].size) ; + if ( value < highLimit) + { + for( j=0; jMXL_Ctrl[i].size; j++) + { + Tuner->MXL_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + // change the register map accordingly + MXL_RegWriteBit( Tuner, (_u8)(Tuner->MXL_Ctrl[i].addr[j]), + (_u8)(Tuner->MXL_Ctrl[i].bit[j]), + (_u8)((value>>j) & 0x01) ) ; + } + ctrlVal = 0 ; + for(k=0; kMXL_Ctrl[i].size; k++) + { + ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1 << k) ; + } + } + else + { + return -1 ; + } + } + } + } +#endif + return 0 ; // successful return +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_RegWrite // +// // +// Description: Update tuner register value // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// RegNum : Register address to be assigned a value // +// RegVal : Register value to write // +// // +// Outputs: // +// NONE // +// // +// Return: // +// 0 : Successful write // +// -1 : Invalid Register Address // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal) +{ + int i ; + + for (i=0; i<104; i++) + { + if (RegNum == Tuner->TunerRegs[i].Reg_Num ) + { + Tuner->TunerRegs[i].Reg_Val = RegVal ; + return 0 ; + } + } + + return 1 ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_RegRead // +// // +// Description: Retrieve tuner register value // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// RegNum : Register address to be assigned a value // +// // +// Outputs: // +// RegVal : Retrieved register value // +// // +// Return: // +// 0 : Successful read // +// -1 : Invalid Register Address // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) +{ + int i ; + + for (i=0; i<104; i++) + { + if (RegNum == Tuner->TunerRegs[i].Reg_Num ) + { + *RegVal = (_u8)(Tuner->TunerRegs[i].Reg_Val) ; + return 0 ; + } + } + + return 1 ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_ControlRead // +// // +// Description: Retrieve the control value based on the control name // +// // +// Globals: // +// NONE // +// // +// Inputs: // +// Tuner_struct : structure defined at higher level // +// ControlName : Control Name // +// // +// Outputs: // +// value : returned control value // +// // +// Return: // +// 0 : Successful read // +// -1 : Invalid control name // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 controlNum, _u32 * value) +{ + _u32 ctrlVal ; + _u16 i, k ; + + for (i=0; iInit_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) + { + ctrlVal = 0 ; + for(k=0; kInit_Ctrl[i].size; k++) + ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ; + *value = ctrlVal ; + return 0 ; + } + } + for (i=0; iCH_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) + { + ctrlVal = 0 ; + for(k=0; kCH_Ctrl[i].size; k++) + ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ; + *value = ctrlVal ; + return 0 ; + } + } + +#ifdef _MXL_INTERNAL + for (i=0; iMXL_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) + { + ctrlVal = 0 ; + for(k=0; kMXL_Ctrl[i].size; k++) + ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1<Init_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) + { + Count = 1 ; + RegNum[0] = (_u8)(Tuner->Init_Ctrl[i].addr[0]) ; + + for(k=1; kInit_Ctrl[i].size; k++) + { + for (j= 0; jInit_Ctrl[i].addr[k] != RegNum[j]) + { + Count ++ ; + RegNum[Count-1] = (_u8)(Tuner->Init_Ctrl[i].addr[k]) ; + } + } + + } + *count = Count ; + return 0 ; + } + } + for (i=0; iCH_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) + { + Count = 1 ; + RegNum[0] = (_u8)(Tuner->CH_Ctrl[i].addr[0]) ; + + for(k=1; kCH_Ctrl[i].size; k++) + { + for (j= 0; jCH_Ctrl[i].addr[k] != RegNum[j]) + { + Count ++ ; + RegNum[Count-1] = (_u8)(Tuner->CH_Ctrl[i].addr[k]) ; + } + } + } + *count = Count ; + return 0 ; + } + } +#ifdef _MXL_INTERNAL + for (i=0; iMXL_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) + { + Count = 1 ; + RegNum[0] = (_u8)(Tuner->MXL_Ctrl[i].addr[0]) ; + + for(k=1; kMXL_Ctrl[i].size; k++) + { + for (j= 0; jMXL_Ctrl[i].addr[k] != RegNum[j]) + { + Count ++ ; + RegNum[Count-1] = (_u8)Tuner->MXL_Ctrl[i].addr[k] ; + } + } + } + *count = Count ; + return 0 ; + } + } +#endif + *count = 0 ; + return 1 ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_RegWriteBit // +// // +// Description: Write a register for specified register address, // +// register bit and register bit value // +// // +// Globals: // +// NONE // +// // +// Inputs: // +// Tuner_struct : structure defined at higher level // +// address : register address // +// bit : register bit number // +// bitVal : register bit value // +// // +// Outputs: // +// NONE // +// // +// Return: // +// NONE // +// // +/////////////////////////////////////////////////////////////////////////////// + +void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal) +{ + int i ; + + // Declare Local Constants + const _u8 AND_MAP[8] = { + 0xFE, 0xFD, 0xFB, 0xF7, + 0xEF, 0xDF, 0xBF, 0x7F } ; + + const _u8 OR_MAP[8] = { + 0x01, 0x02, 0x04, 0x08, + 0x10, 0x20, 0x40, 0x80 } ; + + for(i=0; iTunerRegs_Num; i++) { + if ( Tuner->TunerRegs[i].Reg_Num == address ) { + if (bitVal) + Tuner->TunerRegs[i].Reg_Val |= OR_MAP[bit] ; + else + Tuner->TunerRegs[i].Reg_Val &= AND_MAP[bit] ; + break ; + } + } +} ; + + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_Ceiling // +// // +// Description: Complete to closest increment of resolution // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// value : Input number to compute // +// resolution : Increment step // +// // +// Outputs: // +// NONE // +// // +// Return: // +// Computed value // +// // +/////////////////////////////////////////////////////////////////////////////// +_u32 MXL_Ceiling( _u32 value, _u32 resolution ) +{ + return (value/resolution + (value%resolution > 0 ? 1 : 0)) ; +}; + +// +// Retrieve the Initialzation Registers +// +_u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +{ + _u16 status = 0; + int i ; + + _u8 RegAddr[] = {11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, + 76, 77, 91, 134, 135, 137, 147, + 156, 166, 167, 168, 25 } ; + *count = sizeof(RegAddr) / sizeof(_u8) ; + + status += MXL_BlockInit(Tuner) ; + + for (i=0 ; i< *count; i++) + { + RegNum[i] = RegAddr[i] ; + status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + } + + return status ; +} + +_u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +{ + _u16 status = 0; + int i ; + +//add 77, 166, 167, 168 register for 2.6.12 +#ifdef _MXL_PRODUCTION + _u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, + 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; +#else + _u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, + 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; + //_u8 RegAddr[171]; + //for (i=0; i<=170; i++) + // RegAddr[i] = i; +#endif + + *count = sizeof(RegAddr) / sizeof(_u8) ; + + for (i=0 ; i< *count; i++) + { + RegNum[i] = RegAddr[i] ; + status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + } + + return status ; + +} + +_u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +{ + _u16 status = 0 ; + int i ; + + _u8 RegAddr[] = {43, 136} ; + + *count = sizeof(RegAddr) / sizeof(_u8) ; + + for (i=0; i<*count; i++) + { + RegNum[i] = RegAddr[i] ; + status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + } + return status ; + +} + +_u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +{ + _u16 status = 0 ; + int i ; + + _u8 RegAddr[] = {138} ; + + *count = sizeof(RegAddr) / sizeof(_u8) ; + + for (i=0; i<*count; i++) + { + RegNum[i] = RegAddr[i] ; + status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + } + return status ; + +} + +_u16 MXL_GetMasterControl(_u8 *MasterReg, int state) +{ + if (state == 1) // Load_Start + *MasterReg = 0xF3 ; + if (state == 2) // Power_Down + *MasterReg = 0x41 ; + if (state == 3) // Synth_Reset + *MasterReg = 0xB1 ; + if (state == 4) // Seq_Off + *MasterReg = 0xF1 ; + + return 0 ; +} + +#ifdef _MXL_PRODUCTION +_u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) +{ + _u16 status = 0 ; + + if (VCO_Range == 1) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 180224 ) ; + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 222822 ) ; + } + if (Tuner->Mode == 1) // Digital Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 229376 ) ; + } + } + + if (VCO_Range == 2) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41 ) ; + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; + } + if (Tuner->Mode == 1) // Digital Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 16384 ) ; + } + } + + if (VCO_Range == 3) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670 ) ; + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670 ) ; + } + if (Tuner->Mode == 1) // Digital Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 245760 ) ; + } + } + + if (VCO_Range == 4) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; + } + if (Tuner->Mode == 1) // Digital Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 212992 ) ; + } + } + + return status ; +} + +_u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) +{ + _u16 status = 0 ; + + if (Hystersis == 1) + status += MXL_ControlWrite(Tuner, DN_BYPASS_AGC_I2C, 1) ; + + return status ; +} +#endif + + + + + + + + + + + + + + + -- cgit v1.2.3 From 2637d5b498b979b46a01690d22ecca1e5b79b903 Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 05:01:31 -0300 Subject: V4L/DVB (7864): mxl5005s: Cleanup #1 Cleanup #1 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'drivers/media/common/tuners/mxl5005s.c') diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index a32475fa1472..3c4330614faf 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -35,13 +35,7 @@ MxL5005S module is derived from tuner module. */ -#include "tuner_mxl5005s.h" -#include "tuner_demod_io.h" - - - - - +#include "mxl5005s.h" /** -- cgit v1.2.3 From a8214d48e6d41f3a16c1023ca4f30bbd140ba756 Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 05:02:58 -0300 Subject: V4L/DVB (7865): mxl5005s: Cleanup #2 Cleanup #2 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 907 ++++++++++----------------------- 1 file changed, 271 insertions(+), 636 deletions(-) (limited to 'drivers/media/common/tuners/mxl5005s.c') diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 3c4330614faf..2af14de737e9 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -22,71 +22,10 @@ * Revision: 080314 - original version */ - -/** - -@file - -@brief MxL5005S tuner module definition - -One can manipulate MxL5005S tuner through MxL5005S module. -MxL5005S module is derived from tuner module. - -*/ - - #include "mxl5005s.h" -/** - -@defgroup MXL5005S_TUNER_MODULE MxL5005S tuner module - -MxL5005S tuner module is drived from tuner base module. - -@see TUNER_BASE_MODULE - -*/ - - - - - -/** -@defgroup MXL5005S_MODULE_BUILDER MxL5005S module builder -@ingroup MXL5005S_TUNER_MODULE - -One should call MxL5005S module builder before using MxL5005S module. - -*/ -/// @{ - - - - - -/** - -@brief MxL5005S tuner module builder - -Use BuildMxl5005sModule() to build MxL5005S module, set all module function pointers with the corresponding functions, -and initialize module private variables. - - -@param [in] ppTuner Pointer to MxL5005S tuner module pointer -@param [in] pTunerModuleMemory Pointer to an allocated tuner module memory -@param [in] pMxl5005sExtraModuleMemory Pointer to an allocated MxL5005S extra module memory -@param [in] pI2cBridgeModuleMemory Pointer to an allocated I2C bridge module memory -@param [in] DeviceAddr MxL5005S I2C device address -@param [in] CrystalFreqHz MxL5005S crystal frequency in Hz - - -@note \n - -# One should call BuildMxl5005sModule() to build MxL5005S module before using it. - -*/ -void -BuildMxl5005sModule( +void BuildMxl5005sModule( TUNER_MODULE **ppTuner, TUNER_MODULE *pTunerModuleMemory, MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory, @@ -200,43 +139,7 @@ BuildMxl5005sModule( return; } - - - - -/// @} - - - - - -/** - -@defgroup MXL5005S_MANIPULATING_FUNCTIONS MxL5005S manipulating functions derived from tuner base module -@ingroup MXL5005S_TUNER_MODULE - -One can use the MxL5005S tuner module manipulating interface implemented by MxL5005S manipulating functions to -manipulate MxL5005S tuner. - -*/ -/// @{ - - - - - -/** - -@brief Set MxL5005S tuner I2C device address. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_SET_DEVICE_ADDR() function pointer with mxl5005s_SetDeviceAddr(). - -@see TUNER_FP_SET_DEVICE_ADDR - -*/ -void -mxl5005s_SetDeviceAddr( +void mxl5005s_SetDeviceAddr( TUNER_MODULE *pTuner, unsigned char DeviceAddr ) @@ -249,22 +152,7 @@ mxl5005s_SetDeviceAddr( return; } - - - - -/** - -@brief Get MxL5005S tuner type. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_GET_TUNER_TYPE() function pointer with mxl5005s_GetTunerType(). - -@see TUNER_FP_GET_TUNER_TYPE - -*/ -void -mxl5005s_GetTunerType( +void mxl5005s_GetTunerType( TUNER_MODULE *pTuner, int *pTunerType ) @@ -276,22 +164,7 @@ mxl5005s_GetTunerType( return; } - - - - -/** - -@brief Get MxL5005S tuner I2C device address. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_GET_DEVICE_ADDR() function pointer with mxl5005s_GetDeviceAddr(). - -@see TUNER_FP_GET_DEVICE_ADDR - -*/ -int -mxl5005s_GetDeviceAddr( +int mxl5005s_GetDeviceAddr( TUNER_MODULE *pTuner, unsigned char *pDeviceAddr ) @@ -310,22 +183,7 @@ error_status_get_tuner_i2c_device_addr: return FUNCTION_ERROR; } - - - - -/** - -@brief Initialize MxL5005S tuner. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_INITIALIZE() function pointer with mxl5005s_Initialize(). - -@see TUNER_FP_INITIALIZE - -*/ -int -mxl5005s_Initialize( +int mxl5005s_Initialize( struct dvb_usb_device* dib, TUNER_MODULE *pTuner ) @@ -337,16 +195,12 @@ mxl5005s_Initialize( unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - - // Get tuner extra module. pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - // Get AGC master byte AgcMasterByte = pExtra->AgcMasterByte; - // Initialize MxL5005S tuner according to MxL5005S tuner example code. // Tuner initialization stage 0 @@ -357,37 +211,19 @@ mxl5005s_Initialize( if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS) goto error_status_set_tuner_registers; - // Tuner initialization stage 1 MXL_GetInitRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen); if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) goto error_status_set_tuner_registers; - return FUNCTION_SUCCESS; - error_status_set_tuner_registers: return FUNCTION_ERROR; } - - - - -/** - -@brief Set MxL5005S tuner RF frequency in Hz. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_SET_RF_FREQ_HZ() function pointer with mxl5005s_SetRfFreqHz(). - -@see TUNER_FP_SET_RF_FREQ_HZ - -*/ -int -mxl5005s_SetRfFreqHz( +int mxl5005s_SetRfFreqHz( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned long RfFreqHz @@ -404,8 +240,6 @@ mxl5005s_SetRfFreqHz( unsigned long IfDivval; unsigned char MasterControlByte; - - // Get tuner extra module and base interface module. pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; pBaseInterface = pTuner->pBaseInterface; @@ -476,22 +310,7 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } - - - - -/** - -@brief Get MxL5005S tuner RF frequency in Hz. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_GET_RF_FREQ_HZ() function pointer with mxl5005s_GetRfFreqHz(). - -@see TUNER_FP_GET_RF_FREQ_HZ - -*/ -int -mxl5005s_GetRfFreqHz( +int mxl5005s_GetRfFreqHz( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned long *pRfFreqHz @@ -511,18 +330,7 @@ error_status_get_tuner_rf_frequency: return FUNCTION_ERROR; } - - - - -/** - -@brief Set MxL5005S tuner registers with table. - -*/ -/* -int -mxl5005s_SetRegsWithTable( +int mxl5005s_SetRegsWithTable( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned char *pAddrTable, @@ -585,11 +393,8 @@ mxl5005s_SetRegsWithTable( error_status_set_tuner_registers: return FUNCTION_ERROR; } -*/ - -int -mxl5005s_SetRegsWithTable( +int mxl5005s_SetRegsWithTable( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned char *pAddrTable, @@ -618,17 +423,7 @@ mxl5005s_SetRegsWithTable( return FUNCTION_SUCCESS; } - - - - -/** - -@brief Set MxL5005S tuner register bits. - -*/ -int -mxl5005s_SetRegMaskBits( +int mxl5005s_SetRegMaskBits( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned char RegAddr, @@ -685,17 +480,7 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } - - - - -/** - -@brief Set MxL5005S tuner spectrum mode. - -*/ -int -mxl5005s_SetSpectrumMode( +int mxl5005s_SetSpectrumMode( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, int SpectrumMode @@ -730,17 +515,7 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } - - - - -/** - -@brief Set MxL5005S tuner bandwidth in Hz. - -*/ -int -mxl5005s_SetBandwidthHz( +int mxl5005s_SetBandwidthHz( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned long BandwidthHz @@ -777,48 +552,7 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } - - - - -/// @} - - - - - -/** - -@defgroup MXL5005S_DEPENDENCE MxL5005S dependence -@ingroup MXL5005S_TUNER_MODULE - -MxL5005S dependence is the related functions for MxL5005S tuner module interface. -One should not use MxL5005S dependence directly. - -*/ -/// @{ - - - - - -/** - -@brief Set I2C bridge module tuner arguments. - -MxL5005S builder will use mxl5005s_SetI2cBridgeModuleTunerArg() to set I2C bridge module tuner arguments. - - -@param [in] pTuner The tuner module pointer - - -@see BuildMxl5005sModule() - -*/ -void -mxl5005s_SetI2cBridgeModuleTunerArg( - TUNER_MODULE *pTuner - ) +void mxl5005s_SetI2cBridgeModuleTunerArg(TUNER_MODULE *pTuner) { I2C_BRIDGE_MODULE *pI2cBridge; @@ -833,51 +567,10 @@ mxl5005s_SetI2cBridgeModuleTunerArg( return; } - - - - - -/// @} - - - - - - - - - - - - - - - - - - - - - - // The following context is source code provided by MaxLinear. - - - - - // MaxLinear source code - MXL5005_Initialize.cpp - - - -//#ifdef _MXL_HEADER -//#include "stdafx.h" -//#endif -//#include "MXL5005_c.h" - -_u16 MXL5005_RegisterInit (Tuner_struct * Tuner) +u16 MXL5005_RegisterInit(Tuner_struct *Tuner) { Tuner->TunerRegs_Num = TUNER_REGS_NUM ; // Tuner->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; @@ -1197,7 +890,7 @@ _u16 MXL5005_RegisterInit (Tuner_struct * Tuner) return 0 ; } -_u16 MXL5005_ControlInit (Tuner_struct *Tuner) +u16 MXL5005_ControlInit(Tuner_struct *Tuner) { Tuner->Init_Ctrl_Num = INITCTRL_NUM ; @@ -2136,34 +1829,10 @@ _u16 MXL5005_ControlInit (Tuner_struct *Tuner) return 0 ; } - - - - - - - - - - - - - - // MaxLinear source code - MXL5005_c.cpp - - - // MXL5005.cpp : Defines the initialization routines for the DLL. // 2.6.12 - -//#ifdef _MXL_HEADER -//#include "stdafx.h" -//#endif -//#include "MXL5005_c.h" - - void InitTunerControls(Tuner_struct *Tuner) { MXL5005_RegisterInit(Tuner) ; @@ -2173,8 +1842,6 @@ void InitTunerControls(Tuner_struct *Tuner) #endif } - - /////////////////////////////////////////////////////////////////////////////// // // // Function: MXL_ConfigTuner // @@ -2184,7 +1851,7 @@ void InitTunerControls(Tuner_struct *Tuner) // // // // // Functions used: // -// MXL_SynthIFLO_Calc // +// MXL_SynthIFLO_Calc // // // // Inputs: // // Tuner_struct: structure defined at higher level // @@ -2193,12 +1860,12 @@ void InitTunerControls(Tuner_struct *Tuner) // Bandwidth: Filter Channel Bandwidth (in Hz) // // IF_out: Desired IF out Frequency (in Hz) // // Fxtal: Crystal Frerquency (in Hz) // -// TOP: 0: Dual AGC; Value: take over point // -// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // -// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // -// DIV_OUT: 0: Div-1; 1: Div-4 // -// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // -// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // +// TOP: 0: Dual AGC; Value: take over point // +// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // +// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // +// DIV_OUT: 0: Div-1; 1: Div-4 // +// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // +// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // // // // Outputs: // // Tuner // @@ -2208,26 +1875,26 @@ void InitTunerControls(Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL5005_TunerConfig(Tuner_struct *Tuner, - _u8 Mode, // 0: Analog Mode ; 1: Digital Mode - _u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF - _u32 Bandwidth, // filter channel bandwidth (6, 7, 8) - _u32 IF_out, // Desired IF Out Frequency - _u32 Fxtal, // XTAL Frequency - _u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 - _u16 TOP, // 0: Dual AGC; Value: take over point - _u16 IF_OUT_LOAD, // IF Out Load Resistor (200 / 300 Ohms) - _u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out - _u8 DIV_OUT, // 0: Div-1; 1: Div-4 - _u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable - _u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI - _u8 Mod_Type, // Modulation Type; - // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable - _u8 TF_Type // Tracking Filter - // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H +u16 MXL5005_TunerConfig(Tuner_struct *Tuner, + u8 Mode, // 0: Analog Mode ; 1: Digital Mode + u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF + u32 Bandwidth, // filter channel bandwidth (6, 7, 8) + u32 IF_out, // Desired IF Out Frequency + u32 Fxtal, // XTAL Frequency + u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 + u16 TOP, // 0: Dual AGC; Value: take over point + u16 IF_OUT_LOAD, // IF Out Load Resistor (200 / 300 Ohms) + u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out + u8 DIV_OUT, // 0: Div-1; 1: Div-4 + u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable + u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI + u8 Mod_Type, // Modulation Type; + // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable + u8 TF_Type // Tracking Filter + // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H ) { - _u16 status = 0 ; + u16 status = 0 ; Tuner->Mode = Mode ; Tuner->IF_Mode = IF_mode ; @@ -2244,15 +1911,10 @@ _u16 MXL5005_TunerConfig(Tuner_struct *Tuner, Tuner->Mod_Type = Mod_Type ; Tuner->TF_Type = TF_Type ; - - - // - // Initialize all the controls and registers - // + /* Initialize all the controls and registers */ InitTunerControls (Tuner) ; - // - // Synthesizer LO frequency calculation - // + + /* Synthesizer LO frequency calculation */ MXL_SynthIFLO_Calc( Tuner ) ; return status ; @@ -2366,9 +2028,9 @@ void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) +u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) { - _u16 status = 0 ; + u16 status = 0 ; status += MXL_ControlWrite(Tuner, OVERRIDE_1, 1) ; status += MXL_ControlWrite(Tuner, OVERRIDE_2, 1) ; @@ -2403,20 +2065,20 @@ _u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_BlockInit( Tuner_struct *Tuner ) +u16 MXL_BlockInit( Tuner_struct *Tuner ) { - _u16 status = 0 ; + u16 status = 0 ; status += MXL_OverwriteICDefault(Tuner) ; // // Downconverter Control - // Dig Ana + // Dig Ana status += MXL_ControlWrite(Tuner, DN_IQTN_AMP_CUT, Tuner->Mode ? 1 : 0) ; // // Filter Control - // Dig Ana + // Dig Ana status += MXL_ControlWrite(Tuner, BB_MODE, Tuner->Mode ? 0 : 1) ; status += MXL_ControlWrite(Tuner, BB_BUF, Tuner->Mode ? 3 : 2) ; status += MXL_ControlWrite(Tuner, BB_BUF_OA, Tuner->Mode ? 1 : 0) ; @@ -2439,7 +2101,7 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner ) } } else { // Analog Mode switch (Tuner->Chan_Bandwidth) { - case 8000000: // Low Zero + case 8000000: // Low Zero status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 0 : 3)) ; break ; case 7000000: @@ -2453,7 +2115,7 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner ) // // Charge Pump Control - // Dig Ana + // Dig Ana status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, Tuner->Mode ? 5 : 8) ; status += MXL_ControlWrite(Tuner, RFSYN_EN_CHP_HIGAIN, Tuner->Mode ? 1 : 1) ; status += MXL_ControlWrite(Tuner, EN_CHP_LIN_B, Tuner->Mode ? 0 : 0) ; @@ -2621,8 +2283,6 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner ) // Apply Default value to BB_INITSTATE_DLPF_TUNE // - - // // RSSI Control // @@ -2697,7 +2357,7 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner ) //Tuner->AGC_Mode = 1 ; // Single AGC Mode - // Disable RSSI //change here for v2.6.5 + // Disable RSSI //change here for v2.6.5 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; @@ -2787,13 +2447,13 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner ) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_IFSynthInit( Tuner_struct * Tuner ) +u16 MXL_IFSynthInit(Tuner_struct * Tuner) { - _u16 status = 0 ; + u16 status = 0 ; // Declare Local Variables - _u32 Fref = 0 ; - _u32 Kdbl, intModVal ; - _u32 fracModVal ; + u32 Fref = 0 ; + u32 Kdbl, intModVal ; + u32 fracModVal ; Kdbl = 2 ; if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) @@ -2999,8 +2659,6 @@ _u16 MXL_IFSynthInit( Tuner_struct * Tuner ) fracModVal = fracModVal / ((Tuner->Fxtal * Kdbl/2)/1000) ; status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_IF, fracModVal) ; - - return status ; } @@ -3008,14 +2666,14 @@ _u16 MXL_IFSynthInit( Tuner_struct * Tuner ) // // // Function: MXL_GetXtalInt // // // -// Description: return the Crystal Integration Value for // -// TG_VCO_BIAS calculation // +// Description: return the Crystal Integration Value for // +// TG_VCO_BIAS calculation // // // // Globals: // // NONE // // // // Functions used: // -// NONE // +// NONE // // // // Inputs: // // Crystal Frequency Value in Hz // @@ -3028,7 +2686,7 @@ _u16 MXL_IFSynthInit( Tuner_struct * Tuner ) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -_u32 MXL_GetXtalInt(_u32 Xtal_Freq) +u32 MXL_GetXtalInt(u32 Xtal_Freq) { if ((Xtal_Freq % 1000000) == 0) return (Xtal_Freq / 10000) ; @@ -3048,7 +2706,7 @@ _u32 MXL_GetXtalInt(_u32 Xtal_Freq) // Functions used: // // MXL_SynthRFTGLO_Calc // // MXL5005_ControlWrite // -// MXL_GetXtalInt // +// MXL_GetXtalInt // // // // Inputs: // // Tuner : Tuner structure defined at higher level // @@ -3060,20 +2718,20 @@ _u32 MXL_GetXtalInt(_u32 Xtal_Freq) // 0 : Successful // // 1 : Unsuccessful // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) +u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) { // Declare Local Variables - _u16 status = 0 ; - _u32 divider_val, E3, E4, E5, E5A ; - _u32 Fmax, Fmin, FmaxBin, FminBin ; - _u32 Kdbl_RF = 2; - _u32 tg_divval ; - _u32 tg_lo ; - _u32 Xtal_Int ; + u16 status = 0 ; + u32 divider_val, E3, E4, E5, E5A ; + u32 Fmax, Fmin, FmaxBin, FminBin ; + u32 Kdbl_RF = 2; + u32 tg_divval ; + u32 tg_lo ; + u32 Xtal_Int ; - _u32 Fref_TG; - _u32 Fvco; -// _u32 temp; + u32 Fref_TG; + u32 Fvco; +// u32 temp; Xtal_Int = MXL_GetXtalInt(Tuner->Fxtal ) ; @@ -3774,7 +3432,8 @@ _u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) { status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; - if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) // if UHF and terrestrial => Turn off Tracking Filter + // if UHF and terrestrial => Turn off Tracking Filter + if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) { // Turn off all the banks status += MXL_SetGPIO(Tuner, 3, 1) ; @@ -4089,7 +3748,8 @@ _u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) { status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) //if UHF and terrestrial=> Turn off Tracking Filter + // if UHF and terrestrial=> Turn off Tracking Filter + if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) { // Turn off all the banks status += MXL_SetGPIO(Tuner, 3, 1) ; @@ -4181,9 +3841,9 @@ _u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) return status ; } -_u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val) +u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val) { - _u16 status = 0 ; + u16 status = 0 ; if (GPIO_Num == 1) status += MXL_ControlWrite(Tuner, GPIO_1B, GPIO_Val ? 0 : 1) ; @@ -4247,9 +3907,9 @@ _u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val) // >0 : Value exceed maximum allowed for control number // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value) +u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value) { - _u16 status = 0 ; + u16 status = 0 ; // Will write ALL Matching Control Name status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 1 ) ; // Write Matching INIT Control status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 2 ) ; // Write Matching CH Control @@ -4287,11 +3947,11 @@ _u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value) // 2 : Control name not found // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u16 controlGroup) +u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 controlNum, u32 value, u16 controlGroup) { - _u16 i, j, k ; - _u32 highLimit ; - _u32 ctrlVal ; + u16 i, j, k ; + u32 highLimit ; + u32 ctrlVal ; if( controlGroup == 1) // Initial Control { @@ -4304,11 +3964,11 @@ _u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u { for( j=0; jInit_Ctrl[i].size; j++) { - Tuner->Init_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + Tuner->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; // change the register map accordingly - MXL_RegWriteBit( Tuner, (_u8)(Tuner->Init_Ctrl[i].addr[j]), - (_u8)(Tuner->Init_Ctrl[i].bit[j]), - (_u8)((value>>j) & 0x01) ) ; + MXL_RegWriteBit( Tuner, (u8)(Tuner->Init_Ctrl[i].addr[j]), + (u8)(Tuner->Init_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ) ; } ctrlVal = 0 ; for(k=0; kInit_Ctrl[i].size; k++) @@ -4334,11 +3994,11 @@ _u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u { for( j=0; jCH_Ctrl[i].size; j++) { - Tuner->CH_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + Tuner->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; // change the register map accordingly - MXL_RegWriteBit( Tuner, (_u8)(Tuner->CH_Ctrl[i].addr[j]), - (_u8)(Tuner->CH_Ctrl[i].bit[j]), - (_u8)((value>>j) & 0x01) ) ; + MXL_RegWriteBit( Tuner, (u8)(Tuner->CH_Ctrl[i].addr[j]), + (u8)(Tuner->CH_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ) ; } ctrlVal = 0 ; for(k=0; kCH_Ctrl[i].size; k++) @@ -4365,11 +4025,11 @@ _u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u { for( j=0; jMXL_Ctrl[i].size; j++) { - Tuner->MXL_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + Tuner->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; // change the register map accordingly - MXL_RegWriteBit( Tuner, (_u8)(Tuner->MXL_Ctrl[i].addr[j]), - (_u8)(Tuner->MXL_Ctrl[i].bit[j]), - (_u8)((value>>j) & 0x01) ) ; + MXL_RegWriteBit( Tuner, (u8)(Tuner->MXL_Ctrl[i].addr[j]), + (u8)(Tuner->MXL_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ) ; } ctrlVal = 0 ; for(k=0; kMXL_Ctrl[i].size; k++) @@ -4413,7 +4073,7 @@ _u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal) +u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal) { int i ; @@ -4453,7 +4113,7 @@ _u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal) // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) +u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal) { int i ; @@ -4461,7 +4121,7 @@ _u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) { if (RegNum == Tuner->TunerRegs[i].Reg_Num ) { - *RegVal = (_u8)(Tuner->TunerRegs[i].Reg_Val) ; + *RegVal = (u8)(Tuner->TunerRegs[i].Reg_Val) ; return 0 ; } } @@ -4490,10 +4150,10 @@ _u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 controlNum, _u32 * value) +u16 MXL_ControlRead(Tuner_struct *Tuner, u16 controlNum, u32 * value) { - _u32 ctrlVal ; - _u16 i, k ; + u32 ctrlVal ; + u16 i, k ; for (i=0; iInit_Ctrl_Num ; i++) { @@ -4539,7 +4199,7 @@ _u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 controlNum, _u32 * value) // Function: MXL_ControlRegRead // // // // Description: Retrieve the register addresses and count related to a // -// a specific control name // +// a specific control name // // // // Globals: // // NONE // @@ -4550,24 +4210,24 @@ _u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 controlNum, _u32 * value) // // // Outputs: // // RegNum : returned register address array // -// count : returned register count related to a control // +// count : returned register count related to a control // // // // Return: // // 0 : Successful read // // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * count) +u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 controlNum, u8 *RegNum, int * count) { - _u16 i, j, k ; - _u16 Count ; + u16 i, j, k ; + u16 Count ; for (i=0; iInit_Ctrl_Num ; i++) { if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) { Count = 1 ; - RegNum[0] = (_u8)(Tuner->Init_Ctrl[i].addr[0]) ; + RegNum[0] = (u8)(Tuner->Init_Ctrl[i].addr[0]) ; for(k=1; kInit_Ctrl[i].size; k++) { @@ -4576,7 +4236,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * if (Tuner->Init_Ctrl[i].addr[k] != RegNum[j]) { Count ++ ; - RegNum[Count-1] = (_u8)(Tuner->Init_Ctrl[i].addr[k]) ; + RegNum[Count-1] = (u8)(Tuner->Init_Ctrl[i].addr[k]) ; } } @@ -4590,7 +4250,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) { Count = 1 ; - RegNum[0] = (_u8)(Tuner->CH_Ctrl[i].addr[0]) ; + RegNum[0] = (u8)(Tuner->CH_Ctrl[i].addr[0]) ; for(k=1; kCH_Ctrl[i].size; k++) { @@ -4599,7 +4259,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * if (Tuner->CH_Ctrl[i].addr[k] != RegNum[j]) { Count ++ ; - RegNum[Count-1] = (_u8)(Tuner->CH_Ctrl[i].addr[k]) ; + RegNum[Count-1] = (u8)(Tuner->CH_Ctrl[i].addr[k]) ; } } } @@ -4613,7 +4273,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) { Count = 1 ; - RegNum[0] = (_u8)(Tuner->MXL_Ctrl[i].addr[0]) ; + RegNum[0] = (u8)(Tuner->MXL_Ctrl[i].addr[0]) ; for(k=1; kMXL_Ctrl[i].size; k++) { @@ -4622,7 +4282,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * if (Tuner->MXL_Ctrl[i].addr[k] != RegNum[j]) { Count ++ ; - RegNum[Count-1] = (_u8)Tuner->MXL_Ctrl[i].addr[k] ; + RegNum[Count-1] = (u8)Tuner->MXL_Ctrl[i].addr[k] ; } } } @@ -4648,8 +4308,8 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * // Inputs: // // Tuner_struct : structure defined at higher level // // address : register address // -// bit : register bit number // -// bitVal : register bit value // +// bit : register bit number // +// bitVal : register bit value // // // // Outputs: // // NONE // @@ -4659,16 +4319,16 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * // // /////////////////////////////////////////////////////////////////////////////// -void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal) +void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal) { int i ; // Declare Local Constants - const _u8 AND_MAP[8] = { + const u8 AND_MAP[8] = { 0xFE, 0xFD, 0xFB, 0xF7, 0xEF, 0xDF, 0xBF, 0x7F } ; - const _u8 OR_MAP[8] = { + const u8 OR_MAP[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 } ; @@ -4707,7 +4367,7 @@ void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal) // Computed value // // // /////////////////////////////////////////////////////////////////////////////// -_u32 MXL_Ceiling( _u32 value, _u32 resolution ) +u32 MXL_Ceiling( u32 value, u32 resolution ) { return (value/resolution + (value%resolution > 0 ? 1 : 0)) ; }; @@ -4715,15 +4375,15 @@ _u32 MXL_Ceiling( _u32 value, _u32 resolution ) // // Retrieve the Initialzation Registers // -_u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +u16 MXL_GetInitRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) { - _u16 status = 0; + u16 status = 0; int i ; - _u8 RegAddr[] = {11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, + u8 RegAddr[] = {11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, 76, 77, 91, 134, 135, 137, 147, 156, 166, 167, 168, 25 } ; - *count = sizeof(RegAddr) / sizeof(_u8) ; + *count = sizeof(RegAddr) / sizeof(u8) ; status += MXL_BlockInit(Tuner) ; @@ -4736,24 +4396,24 @@ _u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *co return status ; } -_u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) { - _u16 status = 0; + u16 status = 0; int i ; //add 77, 166, 167, 168 register for 2.6.12 #ifdef _MXL_PRODUCTION - _u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, - 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; + u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, + 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; #else - _u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, - 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; - //_u8 RegAddr[171]; + u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, + 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; + //u8 RegAddr[171]; //for (i=0; i<=170; i++) // RegAddr[i] = i; #endif - *count = sizeof(RegAddr) / sizeof(_u8) ; + *count = sizeof(RegAddr) / sizeof(u8) ; for (i=0 ; i< *count; i++) { @@ -4765,14 +4425,14 @@ _u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *coun } -_u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) { - _u16 status = 0 ; + u16 status = 0 ; int i ; - _u8 RegAddr[] = {43, 136} ; + u8 RegAddr[] = {43, 136} ; - *count = sizeof(RegAddr) / sizeof(_u8) ; + *count = sizeof(RegAddr) / sizeof(u8) ; for (i=0; i<*count; i++) { @@ -4783,14 +4443,14 @@ _u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, in } -_u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) { - _u16 status = 0 ; + u16 status = 0 ; int i ; - _u8 RegAddr[] = {138} ; + u8 RegAddr[] = {138} ; - *count = sizeof(RegAddr) / sizeof(_u8) ; + *count = sizeof(RegAddr) / sizeof(u8) ; for (i=0; i<*count; i++) { @@ -4801,7 +4461,7 @@ _u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int } -_u16 MXL_GetMasterControl(_u8 *MasterReg, int state) +u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) // Load_Start *MasterReg = 0xF3 ; @@ -4816,168 +4476,143 @@ _u16 MXL_GetMasterControl(_u8 *MasterReg, int state) } #ifdef _MXL_PRODUCTION -_u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) -{ - _u16 status = 0 ; - - if (VCO_Range == 1) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 180224 ) ; - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 222822 ) ; - } - if (Tuner->Mode == 1) // Digital Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 229376 ) ; - } - } - - if (VCO_Range == 2) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41 ) ; - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; - } - if (Tuner->Mode == 1) // Digital Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 16384 ) ; - } - } - - if (VCO_Range == 3) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670 ) ; - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670 ) ; - } - if (Tuner->Mode == 1) // Digital Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 245760 ) ; - } - } - - if (VCO_Range == 4) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; - } - if (Tuner->Mode == 1) // Digital Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 212992 ) ; - } - } - - return status ; -} - -_u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) +u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) { - _u16 status = 0 ; - - if (Hystersis == 1) - status += MXL_ControlWrite(Tuner, DN_BYPASS_AGC_I2C, 1) ; - - return status ; -} -#endif - - - - - - + u16 status = 0 ; + + if (VCO_Range == 1) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 180224); + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 222822 ) ; + } + if (Tuner->Mode == 1) // Digital Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 229376 ) ; + } + } + if (VCO_Range == 2) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41); + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); + } + if (Tuner->Mode == 1) // Digital Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 16384); + } + } + if (VCO_Range == 3) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670); + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670); + } + if (Tuner->Mode == 1) // Digital Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 245760); + } + } + if (VCO_Range == 4) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); + } + if (Tuner->Mode == 1) // Digital Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 212992); + } + } + return status; +} +u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) +{ + u16 status = 0; + if (Hystersis == 1) + status += MXL_ControlWrite(Tuner, DN_BYPASS_AGC_I2C, 1); + return status; +} +#endif -- cgit v1.2.3 From 3935c25484bc632b12c447e19c4eacbf5de5f7ae Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 05:45:44 -0300 Subject: V4L/DVB (7866): mxl5005s: Cleanup #3 Cleanup #3 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 5527 ++++++++++++++++---------------- 1 file changed, 2677 insertions(+), 2850 deletions(-) (limited to 'drivers/media/common/tuners/mxl5005s.c') diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 2af14de737e9..d8885484cfbd 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -24,164 +24,61 @@ #include "mxl5005s.h" - -void BuildMxl5005sModule( - TUNER_MODULE **ppTuner, - TUNER_MODULE *pTunerModuleMemory, - MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory, - BASE_INTERFACE_MODULE *pBaseInterfaceModuleMemory, - I2C_BRIDGE_MODULE *pI2cBridgeModuleMemory, - unsigned char DeviceAddr, - int StandardMode - ) -{ - MXL5005S_EXTRA_MODULE *pExtra; - - int MxlModMode; - int MxlIfMode; - unsigned long MxlBandwitdh; - unsigned long MxlIfFreqHz; - unsigned long MxlCrystalFreqHz; - int MxlAgcMode; - unsigned short MxlTop; - unsigned short MxlIfOutputLoad; - int MxlClockOut; - int MxlDivOut; - int MxlCapSel; - int MxlRssiOnOff; - unsigned char MxlStandard; - unsigned char MxlTfType; - - - - // Set tuner module pointer, tuner extra module pointer, and I2C bridge module pointer. - *ppTuner = pTunerModuleMemory; - (*ppTuner)->pExtra = pMxl5005sExtraModuleMemory; - (*ppTuner)->pBaseInterface = pBaseInterfaceModuleMemory; - (*ppTuner)->pI2cBridge = pI2cBridgeModuleMemory; - - // Get tuner extra module pointer. - pExtra = (MXL5005S_EXTRA_MODULE *)(*ppTuner)->pExtra; - - - // Set I2C bridge tuner arguments. - mxl5005s_SetI2cBridgeModuleTunerArg(*ppTuner); - - - // Set tuner module manipulating function pointers. - (*ppTuner)->SetDeviceAddr = mxl5005s_SetDeviceAddr; - - (*ppTuner)->GetTunerType = mxl5005s_GetTunerType; - (*ppTuner)->GetDeviceAddr = mxl5005s_GetDeviceAddr; - - (*ppTuner)->Initialize = mxl5005s_Initialize; - (*ppTuner)->SetRfFreqHz = mxl5005s_SetRfFreqHz; - (*ppTuner)->GetRfFreqHz = mxl5005s_GetRfFreqHz; - - - // Set tuner extra module manipulating function pointers. - pExtra->SetRegsWithTable = mxl5005s_SetRegsWithTable; - pExtra->SetRegMaskBits = mxl5005s_SetRegMaskBits; - pExtra->SetSpectrumMode = mxl5005s_SetSpectrumMode; - pExtra->SetBandwidthHz = mxl5005s_SetBandwidthHz; - - - // Initialize tuner parameter setting status. - (*ppTuner)->IsDeviceAddrSet = NO; - (*ppTuner)->IsRfFreqHzSet = NO; - - - // Set MxL5005S parameters. - MxlModMode = MXL_DIGITAL_MODE; - MxlIfMode = MXL_ZERO_IF; - MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; - MxlIfFreqHz = IF_FREQ_4570000HZ; - MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; - MxlAgcMode = MXL_SINGLE_AGC; - MxlTop = MXL5005S_TOP_25P2; - MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; - MxlClockOut = MXL_CLOCK_OUT_DISABLE; - MxlDivOut = MXL_DIV_OUT_4; - MxlCapSel = MXL_CAP_SEL_ENABLE; - MxlRssiOnOff = MXL_RSSI_ENABLE; - MxlTfType = MXL_TF_C_H; - - - // Set MxL5005S parameters according to standard mode - switch(StandardMode) - { - default: - case MXL5005S_STANDARD_DVBT: MxlStandard = MXL_DVBT; break; - case MXL5005S_STANDARD_ATSC: MxlStandard = MXL_ATSC; break; - } - - - // Set MxL5005S extra module. - pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; - - MXL5005_TunerConfig(&pExtra->MxlDefinedTunerStructure, (unsigned char)MxlModMode, (unsigned char)MxlIfMode, - MxlBandwitdh, MxlIfFreqHz, MxlCrystalFreqHz, (unsigned char)MxlAgcMode, MxlTop, MxlIfOutputLoad, - (unsigned char)MxlClockOut, (unsigned char)MxlDivOut, (unsigned char)MxlCapSel, (unsigned char)MxlRssiOnOff, - MxlStandard, MxlTfType); - - - - // Note: Need to set all module arguments before using module functions. - - - // Set tuner type. - (*ppTuner)->TunerType = TUNER_TYPE_MXL5005S; - - // Set tuner I2C device address. - (*ppTuner)->SetDeviceAddr(*ppTuner, DeviceAddr); - - - return; -} - -void mxl5005s_SetDeviceAddr( - TUNER_MODULE *pTuner, - unsigned char DeviceAddr - ) -{ - // Set tuner I2C device address. - pTuner->DeviceAddr = DeviceAddr; - pTuner->IsDeviceAddrSet = YES; - - - return; -} - -void mxl5005s_GetTunerType( - TUNER_MODULE *pTuner, - int *pTunerType - ) -{ - // Get tuner type from tuner module. - *pTunerType = pTuner->TunerType; - - - return; -} - -int mxl5005s_GetDeviceAddr( - TUNER_MODULE *pTuner, - unsigned char *pDeviceAddr - ) +/* MXL5005 Tuner Control Struct */ +typedef struct _TunerControl_struct { + u16 Ctrl_Num; /* Control Number */ + u16 size; /* Number of bits to represent Value */ + u16 addr[25]; /* Array of Tuner Register Address for each bit position */ + u16 bit[25]; /* Array of bit position in Register Address for each bit position */ + u16 val[25]; /* Binary representation of Value */ +} TunerControl_struct; + +/* MXL5005 Tuner Struct */ +struct mxl5005s_state { - // Get tuner I2C device address from tuner module. - if(pTuner->IsDeviceAddrSet != YES) - goto error_status_get_tuner_i2c_device_addr; - - *pDeviceAddr = pTuner->DeviceAddr; - - - return FUNCTION_SUCCESS; + u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ + u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */ + u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */ + u32 IF_OUT; /* Desired IF Out Frequency */ + u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */ + u32 RF_IN; /* RF Input Frequency */ + u32 Fxtal; /* XTAL Frequency */ + u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */ + u16 TOP; /* Value: take over point */ + u8 CLOCK_OUT; /* 0: turn off clock out; 1: turn on clock out */ + u8 DIV_OUT; /* 4MHz or 16MHz */ + u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */ + u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */ + u8 Mod_Type; /* Modulation Type; */ + /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ + u8 TF_Type; /* Tracking Filter Type */ + /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ + + /* Calculated Settings */ + u32 RF_LO; /* Synth RF LO Frequency */ + u32 IF_LO; /* Synth IF LO Frequency */ + u32 TG_LO; /* Synth TG_LO Frequency */ + + /* Pointers to ControlName Arrays */ + u16 Init_Ctrl_Num; /* Number of INIT Control Names */ + TunerControl_struct + Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ + + u16 CH_Ctrl_Num; /* Number of CH Control Names */ + TunerControl_struct + CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ + + u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ + TunerControl_struct + MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ + + /* Pointer to Tuner Register Array */ + u16 TunerRegs_Num; /* Number of Tuner Registers */ + TunerReg_struct + TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ +}; -error_status_get_tuner_i2c_device_addr: - return FUNCTION_ERROR; -} int mxl5005s_Initialize( struct dvb_usb_device* dib, @@ -310,24 +207,19 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } -int mxl5005s_GetRfFreqHz( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned long *pRfFreqHz - ) +// DONE +int mxl5005s_GetRfFreqHz(struct dvb_frontend *fe, unsigned long *pRfFreqHz) { - // Get tuner RF frequency in Hz from tuner module. - if(pTuner->IsRfFreqHzSet != YES) - goto error_status_get_tuner_rf_frequency; - - *pRfFreqHz = pTuner->RfFreqHz; - - - return FUNCTION_SUCCESS; + struct mxl5005s_state *state = fe->demodulator_priv; + int ret = -1; + /* Get tuner RF frequency in Hz from tuner module. */ + if(state->IsRfFreqHzSet == YES) { + *pRfFreqHz = state->RfFreqHz; + ret = 0; + } -error_status_get_tuner_rf_frequency: - return FUNCTION_ERROR; + return -1; } int mxl5005s_SetRegsWithTable( @@ -394,14 +286,13 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } -int mxl5005s_SetRegsWithTable( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, +int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, unsigned char *pAddrTable, unsigned char *pByteTable, int TableLen ) { + struct mxl5005s_state *state = fe->demodulator_priv; int i; u8 end_two_bytes_buf[]={ 0 , 0 }; u8 tuner_addr=0x00; @@ -423,31 +314,21 @@ int mxl5005s_SetRegsWithTable( return FUNCTION_SUCCESS; } -int mxl5005s_SetRegMaskBits( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, +int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, unsigned char RegAddr, unsigned char Msb, unsigned char Lsb, const unsigned char WritingValue ) { - MXL5005S_EXTRA_MODULE *pExtra; - + struct mxl5005s_state *state = fe->demodulator_priv; int i; unsigned char Mask; unsigned char Shift; - unsigned char RegByte; - - - // Get tuner extra module. - pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - - - // Generate mask and shift according to MSB and LSB. + /* Generate mask and shift according to MSB and LSB. */ Mask = 0; for(i = Lsb; i < (unsigned char)(Msb + 1); i++) Mask |= 0x1 << i; @@ -455,20 +336,17 @@ int mxl5005s_SetRegMaskBits( Shift = Lsb; - // Get tuner register byte according to register adddress. + /* Get tuner register byte according to register adddress. */ MXL_RegRead(&pExtra->MxlDefinedTunerStructure, RegAddr, &RegByte); - - // Reserve register byte unmask bit with mask and inlay writing value into it. + /* Reserve register byte unmask bit with mask and inlay writing value into it. */ RegByte &= ~Mask; RegByte |= (WritingValue << Shift) & Mask; - - // Update tuner register byte table. + /* Update tuner register byte table. */ MXL_RegWrite(&pExtra->MxlDefinedTunerStructure, RegAddr, RegByte); - - // Write tuner register byte with writing byte. + /* Write tuner register byte with writing byte. */ if(pExtra->SetRegsWithTable( dib, pTuner, &RegAddr, &RegByte, LEN_1_BYTE) != FUNCTION_SUCCESS) goto error_status_set_tuner_registers; @@ -480,1350 +358,1321 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } -int mxl5005s_SetSpectrumMode( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - int SpectrumMode - ) +// DONE +int mxl5005s_SetSpectrumMode(struct dvb_frontend *fe, int SpectrumMode) { + struct mxl5005s_state *state = fe->demodulator_priv; static const unsigned char BbIqswapTable[SPECTRUM_MODE_NUM] = { - // BB_IQSWAP - 0, // Normal spectrum - 1, // Inverse spectrum + /* BB_IQSWAP */ + 0, /* Normal spectrum */ + 1, /* Inverse spectrum */ }; - - MXL5005S_EXTRA_MODULE *pExtra; - - - - // Get tuner extra module. - pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - - - // Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode. - if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_IQSWAP_ADDR, MXL5005S_BB_IQSWAP_MSB, - MXL5005S_BB_IQSWAP_LSB, BbIqswapTable[SpectrumMode]) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - + /* Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode. */ + mxl5005s_SetRegMaskBits(fe, + MXL5005S_BB_IQSWAP_ADDR, + MXL5005S_BB_IQSWAP_MSB, + MXL5005S_BB_IQSWAP_LSB, + BbIqswapTable[SpectrumMode]); return FUNCTION_SUCCESS; - - -error_status_set_tuner_registers: - return FUNCTION_ERROR; } -int mxl5005s_SetBandwidthHz( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned long BandwidthHz - ) +// DONE +int mxl5005s_SetBandwidthHz(struct dvb_frontend *fe, unsigned long BandwidthHz) { - MXL5005S_EXTRA_MODULE *pExtra; + struct mxl5005s_state *state = fe->demodulator_priv; unsigned char BbDlpfBandsel; - - - // Get tuner extra module. - pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - - - // Set BB_DLPF_BANDSEL according to bandwidth. + /* Set BB_DLPF_BANDSEL according to bandwidth. */ switch(BandwidthHz) { default: - case MXL5005S_BANDWIDTH_6MHZ: BbDlpfBandsel = 3; break; - case MXL5005S_BANDWIDTH_7MHZ: BbDlpfBandsel = 2; break; - case MXL5005S_BANDWIDTH_8MHZ: BbDlpfBandsel = 0; break; + case MXL5005S_BANDWIDTH_6MHZ: + BbDlpfBandsel = 3; + break; + case MXL5005S_BANDWIDTH_7MHZ: + BbDlpfBandsel = 2; + break; + case MXL5005S_BANDWIDTH_8MHZ: + BbDlpfBandsel = 0; + break; } if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_DLPF_BANDSEL_ADDR, MXL5005S_BB_DLPF_BANDSEL_MSB, - MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != FUNCTION_SUCCESS) + MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != 0) goto error_status_set_tuner_registers; - return FUNCTION_SUCCESS; + return 0; error_status_set_tuner_registers: - return FUNCTION_ERROR; -} - -void mxl5005s_SetI2cBridgeModuleTunerArg(TUNER_MODULE *pTuner) -{ - I2C_BRIDGE_MODULE *pI2cBridge; - - - - // Get I2C bridge module. - pI2cBridge = pTuner->pI2cBridge; - - // Set I2C bridge module tuner arguments. - pI2cBridge->pTunerDeviceAddr = &pTuner->DeviceAddr; - - - return; + return -1; } // The following context is source code provided by MaxLinear. // MaxLinear source code - MXL5005_Initialize.cpp -u16 MXL5005_RegisterInit(Tuner_struct *Tuner) +// DONE +u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { - Tuner->TunerRegs_Num = TUNER_REGS_NUM ; -// Tuner->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; + struct mxl5005s_state *state = fe->demodulator_priv; + state->TunerRegs_Num = TUNER_REGS_NUM ; +// state->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; - Tuner->TunerRegs[0].Reg_Num = 9 ; - Tuner->TunerRegs[0].Reg_Val = 0x40 ; + state->TunerRegs[0].Reg_Num = 9 ; + state->TunerRegs[0].Reg_Val = 0x40 ; - Tuner->TunerRegs[1].Reg_Num = 11 ; - Tuner->TunerRegs[1].Reg_Val = 0x19 ; + state->TunerRegs[1].Reg_Num = 11 ; + state->TunerRegs[1].Reg_Val = 0x19 ; - Tuner->TunerRegs[2].Reg_Num = 12 ; - Tuner->TunerRegs[2].Reg_Val = 0x60 ; + state->TunerRegs[2].Reg_Num = 12 ; + state->TunerRegs[2].Reg_Val = 0x60 ; - Tuner->TunerRegs[3].Reg_Num = 13 ; - Tuner->TunerRegs[3].Reg_Val = 0x00 ; + state->TunerRegs[3].Reg_Num = 13 ; + state->TunerRegs[3].Reg_Val = 0x00 ; - Tuner->TunerRegs[4].Reg_Num = 14 ; - Tuner->TunerRegs[4].Reg_Val = 0x00 ; + state->TunerRegs[4].Reg_Num = 14 ; + state->TunerRegs[4].Reg_Val = 0x00 ; - Tuner->TunerRegs[5].Reg_Num = 15 ; - Tuner->TunerRegs[5].Reg_Val = 0xC0 ; + state->TunerRegs[5].Reg_Num = 15 ; + state->TunerRegs[5].Reg_Val = 0xC0 ; - Tuner->TunerRegs[6].Reg_Num = 16 ; - Tuner->TunerRegs[6].Reg_Val = 0x00 ; + state->TunerRegs[6].Reg_Num = 16 ; + state->TunerRegs[6].Reg_Val = 0x00 ; - Tuner->TunerRegs[7].Reg_Num = 17 ; - Tuner->TunerRegs[7].Reg_Val = 0x00 ; + state->TunerRegs[7].Reg_Num = 17 ; + state->TunerRegs[7].Reg_Val = 0x00 ; - Tuner->TunerRegs[8].Reg_Num = 18 ; - Tuner->TunerRegs[8].Reg_Val = 0x00 ; + state->TunerRegs[8].Reg_Num = 18 ; + state->TunerRegs[8].Reg_Val = 0x00 ; - Tuner->TunerRegs[9].Reg_Num = 19 ; - Tuner->TunerRegs[9].Reg_Val = 0x34 ; + state->TunerRegs[9].Reg_Num = 19 ; + state->TunerRegs[9].Reg_Val = 0x34 ; - Tuner->TunerRegs[10].Reg_Num = 21 ; - Tuner->TunerRegs[10].Reg_Val = 0x00 ; + state->TunerRegs[10].Reg_Num = 21 ; + state->TunerRegs[10].Reg_Val = 0x00 ; - Tuner->TunerRegs[11].Reg_Num = 22 ; - Tuner->TunerRegs[11].Reg_Val = 0x6B ; + state->TunerRegs[11].Reg_Num = 22 ; + state->TunerRegs[11].Reg_Val = 0x6B ; - Tuner->TunerRegs[12].Reg_Num = 23 ; - Tuner->TunerRegs[12].Reg_Val = 0x35 ; + state->TunerRegs[12].Reg_Num = 23 ; + state->TunerRegs[12].Reg_Val = 0x35 ; - Tuner->TunerRegs[13].Reg_Num = 24 ; - Tuner->TunerRegs[13].Reg_Val = 0x70 ; + state->TunerRegs[13].Reg_Num = 24 ; + state->TunerRegs[13].Reg_Val = 0x70 ; - Tuner->TunerRegs[14].Reg_Num = 25 ; - Tuner->TunerRegs[14].Reg_Val = 0x3E ; + state->TunerRegs[14].Reg_Num = 25 ; + state->TunerRegs[14].Reg_Val = 0x3E ; - Tuner->TunerRegs[15].Reg_Num = 26 ; - Tuner->TunerRegs[15].Reg_Val = 0x82 ; + state->TunerRegs[15].Reg_Num = 26 ; + state->TunerRegs[15].Reg_Val = 0x82 ; - Tuner->TunerRegs[16].Reg_Num = 31 ; - Tuner->TunerRegs[16].Reg_Val = 0x00 ; + state->TunerRegs[16].Reg_Num = 31 ; + state->TunerRegs[16].Reg_Val = 0x00 ; - Tuner->TunerRegs[17].Reg_Num = 32 ; - Tuner->TunerRegs[17].Reg_Val = 0x40 ; + state->TunerRegs[17].Reg_Num = 32 ; + state->TunerRegs[17].Reg_Val = 0x40 ; - Tuner->TunerRegs[18].Reg_Num = 33 ; - Tuner->TunerRegs[18].Reg_Val = 0x53 ; + state->TunerRegs[18].Reg_Num = 33 ; + state->TunerRegs[18].Reg_Val = 0x53 ; - Tuner->TunerRegs[19].Reg_Num = 34 ; - Tuner->TunerRegs[19].Reg_Val = 0x81 ; + state->TunerRegs[19].Reg_Num = 34 ; + state->TunerRegs[19].Reg_Val = 0x81 ; - Tuner->TunerRegs[20].Reg_Num = 35 ; - Tuner->TunerRegs[20].Reg_Val = 0xC9 ; + state->TunerRegs[20].Reg_Num = 35 ; + state->TunerRegs[20].Reg_Val = 0xC9 ; - Tuner->TunerRegs[21].Reg_Num = 36 ; - Tuner->TunerRegs[21].Reg_Val = 0x01 ; + state->TunerRegs[21].Reg_Num = 36 ; + state->TunerRegs[21].Reg_Val = 0x01 ; - Tuner->TunerRegs[22].Reg_Num = 37 ; - Tuner->TunerRegs[22].Reg_Val = 0x00 ; + state->TunerRegs[22].Reg_Num = 37 ; + state->TunerRegs[22].Reg_Val = 0x00 ; - Tuner->TunerRegs[23].Reg_Num = 41 ; - Tuner->TunerRegs[23].Reg_Val = 0x00 ; + state->TunerRegs[23].Reg_Num = 41 ; + state->TunerRegs[23].Reg_Val = 0x00 ; - Tuner->TunerRegs[24].Reg_Num = 42 ; - Tuner->TunerRegs[24].Reg_Val = 0xF8 ; + state->TunerRegs[24].Reg_Num = 42 ; + state->TunerRegs[24].Reg_Val = 0xF8 ; - Tuner->TunerRegs[25].Reg_Num = 43 ; - Tuner->TunerRegs[25].Reg_Val = 0x43 ; + state->TunerRegs[25].Reg_Num = 43 ; + state->TunerRegs[25].Reg_Val = 0x43 ; - Tuner->TunerRegs[26].Reg_Num = 44 ; - Tuner->TunerRegs[26].Reg_Val = 0x20 ; + state->TunerRegs[26].Reg_Num = 44 ; + state->TunerRegs[26].Reg_Val = 0x20 ; - Tuner->TunerRegs[27].Reg_Num = 45 ; - Tuner->TunerRegs[27].Reg_Val = 0x80 ; + state->TunerRegs[27].Reg_Num = 45 ; + state->TunerRegs[27].Reg_Val = 0x80 ; - Tuner->TunerRegs[28].Reg_Num = 46 ; - Tuner->TunerRegs[28].Reg_Val = 0x88 ; + state->TunerRegs[28].Reg_Num = 46 ; + state->TunerRegs[28].Reg_Val = 0x88 ; - Tuner->TunerRegs[29].Reg_Num = 47 ; - Tuner->TunerRegs[29].Reg_Val = 0x86 ; + state->TunerRegs[29].Reg_Num = 47 ; + state->TunerRegs[29].Reg_Val = 0x86 ; - Tuner->TunerRegs[30].Reg_Num = 48 ; - Tuner->TunerRegs[30].Reg_Val = 0x00 ; + state->TunerRegs[30].Reg_Num = 48 ; + state->TunerRegs[30].Reg_Val = 0x00 ; - Tuner->TunerRegs[31].Reg_Num = 49 ; - Tuner->TunerRegs[31].Reg_Val = 0x00 ; + state->TunerRegs[31].Reg_Num = 49 ; + state->TunerRegs[31].Reg_Val = 0x00 ; - Tuner->TunerRegs[32].Reg_Num = 53 ; - Tuner->TunerRegs[32].Reg_Val = 0x94 ; + state->TunerRegs[32].Reg_Num = 53 ; + state->TunerRegs[32].Reg_Val = 0x94 ; - Tuner->TunerRegs[33].Reg_Num = 54 ; - Tuner->TunerRegs[33].Reg_Val = 0xFA ; + state->TunerRegs[33].Reg_Num = 54 ; + state->TunerRegs[33].Reg_Val = 0xFA ; - Tuner->TunerRegs[34].Reg_Num = 55 ; - Tuner->TunerRegs[34].Reg_Val = 0x92 ; + state->TunerRegs[34].Reg_Num = 55 ; + state->TunerRegs[34].Reg_Val = 0x92 ; - Tuner->TunerRegs[35].Reg_Num = 56 ; - Tuner->TunerRegs[35].Reg_Val = 0x80 ; + state->TunerRegs[35].Reg_Num = 56 ; + state->TunerRegs[35].Reg_Val = 0x80 ; - Tuner->TunerRegs[36].Reg_Num = 57 ; - Tuner->TunerRegs[36].Reg_Val = 0x41 ; + state->TunerRegs[36].Reg_Num = 57 ; + state->TunerRegs[36].Reg_Val = 0x41 ; - Tuner->TunerRegs[37].Reg_Num = 58 ; - Tuner->TunerRegs[37].Reg_Val = 0xDB ; + state->TunerRegs[37].Reg_Num = 58 ; + state->TunerRegs[37].Reg_Val = 0xDB ; - Tuner->TunerRegs[38].Reg_Num = 59 ; - Tuner->TunerRegs[38].Reg_Val = 0x00 ; + state->TunerRegs[38].Reg_Num = 59 ; + state->TunerRegs[38].Reg_Val = 0x00 ; - Tuner->TunerRegs[39].Reg_Num = 60 ; - Tuner->TunerRegs[39].Reg_Val = 0x00 ; + state->TunerRegs[39].Reg_Num = 60 ; + state->TunerRegs[39].Reg_Val = 0x00 ; - Tuner->TunerRegs[40].Reg_Num = 61 ; - Tuner->TunerRegs[40].Reg_Val = 0x00 ; + state->TunerRegs[40].Reg_Num = 61 ; + state->TunerRegs[40].Reg_Val = 0x00 ; - Tuner->TunerRegs[41].Reg_Num = 62 ; - Tuner->TunerRegs[41].Reg_Val = 0x00 ; + state->TunerRegs[41].Reg_Num = 62 ; + state->TunerRegs[41].Reg_Val = 0x00 ; - Tuner->TunerRegs[42].Reg_Num = 65 ; - Tuner->TunerRegs[42].Reg_Val = 0xF8 ; + state->TunerRegs[42].Reg_Num = 65 ; + state->TunerRegs[42].Reg_Val = 0xF8 ; - Tuner->TunerRegs[43].Reg_Num = 66 ; - Tuner->TunerRegs[43].Reg_Val = 0xE4 ; + state->TunerRegs[43].Reg_Num = 66 ; + state->TunerRegs[43].Reg_Val = 0xE4 ; - Tuner->TunerRegs[44].Reg_Num = 67 ; - Tuner->TunerRegs[44].Reg_Val = 0x90 ; + state->TunerRegs[44].Reg_Num = 67 ; + state->TunerRegs[44].Reg_Val = 0x90 ; - Tuner->TunerRegs[45].Reg_Num = 68 ; - Tuner->TunerRegs[45].Reg_Val = 0xC0 ; + state->TunerRegs[45].Reg_Num = 68 ; + state->TunerRegs[45].Reg_Val = 0xC0 ; - Tuner->TunerRegs[46].Reg_Num = 69 ; - Tuner->TunerRegs[46].Reg_Val = 0x01 ; + state->TunerRegs[46].Reg_Num = 69 ; + state->TunerRegs[46].Reg_Val = 0x01 ; - Tuner->TunerRegs[47].Reg_Num = 70 ; - Tuner->TunerRegs[47].Reg_Val = 0x50 ; + state->TunerRegs[47].Reg_Num = 70 ; + state->TunerRegs[47].Reg_Val = 0x50 ; - Tuner->TunerRegs[48].Reg_Num = 71 ; - Tuner->TunerRegs[48].Reg_Val = 0x06 ; + state->TunerRegs[48].Reg_Num = 71 ; + state->TunerRegs[48].Reg_Val = 0x06 ; - Tuner->TunerRegs[49].Reg_Num = 72 ; - Tuner->TunerRegs[49].Reg_Val = 0x00 ; + state->TunerRegs[49].Reg_Num = 72 ; + state->TunerRegs[49].Reg_Val = 0x00 ; - Tuner->TunerRegs[50].Reg_Num = 73 ; - Tuner->TunerRegs[50].Reg_Val = 0x20 ; + state->TunerRegs[50].Reg_Num = 73 ; + state->TunerRegs[50].Reg_Val = 0x20 ; - Tuner->TunerRegs[51].Reg_Num = 76 ; - Tuner->TunerRegs[51].Reg_Val = 0xBB ; + state->TunerRegs[51].Reg_Num = 76 ; + state->TunerRegs[51].Reg_Val = 0xBB ; - Tuner->TunerRegs[52].Reg_Num = 77 ; - Tuner->TunerRegs[52].Reg_Val = 0x13 ; + state->TunerRegs[52].Reg_Num = 77 ; + state->TunerRegs[52].Reg_Val = 0x13 ; - Tuner->TunerRegs[53].Reg_Num = 81 ; - Tuner->TunerRegs[53].Reg_Val = 0x04 ; + state->TunerRegs[53].Reg_Num = 81 ; + state->TunerRegs[53].Reg_Val = 0x04 ; - Tuner->TunerRegs[54].Reg_Num = 82 ; - Tuner->TunerRegs[54].Reg_Val = 0x75 ; + state->TunerRegs[54].Reg_Num = 82 ; + state->TunerRegs[54].Reg_Val = 0x75 ; - Tuner->TunerRegs[55].Reg_Num = 83 ; - Tuner->TunerRegs[55].Reg_Val = 0x00 ; + state->TunerRegs[55].Reg_Num = 83 ; + state->TunerRegs[55].Reg_Val = 0x00 ; - Tuner->TunerRegs[56].Reg_Num = 84 ; - Tuner->TunerRegs[56].Reg_Val = 0x00 ; + state->TunerRegs[56].Reg_Num = 84 ; + state->TunerRegs[56].Reg_Val = 0x00 ; - Tuner->TunerRegs[57].Reg_Num = 85 ; - Tuner->TunerRegs[57].Reg_Val = 0x00 ; + state->TunerRegs[57].Reg_Num = 85 ; + state->TunerRegs[57].Reg_Val = 0x00 ; - Tuner->TunerRegs[58].Reg_Num = 91 ; - Tuner->TunerRegs[58].Reg_Val = 0x70 ; + state->TunerRegs[58].Reg_Num = 91 ; + state->TunerRegs[58].Reg_Val = 0x70 ; - Tuner->TunerRegs[59].Reg_Num = 92 ; - Tuner->TunerRegs[59].Reg_Val = 0x00 ; + state->TunerRegs[59].Reg_Num = 92 ; + state->TunerRegs[59].Reg_Val = 0x00 ; - Tuner->TunerRegs[60].Reg_Num = 93 ; - Tuner->TunerRegs[60].Reg_Val = 0x00 ; + state->TunerRegs[60].Reg_Num = 93 ; + state->TunerRegs[60].Reg_Val = 0x00 ; - Tuner->TunerRegs[61].Reg_Num = 94 ; - Tuner->TunerRegs[61].Reg_Val = 0x00 ; + state->TunerRegs[61].Reg_Num = 94 ; + state->TunerRegs[61].Reg_Val = 0x00 ; - Tuner->TunerRegs[62].Reg_Num = 95 ; - Tuner->TunerRegs[62].Reg_Val = 0x0C ; + state->TunerRegs[62].Reg_Num = 95 ; + state->TunerRegs[62].Reg_Val = 0x0C ; - Tuner->TunerRegs[63].Reg_Num = 96 ; - Tuner->TunerRegs[63].Reg_Val = 0x00 ; + state->TunerRegs[63].Reg_Num = 96 ; + state->TunerRegs[63].Reg_Val = 0x00 ; - Tuner->TunerRegs[64].Reg_Num = 97 ; - Tuner->TunerRegs[64].Reg_Val = 0x00 ; + state->TunerRegs[64].Reg_Num = 97 ; + state->TunerRegs[64].Reg_Val = 0x00 ; - Tuner->TunerRegs[65].Reg_Num = 98 ; - Tuner->TunerRegs[65].Reg_Val = 0xE2 ; + state->TunerRegs[65].Reg_Num = 98 ; + state->TunerRegs[65].Reg_Val = 0xE2 ; - Tuner->TunerRegs[66].Reg_Num = 99 ; - Tuner->TunerRegs[66].Reg_Val = 0x00 ; + state->TunerRegs[66].Reg_Num = 99 ; + state->TunerRegs[66].Reg_Val = 0x00 ; - Tuner->TunerRegs[67].Reg_Num = 100 ; - Tuner->TunerRegs[67].Reg_Val = 0x00 ; + state->TunerRegs[67].Reg_Num = 100 ; + state->TunerRegs[67].Reg_Val = 0x00 ; - Tuner->TunerRegs[68].Reg_Num = 101 ; - Tuner->TunerRegs[68].Reg_Val = 0x12 ; + state->TunerRegs[68].Reg_Num = 101 ; + state->TunerRegs[68].Reg_Val = 0x12 ; - Tuner->TunerRegs[69].Reg_Num = 102 ; - Tuner->TunerRegs[69].Reg_Val = 0x80 ; + state->TunerRegs[69].Reg_Num = 102 ; + state->TunerRegs[69].Reg_Val = 0x80 ; - Tuner->TunerRegs[70].Reg_Num = 103 ; - Tuner->TunerRegs[70].Reg_Val = 0x32 ; + state->TunerRegs[70].Reg_Num = 103 ; + state->TunerRegs[70].Reg_Val = 0x32 ; - Tuner->TunerRegs[71].Reg_Num = 104 ; - Tuner->TunerRegs[71].Reg_Val = 0xB4 ; + state->TunerRegs[71].Reg_Num = 104 ; + state->TunerRegs[71].Reg_Val = 0xB4 ; - Tuner->TunerRegs[72].Reg_Num = 105 ; - Tuner->TunerRegs[72].Reg_Val = 0x60 ; + state->TunerRegs[72].Reg_Num = 105 ; + state->TunerRegs[72].Reg_Val = 0x60 ; - Tuner->TunerRegs[73].Reg_Num = 106 ; - Tuner->TunerRegs[73].Reg_Val = 0x83 ; + state->TunerRegs[73].Reg_Num = 106 ; + state->TunerRegs[73].Reg_Val = 0x83 ; - Tuner->TunerRegs[74].Reg_Num = 107 ; - Tuner->TunerRegs[74].Reg_Val = 0x84 ; + state->TunerRegs[74].Reg_Num = 107 ; + state->TunerRegs[74].Reg_Val = 0x84 ; - Tuner->TunerRegs[75].Reg_Num = 108 ; - Tuner->TunerRegs[75].Reg_Val = 0x9C ; + state->TunerRegs[75].Reg_Num = 108 ; + state->TunerRegs[75].Reg_Val = 0x9C ; - Tuner->TunerRegs[76].Reg_Num = 109 ; - Tuner->TunerRegs[76].Reg_Val = 0x02 ; + state->TunerRegs[76].Reg_Num = 109 ; + state->TunerRegs[76].Reg_Val = 0x02 ; - Tuner->TunerRegs[77].Reg_Num = 110 ; - Tuner->TunerRegs[77].Reg_Val = 0x81 ; + state->TunerRegs[77].Reg_Num = 110 ; + state->TunerRegs[77].Reg_Val = 0x81 ; - Tuner->TunerRegs[78].Reg_Num = 111 ; - Tuner->TunerRegs[78].Reg_Val = 0xC0 ; + state->TunerRegs[78].Reg_Num = 111 ; + state->TunerRegs[78].Reg_Val = 0xC0 ; - Tuner->TunerRegs[79].Reg_Num = 112 ; - Tuner->TunerRegs[79].Reg_Val = 0x10 ; + state->TunerRegs[79].Reg_Num = 112 ; + state->TunerRegs[79].Reg_Val = 0x10 ; - Tuner->TunerRegs[80].Reg_Num = 131 ; - Tuner->TunerRegs[80].Reg_Val = 0x8A ; + state->TunerRegs[80].Reg_Num = 131 ; + state->TunerRegs[80].Reg_Val = 0x8A ; - Tuner->TunerRegs[81].Reg_Num = 132 ; - Tuner->TunerRegs[81].Reg_Val = 0x10 ; + state->TunerRegs[81].Reg_Num = 132 ; + state->TunerRegs[81].Reg_Val = 0x10 ; - Tuner->TunerRegs[82].Reg_Num = 133 ; - Tuner->TunerRegs[82].Reg_Val = 0x24 ; + state->TunerRegs[82].Reg_Num = 133 ; + state->TunerRegs[82].Reg_Val = 0x24 ; - Tuner->TunerRegs[83].Reg_Num = 134 ; - Tuner->TunerRegs[83].Reg_Val = 0x00 ; + state->TunerRegs[83].Reg_Num = 134 ; + state->TunerRegs[83].Reg_Val = 0x00 ; - Tuner->TunerRegs[84].Reg_Num = 135 ; - Tuner->TunerRegs[84].Reg_Val = 0x00 ; + state->TunerRegs[84].Reg_Num = 135 ; + state->TunerRegs[84].Reg_Val = 0x00 ; - Tuner->TunerRegs[85].Reg_Num = 136 ; - Tuner->TunerRegs[85].Reg_Val = 0x7E ; + state->TunerRegs[85].Reg_Num = 136 ; + state->TunerRegs[85].Reg_Val = 0x7E ; - Tuner->TunerRegs[86].Reg_Num = 137 ; - Tuner->TunerRegs[86].Reg_Val = 0x40 ; + state->TunerRegs[86].Reg_Num = 137 ; + state->TunerRegs[86].Reg_Val = 0x40 ; - Tuner->TunerRegs[87].Reg_Num = 138 ; - Tuner->TunerRegs[87].Reg_Val = 0x38 ; + state->TunerRegs[87].Reg_Num = 138 ; + state->TunerRegs[87].Reg_Val = 0x38 ; - Tuner->TunerRegs[88].Reg_Num = 146 ; - Tuner->TunerRegs[88].Reg_Val = 0xF6 ; + state->TunerRegs[88].Reg_Num = 146 ; + state->TunerRegs[88].Reg_Val = 0xF6 ; - Tuner->TunerRegs[89].Reg_Num = 147 ; - Tuner->TunerRegs[89].Reg_Val = 0x1A ; + state->TunerRegs[89].Reg_Num = 147 ; + state->TunerRegs[89].Reg_Val = 0x1A ; - Tuner->TunerRegs[90].Reg_Num = 148 ; - Tuner->TunerRegs[90].Reg_Val = 0x62 ; + state->TunerRegs[90].Reg_Num = 148 ; + state->TunerRegs[90].Reg_Val = 0x62 ; - Tuner->TunerRegs[91].Reg_Num = 149 ; - Tuner->TunerRegs[91].Reg_Val = 0x33 ; + state->TunerRegs[91].Reg_Num = 149 ; + state->TunerRegs[91].Reg_Val = 0x33 ; - Tuner->TunerRegs[92].Reg_Num = 150 ; - Tuner->TunerRegs[92].Reg_Val = 0x80 ; + state->TunerRegs[92].Reg_Num = 150 ; + state->TunerRegs[92].Reg_Val = 0x80 ; - Tuner->TunerRegs[93].Reg_Num = 156 ; - Tuner->TunerRegs[93].Reg_Val = 0x56 ; + state->TunerRegs[93].Reg_Num = 156 ; + state->TunerRegs[93].Reg_Val = 0x56 ; - Tuner->TunerRegs[94].Reg_Num = 157 ; - Tuner->TunerRegs[94].Reg_Val = 0x17 ; + state->TunerRegs[94].Reg_Num = 157 ; + state->TunerRegs[94].Reg_Val = 0x17 ; - Tuner->TunerRegs[95].Reg_Num = 158 ; - Tuner->TunerRegs[95].Reg_Val = 0xA9 ; + state->TunerRegs[95].Reg_Num = 158 ; + state->TunerRegs[95].Reg_Val = 0xA9 ; - Tuner->TunerRegs[96].Reg_Num = 159 ; - Tuner->TunerRegs[96].Reg_Val = 0x00 ; + state->TunerRegs[96].Reg_Num = 159 ; + state->TunerRegs[96].Reg_Val = 0x00 ; - Tuner->TunerRegs[97].Reg_Num = 160 ; - Tuner->TunerRegs[97].Reg_Val = 0x00 ; + state->TunerRegs[97].Reg_Num = 160 ; + state->TunerRegs[97].Reg_Val = 0x00 ; - Tuner->TunerRegs[98].Reg_Num = 161 ; - Tuner->TunerRegs[98].Reg_Val = 0x00 ; + state->TunerRegs[98].Reg_Num = 161 ; + state->TunerRegs[98].Reg_Val = 0x00 ; - Tuner->TunerRegs[99].Reg_Num = 162 ; - Tuner->TunerRegs[99].Reg_Val = 0x40 ; + state->TunerRegs[99].Reg_Num = 162 ; + state->TunerRegs[99].Reg_Val = 0x40 ; - Tuner->TunerRegs[100].Reg_Num = 166 ; - Tuner->TunerRegs[100].Reg_Val = 0xAE ; + state->TunerRegs[100].Reg_Num = 166 ; + state->TunerRegs[100].Reg_Val = 0xAE ; - Tuner->TunerRegs[101].Reg_Num = 167 ; - Tuner->TunerRegs[101].Reg_Val = 0x1B ; + state->TunerRegs[101].Reg_Num = 167 ; + state->TunerRegs[101].Reg_Val = 0x1B ; - Tuner->TunerRegs[102].Reg_Num = 168 ; - Tuner->TunerRegs[102].Reg_Val = 0xF2 ; + state->TunerRegs[102].Reg_Num = 168 ; + state->TunerRegs[102].Reg_Val = 0xF2 ; - Tuner->TunerRegs[103].Reg_Num = 195 ; - Tuner->TunerRegs[103].Reg_Val = 0x00 ; + state->TunerRegs[103].Reg_Num = 195 ; + state->TunerRegs[103].Reg_Val = 0x00 ; return 0 ; } -u16 MXL5005_ControlInit(Tuner_struct *Tuner) +// DONE +u16 MXL5005_ControlInit(struct dvb_frontend *fe) { - Tuner->Init_Ctrl_Num = INITCTRL_NUM ; - - Tuner->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; - Tuner->Init_Ctrl[0].size = 1 ; - Tuner->Init_Ctrl[0].addr[0] = 73; - Tuner->Init_Ctrl[0].bit[0] = 7; - Tuner->Init_Ctrl[0].val[0] = 0; - - Tuner->Init_Ctrl[1].Ctrl_Num = BB_MODE ; - Tuner->Init_Ctrl[1].size = 1 ; - Tuner->Init_Ctrl[1].addr[0] = 53; - Tuner->Init_Ctrl[1].bit[0] = 2; - Tuner->Init_Ctrl[1].val[0] = 1; - - Tuner->Init_Ctrl[2].Ctrl_Num = BB_BUF ; - Tuner->Init_Ctrl[2].size = 2 ; - Tuner->Init_Ctrl[2].addr[0] = 53; - Tuner->Init_Ctrl[2].bit[0] = 1; - Tuner->Init_Ctrl[2].val[0] = 0; - Tuner->Init_Ctrl[2].addr[1] = 57; - Tuner->Init_Ctrl[2].bit[1] = 0; - Tuner->Init_Ctrl[2].val[1] = 1; - - Tuner->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ; - Tuner->Init_Ctrl[3].size = 1 ; - Tuner->Init_Ctrl[3].addr[0] = 53; - Tuner->Init_Ctrl[3].bit[0] = 0; - Tuner->Init_Ctrl[3].val[0] = 0; - - Tuner->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ; - Tuner->Init_Ctrl[4].size = 3 ; - Tuner->Init_Ctrl[4].addr[0] = 53; - Tuner->Init_Ctrl[4].bit[0] = 5; - Tuner->Init_Ctrl[4].val[0] = 0; - Tuner->Init_Ctrl[4].addr[1] = 53; - Tuner->Init_Ctrl[4].bit[1] = 6; - Tuner->Init_Ctrl[4].val[1] = 0; - Tuner->Init_Ctrl[4].addr[2] = 53; - Tuner->Init_Ctrl[4].bit[2] = 7; - Tuner->Init_Ctrl[4].val[2] = 1; - - Tuner->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ; - Tuner->Init_Ctrl[5].size = 1 ; - Tuner->Init_Ctrl[5].addr[0] = 59; - Tuner->Init_Ctrl[5].bit[0] = 0; - Tuner->Init_Ctrl[5].val[0] = 0; - - Tuner->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ; - Tuner->Init_Ctrl[6].size = 2 ; - Tuner->Init_Ctrl[6].addr[0] = 53; - Tuner->Init_Ctrl[6].bit[0] = 3; - Tuner->Init_Ctrl[6].val[0] = 0; - Tuner->Init_Ctrl[6].addr[1] = 53; - Tuner->Init_Ctrl[6].bit[1] = 4; - Tuner->Init_Ctrl[6].val[1] = 1; - - Tuner->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ; - Tuner->Init_Ctrl[7].size = 4 ; - Tuner->Init_Ctrl[7].addr[0] = 22; - Tuner->Init_Ctrl[7].bit[0] = 4; - Tuner->Init_Ctrl[7].val[0] = 0; - Tuner->Init_Ctrl[7].addr[1] = 22; - Tuner->Init_Ctrl[7].bit[1] = 5; - Tuner->Init_Ctrl[7].val[1] = 1; - Tuner->Init_Ctrl[7].addr[2] = 22; - Tuner->Init_Ctrl[7].bit[2] = 6; - Tuner->Init_Ctrl[7].val[2] = 1; - Tuner->Init_Ctrl[7].addr[3] = 22; - Tuner->Init_Ctrl[7].bit[3] = 7; - Tuner->Init_Ctrl[7].val[3] = 0; - - Tuner->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ; - Tuner->Init_Ctrl[8].size = 1 ; - Tuner->Init_Ctrl[8].addr[0] = 22; - Tuner->Init_Ctrl[8].bit[0] = 2; - Tuner->Init_Ctrl[8].val[0] = 0; - - Tuner->Init_Ctrl[9].Ctrl_Num = AGC_IF ; - Tuner->Init_Ctrl[9].size = 4 ; - Tuner->Init_Ctrl[9].addr[0] = 76; - Tuner->Init_Ctrl[9].bit[0] = 0; - Tuner->Init_Ctrl[9].val[0] = 1; - Tuner->Init_Ctrl[9].addr[1] = 76; - Tuner->Init_Ctrl[9].bit[1] = 1; - Tuner->Init_Ctrl[9].val[1] = 1; - Tuner->Init_Ctrl[9].addr[2] = 76; - Tuner->Init_Ctrl[9].bit[2] = 2; - Tuner->Init_Ctrl[9].val[2] = 0; - Tuner->Init_Ctrl[9].addr[3] = 76; - Tuner->Init_Ctrl[9].bit[3] = 3; - Tuner->Init_Ctrl[9].val[3] = 1; - - Tuner->Init_Ctrl[10].Ctrl_Num = AGC_RF ; - Tuner->Init_Ctrl[10].size = 4 ; - Tuner->Init_Ctrl[10].addr[0] = 76; - Tuner->Init_Ctrl[10].bit[0] = 4; - Tuner->Init_Ctrl[10].val[0] = 1; - Tuner->Init_Ctrl[10].addr[1] = 76; - Tuner->Init_Ctrl[10].bit[1] = 5; - Tuner->Init_Ctrl[10].val[1] = 1; - Tuner->Init_Ctrl[10].addr[2] = 76; - Tuner->Init_Ctrl[10].bit[2] = 6; - Tuner->Init_Ctrl[10].val[2] = 0; - Tuner->Init_Ctrl[10].addr[3] = 76; - Tuner->Init_Ctrl[10].bit[3] = 7; - Tuner->Init_Ctrl[10].val[3] = 1; - - Tuner->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ; - Tuner->Init_Ctrl[11].size = 5 ; - Tuner->Init_Ctrl[11].addr[0] = 43; - Tuner->Init_Ctrl[11].bit[0] = 3; - Tuner->Init_Ctrl[11].val[0] = 0; - Tuner->Init_Ctrl[11].addr[1] = 43; - Tuner->Init_Ctrl[11].bit[1] = 4; - Tuner->Init_Ctrl[11].val[1] = 0; - Tuner->Init_Ctrl[11].addr[2] = 43; - Tuner->Init_Ctrl[11].bit[2] = 5; - Tuner->Init_Ctrl[11].val[2] = 0; - Tuner->Init_Ctrl[11].addr[3] = 43; - Tuner->Init_Ctrl[11].bit[3] = 6; - Tuner->Init_Ctrl[11].val[3] = 1; - Tuner->Init_Ctrl[11].addr[4] = 43; - Tuner->Init_Ctrl[11].bit[4] = 7; - Tuner->Init_Ctrl[11].val[4] = 0; - - Tuner->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ; - Tuner->Init_Ctrl[12].size = 6 ; - Tuner->Init_Ctrl[12].addr[0] = 44; - Tuner->Init_Ctrl[12].bit[0] = 2; - Tuner->Init_Ctrl[12].val[0] = 0; - Tuner->Init_Ctrl[12].addr[1] = 44; - Tuner->Init_Ctrl[12].bit[1] = 3; - Tuner->Init_Ctrl[12].val[1] = 0; - Tuner->Init_Ctrl[12].addr[2] = 44; - Tuner->Init_Ctrl[12].bit[2] = 4; - Tuner->Init_Ctrl[12].val[2] = 0; - Tuner->Init_Ctrl[12].addr[3] = 44; - Tuner->Init_Ctrl[12].bit[3] = 5; - Tuner->Init_Ctrl[12].val[3] = 1; - Tuner->Init_Ctrl[12].addr[4] = 44; - Tuner->Init_Ctrl[12].bit[4] = 6; - Tuner->Init_Ctrl[12].val[4] = 0; - Tuner->Init_Ctrl[12].addr[5] = 44; - Tuner->Init_Ctrl[12].bit[5] = 7; - Tuner->Init_Ctrl[12].val[5] = 0; - - Tuner->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ; - Tuner->Init_Ctrl[13].size = 7 ; - Tuner->Init_Ctrl[13].addr[0] = 11; - Tuner->Init_Ctrl[13].bit[0] = 0; - Tuner->Init_Ctrl[13].val[0] = 1; - Tuner->Init_Ctrl[13].addr[1] = 11; - Tuner->Init_Ctrl[13].bit[1] = 1; - Tuner->Init_Ctrl[13].val[1] = 0; - Tuner->Init_Ctrl[13].addr[2] = 11; - Tuner->Init_Ctrl[13].bit[2] = 2; - Tuner->Init_Ctrl[13].val[2] = 0; - Tuner->Init_Ctrl[13].addr[3] = 11; - Tuner->Init_Ctrl[13].bit[3] = 3; - Tuner->Init_Ctrl[13].val[3] = 1; - Tuner->Init_Ctrl[13].addr[4] = 11; - Tuner->Init_Ctrl[13].bit[4] = 4; - Tuner->Init_Ctrl[13].val[4] = 1; - Tuner->Init_Ctrl[13].addr[5] = 11; - Tuner->Init_Ctrl[13].bit[5] = 5; - Tuner->Init_Ctrl[13].val[5] = 0; - Tuner->Init_Ctrl[13].addr[6] = 11; - Tuner->Init_Ctrl[13].bit[6] = 6; - Tuner->Init_Ctrl[13].val[6] = 0; - - Tuner->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ; - Tuner->Init_Ctrl[14].size = 16 ; - Tuner->Init_Ctrl[14].addr[0] = 13; - Tuner->Init_Ctrl[14].bit[0] = 0; - Tuner->Init_Ctrl[14].val[0] = 0; - Tuner->Init_Ctrl[14].addr[1] = 13; - Tuner->Init_Ctrl[14].bit[1] = 1; - Tuner->Init_Ctrl[14].val[1] = 0; - Tuner->Init_Ctrl[14].addr[2] = 13; - Tuner->Init_Ctrl[14].bit[2] = 2; - Tuner->Init_Ctrl[14].val[2] = 0; - Tuner->Init_Ctrl[14].addr[3] = 13; - Tuner->Init_Ctrl[14].bit[3] = 3; - Tuner->Init_Ctrl[14].val[3] = 0; - Tuner->Init_Ctrl[14].addr[4] = 13; - Tuner->Init_Ctrl[14].bit[4] = 4; - Tuner->Init_Ctrl[14].val[4] = 0; - Tuner->Init_Ctrl[14].addr[5] = 13; - Tuner->Init_Ctrl[14].bit[5] = 5; - Tuner->Init_Ctrl[14].val[5] = 0; - Tuner->Init_Ctrl[14].addr[6] = 13; - Tuner->Init_Ctrl[14].bit[6] = 6; - Tuner->Init_Ctrl[14].val[6] = 0; - Tuner->Init_Ctrl[14].addr[7] = 13; - Tuner->Init_Ctrl[14].bit[7] = 7; - Tuner->Init_Ctrl[14].val[7] = 0; - Tuner->Init_Ctrl[14].addr[8] = 12; - Tuner->Init_Ctrl[14].bit[8] = 0; - Tuner->Init_Ctrl[14].val[8] = 0; - Tuner->Init_Ctrl[14].addr[9] = 12; - Tuner->Init_Ctrl[14].bit[9] = 1; - Tuner->Init_Ctrl[14].val[9] = 0; - Tuner->Init_Ctrl[14].addr[10] = 12; - Tuner->Init_Ctrl[14].bit[10] = 2; - Tuner->Init_Ctrl[14].val[10] = 0; - Tuner->Init_Ctrl[14].addr[11] = 12; - Tuner->Init_Ctrl[14].bit[11] = 3; - Tuner->Init_Ctrl[14].val[11] = 0; - Tuner->Init_Ctrl[14].addr[12] = 12; - Tuner->Init_Ctrl[14].bit[12] = 4; - Tuner->Init_Ctrl[14].val[12] = 0; - Tuner->Init_Ctrl[14].addr[13] = 12; - Tuner->Init_Ctrl[14].bit[13] = 5; - Tuner->Init_Ctrl[14].val[13] = 1; - Tuner->Init_Ctrl[14].addr[14] = 12; - Tuner->Init_Ctrl[14].bit[14] = 6; - Tuner->Init_Ctrl[14].val[14] = 1; - Tuner->Init_Ctrl[14].addr[15] = 12; - Tuner->Init_Ctrl[14].bit[15] = 7; - Tuner->Init_Ctrl[14].val[15] = 0; - - Tuner->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ; - Tuner->Init_Ctrl[15].size = 3 ; - Tuner->Init_Ctrl[15].addr[0] = 147; - Tuner->Init_Ctrl[15].bit[0] = 2; - Tuner->Init_Ctrl[15].val[0] = 0; - Tuner->Init_Ctrl[15].addr[1] = 147; - Tuner->Init_Ctrl[15].bit[1] = 3; - Tuner->Init_Ctrl[15].val[1] = 1; - Tuner->Init_Ctrl[15].addr[2] = 147; - Tuner->Init_Ctrl[15].bit[2] = 4; - Tuner->Init_Ctrl[15].val[2] = 1; - - Tuner->Init_Ctrl[16].Ctrl_Num = I_DRIVER ; - Tuner->Init_Ctrl[16].size = 2 ; - Tuner->Init_Ctrl[16].addr[0] = 147; - Tuner->Init_Ctrl[16].bit[0] = 0; - Tuner->Init_Ctrl[16].val[0] = 0; - Tuner->Init_Ctrl[16].addr[1] = 147; - Tuner->Init_Ctrl[16].bit[1] = 1; - Tuner->Init_Ctrl[16].val[1] = 1; - - Tuner->Init_Ctrl[17].Ctrl_Num = EN_AAF ; - Tuner->Init_Ctrl[17].size = 1 ; - Tuner->Init_Ctrl[17].addr[0] = 147; - Tuner->Init_Ctrl[17].bit[0] = 7; - Tuner->Init_Ctrl[17].val[0] = 0; - - Tuner->Init_Ctrl[18].Ctrl_Num = EN_3P ; - Tuner->Init_Ctrl[18].size = 1 ; - Tuner->Init_Ctrl[18].addr[0] = 147; - Tuner->Init_Ctrl[18].bit[0] = 6; - Tuner->Init_Ctrl[18].val[0] = 0; - - Tuner->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ; - Tuner->Init_Ctrl[19].size = 1 ; - Tuner->Init_Ctrl[19].addr[0] = 156; - Tuner->Init_Ctrl[19].bit[0] = 0; - Tuner->Init_Ctrl[19].val[0] = 0; - - Tuner->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ; - Tuner->Init_Ctrl[20].size = 1 ; - Tuner->Init_Ctrl[20].addr[0] = 147; - Tuner->Init_Ctrl[20].bit[0] = 5; - Tuner->Init_Ctrl[20].val[0] = 0; - - Tuner->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ; - Tuner->Init_Ctrl[21].size = 1 ; - Tuner->Init_Ctrl[21].addr[0] = 137; - Tuner->Init_Ctrl[21].bit[0] = 4; - Tuner->Init_Ctrl[21].val[0] = 0; - - Tuner->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ; - Tuner->Init_Ctrl[22].size = 1 ; - Tuner->Init_Ctrl[22].addr[0] = 137; - Tuner->Init_Ctrl[22].bit[0] = 7; - Tuner->Init_Ctrl[22].val[0] = 0; - - Tuner->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ; - Tuner->Init_Ctrl[23].size = 1 ; - Tuner->Init_Ctrl[23].addr[0] = 91; - Tuner->Init_Ctrl[23].bit[0] = 5; - Tuner->Init_Ctrl[23].val[0] = 1; - - Tuner->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ; - Tuner->Init_Ctrl[24].size = 1 ; - Tuner->Init_Ctrl[24].addr[0] = 43; - Tuner->Init_Ctrl[24].bit[0] = 0; - Tuner->Init_Ctrl[24].val[0] = 1; - - Tuner->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ; - Tuner->Init_Ctrl[25].size = 2 ; - Tuner->Init_Ctrl[25].addr[0] = 22; - Tuner->Init_Ctrl[25].bit[0] = 0; - Tuner->Init_Ctrl[25].val[0] = 1; - Tuner->Init_Ctrl[25].addr[1] = 22; - Tuner->Init_Ctrl[25].bit[1] = 1; - Tuner->Init_Ctrl[25].val[1] = 1; - - Tuner->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ; - Tuner->Init_Ctrl[26].size = 1 ; - Tuner->Init_Ctrl[26].addr[0] = 134; - Tuner->Init_Ctrl[26].bit[0] = 2; - Tuner->Init_Ctrl[26].val[0] = 0; - - Tuner->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ; - Tuner->Init_Ctrl[27].size = 1 ; - Tuner->Init_Ctrl[27].addr[0] = 137; - Tuner->Init_Ctrl[27].bit[0] = 3; - Tuner->Init_Ctrl[27].val[0] = 0; - - Tuner->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ; - Tuner->Init_Ctrl[28].size = 1 ; - Tuner->Init_Ctrl[28].addr[0] = 77; - Tuner->Init_Ctrl[28].bit[0] = 7; - Tuner->Init_Ctrl[28].val[0] = 0; - - Tuner->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ; - Tuner->Init_Ctrl[29].size = 1 ; - Tuner->Init_Ctrl[29].addr[0] = 166; - Tuner->Init_Ctrl[29].bit[0] = 7; - Tuner->Init_Ctrl[29].val[0] = 1; - - Tuner->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ; - Tuner->Init_Ctrl[30].size = 3 ; - Tuner->Init_Ctrl[30].addr[0] = 166; - Tuner->Init_Ctrl[30].bit[0] = 0; - Tuner->Init_Ctrl[30].val[0] = 0; - Tuner->Init_Ctrl[30].addr[1] = 166; - Tuner->Init_Ctrl[30].bit[1] = 1; - Tuner->Init_Ctrl[30].val[1] = 1; - Tuner->Init_Ctrl[30].addr[2] = 166; - Tuner->Init_Ctrl[30].bit[2] = 2; - Tuner->Init_Ctrl[30].val[2] = 1; - - Tuner->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ; - Tuner->Init_Ctrl[31].size = 3 ; - Tuner->Init_Ctrl[31].addr[0] = 166; - Tuner->Init_Ctrl[31].bit[0] = 3; - Tuner->Init_Ctrl[31].val[0] = 1; - Tuner->Init_Ctrl[31].addr[1] = 166; - Tuner->Init_Ctrl[31].bit[1] = 4; - Tuner->Init_Ctrl[31].val[1] = 0; - Tuner->Init_Ctrl[31].addr[2] = 166; - Tuner->Init_Ctrl[31].bit[2] = 5; - Tuner->Init_Ctrl[31].val[2] = 1; - - Tuner->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ; - Tuner->Init_Ctrl[32].size = 3 ; - Tuner->Init_Ctrl[32].addr[0] = 167; - Tuner->Init_Ctrl[32].bit[0] = 0; - Tuner->Init_Ctrl[32].val[0] = 1; - Tuner->Init_Ctrl[32].addr[1] = 167; - Tuner->Init_Ctrl[32].bit[1] = 1; - Tuner->Init_Ctrl[32].val[1] = 1; - Tuner->Init_Ctrl[32].addr[2] = 167; - Tuner->Init_Ctrl[32].bit[2] = 2; - Tuner->Init_Ctrl[32].val[2] = 0; - - Tuner->Init_Ctrl[33].Ctrl_Num = RFA_FLR ; - Tuner->Init_Ctrl[33].size = 4 ; - Tuner->Init_Ctrl[33].addr[0] = 168; - Tuner->Init_Ctrl[33].bit[0] = 0; - Tuner->Init_Ctrl[33].val[0] = 0; - Tuner->Init_Ctrl[33].addr[1] = 168; - Tuner->Init_Ctrl[33].bit[1] = 1; - Tuner->Init_Ctrl[33].val[1] = 1; - Tuner->Init_Ctrl[33].addr[2] = 168; - Tuner->Init_Ctrl[33].bit[2] = 2; - Tuner->Init_Ctrl[33].val[2] = 0; - Tuner->Init_Ctrl[33].addr[3] = 168; - Tuner->Init_Ctrl[33].bit[3] = 3; - Tuner->Init_Ctrl[33].val[3] = 0; - - Tuner->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ; - Tuner->Init_Ctrl[34].size = 4 ; - Tuner->Init_Ctrl[34].addr[0] = 168; - Tuner->Init_Ctrl[34].bit[0] = 4; - Tuner->Init_Ctrl[34].val[0] = 1; - Tuner->Init_Ctrl[34].addr[1] = 168; - Tuner->Init_Ctrl[34].bit[1] = 5; - Tuner->Init_Ctrl[34].val[1] = 1; - Tuner->Init_Ctrl[34].addr[2] = 168; - Tuner->Init_Ctrl[34].bit[2] = 6; - Tuner->Init_Ctrl[34].val[2] = 1; - Tuner->Init_Ctrl[34].addr[3] = 168; - Tuner->Init_Ctrl[34].bit[3] = 7; - Tuner->Init_Ctrl[34].val[3] = 1; - - Tuner->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ; - Tuner->Init_Ctrl[35].size = 1 ; - Tuner->Init_Ctrl[35].addr[0] = 135; - Tuner->Init_Ctrl[35].bit[0] = 0; - Tuner->Init_Ctrl[35].val[0] = 0; - - Tuner->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ; - Tuner->Init_Ctrl[36].size = 1 ; - Tuner->Init_Ctrl[36].addr[0] = 56; - Tuner->Init_Ctrl[36].bit[0] = 3; - Tuner->Init_Ctrl[36].val[0] = 0; - - Tuner->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ; - Tuner->Init_Ctrl[37].size = 7 ; - Tuner->Init_Ctrl[37].addr[0] = 59; - Tuner->Init_Ctrl[37].bit[0] = 1; - Tuner->Init_Ctrl[37].val[0] = 0; - Tuner->Init_Ctrl[37].addr[1] = 59; - Tuner->Init_Ctrl[37].bit[1] = 2; - Tuner->Init_Ctrl[37].val[1] = 0; - Tuner->Init_Ctrl[37].addr[2] = 59; - Tuner->Init_Ctrl[37].bit[2] = 3; - Tuner->Init_Ctrl[37].val[2] = 0; - Tuner->Init_Ctrl[37].addr[3] = 59; - Tuner->Init_Ctrl[37].bit[3] = 4; - Tuner->Init_Ctrl[37].val[3] = 0; - Tuner->Init_Ctrl[37].addr[4] = 59; - Tuner->Init_Ctrl[37].bit[4] = 5; - Tuner->Init_Ctrl[37].val[4] = 0; - Tuner->Init_Ctrl[37].addr[5] = 59; - Tuner->Init_Ctrl[37].bit[5] = 6; - Tuner->Init_Ctrl[37].val[5] = 0; - Tuner->Init_Ctrl[37].addr[6] = 59; - Tuner->Init_Ctrl[37].bit[6] = 7; - Tuner->Init_Ctrl[37].val[6] = 0; - - Tuner->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ; - Tuner->Init_Ctrl[38].size = 6 ; - Tuner->Init_Ctrl[38].addr[0] = 32; - Tuner->Init_Ctrl[38].bit[0] = 2; - Tuner->Init_Ctrl[38].val[0] = 0; - Tuner->Init_Ctrl[38].addr[1] = 32; - Tuner->Init_Ctrl[38].bit[1] = 3; - Tuner->Init_Ctrl[38].val[1] = 0; - Tuner->Init_Ctrl[38].addr[2] = 32; - Tuner->Init_Ctrl[38].bit[2] = 4; - Tuner->Init_Ctrl[38].val[2] = 0; - Tuner->Init_Ctrl[38].addr[3] = 32; - Tuner->Init_Ctrl[38].bit[3] = 5; - Tuner->Init_Ctrl[38].val[3] = 0; - Tuner->Init_Ctrl[38].addr[4] = 32; - Tuner->Init_Ctrl[38].bit[4] = 6; - Tuner->Init_Ctrl[38].val[4] = 1; - Tuner->Init_Ctrl[38].addr[5] = 32; - Tuner->Init_Ctrl[38].bit[5] = 7; - Tuner->Init_Ctrl[38].val[5] = 0; - - Tuner->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ; - Tuner->Init_Ctrl[39].size = 1 ; - Tuner->Init_Ctrl[39].addr[0] = 25; - Tuner->Init_Ctrl[39].bit[0] = 3; - Tuner->Init_Ctrl[39].val[0] = 1; - - - Tuner->CH_Ctrl_Num = CHCTRL_NUM ; - - Tuner->CH_Ctrl[0].Ctrl_Num = DN_POLY ; - Tuner->CH_Ctrl[0].size = 2 ; - Tuner->CH_Ctrl[0].addr[0] = 68; - Tuner->CH_Ctrl[0].bit[0] = 6; - Tuner->CH_Ctrl[0].val[0] = 1; - Tuner->CH_Ctrl[0].addr[1] = 68; - Tuner->CH_Ctrl[0].bit[1] = 7; - Tuner->CH_Ctrl[0].val[1] = 1; - - Tuner->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ; - Tuner->CH_Ctrl[1].size = 2 ; - Tuner->CH_Ctrl[1].addr[0] = 70; - Tuner->CH_Ctrl[1].bit[0] = 6; - Tuner->CH_Ctrl[1].val[0] = 1; - Tuner->CH_Ctrl[1].addr[1] = 70; - Tuner->CH_Ctrl[1].bit[1] = 7; - Tuner->CH_Ctrl[1].val[1] = 0; - - Tuner->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ; - Tuner->CH_Ctrl[2].size = 9 ; - Tuner->CH_Ctrl[2].addr[0] = 69; - Tuner->CH_Ctrl[2].bit[0] = 5; - Tuner->CH_Ctrl[2].val[0] = 0; - Tuner->CH_Ctrl[2].addr[1] = 69; - Tuner->CH_Ctrl[2].bit[1] = 6; - Tuner->CH_Ctrl[2].val[1] = 0; - Tuner->CH_Ctrl[2].addr[2] = 69; - Tuner->CH_Ctrl[2].bit[2] = 7; - Tuner->CH_Ctrl[2].val[2] = 0; - Tuner->CH_Ctrl[2].addr[3] = 68; - Tuner->CH_Ctrl[2].bit[3] = 0; - Tuner->CH_Ctrl[2].val[3] = 0; - Tuner->CH_Ctrl[2].addr[4] = 68; - Tuner->CH_Ctrl[2].bit[4] = 1; - Tuner->CH_Ctrl[2].val[4] = 0; - Tuner->CH_Ctrl[2].addr[5] = 68; - Tuner->CH_Ctrl[2].bit[5] = 2; - Tuner->CH_Ctrl[2].val[5] = 0; - Tuner->CH_Ctrl[2].addr[6] = 68; - Tuner->CH_Ctrl[2].bit[6] = 3; - Tuner->CH_Ctrl[2].val[6] = 0; - Tuner->CH_Ctrl[2].addr[7] = 68; - Tuner->CH_Ctrl[2].bit[7] = 4; - Tuner->CH_Ctrl[2].val[7] = 0; - Tuner->CH_Ctrl[2].addr[8] = 68; - Tuner->CH_Ctrl[2].bit[8] = 5; - Tuner->CH_Ctrl[2].val[8] = 0; - - Tuner->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ; - Tuner->CH_Ctrl[3].size = 1 ; - Tuner->CH_Ctrl[3].addr[0] = 70; - Tuner->CH_Ctrl[3].bit[0] = 5; - Tuner->CH_Ctrl[3].val[0] = 0; - - Tuner->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ; - Tuner->CH_Ctrl[4].size = 3 ; - Tuner->CH_Ctrl[4].addr[0] = 73; - Tuner->CH_Ctrl[4].bit[0] = 4; - Tuner->CH_Ctrl[4].val[0] = 0; - Tuner->CH_Ctrl[4].addr[1] = 73; - Tuner->CH_Ctrl[4].bit[1] = 5; - Tuner->CH_Ctrl[4].val[1] = 1; - Tuner->CH_Ctrl[4].addr[2] = 73; - Tuner->CH_Ctrl[4].bit[2] = 6; - Tuner->CH_Ctrl[4].val[2] = 0; - - Tuner->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ; - Tuner->CH_Ctrl[5].size = 4 ; - Tuner->CH_Ctrl[5].addr[0] = 70; - Tuner->CH_Ctrl[5].bit[0] = 0; - Tuner->CH_Ctrl[5].val[0] = 0; - Tuner->CH_Ctrl[5].addr[1] = 70; - Tuner->CH_Ctrl[5].bit[1] = 1; - Tuner->CH_Ctrl[5].val[1] = 0; - Tuner->CH_Ctrl[5].addr[2] = 70; - Tuner->CH_Ctrl[5].bit[2] = 2; - Tuner->CH_Ctrl[5].val[2] = 0; - Tuner->CH_Ctrl[5].addr[3] = 70; - Tuner->CH_Ctrl[5].bit[3] = 3; - Tuner->CH_Ctrl[5].val[3] = 0; - - Tuner->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ; - Tuner->CH_Ctrl[6].size = 1 ; - Tuner->CH_Ctrl[6].addr[0] = 70; - Tuner->CH_Ctrl[6].bit[0] = 4; - Tuner->CH_Ctrl[6].val[0] = 1; - - Tuner->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ; - Tuner->CH_Ctrl[7].size = 1 ; - Tuner->CH_Ctrl[7].addr[0] = 111; - Tuner->CH_Ctrl[7].bit[0] = 4; - Tuner->CH_Ctrl[7].val[0] = 0; - - Tuner->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ; - Tuner->CH_Ctrl[8].size = 1 ; - Tuner->CH_Ctrl[8].addr[0] = 111; - Tuner->CH_Ctrl[8].bit[0] = 7; - Tuner->CH_Ctrl[8].val[0] = 1; - - Tuner->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ; - Tuner->CH_Ctrl[9].size = 1 ; - Tuner->CH_Ctrl[9].addr[0] = 111; - Tuner->CH_Ctrl[9].bit[0] = 6; - Tuner->CH_Ctrl[9].val[0] = 1; - - Tuner->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ; - Tuner->CH_Ctrl[10].size = 1 ; - Tuner->CH_Ctrl[10].addr[0] = 111; - Tuner->CH_Ctrl[10].bit[0] = 5; - Tuner->CH_Ctrl[10].val[0] = 0; - - Tuner->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ; - Tuner->CH_Ctrl[11].size = 2 ; - Tuner->CH_Ctrl[11].addr[0] = 110; - Tuner->CH_Ctrl[11].bit[0] = 0; - Tuner->CH_Ctrl[11].val[0] = 1; - Tuner->CH_Ctrl[11].addr[1] = 110; - Tuner->CH_Ctrl[11].bit[1] = 1; - Tuner->CH_Ctrl[11].val[1] = 0; - - Tuner->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ; - Tuner->CH_Ctrl[12].size = 3 ; - Tuner->CH_Ctrl[12].addr[0] = 69; - Tuner->CH_Ctrl[12].bit[0] = 2; - Tuner->CH_Ctrl[12].val[0] = 0; - Tuner->CH_Ctrl[12].addr[1] = 69; - Tuner->CH_Ctrl[12].bit[1] = 3; - Tuner->CH_Ctrl[12].val[1] = 0; - Tuner->CH_Ctrl[12].addr[2] = 69; - Tuner->CH_Ctrl[12].bit[2] = 4; - Tuner->CH_Ctrl[12].val[2] = 0; - - Tuner->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ; - Tuner->CH_Ctrl[13].size = 6 ; - Tuner->CH_Ctrl[13].addr[0] = 110; - Tuner->CH_Ctrl[13].bit[0] = 2; - Tuner->CH_Ctrl[13].val[0] = 0; - Tuner->CH_Ctrl[13].addr[1] = 110; - Tuner->CH_Ctrl[13].bit[1] = 3; - Tuner->CH_Ctrl[13].val[1] = 0; - Tuner->CH_Ctrl[13].addr[2] = 110; - Tuner->CH_Ctrl[13].bit[2] = 4; - Tuner->CH_Ctrl[13].val[2] = 0; - Tuner->CH_Ctrl[13].addr[3] = 110; - Tuner->CH_Ctrl[13].bit[3] = 5; - Tuner->CH_Ctrl[13].val[3] = 0; - Tuner->CH_Ctrl[13].addr[4] = 110; - Tuner->CH_Ctrl[13].bit[4] = 6; - Tuner->CH_Ctrl[13].val[4] = 0; - Tuner->CH_Ctrl[13].addr[5] = 110; - Tuner->CH_Ctrl[13].bit[5] = 7; - Tuner->CH_Ctrl[13].val[5] = 1; - - Tuner->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ; - Tuner->CH_Ctrl[14].size = 7 ; - Tuner->CH_Ctrl[14].addr[0] = 14; - Tuner->CH_Ctrl[14].bit[0] = 0; - Tuner->CH_Ctrl[14].val[0] = 0; - Tuner->CH_Ctrl[14].addr[1] = 14; - Tuner->CH_Ctrl[14].bit[1] = 1; - Tuner->CH_Ctrl[14].val[1] = 0; - Tuner->CH_Ctrl[14].addr[2] = 14; - Tuner->CH_Ctrl[14].bit[2] = 2; - Tuner->CH_Ctrl[14].val[2] = 0; - Tuner->CH_Ctrl[14].addr[3] = 14; - Tuner->CH_Ctrl[14].bit[3] = 3; - Tuner->CH_Ctrl[14].val[3] = 0; - Tuner->CH_Ctrl[14].addr[4] = 14; - Tuner->CH_Ctrl[14].bit[4] = 4; - Tuner->CH_Ctrl[14].val[4] = 0; - Tuner->CH_Ctrl[14].addr[5] = 14; - Tuner->CH_Ctrl[14].bit[5] = 5; - Tuner->CH_Ctrl[14].val[5] = 0; - Tuner->CH_Ctrl[14].addr[6] = 14; - Tuner->CH_Ctrl[14].bit[6] = 6; - Tuner->CH_Ctrl[14].val[6] = 0; - - Tuner->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ; - Tuner->CH_Ctrl[15].size = 18 ; - Tuner->CH_Ctrl[15].addr[0] = 17; - Tuner->CH_Ctrl[15].bit[0] = 6; - Tuner->CH_Ctrl[15].val[0] = 0; - Tuner->CH_Ctrl[15].addr[1] = 17; - Tuner->CH_Ctrl[15].bit[1] = 7; - Tuner->CH_Ctrl[15].val[1] = 0; - Tuner->CH_Ctrl[15].addr[2] = 16; - Tuner->CH_Ctrl[15].bit[2] = 0; - Tuner->CH_Ctrl[15].val[2] = 0; - Tuner->CH_Ctrl[15].addr[3] = 16; - Tuner->CH_Ctrl[15].bit[3] = 1; - Tuner->CH_Ctrl[15].val[3] = 0; - Tuner->CH_Ctrl[15].addr[4] = 16; - Tuner->CH_Ctrl[15].bit[4] = 2; - Tuner->CH_Ctrl[15].val[4] = 0; - Tuner->CH_Ctrl[15].addr[5] = 16; - Tuner->CH_Ctrl[15].bit[5] = 3; - Tuner->CH_Ctrl[15].val[5] = 0; - Tuner->CH_Ctrl[15].addr[6] = 16; - Tuner->CH_Ctrl[15].bit[6] = 4; - Tuner->CH_Ctrl[15].val[6] = 0; - Tuner->CH_Ctrl[15].addr[7] = 16; - Tuner->CH_Ctrl[15].bit[7] = 5; - Tuner->CH_Ctrl[15].val[7] = 0; - Tuner->CH_Ctrl[15].addr[8] = 16; - Tuner->CH_Ctrl[15].bit[8] = 6; - Tuner->CH_Ctrl[15].val[8] = 0; - Tuner->CH_Ctrl[15].addr[9] = 16; - Tuner->CH_Ctrl[15].bit[9] = 7; - Tuner->CH_Ctrl[15].val[9] = 0; - Tuner->CH_Ctrl[15].addr[10] = 15; - Tuner->CH_Ctrl[15].bit[10] = 0; - Tuner->CH_Ctrl[15].val[10] = 0; - Tuner->CH_Ctrl[15].addr[11] = 15; - Tuner->CH_Ctrl[15].bit[11] = 1; - Tuner->CH_Ctrl[15].val[11] = 0; - Tuner->CH_Ctrl[15].addr[12] = 15; - Tuner->CH_Ctrl[15].bit[12] = 2; - Tuner->CH_Ctrl[15].val[12] = 0; - Tuner->CH_Ctrl[15].addr[13] = 15; - Tuner->CH_Ctrl[15].bit[13] = 3; - Tuner->CH_Ctrl[15].val[13] = 0; - Tuner->CH_Ctrl[15].addr[14] = 15; - Tuner->CH_Ctrl[15].bit[14] = 4; - Tuner->CH_Ctrl[15].val[14] = 0; - Tuner->CH_Ctrl[15].addr[15] = 15; - Tuner->CH_Ctrl[15].bit[15] = 5; - Tuner->CH_Ctrl[15].val[15] = 0; - Tuner->CH_Ctrl[15].addr[16] = 15; - Tuner->CH_Ctrl[15].bit[16] = 6; - Tuner->CH_Ctrl[15].val[16] = 1; - Tuner->CH_Ctrl[15].addr[17] = 15; - Tuner->CH_Ctrl[15].bit[17] = 7; - Tuner->CH_Ctrl[15].val[17] = 1; - - Tuner->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ; - Tuner->CH_Ctrl[16].size = 5 ; - Tuner->CH_Ctrl[16].addr[0] = 112; - Tuner->CH_Ctrl[16].bit[0] = 0; - Tuner->CH_Ctrl[16].val[0] = 0; - Tuner->CH_Ctrl[16].addr[1] = 112; - Tuner->CH_Ctrl[16].bit[1] = 1; - Tuner->CH_Ctrl[16].val[1] = 0; - Tuner->CH_Ctrl[16].addr[2] = 112; - Tuner->CH_Ctrl[16].bit[2] = 2; - Tuner->CH_Ctrl[16].val[2] = 0; - Tuner->CH_Ctrl[16].addr[3] = 112; - Tuner->CH_Ctrl[16].bit[3] = 3; - Tuner->CH_Ctrl[16].val[3] = 0; - Tuner->CH_Ctrl[16].addr[4] = 112; - Tuner->CH_Ctrl[16].bit[4] = 4; - Tuner->CH_Ctrl[16].val[4] = 1; - - Tuner->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ; - Tuner->CH_Ctrl[17].size = 1 ; - Tuner->CH_Ctrl[17].addr[0] = 14; - Tuner->CH_Ctrl[17].bit[0] = 7; - Tuner->CH_Ctrl[17].val[0] = 0; - - Tuner->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ; - Tuner->CH_Ctrl[18].size = 4 ; - Tuner->CH_Ctrl[18].addr[0] = 107; - Tuner->CH_Ctrl[18].bit[0] = 3; - Tuner->CH_Ctrl[18].val[0] = 0; - Tuner->CH_Ctrl[18].addr[1] = 107; - Tuner->CH_Ctrl[18].bit[1] = 4; - Tuner->CH_Ctrl[18].val[1] = 0; - Tuner->CH_Ctrl[18].addr[2] = 107; - Tuner->CH_Ctrl[18].bit[2] = 5; - Tuner->CH_Ctrl[18].val[2] = 0; - Tuner->CH_Ctrl[18].addr[3] = 107; - Tuner->CH_Ctrl[18].bit[3] = 6; - Tuner->CH_Ctrl[18].val[3] = 0; - - Tuner->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ; - Tuner->CH_Ctrl[19].size = 3 ; - Tuner->CH_Ctrl[19].addr[0] = 107; - Tuner->CH_Ctrl[19].bit[0] = 7; - Tuner->CH_Ctrl[19].val[0] = 1; - Tuner->CH_Ctrl[19].addr[1] = 106; - Tuner->CH_Ctrl[19].bit[1] = 0; - Tuner->CH_Ctrl[19].val[1] = 1; - Tuner->CH_Ctrl[19].addr[2] = 106; - Tuner->CH_Ctrl[19].bit[2] = 1; - Tuner->CH_Ctrl[19].val[2] = 1; - - Tuner->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ; - Tuner->CH_Ctrl[20].size = 11 ; - Tuner->CH_Ctrl[20].addr[0] = 109; - Tuner->CH_Ctrl[20].bit[0] = 2; - Tuner->CH_Ctrl[20].val[0] = 0; - Tuner->CH_Ctrl[20].addr[1] = 109; - Tuner->CH_Ctrl[20].bit[1] = 3; - Tuner->CH_Ctrl[20].val[1] = 0; - Tuner->CH_Ctrl[20].addr[2] = 109; - Tuner->CH_Ctrl[20].bit[2] = 4; - Tuner->CH_Ctrl[20].val[2] = 0; - Tuner->CH_Ctrl[20].addr[3] = 109; - Tuner->CH_Ctrl[20].bit[3] = 5; - Tuner->CH_Ctrl[20].val[3] = 0; - Tuner->CH_Ctrl[20].addr[4] = 109; - Tuner->CH_Ctrl[20].bit[4] = 6; - Tuner->CH_Ctrl[20].val[4] = 0; - Tuner->CH_Ctrl[20].addr[5] = 109; - Tuner->CH_Ctrl[20].bit[5] = 7; - Tuner->CH_Ctrl[20].val[5] = 0; - Tuner->CH_Ctrl[20].addr[6] = 108; - Tuner->CH_Ctrl[20].bit[6] = 0; - Tuner->CH_Ctrl[20].val[6] = 0; - Tuner->CH_Ctrl[20].addr[7] = 108; - Tuner->CH_Ctrl[20].bit[7] = 1; - Tuner->CH_Ctrl[20].val[7] = 0; - Tuner->CH_Ctrl[20].addr[8] = 108; - Tuner->CH_Ctrl[20].bit[8] = 2; - Tuner->CH_Ctrl[20].val[8] = 1; - Tuner->CH_Ctrl[20].addr[9] = 108; - Tuner->CH_Ctrl[20].bit[9] = 3; - Tuner->CH_Ctrl[20].val[9] = 1; - Tuner->CH_Ctrl[20].addr[10] = 108; - Tuner->CH_Ctrl[20].bit[10] = 4; - Tuner->CH_Ctrl[20].val[10] = 1; - - Tuner->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ; - Tuner->CH_Ctrl[21].size = 6 ; - Tuner->CH_Ctrl[21].addr[0] = 106; - Tuner->CH_Ctrl[21].bit[0] = 2; - Tuner->CH_Ctrl[21].val[0] = 0; - Tuner->CH_Ctrl[21].addr[1] = 106; - Tuner->CH_Ctrl[21].bit[1] = 3; - Tuner->CH_Ctrl[21].val[1] = 0; - Tuner->CH_Ctrl[21].addr[2] = 106; - Tuner->CH_Ctrl[21].bit[2] = 4; - Tuner->CH_Ctrl[21].val[2] = 0; - Tuner->CH_Ctrl[21].addr[3] = 106; - Tuner->CH_Ctrl[21].bit[3] = 5; - Tuner->CH_Ctrl[21].val[3] = 0; - Tuner->CH_Ctrl[21].addr[4] = 106; - Tuner->CH_Ctrl[21].bit[4] = 6; - Tuner->CH_Ctrl[21].val[4] = 0; - Tuner->CH_Ctrl[21].addr[5] = 106; - Tuner->CH_Ctrl[21].bit[5] = 7; - Tuner->CH_Ctrl[21].val[5] = 1; - - Tuner->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ; - Tuner->CH_Ctrl[22].size = 1 ; - Tuner->CH_Ctrl[22].addr[0] = 138; - Tuner->CH_Ctrl[22].bit[0] = 4; - Tuner->CH_Ctrl[22].val[0] = 1; - - Tuner->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ; - Tuner->CH_Ctrl[23].size = 1 ; - Tuner->CH_Ctrl[23].addr[0] = 17; - Tuner->CH_Ctrl[23].bit[0] = 5; - Tuner->CH_Ctrl[23].val[0] = 0; - - Tuner->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ; - Tuner->CH_Ctrl[24].size = 1 ; - Tuner->CH_Ctrl[24].addr[0] = 111; - Tuner->CH_Ctrl[24].bit[0] = 3; - Tuner->CH_Ctrl[24].val[0] = 0; - - Tuner->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ; - Tuner->CH_Ctrl[25].size = 1 ; - Tuner->CH_Ctrl[25].addr[0] = 112; - Tuner->CH_Ctrl[25].bit[0] = 7; - Tuner->CH_Ctrl[25].val[0] = 0; - - Tuner->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ; - Tuner->CH_Ctrl[26].size = 1 ; - Tuner->CH_Ctrl[26].addr[0] = 136; - Tuner->CH_Ctrl[26].bit[0] = 7; - Tuner->CH_Ctrl[26].val[0] = 0; - - Tuner->CH_Ctrl[27].Ctrl_Num = GPIO_4B ; - Tuner->CH_Ctrl[27].size = 1 ; - Tuner->CH_Ctrl[27].addr[0] = 149; - Tuner->CH_Ctrl[27].bit[0] = 7; - Tuner->CH_Ctrl[27].val[0] = 0; - - Tuner->CH_Ctrl[28].Ctrl_Num = GPIO_3B ; - Tuner->CH_Ctrl[28].size = 1 ; - Tuner->CH_Ctrl[28].addr[0] = 149; - Tuner->CH_Ctrl[28].bit[0] = 6; - Tuner->CH_Ctrl[28].val[0] = 0; - - Tuner->CH_Ctrl[29].Ctrl_Num = GPIO_4 ; - Tuner->CH_Ctrl[29].size = 1 ; - Tuner->CH_Ctrl[29].addr[0] = 149; - Tuner->CH_Ctrl[29].bit[0] = 5; - Tuner->CH_Ctrl[29].val[0] = 1; - - Tuner->CH_Ctrl[30].Ctrl_Num = GPIO_3 ; - Tuner->CH_Ctrl[30].size = 1 ; - Tuner->CH_Ctrl[30].addr[0] = 149; - Tuner->CH_Ctrl[30].bit[0] = 4; - Tuner->CH_Ctrl[30].val[0] = 1; - - Tuner->CH_Ctrl[31].Ctrl_Num = GPIO_1B ; - Tuner->CH_Ctrl[31].size = 1 ; - Tuner->CH_Ctrl[31].addr[0] = 149; - Tuner->CH_Ctrl[31].bit[0] = 3; - Tuner->CH_Ctrl[31].val[0] = 0; - - Tuner->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ; - Tuner->CH_Ctrl[32].size = 1 ; - Tuner->CH_Ctrl[32].addr[0] = 93; - Tuner->CH_Ctrl[32].bit[0] = 1; - Tuner->CH_Ctrl[32].val[0] = 0; - - Tuner->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ; - Tuner->CH_Ctrl[33].size = 1 ; - Tuner->CH_Ctrl[33].addr[0] = 93; - Tuner->CH_Ctrl[33].bit[0] = 0; - Tuner->CH_Ctrl[33].val[0] = 0; - - Tuner->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ; - Tuner->CH_Ctrl[34].size = 6 ; - Tuner->CH_Ctrl[34].addr[0] = 92; - Tuner->CH_Ctrl[34].bit[0] = 2; - Tuner->CH_Ctrl[34].val[0] = 0; - Tuner->CH_Ctrl[34].addr[1] = 92; - Tuner->CH_Ctrl[34].bit[1] = 3; - Tuner->CH_Ctrl[34].val[1] = 0; - Tuner->CH_Ctrl[34].addr[2] = 92; - Tuner->CH_Ctrl[34].bit[2] = 4; - Tuner->CH_Ctrl[34].val[2] = 0; - Tuner->CH_Ctrl[34].addr[3] = 92; - Tuner->CH_Ctrl[34].bit[3] = 5; - Tuner->CH_Ctrl[34].val[3] = 0; - Tuner->CH_Ctrl[34].addr[4] = 92; - Tuner->CH_Ctrl[34].bit[4] = 6; - Tuner->CH_Ctrl[34].val[4] = 0; - Tuner->CH_Ctrl[34].addr[5] = 92; - Tuner->CH_Ctrl[34].bit[5] = 7; - Tuner->CH_Ctrl[34].val[5] = 0; - - Tuner->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ; - Tuner->CH_Ctrl[35].size = 6 ; - Tuner->CH_Ctrl[35].addr[0] = 93; - Tuner->CH_Ctrl[35].bit[0] = 2; - Tuner->CH_Ctrl[35].val[0] = 0; - Tuner->CH_Ctrl[35].addr[1] = 93; - Tuner->CH_Ctrl[35].bit[1] = 3; - Tuner->CH_Ctrl[35].val[1] = 0; - Tuner->CH_Ctrl[35].addr[2] = 93; - Tuner->CH_Ctrl[35].bit[2] = 4; - Tuner->CH_Ctrl[35].val[2] = 0; - Tuner->CH_Ctrl[35].addr[3] = 93; - Tuner->CH_Ctrl[35].bit[3] = 5; - Tuner->CH_Ctrl[35].val[3] = 0; - Tuner->CH_Ctrl[35].addr[4] = 93; - Tuner->CH_Ctrl[35].bit[4] = 6; - Tuner->CH_Ctrl[35].val[4] = 0; - Tuner->CH_Ctrl[35].addr[5] = 93; - Tuner->CH_Ctrl[35].bit[5] = 7; - Tuner->CH_Ctrl[35].val[5] = 0; + struct mxl5005s_state *state = fe->demodulator_priv; + state->Init_Ctrl_Num = INITCTRL_NUM; + + state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; + state->Init_Ctrl[0].size = 1 ; + state->Init_Ctrl[0].addr[0] = 73; + state->Init_Ctrl[0].bit[0] = 7; + state->Init_Ctrl[0].val[0] = 0; + + state->Init_Ctrl[1].Ctrl_Num = BB_MODE ; + state->Init_Ctrl[1].size = 1 ; + state->Init_Ctrl[1].addr[0] = 53; + state->Init_Ctrl[1].bit[0] = 2; + state->Init_Ctrl[1].val[0] = 1; + + state->Init_Ctrl[2].Ctrl_Num = BB_BUF ; + state->Init_Ctrl[2].size = 2 ; + state->Init_Ctrl[2].addr[0] = 53; + state->Init_Ctrl[2].bit[0] = 1; + state->Init_Ctrl[2].val[0] = 0; + state->Init_Ctrl[2].addr[1] = 57; + state->Init_Ctrl[2].bit[1] = 0; + state->Init_Ctrl[2].val[1] = 1; + + state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ; + state->Init_Ctrl[3].size = 1 ; + state->Init_Ctrl[3].addr[0] = 53; + state->Init_Ctrl[3].bit[0] = 0; + state->Init_Ctrl[3].val[0] = 0; + + state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ; + state->Init_Ctrl[4].size = 3 ; + state->Init_Ctrl[4].addr[0] = 53; + state->Init_Ctrl[4].bit[0] = 5; + state->Init_Ctrl[4].val[0] = 0; + state->Init_Ctrl[4].addr[1] = 53; + state->Init_Ctrl[4].bit[1] = 6; + state->Init_Ctrl[4].val[1] = 0; + state->Init_Ctrl[4].addr[2] = 53; + state->Init_Ctrl[4].bit[2] = 7; + state->Init_Ctrl[4].val[2] = 1; + + state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ; + state->Init_Ctrl[5].size = 1 ; + state->Init_Ctrl[5].addr[0] = 59; + state->Init_Ctrl[5].bit[0] = 0; + state->Init_Ctrl[5].val[0] = 0; + + state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ; + state->Init_Ctrl[6].size = 2 ; + state->Init_Ctrl[6].addr[0] = 53; + state->Init_Ctrl[6].bit[0] = 3; + state->Init_Ctrl[6].val[0] = 0; + state->Init_Ctrl[6].addr[1] = 53; + state->Init_Ctrl[6].bit[1] = 4; + state->Init_Ctrl[6].val[1] = 1; + + state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ; + state->Init_Ctrl[7].size = 4 ; + state->Init_Ctrl[7].addr[0] = 22; + state->Init_Ctrl[7].bit[0] = 4; + state->Init_Ctrl[7].val[0] = 0; + state->Init_Ctrl[7].addr[1] = 22; + state->Init_Ctrl[7].bit[1] = 5; + state->Init_Ctrl[7].val[1] = 1; + state->Init_Ctrl[7].addr[2] = 22; + state->Init_Ctrl[7].bit[2] = 6; + state->Init_Ctrl[7].val[2] = 1; + state->Init_Ctrl[7].addr[3] = 22; + state->Init_Ctrl[7].bit[3] = 7; + state->Init_Ctrl[7].val[3] = 0; + + state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ; + state->Init_Ctrl[8].size = 1 ; + state->Init_Ctrl[8].addr[0] = 22; + state->Init_Ctrl[8].bit[0] = 2; + state->Init_Ctrl[8].val[0] = 0; + + state->Init_Ctrl[9].Ctrl_Num = AGC_IF ; + state->Init_Ctrl[9].size = 4 ; + state->Init_Ctrl[9].addr[0] = 76; + state->Init_Ctrl[9].bit[0] = 0; + state->Init_Ctrl[9].val[0] = 1; + state->Init_Ctrl[9].addr[1] = 76; + state->Init_Ctrl[9].bit[1] = 1; + state->Init_Ctrl[9].val[1] = 1; + state->Init_Ctrl[9].addr[2] = 76; + state->Init_Ctrl[9].bit[2] = 2; + state->Init_Ctrl[9].val[2] = 0; + state->Init_Ctrl[9].addr[3] = 76; + state->Init_Ctrl[9].bit[3] = 3; + state->Init_Ctrl[9].val[3] = 1; + + state->Init_Ctrl[10].Ctrl_Num = AGC_RF ; + state->Init_Ctrl[10].size = 4 ; + state->Init_Ctrl[10].addr[0] = 76; + state->Init_Ctrl[10].bit[0] = 4; + state->Init_Ctrl[10].val[0] = 1; + state->Init_Ctrl[10].addr[1] = 76; + state->Init_Ctrl[10].bit[1] = 5; + state->Init_Ctrl[10].val[1] = 1; + state->Init_Ctrl[10].addr[2] = 76; + state->Init_Ctrl[10].bit[2] = 6; + state->Init_Ctrl[10].val[2] = 0; + state->Init_Ctrl[10].addr[3] = 76; + state->Init_Ctrl[10].bit[3] = 7; + state->Init_Ctrl[10].val[3] = 1; + + state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ; + state->Init_Ctrl[11].size = 5 ; + state->Init_Ctrl[11].addr[0] = 43; + state->Init_Ctrl[11].bit[0] = 3; + state->Init_Ctrl[11].val[0] = 0; + state->Init_Ctrl[11].addr[1] = 43; + state->Init_Ctrl[11].bit[1] = 4; + state->Init_Ctrl[11].val[1] = 0; + state->Init_Ctrl[11].addr[2] = 43; + state->Init_Ctrl[11].bit[2] = 5; + state->Init_Ctrl[11].val[2] = 0; + state->Init_Ctrl[11].addr[3] = 43; + state->Init_Ctrl[11].bit[3] = 6; + state->Init_Ctrl[11].val[3] = 1; + state->Init_Ctrl[11].addr[4] = 43; + state->Init_Ctrl[11].bit[4] = 7; + state->Init_Ctrl[11].val[4] = 0; + + state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ; + state->Init_Ctrl[12].size = 6 ; + state->Init_Ctrl[12].addr[0] = 44; + state->Init_Ctrl[12].bit[0] = 2; + state->Init_Ctrl[12].val[0] = 0; + state->Init_Ctrl[12].addr[1] = 44; + state->Init_Ctrl[12].bit[1] = 3; + state->Init_Ctrl[12].val[1] = 0; + state->Init_Ctrl[12].addr[2] = 44; + state->Init_Ctrl[12].bit[2] = 4; + state->Init_Ctrl[12].val[2] = 0; + state->Init_Ctrl[12].addr[3] = 44; + state->Init_Ctrl[12].bit[3] = 5; + state->Init_Ctrl[12].val[3] = 1; + state->Init_Ctrl[12].addr[4] = 44; + state->Init_Ctrl[12].bit[4] = 6; + state->Init_Ctrl[12].val[4] = 0; + state->Init_Ctrl[12].addr[5] = 44; + state->Init_Ctrl[12].bit[5] = 7; + state->Init_Ctrl[12].val[5] = 0; + + state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ; + state->Init_Ctrl[13].size = 7 ; + state->Init_Ctrl[13].addr[0] = 11; + state->Init_Ctrl[13].bit[0] = 0; + state->Init_Ctrl[13].val[0] = 1; + state->Init_Ctrl[13].addr[1] = 11; + state->Init_Ctrl[13].bit[1] = 1; + state->Init_Ctrl[13].val[1] = 0; + state->Init_Ctrl[13].addr[2] = 11; + state->Init_Ctrl[13].bit[2] = 2; + state->Init_Ctrl[13].val[2] = 0; + state->Init_Ctrl[13].addr[3] = 11; + state->Init_Ctrl[13].bit[3] = 3; + state->Init_Ctrl[13].val[3] = 1; + state->Init_Ctrl[13].addr[4] = 11; + state->Init_Ctrl[13].bit[4] = 4; + state->Init_Ctrl[13].val[4] = 1; + state->Init_Ctrl[13].addr[5] = 11; + state->Init_Ctrl[13].bit[5] = 5; + state->Init_Ctrl[13].val[5] = 0; + state->Init_Ctrl[13].addr[6] = 11; + state->Init_Ctrl[13].bit[6] = 6; + state->Init_Ctrl[13].val[6] = 0; + + state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ; + state->Init_Ctrl[14].size = 16 ; + state->Init_Ctrl[14].addr[0] = 13; + state->Init_Ctrl[14].bit[0] = 0; + state->Init_Ctrl[14].val[0] = 0; + state->Init_Ctrl[14].addr[1] = 13; + state->Init_Ctrl[14].bit[1] = 1; + state->Init_Ctrl[14].val[1] = 0; + state->Init_Ctrl[14].addr[2] = 13; + state->Init_Ctrl[14].bit[2] = 2; + state->Init_Ctrl[14].val[2] = 0; + state->Init_Ctrl[14].addr[3] = 13; + state->Init_Ctrl[14].bit[3] = 3; + state->Init_Ctrl[14].val[3] = 0; + state->Init_Ctrl[14].addr[4] = 13; + state->Init_Ctrl[14].bit[4] = 4; + state->Init_Ctrl[14].val[4] = 0; + state->Init_Ctrl[14].addr[5] = 13; + state->Init_Ctrl[14].bit[5] = 5; + state->Init_Ctrl[14].val[5] = 0; + state->Init_Ctrl[14].addr[6] = 13; + state->Init_Ctrl[14].bit[6] = 6; + state->Init_Ctrl[14].val[6] = 0; + state->Init_Ctrl[14].addr[7] = 13; + state->Init_Ctrl[14].bit[7] = 7; + state->Init_Ctrl[14].val[7] = 0; + state->Init_Ctrl[14].addr[8] = 12; + state->Init_Ctrl[14].bit[8] = 0; + state->Init_Ctrl[14].val[8] = 0; + state->Init_Ctrl[14].addr[9] = 12; + state->Init_Ctrl[14].bit[9] = 1; + state->Init_Ctrl[14].val[9] = 0; + state->Init_Ctrl[14].addr[10] = 12; + state->Init_Ctrl[14].bit[10] = 2; + state->Init_Ctrl[14].val[10] = 0; + state->Init_Ctrl[14].addr[11] = 12; + state->Init_Ctrl[14].bit[11] = 3; + state->Init_Ctrl[14].val[11] = 0; + state->Init_Ctrl[14].addr[12] = 12; + state->Init_Ctrl[14].bit[12] = 4; + state->Init_Ctrl[14].val[12] = 0; + state->Init_Ctrl[14].addr[13] = 12; + state->Init_Ctrl[14].bit[13] = 5; + state->Init_Ctrl[14].val[13] = 1; + state->Init_Ctrl[14].addr[14] = 12; + state->Init_Ctrl[14].bit[14] = 6; + state->Init_Ctrl[14].val[14] = 1; + state->Init_Ctrl[14].addr[15] = 12; + state->Init_Ctrl[14].bit[15] = 7; + state->Init_Ctrl[14].val[15] = 0; + + state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ; + state->Init_Ctrl[15].size = 3 ; + state->Init_Ctrl[15].addr[0] = 147; + state->Init_Ctrl[15].bit[0] = 2; + state->Init_Ctrl[15].val[0] = 0; + state->Init_Ctrl[15].addr[1] = 147; + state->Init_Ctrl[15].bit[1] = 3; + state->Init_Ctrl[15].val[1] = 1; + state->Init_Ctrl[15].addr[2] = 147; + state->Init_Ctrl[15].bit[2] = 4; + state->Init_Ctrl[15].val[2] = 1; + + state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ; + state->Init_Ctrl[16].size = 2 ; + state->Init_Ctrl[16].addr[0] = 147; + state->Init_Ctrl[16].bit[0] = 0; + state->Init_Ctrl[16].val[0] = 0; + state->Init_Ctrl[16].addr[1] = 147; + state->Init_Ctrl[16].bit[1] = 1; + state->Init_Ctrl[16].val[1] = 1; + + state->Init_Ctrl[17].Ctrl_Num = EN_AAF ; + state->Init_Ctrl[17].size = 1 ; + state->Init_Ctrl[17].addr[0] = 147; + state->Init_Ctrl[17].bit[0] = 7; + state->Init_Ctrl[17].val[0] = 0; + + state->Init_Ctrl[18].Ctrl_Num = EN_3P ; + state->Init_Ctrl[18].size = 1 ; + state->Init_Ctrl[18].addr[0] = 147; + state->Init_Ctrl[18].bit[0] = 6; + state->Init_Ctrl[18].val[0] = 0; + + state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ; + state->Init_Ctrl[19].size = 1 ; + state->Init_Ctrl[19].addr[0] = 156; + state->Init_Ctrl[19].bit[0] = 0; + state->Init_Ctrl[19].val[0] = 0; + + state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ; + state->Init_Ctrl[20].size = 1 ; + state->Init_Ctrl[20].addr[0] = 147; + state->Init_Ctrl[20].bit[0] = 5; + state->Init_Ctrl[20].val[0] = 0; + + state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ; + state->Init_Ctrl[21].size = 1 ; + state->Init_Ctrl[21].addr[0] = 137; + state->Init_Ctrl[21].bit[0] = 4; + state->Init_Ctrl[21].val[0] = 0; + + state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ; + state->Init_Ctrl[22].size = 1 ; + state->Init_Ctrl[22].addr[0] = 137; + state->Init_Ctrl[22].bit[0] = 7; + state->Init_Ctrl[22].val[0] = 0; + + state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ; + state->Init_Ctrl[23].size = 1 ; + state->Init_Ctrl[23].addr[0] = 91; + state->Init_Ctrl[23].bit[0] = 5; + state->Init_Ctrl[23].val[0] = 1; + + state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ; + state->Init_Ctrl[24].size = 1 ; + state->Init_Ctrl[24].addr[0] = 43; + state->Init_Ctrl[24].bit[0] = 0; + state->Init_Ctrl[24].val[0] = 1; + + state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ; + state->Init_Ctrl[25].size = 2 ; + state->Init_Ctrl[25].addr[0] = 22; + state->Init_Ctrl[25].bit[0] = 0; + state->Init_Ctrl[25].val[0] = 1; + state->Init_Ctrl[25].addr[1] = 22; + state->Init_Ctrl[25].bit[1] = 1; + state->Init_Ctrl[25].val[1] = 1; + + state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ; + state->Init_Ctrl[26].size = 1 ; + state->Init_Ctrl[26].addr[0] = 134; + state->Init_Ctrl[26].bit[0] = 2; + state->Init_Ctrl[26].val[0] = 0; + + state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ; + state->Init_Ctrl[27].size = 1 ; + state->Init_Ctrl[27].addr[0] = 137; + state->Init_Ctrl[27].bit[0] = 3; + state->Init_Ctrl[27].val[0] = 0; + + state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ; + state->Init_Ctrl[28].size = 1 ; + state->Init_Ctrl[28].addr[0] = 77; + state->Init_Ctrl[28].bit[0] = 7; + state->Init_Ctrl[28].val[0] = 0; + + state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ; + state->Init_Ctrl[29].size = 1 ; + state->Init_Ctrl[29].addr[0] = 166; + state->Init_Ctrl[29].bit[0] = 7; + state->Init_Ctrl[29].val[0] = 1; + + state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ; + state->Init_Ctrl[30].size = 3 ; + state->Init_Ctrl[30].addr[0] = 166; + state->Init_Ctrl[30].bit[0] = 0; + state->Init_Ctrl[30].val[0] = 0; + state->Init_Ctrl[30].addr[1] = 166; + state->Init_Ctrl[30].bit[1] = 1; + state->Init_Ctrl[30].val[1] = 1; + state->Init_Ctrl[30].addr[2] = 166; + state->Init_Ctrl[30].bit[2] = 2; + state->Init_Ctrl[30].val[2] = 1; + + state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ; + state->Init_Ctrl[31].size = 3 ; + state->Init_Ctrl[31].addr[0] = 166; + state->Init_Ctrl[31].bit[0] = 3; + state->Init_Ctrl[31].val[0] = 1; + state->Init_Ctrl[31].addr[1] = 166; + state->Init_Ctrl[31].bit[1] = 4; + state->Init_Ctrl[31].val[1] = 0; + state->Init_Ctrl[31].addr[2] = 166; + state->Init_Ctrl[31].bit[2] = 5; + state->Init_Ctrl[31].val[2] = 1; + + state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ; + state->Init_Ctrl[32].size = 3 ; + state->Init_Ctrl[32].addr[0] = 167; + state->Init_Ctrl[32].bit[0] = 0; + state->Init_Ctrl[32].val[0] = 1; + state->Init_Ctrl[32].addr[1] = 167; + state->Init_Ctrl[32].bit[1] = 1; + state->Init_Ctrl[32].val[1] = 1; + state->Init_Ctrl[32].addr[2] = 167; + state->Init_Ctrl[32].bit[2] = 2; + state->Init_Ctrl[32].val[2] = 0; + + state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ; + state->Init_Ctrl[33].size = 4 ; + state->Init_Ctrl[33].addr[0] = 168; + state->Init_Ctrl[33].bit[0] = 0; + state->Init_Ctrl[33].val[0] = 0; + state->Init_Ctrl[33].addr[1] = 168; + state->Init_Ctrl[33].bit[1] = 1; + state->Init_Ctrl[33].val[1] = 1; + state->Init_Ctrl[33].addr[2] = 168; + state->Init_Ctrl[33].bit[2] = 2; + state->Init_Ctrl[33].val[2] = 0; + state->Init_Ctrl[33].addr[3] = 168; + state->Init_Ctrl[33].bit[3] = 3; + state->Init_Ctrl[33].val[3] = 0; + + state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ; + state->Init_Ctrl[34].size = 4 ; + state->Init_Ctrl[34].addr[0] = 168; + state->Init_Ctrl[34].bit[0] = 4; + state->Init_Ctrl[34].val[0] = 1; + state->Init_Ctrl[34].addr[1] = 168; + state->Init_Ctrl[34].bit[1] = 5; + state->Init_Ctrl[34].val[1] = 1; + state->Init_Ctrl[34].addr[2] = 168; + state->Init_Ctrl[34].bit[2] = 6; + state->Init_Ctrl[34].val[2] = 1; + state->Init_Ctrl[34].addr[3] = 168; + state->Init_Ctrl[34].bit[3] = 7; + state->Init_Ctrl[34].val[3] = 1; + + state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ; + state->Init_Ctrl[35].size = 1 ; + state->Init_Ctrl[35].addr[0] = 135; + state->Init_Ctrl[35].bit[0] = 0; + state->Init_Ctrl[35].val[0] = 0; + + state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ; + state->Init_Ctrl[36].size = 1 ; + state->Init_Ctrl[36].addr[0] = 56; + state->Init_Ctrl[36].bit[0] = 3; + state->Init_Ctrl[36].val[0] = 0; + + state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ; + state->Init_Ctrl[37].size = 7 ; + state->Init_Ctrl[37].addr[0] = 59; + state->Init_Ctrl[37].bit[0] = 1; + state->Init_Ctrl[37].val[0] = 0; + state->Init_Ctrl[37].addr[1] = 59; + state->Init_Ctrl[37].bit[1] = 2; + state->Init_Ctrl[37].val[1] = 0; + state->Init_Ctrl[37].addr[2] = 59; + state->Init_Ctrl[37].bit[2] = 3; + state->Init_Ctrl[37].val[2] = 0; + state->Init_Ctrl[37].addr[3] = 59; + state->Init_Ctrl[37].bit[3] = 4; + state->Init_Ctrl[37].val[3] = 0; + state->Init_Ctrl[37].addr[4] = 59; + state->Init_Ctrl[37].bit[4] = 5; + state->Init_Ctrl[37].val[4] = 0; + state->Init_Ctrl[37].addr[5] = 59; + state->Init_Ctrl[37].bit[5] = 6; + state->Init_Ctrl[37].val[5] = 0; + state->Init_Ctrl[37].addr[6] = 59; + state->Init_Ctrl[37].bit[6] = 7; + state->Init_Ctrl[37].val[6] = 0; + + state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ; + state->Init_Ctrl[38].size = 6 ; + state->Init_Ctrl[38].addr[0] = 32; + state->Init_Ctrl[38].bit[0] = 2; + state->Init_Ctrl[38].val[0] = 0; + state->Init_Ctrl[38].addr[1] = 32; + state->Init_Ctrl[38].bit[1] = 3; + state->Init_Ctrl[38].val[1] = 0; + state->Init_Ctrl[38].addr[2] = 32; + state->Init_Ctrl[38].bit[2] = 4; + state->Init_Ctrl[38].val[2] = 0; + state->Init_Ctrl[38].addr[3] = 32; + state->Init_Ctrl[38].bit[3] = 5; + state->Init_Ctrl[38].val[3] = 0; + state->Init_Ctrl[38].addr[4] = 32; + state->Init_Ctrl[38].bit[4] = 6; + state->Init_Ctrl[38].val[4] = 1; + state->Init_Ctrl[38].addr[5] = 32; + state->Init_Ctrl[38].bit[5] = 7; + state->Init_Ctrl[38].val[5] = 0; + + state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ; + state->Init_Ctrl[39].size = 1 ; + state->Init_Ctrl[39].addr[0] = 25; + state->Init_Ctrl[39].bit[0] = 3; + state->Init_Ctrl[39].val[0] = 1; + + + state->CH_Ctrl_Num = CHCTRL_NUM ; + + state->CH_Ctrl[0].Ctrl_Num = DN_POLY ; + state->CH_Ctrl[0].size = 2 ; + state->CH_Ctrl[0].addr[0] = 68; + state->CH_Ctrl[0].bit[0] = 6; + state->CH_Ctrl[0].val[0] = 1; + state->CH_Ctrl[0].addr[1] = 68; + state->CH_Ctrl[0].bit[1] = 7; + state->CH_Ctrl[0].val[1] = 1; + + state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ; + state->CH_Ctrl[1].size = 2 ; + state->CH_Ctrl[1].addr[0] = 70; + state->CH_Ctrl[1].bit[0] = 6; + state->CH_Ctrl[1].val[0] = 1; + state->CH_Ctrl[1].addr[1] = 70; + state->CH_Ctrl[1].bit[1] = 7; + state->CH_Ctrl[1].val[1] = 0; + + state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ; + state->CH_Ctrl[2].size = 9 ; + state->CH_Ctrl[2].addr[0] = 69; + state->CH_Ctrl[2].bit[0] = 5; + state->CH_Ctrl[2].val[0] = 0; + state->CH_Ctrl[2].addr[1] = 69; + state->CH_Ctrl[2].bit[1] = 6; + state->CH_Ctrl[2].val[1] = 0; + state->CH_Ctrl[2].addr[2] = 69; + state->CH_Ctrl[2].bit[2] = 7; + state->CH_Ctrl[2].val[2] = 0; + state->CH_Ctrl[2].addr[3] = 68; + state->CH_Ctrl[2].bit[3] = 0; + state->CH_Ctrl[2].val[3] = 0; + state->CH_Ctrl[2].addr[4] = 68; + state->CH_Ctrl[2].bit[4] = 1; + state->CH_Ctrl[2].val[4] = 0; + state->CH_Ctrl[2].addr[5] = 68; + state->CH_Ctrl[2].bit[5] = 2; + state->CH_Ctrl[2].val[5] = 0; + state->CH_Ctrl[2].addr[6] = 68; + state->CH_Ctrl[2].bit[6] = 3; + state->CH_Ctrl[2].val[6] = 0; + state->CH_Ctrl[2].addr[7] = 68; + state->CH_Ctrl[2].bit[7] = 4; + state->CH_Ctrl[2].val[7] = 0; + state->CH_Ctrl[2].addr[8] = 68; + state->CH_Ctrl[2].bit[8] = 5; + state->CH_Ctrl[2].val[8] = 0; + + state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ; + state->CH_Ctrl[3].size = 1 ; + state->CH_Ctrl[3].addr[0] = 70; + state->CH_Ctrl[3].bit[0] = 5; + state->CH_Ctrl[3].val[0] = 0; + + state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ; + state->CH_Ctrl[4].size = 3 ; + state->CH_Ctrl[4].addr[0] = 73; + state->CH_Ctrl[4].bit[0] = 4; + state->CH_Ctrl[4].val[0] = 0; + state->CH_Ctrl[4].addr[1] = 73; + state->CH_Ctrl[4].bit[1] = 5; + state->CH_Ctrl[4].val[1] = 1; + state->CH_Ctrl[4].addr[2] = 73; + state->CH_Ctrl[4].bit[2] = 6; + state->CH_Ctrl[4].val[2] = 0; + + state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ; + state->CH_Ctrl[5].size = 4 ; + state->CH_Ctrl[5].addr[0] = 70; + state->CH_Ctrl[5].bit[0] = 0; + state->CH_Ctrl[5].val[0] = 0; + state->CH_Ctrl[5].addr[1] = 70; + state->CH_Ctrl[5].bit[1] = 1; + state->CH_Ctrl[5].val[1] = 0; + state->CH_Ctrl[5].addr[2] = 70; + state->CH_Ctrl[5].bit[2] = 2; + state->CH_Ctrl[5].val[2] = 0; + state->CH_Ctrl[5].addr[3] = 70; + state->CH_Ctrl[5].bit[3] = 3; + state->CH_Ctrl[5].val[3] = 0; + + state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ; + state->CH_Ctrl[6].size = 1 ; + state->CH_Ctrl[6].addr[0] = 70; + state->CH_Ctrl[6].bit[0] = 4; + state->CH_Ctrl[6].val[0] = 1; + + state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ; + state->CH_Ctrl[7].size = 1 ; + state->CH_Ctrl[7].addr[0] = 111; + state->CH_Ctrl[7].bit[0] = 4; + state->CH_Ctrl[7].val[0] = 0; + + state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ; + state->CH_Ctrl[8].size = 1 ; + state->CH_Ctrl[8].addr[0] = 111; + state->CH_Ctrl[8].bit[0] = 7; + state->CH_Ctrl[8].val[0] = 1; + + state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ; + state->CH_Ctrl[9].size = 1 ; + state->CH_Ctrl[9].addr[0] = 111; + state->CH_Ctrl[9].bit[0] = 6; + state->CH_Ctrl[9].val[0] = 1; + + state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ; + state->CH_Ctrl[10].size = 1 ; + state->CH_Ctrl[10].addr[0] = 111; + state->CH_Ctrl[10].bit[0] = 5; + state->CH_Ctrl[10].val[0] = 0; + + state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ; + state->CH_Ctrl[11].size = 2 ; + state->CH_Ctrl[11].addr[0] = 110; + state->CH_Ctrl[11].bit[0] = 0; + state->CH_Ctrl[11].val[0] = 1; + state->CH_Ctrl[11].addr[1] = 110; + state->CH_Ctrl[11].bit[1] = 1; + state->CH_Ctrl[11].val[1] = 0; + + state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ; + state->CH_Ctrl[12].size = 3 ; + state->CH_Ctrl[12].addr[0] = 69; + state->CH_Ctrl[12].bit[0] = 2; + state->CH_Ctrl[12].val[0] = 0; + state->CH_Ctrl[12].addr[1] = 69; + state->CH_Ctrl[12].bit[1] = 3; + state->CH_Ctrl[12].val[1] = 0; + state->CH_Ctrl[12].addr[2] = 69; + state->CH_Ctrl[12].bit[2] = 4; + state->CH_Ctrl[12].val[2] = 0; + + state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ; + state->CH_Ctrl[13].size = 6 ; + state->CH_Ctrl[13].addr[0] = 110; + state->CH_Ctrl[13].bit[0] = 2; + state->CH_Ctrl[13].val[0] = 0; + state->CH_Ctrl[13].addr[1] = 110; + state->CH_Ctrl[13].bit[1] = 3; + state->CH_Ctrl[13].val[1] = 0; + state->CH_Ctrl[13].addr[2] = 110; + state->CH_Ctrl[13].bit[2] = 4; + state->CH_Ctrl[13].val[2] = 0; + state->CH_Ctrl[13].addr[3] = 110; + state->CH_Ctrl[13].bit[3] = 5; + state->CH_Ctrl[13].val[3] = 0; + state->CH_Ctrl[13].addr[4] = 110; + state->CH_Ctrl[13].bit[4] = 6; + state->CH_Ctrl[13].val[4] = 0; + state->CH_Ctrl[13].addr[5] = 110; + state->CH_Ctrl[13].bit[5] = 7; + state->CH_Ctrl[13].val[5] = 1; + + state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ; + state->CH_Ctrl[14].size = 7 ; + state->CH_Ctrl[14].addr[0] = 14; + state->CH_Ctrl[14].bit[0] = 0; + state->CH_Ctrl[14].val[0] = 0; + state->CH_Ctrl[14].addr[1] = 14; + state->CH_Ctrl[14].bit[1] = 1; + state->CH_Ctrl[14].val[1] = 0; + state->CH_Ctrl[14].addr[2] = 14; + state->CH_Ctrl[14].bit[2] = 2; + state->CH_Ctrl[14].val[2] = 0; + state->CH_Ctrl[14].addr[3] = 14; + state->CH_Ctrl[14].bit[3] = 3; + state->CH_Ctrl[14].val[3] = 0; + state->CH_Ctrl[14].addr[4] = 14; + state->CH_Ctrl[14].bit[4] = 4; + state->CH_Ctrl[14].val[4] = 0; + state->CH_Ctrl[14].addr[5] = 14; + state->CH_Ctrl[14].bit[5] = 5; + state->CH_Ctrl[14].val[5] = 0; + state->CH_Ctrl[14].addr[6] = 14; + state->CH_Ctrl[14].bit[6] = 6; + state->CH_Ctrl[14].val[6] = 0; + + state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ; + state->CH_Ctrl[15].size = 18 ; + state->CH_Ctrl[15].addr[0] = 17; + state->CH_Ctrl[15].bit[0] = 6; + state->CH_Ctrl[15].val[0] = 0; + state->CH_Ctrl[15].addr[1] = 17; + state->CH_Ctrl[15].bit[1] = 7; + state->CH_Ctrl[15].val[1] = 0; + state->CH_Ctrl[15].addr[2] = 16; + state->CH_Ctrl[15].bit[2] = 0; + state->CH_Ctrl[15].val[2] = 0; + state->CH_Ctrl[15].addr[3] = 16; + state->CH_Ctrl[15].bit[3] = 1; + state->CH_Ctrl[15].val[3] = 0; + state->CH_Ctrl[15].addr[4] = 16; + state->CH_Ctrl[15].bit[4] = 2; + state->CH_Ctrl[15].val[4] = 0; + state->CH_Ctrl[15].addr[5] = 16; + state->CH_Ctrl[15].bit[5] = 3; + state->CH_Ctrl[15].val[5] = 0; + state->CH_Ctrl[15].addr[6] = 16; + state->CH_Ctrl[15].bit[6] = 4; + state->CH_Ctrl[15].val[6] = 0; + state->CH_Ctrl[15].addr[7] = 16; + state->CH_Ctrl[15].bit[7] = 5; + state->CH_Ctrl[15].val[7] = 0; + state->CH_Ctrl[15].addr[8] = 16; + state->CH_Ctrl[15].bit[8] = 6; + state->CH_Ctrl[15].val[8] = 0; + state->CH_Ctrl[15].addr[9] = 16; + state->CH_Ctrl[15].bit[9] = 7; + state->CH_Ctrl[15].val[9] = 0; + state->CH_Ctrl[15].addr[10] = 15; + state->CH_Ctrl[15].bit[10] = 0; + state->CH_Ctrl[15].val[10] = 0; + state->CH_Ctrl[15].addr[11] = 15; + state->CH_Ctrl[15].bit[11] = 1; + state->CH_Ctrl[15].val[11] = 0; + state->CH_Ctrl[15].addr[12] = 15; + state->CH_Ctrl[15].bit[12] = 2; + state->CH_Ctrl[15].val[12] = 0; + state->CH_Ctrl[15].addr[13] = 15; + state->CH_Ctrl[15].bit[13] = 3; + state->CH_Ctrl[15].val[13] = 0; + state->CH_Ctrl[15].addr[14] = 15; + state->CH_Ctrl[15].bit[14] = 4; + state->CH_Ctrl[15].val[14] = 0; + state->CH_Ctrl[15].addr[15] = 15; + state->CH_Ctrl[15].bit[15] = 5; + state->CH_Ctrl[15].val[15] = 0; + state->CH_Ctrl[15].addr[16] = 15; + state->CH_Ctrl[15].bit[16] = 6; + state->CH_Ctrl[15].val[16] = 1; + state->CH_Ctrl[15].addr[17] = 15; + state->CH_Ctrl[15].bit[17] = 7; + state->CH_Ctrl[15].val[17] = 1; + + state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ; + state->CH_Ctrl[16].size = 5 ; + state->CH_Ctrl[16].addr[0] = 112; + state->CH_Ctrl[16].bit[0] = 0; + state->CH_Ctrl[16].val[0] = 0; + state->CH_Ctrl[16].addr[1] = 112; + state->CH_Ctrl[16].bit[1] = 1; + state->CH_Ctrl[16].val[1] = 0; + state->CH_Ctrl[16].addr[2] = 112; + state->CH_Ctrl[16].bit[2] = 2; + state->CH_Ctrl[16].val[2] = 0; + state->CH_Ctrl[16].addr[3] = 112; + state->CH_Ctrl[16].bit[3] = 3; + state->CH_Ctrl[16].val[3] = 0; + state->CH_Ctrl[16].addr[4] = 112; + state->CH_Ctrl[16].bit[4] = 4; + state->CH_Ctrl[16].val[4] = 1; + + state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ; + state->CH_Ctrl[17].size = 1 ; + state->CH_Ctrl[17].addr[0] = 14; + state->CH_Ctrl[17].bit[0] = 7; + state->CH_Ctrl[17].val[0] = 0; + + state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ; + state->CH_Ctrl[18].size = 4 ; + state->CH_Ctrl[18].addr[0] = 107; + state->CH_Ctrl[18].bit[0] = 3; + state->CH_Ctrl[18].val[0] = 0; + state->CH_Ctrl[18].addr[1] = 107; + state->CH_Ctrl[18].bit[1] = 4; + state->CH_Ctrl[18].val[1] = 0; + state->CH_Ctrl[18].addr[2] = 107; + state->CH_Ctrl[18].bit[2] = 5; + state->CH_Ctrl[18].val[2] = 0; + state->CH_Ctrl[18].addr[3] = 107; + state->CH_Ctrl[18].bit[3] = 6; + state->CH_Ctrl[18].val[3] = 0; + + state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ; + state->CH_Ctrl[19].size = 3 ; + state->CH_Ctrl[19].addr[0] = 107; + state->CH_Ctrl[19].bit[0] = 7; + state->CH_Ctrl[19].val[0] = 1; + state->CH_Ctrl[19].addr[1] = 106; + state->CH_Ctrl[19].bit[1] = 0; + state->CH_Ctrl[19].val[1] = 1; + state->CH_Ctrl[19].addr[2] = 106; + state->CH_Ctrl[19].bit[2] = 1; + state->CH_Ctrl[19].val[2] = 1; + + state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ; + state->CH_Ctrl[20].size = 11 ; + state->CH_Ctrl[20].addr[0] = 109; + state->CH_Ctrl[20].bit[0] = 2; + state->CH_Ctrl[20].val[0] = 0; + state->CH_Ctrl[20].addr[1] = 109; + state->CH_Ctrl[20].bit[1] = 3; + state->CH_Ctrl[20].val[1] = 0; + state->CH_Ctrl[20].addr[2] = 109; + state->CH_Ctrl[20].bit[2] = 4; + state->CH_Ctrl[20].val[2] = 0; + state->CH_Ctrl[20].addr[3] = 109; + state->CH_Ctrl[20].bit[3] = 5; + state->CH_Ctrl[20].val[3] = 0; + state->CH_Ctrl[20].addr[4] = 109; + state->CH_Ctrl[20].bit[4] = 6; + state->CH_Ctrl[20].val[4] = 0; + state->CH_Ctrl[20].addr[5] = 109; + state->CH_Ctrl[20].bit[5] = 7; + state->CH_Ctrl[20].val[5] = 0; + state->CH_Ctrl[20].addr[6] = 108; + state->CH_Ctrl[20].bit[6] = 0; + state->CH_Ctrl[20].val[6] = 0; + state->CH_Ctrl[20].addr[7] = 108; + state->CH_Ctrl[20].bit[7] = 1; + state->CH_Ctrl[20].val[7] = 0; + state->CH_Ctrl[20].addr[8] = 108; + state->CH_Ctrl[20].bit[8] = 2; + state->CH_Ctrl[20].val[8] = 1; + state->CH_Ctrl[20].addr[9] = 108; + state->CH_Ctrl[20].bit[9] = 3; + state->CH_Ctrl[20].val[9] = 1; + state->CH_Ctrl[20].addr[10] = 108; + state->CH_Ctrl[20].bit[10] = 4; + state->CH_Ctrl[20].val[10] = 1; + + state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ; + state->CH_Ctrl[21].size = 6 ; + state->CH_Ctrl[21].addr[0] = 106; + state->CH_Ctrl[21].bit[0] = 2; + state->CH_Ctrl[21].val[0] = 0; + state->CH_Ctrl[21].addr[1] = 106; + state->CH_Ctrl[21].bit[1] = 3; + state->CH_Ctrl[21].val[1] = 0; + state->CH_Ctrl[21].addr[2] = 106; + state->CH_Ctrl[21].bit[2] = 4; + state->CH_Ctrl[21].val[2] = 0; + state->CH_Ctrl[21].addr[3] = 106; + state->CH_Ctrl[21].bit[3] = 5; + state->CH_Ctrl[21].val[3] = 0; + state->CH_Ctrl[21].addr[4] = 106; + state->CH_Ctrl[21].bit[4] = 6; + state->CH_Ctrl[21].val[4] = 0; + state->CH_Ctrl[21].addr[5] = 106; + state->CH_Ctrl[21].bit[5] = 7; + state->CH_Ctrl[21].val[5] = 1; + + state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ; + state->CH_Ctrl[22].size = 1 ; + state->CH_Ctrl[22].addr[0] = 138; + state->CH_Ctrl[22].bit[0] = 4; + state->CH_Ctrl[22].val[0] = 1; + + state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ; + state->CH_Ctrl[23].size = 1 ; + state->CH_Ctrl[23].addr[0] = 17; + state->CH_Ctrl[23].bit[0] = 5; + state->CH_Ctrl[23].val[0] = 0; + + state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ; + state->CH_Ctrl[24].size = 1 ; + state->CH_Ctrl[24].addr[0] = 111; + state->CH_Ctrl[24].bit[0] = 3; + state->CH_Ctrl[24].val[0] = 0; + + state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ; + state->CH_Ctrl[25].size = 1 ; + state->CH_Ctrl[25].addr[0] = 112; + state->CH_Ctrl[25].bit[0] = 7; + state->CH_Ctrl[25].val[0] = 0; + + state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ; + state->CH_Ctrl[26].size = 1 ; + state->CH_Ctrl[26].addr[0] = 136; + state->CH_Ctrl[26].bit[0] = 7; + state->CH_Ctrl[26].val[0] = 0; + + state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ; + state->CH_Ctrl[27].size = 1 ; + state->CH_Ctrl[27].addr[0] = 149; + state->CH_Ctrl[27].bit[0] = 7; + state->CH_Ctrl[27].val[0] = 0; + + state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ; + state->CH_Ctrl[28].size = 1 ; + state->CH_Ctrl[28].addr[0] = 149; + state->CH_Ctrl[28].bit[0] = 6; + state->CH_Ctrl[28].val[0] = 0; + + state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ; + state->CH_Ctrl[29].size = 1 ; + state->CH_Ctrl[29].addr[0] = 149; + state->CH_Ctrl[29].bit[0] = 5; + state->CH_Ctrl[29].val[0] = 1; + + state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ; + state->CH_Ctrl[30].size = 1 ; + state->CH_Ctrl[30].addr[0] = 149; + state->CH_Ctrl[30].bit[0] = 4; + state->CH_Ctrl[30].val[0] = 1; + + state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ; + state->CH_Ctrl[31].size = 1 ; + state->CH_Ctrl[31].addr[0] = 149; + state->CH_Ctrl[31].bit[0] = 3; + state->CH_Ctrl[31].val[0] = 0; + + state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ; + state->CH_Ctrl[32].size = 1 ; + state->CH_Ctrl[32].addr[0] = 93; + state->CH_Ctrl[32].bit[0] = 1; + state->CH_Ctrl[32].val[0] = 0; + + state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ; + state->CH_Ctrl[33].size = 1 ; + state->CH_Ctrl[33].addr[0] = 93; + state->CH_Ctrl[33].bit[0] = 0; + state->CH_Ctrl[33].val[0] = 0; + + state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ; + state->CH_Ctrl[34].size = 6 ; + state->CH_Ctrl[34].addr[0] = 92; + state->CH_Ctrl[34].bit[0] = 2; + state->CH_Ctrl[34].val[0] = 0; + state->CH_Ctrl[34].addr[1] = 92; + state->CH_Ctrl[34].bit[1] = 3; + state->CH_Ctrl[34].val[1] = 0; + state->CH_Ctrl[34].addr[2] = 92; + state->CH_Ctrl[34].bit[2] = 4; + state->CH_Ctrl[34].val[2] = 0; + state->CH_Ctrl[34].addr[3] = 92; + state->CH_Ctrl[34].bit[3] = 5; + state->CH_Ctrl[34].val[3] = 0; + state->CH_Ctrl[34].addr[4] = 92; + state->CH_Ctrl[34].bit[4] = 6; + state->CH_Ctrl[34].val[4] = 0; + state->CH_Ctrl[34].addr[5] = 92; + state->CH_Ctrl[34].bit[5] = 7; + state->CH_Ctrl[34].val[5] = 0; + + state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ; + state->CH_Ctrl[35].size = 6 ; + state->CH_Ctrl[35].addr[0] = 93; + state->CH_Ctrl[35].bit[0] = 2; + state->CH_Ctrl[35].val[0] = 0; + state->CH_Ctrl[35].addr[1] = 93; + state->CH_Ctrl[35].bit[1] = 3; + state->CH_Ctrl[35].val[1] = 0; + state->CH_Ctrl[35].addr[2] = 93; + state->CH_Ctrl[35].bit[2] = 4; + state->CH_Ctrl[35].val[2] = 0; + state->CH_Ctrl[35].addr[3] = 93; + state->CH_Ctrl[35].bit[3] = 5; + state->CH_Ctrl[35].val[3] = 0; + state->CH_Ctrl[35].addr[4] = 93; + state->CH_Ctrl[35].bit[4] = 6; + state->CH_Ctrl[35].val[4] = 0; + state->CH_Ctrl[35].addr[5] = 93; + state->CH_Ctrl[35].bit[5] = 7; + state->CH_Ctrl[35].val[5] = 0; #ifdef _MXL_PRODUCTION - Tuner->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ; - Tuner->CH_Ctrl[36].size = 1 ; - Tuner->CH_Ctrl[36].addr[0] = 109; - Tuner->CH_Ctrl[36].bit[0] = 1; - Tuner->CH_Ctrl[36].val[0] = 1; - - Tuner->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ; - Tuner->CH_Ctrl[37].size = 2 ; - Tuner->CH_Ctrl[37].addr[0] = 112; - Tuner->CH_Ctrl[37].bit[0] = 5; - Tuner->CH_Ctrl[37].val[0] = 0; - Tuner->CH_Ctrl[37].addr[1] = 112; - Tuner->CH_Ctrl[37].bit[1] = 6; - Tuner->CH_Ctrl[37].val[1] = 0; - - Tuner->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ; - Tuner->CH_Ctrl[38].size = 1 ; - Tuner->CH_Ctrl[38].addr[0] = 65; - Tuner->CH_Ctrl[38].bit[0] = 1; - Tuner->CH_Ctrl[38].val[0] = 0; + state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ; + state->CH_Ctrl[36].size = 1 ; + state->CH_Ctrl[36].addr[0] = 109; + state->CH_Ctrl[36].bit[0] = 1; + state->CH_Ctrl[36].val[0] = 1; + + state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ; + state->CH_Ctrl[37].size = 2 ; + state->CH_Ctrl[37].addr[0] = 112; + state->CH_Ctrl[37].bit[0] = 5; + state->CH_Ctrl[37].val[0] = 0; + state->CH_Ctrl[37].addr[1] = 112; + state->CH_Ctrl[37].bit[1] = 6; + state->CH_Ctrl[37].val[1] = 0; + + state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ; + state->CH_Ctrl[38].size = 1 ; + state->CH_Ctrl[38].addr[0] = 65; + state->CH_Ctrl[38].bit[0] = 1; + state->CH_Ctrl[38].val[0] = 0; #endif return 0 ; @@ -1832,13 +1681,14 @@ u16 MXL5005_ControlInit(Tuner_struct *Tuner) // MaxLinear source code - MXL5005_c.cpp // MXL5005.cpp : Defines the initialization routines for the DLL. // 2.6.12 - -void InitTunerControls(Tuner_struct *Tuner) +// DONE +void InitTunerControls(struct dvb_frontend *fe) { - MXL5005_RegisterInit(Tuner) ; - MXL5005_ControlInit(Tuner) ; + struct mxl5005s_state *state = fe->demodulator_priv; + MXL5005_RegisterInit(fe); + MXL5005_ControlInit(fe); #ifdef _MXL_INTERNAL - MXL5005_MXLControlInit(Tuner) ; + MXL5005_MXLControlInit(fe); #endif } @@ -1857,15 +1707,15 @@ void InitTunerControls(Tuner_struct *Tuner) // Tuner_struct: structure defined at higher level // // Mode: Tuner Mode (Analog/Digital) // // IF_Mode: IF Mode ( Zero/Low ) // -// Bandwidth: Filter Channel Bandwidth (in Hz) // +// Bandwidth: Filter Channel Bandwidth (in Hz) // // IF_out: Desired IF out Frequency (in Hz) // // Fxtal: Crystal Frerquency (in Hz) // -// TOP: 0: Dual AGC; Value: take over point // -// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // -// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // -// DIV_OUT: 0: Div-1; 1: Div-4 // -// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // -// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // +// TOP: 0: Dual AGC; Value: take over point // +// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // +// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // +// DIV_OUT: 0: Div-1; 1: Div-4 // +// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // +// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // // // // Outputs: // // Tuner // @@ -1875,49 +1725,51 @@ void InitTunerControls(Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL5005_TunerConfig(Tuner_struct *Tuner, - u8 Mode, // 0: Analog Mode ; 1: Digital Mode - u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF - u32 Bandwidth, // filter channel bandwidth (6, 7, 8) - u32 IF_out, // Desired IF Out Frequency - u32 Fxtal, // XTAL Frequency - u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 - u16 TOP, // 0: Dual AGC; Value: take over point - u16 IF_OUT_LOAD, // IF Out Load Resistor (200 / 300 Ohms) - u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out - u8 DIV_OUT, // 0: Div-1; 1: Div-4 - u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable - u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI - u8 Mod_Type, // Modulation Type; - // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable - u8 TF_Type // Tracking Filter - // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H +// DONE +u16 MXL5005_TunerConfig(struct dvb_frontend *fe, + u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ + u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ + u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ + u32 IF_out, /* Desired IF Out Frequency */ + u32 Fxtal, /* XTAL Frequency */ + u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ + u16 TOP, /* 0: Dual AGC; Value: take over point */ + u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ + u8 CLOCK_OUT, /* 0: turn off clock out; 1: turn on clock out */ + u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */ + u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ + u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ + u8 Mod_Type, /* Modulation Type; */ + /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ + u8 TF_Type /* Tracking Filter */ + /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ ) { - u16 status = 0 ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; - Tuner->Mode = Mode ; - Tuner->IF_Mode = IF_mode ; - Tuner->Chan_Bandwidth = Bandwidth ; - Tuner->IF_OUT = IF_out ; - Tuner->Fxtal = Fxtal ; - Tuner->AGC_Mode = AGC_Mode ; - Tuner->TOP = TOP ; - Tuner->IF_OUT_LOAD = IF_OUT_LOAD ; - Tuner->CLOCK_OUT = CLOCK_OUT ; - Tuner->DIV_OUT = DIV_OUT ; - Tuner->CAPSELECT = CAPSELECT ; - Tuner->EN_RSSI = EN_RSSI ; - Tuner->Mod_Type = Mod_Type ; - Tuner->TF_Type = TF_Type ; + state->Mode = Mode; + state->IF_Mode = IF_mode; + state->Chan_Bandwidth = Bandwidth; + state->IF_OUT = IF_out; + state->Fxtal = Fxtal; + state->AGC_Mode = AGC_Mode; + state->TOP = TOP; + state->IF_OUT_LOAD = IF_OUT_LOAD; + state->CLOCK_OUT = CLOCK_OUT; + state->DIV_OUT = DIV_OUT; + state->CAPSELECT = CAPSELECT; + state->EN_RSSI = EN_RSSI; + state->Mod_Type = Mod_Type; + state->TF_Type = TF_Type; /* Initialize all the controls and registers */ - InitTunerControls (Tuner) ; + InitTunerControls(fe); /* Synthesizer LO frequency calculation */ - MXL_SynthIFLO_Calc( Tuner ) ; + MXL_SynthIFLO_Calc(fe); - return status ; + return status; } /////////////////////////////////////////////////////////////////////////////// @@ -1943,22 +1795,18 @@ u16 MXL5005_TunerConfig(Tuner_struct *Tuner, // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -void MXL_SynthIFLO_Calc(Tuner_struct *Tuner) +// DONE +void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { - if (Tuner->Mode == 1) // Digital Mode - { - Tuner->IF_LO = Tuner->IF_OUT ; - } - else // Analog Mode + struct mxl5005s_state *state = fe->demodulator_priv; + if (Tuner->Mode == 1) /* Digital Mode */ + state->IF_LO = state->IF_OUT; + else /* Analog Mode */ { - if(Tuner->IF_Mode == 0) // Analog Zero IF mode - { - Tuner->IF_LO = Tuner->IF_OUT + 400000 ; - } - else // Analog Low IF mode - { - Tuner->IF_LO = Tuner->IF_OUT + Tuner->Chan_Bandwidth/2 ; - } + if(state->IF_Mode == 0) /* Analog Zero IF mode */ + state->IF_LO = state->IF_OUT + 400000; + else /* Analog Low IF mode */ + state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2; } } @@ -1986,25 +1834,22 @@ void MXL_SynthIFLO_Calc(Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) +// DONE +void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { - if (Tuner->Mode == 1) // Digital Mode - { + struct mxl5005s_state *state = fe->demodulator_priv; + + if (state->Mode == 1) /* Digital Mode */ { //remove 20.48MHz setting for 2.6.10 - Tuner->RF_LO = Tuner->RF_IN ; - Tuner->TG_LO = Tuner->RF_IN - 750000 ; //change for 2.6.6 - } - else // Analog Mode - { - if(Tuner->IF_Mode == 0) // Analog Zero IF mode - { - Tuner->RF_LO = Tuner->RF_IN - 400000 ; - Tuner->TG_LO = Tuner->RF_IN - 1750000 ; - } - else // Analog Low IF mode - { - Tuner->RF_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth/2 ; - Tuner->TG_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth + 500000 ; + state->RF_LO = state->RF_IN; + state->TG_LO = state->RF_IN - 750000; //change for 2.6.6 + } else /* Analog Mode */ { + if(state->IF_Mode == 0) /* Analog Zero IF mode */ { + state->RF_LO = state->RF_IN - 400000; + state->TG_LO = state->RF_IN - 1750000; + } else /* Analog Low IF mode */ { + state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2; + state->TG_LO = state->RF_IN - state->Chan_Bandwidth + 500000; } } } @@ -2028,16 +1873,18 @@ void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) +// DONE +u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { - u16 status = 0 ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; - status += MXL_ControlWrite(Tuner, OVERRIDE_1, 1) ; - status += MXL_ControlWrite(Tuner, OVERRIDE_2, 1) ; - status += MXL_ControlWrite(Tuner, OVERRIDE_3, 1) ; - status += MXL_ControlWrite(Tuner, OVERRIDE_4, 1) ; + status += MXL_ControlWrite(fe, OVERRIDE_1, 1); + status += MXL_ControlWrite(fe, OVERRIDE_2, 1); + status += MXL_ControlWrite(fe, OVERRIDE_3, 1); + status += MXL_ControlWrite(fe, OVERRIDE_4, 1); - return status ; + return status; } /////////////////////////////////////////////////////////////////////////////// @@ -2065,363 +1912,338 @@ u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_BlockInit( Tuner_struct *Tuner ) +// DONE +u16 MXL_BlockInit(struct dvb_frontend *fe) { - u16 status = 0 ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; - status += MXL_OverwriteICDefault(Tuner) ; + status += MXL_OverwriteICDefault(fe); - // - // Downconverter Control - // Dig Ana - status += MXL_ControlWrite(Tuner, DN_IQTN_AMP_CUT, Tuner->Mode ? 1 : 0) ; + /* Downconverter Control Dig Ana */ + status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0); - // - // Filter Control - // Dig Ana - status += MXL_ControlWrite(Tuner, BB_MODE, Tuner->Mode ? 0 : 1) ; - status += MXL_ControlWrite(Tuner, BB_BUF, Tuner->Mode ? 3 : 2) ; - status += MXL_ControlWrite(Tuner, BB_BUF_OA, Tuner->Mode ? 1 : 0) ; - - status += MXL_ControlWrite(Tuner, BB_IQSWAP, Tuner->Mode ? 0 : 1) ; - status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 0) ; - - // Initialize Low-Pass Filter - if (Tuner->Mode) { // Digital Mode - switch (Tuner->Chan_Bandwidth) { + /* Filter Control Dig Ana */ + status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1); + status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2); + status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0); + status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1); + status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 0); + + /* Initialize Low-Pass Filter */ + if (state->Mode) { /* Digital Mode */ + switch (state->Chan_Bandwidth) { case 8000000: - status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 0) ; - break ; + status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0); + break; case 7000000: - status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 2) ; - break ; + status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); + break; case 6000000: - status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 3) ; - break ; - } - } else { // Analog Mode - switch (Tuner->Chan_Bandwidth) { - case 8000000: // Low Zero - status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 0 : 3)) ; - break ; + status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); + break; + } + } else { /* Analog Mode */ + switch (state->Chan_Bandwidth) { + case 8000000: /* Low Zero */ + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 0 : 3)); + break; case 7000000: - status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 1 : 4)) ; - break ; + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 1 : 4)); + break; case 6000000: - status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 2 : 5)) ; - break ; + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 2 : 5)); + break; } } - // - // Charge Pump Control - // Dig Ana - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, Tuner->Mode ? 5 : 8) ; - status += MXL_ControlWrite(Tuner, RFSYN_EN_CHP_HIGAIN, Tuner->Mode ? 1 : 1) ; - status += MXL_ControlWrite(Tuner, EN_CHP_LIN_B, Tuner->Mode ? 0 : 0) ; + /* Charge Pump Control Dig Ana */ + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8); + status += MXL_ControlWrite(fe, RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1); + status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0); - // - // AGC TOP Control - // - if (Tuner->AGC_Mode == 0) // Dual AGC - { - status += MXL_ControlWrite(Tuner, AGC_IF, 15) ; - status += MXL_ControlWrite(Tuner, AGC_RF, 15) ; + /* AGC TOP Control */ + if (state->AGC_Mode == 0) /* Dual AGC */ { + status += MXL_ControlWrite(fe, AGC_IF, 15); + status += MXL_ControlWrite(fe, AGC_RF, 15); } - else // Single AGC Mode Dig Ana - status += MXL_ControlWrite(Tuner, AGC_RF, Tuner->Mode? 15 : 12) ; + else /* Single AGC Mode Dig Ana */ + status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); - if (Tuner->TOP == 55) // TOP == 5.5 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x0) ; + if (state->TOP == 55) /* TOP == 5.5 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x0); - if (Tuner->TOP == 72) // TOP == 7.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x1) ; + if (state->TOP == 72) /* TOP == 7.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x1); - if (Tuner->TOP == 92) // TOP == 9.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x2) ; + if (state->TOP == 92) /* TOP == 9.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x2); - if (Tuner->TOP == 110) // TOP == 11.0 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x3) ; + if (state->TOP == 110) /* TOP == 11.0 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x3); - if (Tuner->TOP == 129) // TOP == 12.9 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x4) ; + if (state->TOP == 129) /* TOP == 12.9 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x4); - if (Tuner->TOP == 147) // TOP == 14.7 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x5) ; + if (state->TOP == 147) /* TOP == 14.7 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x5); - if (Tuner->TOP == 168) // TOP == 16.8 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x6) ; + if (state->TOP == 168) /* TOP == 16.8 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x6); - if (Tuner->TOP == 194) // TOP == 19.4 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x7) ; + if (state->TOP == 194) /* TOP == 19.4 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x7); - if (Tuner->TOP == 212) // TOP == 21.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x9) ; + if (state->TOP == 212) /* TOP == 21.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x9); - if (Tuner->TOP == 232) // TOP == 23.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xA) ; + if (state->TOP == 232) /* TOP == 23.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xA); - if (Tuner->TOP == 252) // TOP == 25.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xB) ; + if (state->TOP == 252) /* TOP == 25.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xB); - if (Tuner->TOP == 271) // TOP == 27.1 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xC) ; + if (state->TOP == 271) /* TOP == 27.1 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xC); - if (Tuner->TOP == 292) // TOP == 29.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xD) ; + if (state->TOP == 292) /* TOP == 29.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xD); - if (Tuner->TOP == 317) // TOP == 31.7 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xE) ; + if (state->TOP == 317) /* TOP == 31.7 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xE); - if (Tuner->TOP == 349) // TOP == 34.9 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xF) ; + if (state->TOP == 349) /* TOP == 34.9 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xF); - // - // IF Synthesizer Control - // - status += MXL_IFSynthInit( Tuner ) ; + /* IF Synthesizer Control */ + status += MXL_IFSynthInit(fe); - // - // IF UpConverter Control - if (Tuner->IF_OUT_LOAD == 200) - { - status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 6) ; - status += MXL_ControlWrite(Tuner, I_DRIVER, 2) ; + /* IF UpConverter Control */ + if (state->IF_OUT_LOAD == 200) { + status += MXL_ControlWrite(fe, DRV_RES_SEL, 6); + status += MXL_ControlWrite(fe, I_DRIVER, 2); } - if (Tuner->IF_OUT_LOAD == 300) - { - status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 4) ; - status += MXL_ControlWrite(Tuner, I_DRIVER, 1) ; + if (state->IF_OUT_LOAD == 300) { + status += MXL_ControlWrite(fe, DRV_RES_SEL, 4); + status += MXL_ControlWrite(fe, I_DRIVER, 1); } - // - // Anti-Alias Filtering Control - // - // initialise Anti-Aliasing Filter - if (Tuner->Mode) {// Digital Mode - if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 6280000UL) { - status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; - status += MXL_ControlWrite(Tuner, EN_3P, 1) ; - status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; - status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; - } - if ((Tuner->IF_OUT == 36125000UL) || (Tuner->IF_OUT == 36150000UL)) { - status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; - status += MXL_ControlWrite(Tuner, EN_3P, 1) ; - status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; - status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ; - } - if (Tuner->IF_OUT > 36150000UL) { - status += MXL_ControlWrite(Tuner, EN_AAF, 0) ; - status += MXL_ControlWrite(Tuner, EN_3P, 1) ; - status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; - status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ; - } - } else { // Analog Mode - if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 5000000UL) + /* Anti-Alias Filtering Control + * initialise Anti-Aliasing Filter + */ + if (state->Mode) { /* Digital Mode */ + if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) { + status += MXL_ControlWrite(fe, EN_AAF, 1); + status += MXL_ControlWrite(fe, EN_3P, 1); + status += MXL_ControlWrite(fe, EN_AUX_3P, 1); + status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); + } + if ((state->IF_OUT == 36125000UL) || (state->IF_OUT == 36150000UL)) { + status += MXL_ControlWrite(fe, EN_AAF, 1); + status += MXL_ControlWrite(fe, EN_3P, 1); + status += MXL_ControlWrite(fe, EN_AUX_3P, 1); + status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1); + } + if (state->IF_OUT > 36150000UL) { + status += MXL_ControlWrite(fe, EN_AAF, 0); + status += MXL_ControlWrite(fe, EN_3P, 1); + status += MXL_ControlWrite(fe, EN_AUX_3P, 1); + status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1); + } + } else { /* Analog Mode */ + if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) { - status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; - status += MXL_ControlWrite(Tuner, EN_3P, 1) ; - status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; - status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; + status += MXL_ControlWrite(fe, EN_AAF, 1); + status += MXL_ControlWrite(fe, EN_3P, 1); + status += MXL_ControlWrite(fe, EN_AUX_3P, 1); + status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); } - if (Tuner->IF_OUT > 5000000UL) + if (state->IF_OUT > 5000000UL) { - status += MXL_ControlWrite(Tuner, EN_AAF, 0) ; - status += MXL_ControlWrite(Tuner, EN_3P, 0) ; - status += MXL_ControlWrite(Tuner, EN_AUX_3P, 0) ; - status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; + status += MXL_ControlWrite(fe, EN_AAF, 0); + status += MXL_ControlWrite(fe, EN_3P, 0); + status += MXL_ControlWrite(fe, EN_AUX_3P, 0); + status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); } } - // - // Demod Clock Out - // - if (Tuner->CLOCK_OUT) - status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 1) ; + /* Demod Clock Out */ + if (state->CLOCK_OUT) + status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 1); else - status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 0) ; + status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 0); - if (Tuner->DIV_OUT == 1) - status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 1) ; - if (Tuner->DIV_OUT == 0) - status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 0) ; + if (state->DIV_OUT == 1) + status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 1); + if (state->DIV_OUT == 0) + status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 0); - // - // Crystal Control - // - if (Tuner->CAPSELECT) - status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 1) ; + /* Crystal Control */ + if (state->CAPSELECT) + status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 1); else - status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 0) ; + status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 0); - if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) - status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 1) ; - if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL) - status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 0) ; + if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL) + status += MXL_ControlWrite(fe, IF_SEL_DBL, 1); + if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) + status += MXL_ControlWrite(fe, IF_SEL_DBL, 0); - if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL) - status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 3) ; - if (Tuner->Fxtal > 22000000UL && Tuner->Fxtal <= 32000000UL) - status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 0) ; + if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL) + status += MXL_ControlWrite(fe, RFSYN_R_DIV, 3); + if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL) + status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0); - // - // Misc Controls - // - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog LowIF mode - status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 0); + /* Misc Controls */ + if (state->Mode == 0 && Tuner->IF_Mode == 1) /* Analog LowIF mode */ + status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0); else - status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 1); + status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1); -// status += MXL_ControlRead(Tuner, IF_DIVVAL, &IF_DIVVAL_Val) ; + /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */ - // Set TG_R_DIV - status += MXL_ControlWrite(Tuner, TG_R_DIV, MXL_Ceiling(Tuner->Fxtal, 1000000)) ; + /* Set TG_R_DIV */ + status += MXL_ControlWrite(fe, TG_R_DIV, MXL_Ceiling(state->Fxtal, 1000000)); - // - // Apply Default value to BB_INITSTATE_DLPF_TUNE - // + /* Apply Default value to BB_INITSTATE_DLPF_TUNE */ - // - // RSSI Control - // - if(Tuner->EN_RSSI) + /* RSSI Control */ + if (state->EN_RSSI) { - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 3) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; - // TOP point - status += MXL_ControlWrite(Tuner, RFA_FLR, 0) ; - status += MXL_ControlWrite(Tuner, RFA_CEIL, 12) ; + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2); + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 3); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1); + + /* TOP point */ + status += MXL_ControlWrite(fe, RFA_FLR, 0); + status += MXL_ControlWrite(fe, RFA_CEIL, 12); } - // - // Modulation type bit settings - // Override the control values preset - // - if (Tuner->Mod_Type == MXL_DVBT) // DVB-T Mode + /* Modulation type bit settings + * Override the control values preset + */ + if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ { - Tuner->AGC_Mode = 1 ; // Single AGC Mode - - // Enable RSSI - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; - // TOP point - status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ; - status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ; - if (Tuner->IF_OUT <= 6280000UL) // Low IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; - else // High IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + state->AGC_Mode = 1; /* Single AGC Mode */ + + /* Enable RSSI */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1); + + /* TOP point */ + status += MXL_ControlWrite(fe, RFA_FLR, 2); + status += MXL_ControlWrite(fe, RFA_CEIL, 13); + if (state->IF_OUT <= 6280000UL) /* Low IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 0); + else /* High IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (Tuner->Mod_Type == MXL_ATSC) // ATSC Mode + if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ { - Tuner->AGC_Mode = 1 ; // Single AGC Mode - - // Enable RSSI - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 4) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; - // TOP point - status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ; - status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ; - - status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ; // Low Zero - if (Tuner->IF_OUT <= 6280000UL) // Low IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; - else // High IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + Tuner->AGC_Mode = 1; /* Single AGC Mode */ + + /* Enable RSSI */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2); + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 4); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1); + + /* TOP point */ + status += MXL_ControlWrite(fe, RFA_FLR, 2); + status += MXL_ControlWrite(fe, RFA_CEIL, 13); + status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1); + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); /* Low Zero */ + if (state->IF_OUT <= 6280000UL) /* Low IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 0); + else /* High IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (Tuner->Mod_Type == MXL_QAM) // QAM Mode + if (state->Mod_Type == MXL_QAM) /* QAM Mode */ { - Tuner->Mode = MXL_DIGITAL_MODE; - - //Tuner->AGC_Mode = 1 ; // Single AGC Mode - - // Disable RSSI //change here for v2.6.5 - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - - // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; - - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; //change here for v2.6.5 - - if (Tuner->IF_OUT <= 6280000UL) // Low IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; - else // High IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + state->Mode = MXL_DIGITAL_MODE; + + /* state->AGC_Mode = 1; */ /* Single AGC Mode */ + + /* Disable RSSI */ /* change here for v2.6.5 */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); /* change here for v2.6.5 */ + + if (state->IF_OUT <= 6280000UL) /* Low IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 0); + else /* High IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (Tuner->Mod_Type == MXL_ANALOG_CABLE) // Analog Cable Mode - { - //Tuner->Mode = MXL_DIGITAL_MODE ; - Tuner->AGC_Mode = 1 ; // Single AGC Mode - - // Disable RSSI - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - - status += MXL_ControlWrite(Tuner, AGC_IF, 1) ; //change for 2.6.3 - status += MXL_ControlWrite(Tuner, AGC_RF, 15) ; - - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + if (state->Mod_Type == MXL_ANALOG_CABLE) { + /* Analog Cable Mode */ + /* Tuner->Mode = MXL_DIGITAL_MODE; */ + + state->AGC_Mode = 1; /* Single AGC Mode */ + + /* Disable RSSI */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + status += MXL_ControlWrite(fe, AGC_IF, 1); /* change for 2.6.3 */ + status += MXL_ControlWrite(fe, AGC_RF, 15); + status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (Tuner->Mod_Type == MXL_ANALOG_OTA) //Analog OTA Terrestrial mode add for 2.6.7 - { - //Tuner->Mode = MXL_ANALOG_MODE; - - // Enable RSSI - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - - // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; - - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; - - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + if (state->Mod_Type == MXL_ANALOG_OTA) { + /* Analog OTA Terrestrial mode add for 2.6.7 */ + /* state->Mode = MXL_ANALOG_MODE; */ + + /* Enable RSSI */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); + status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - // RSSI disable - if(Tuner->EN_RSSI==0) - { - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + /* RSSI disable */ + if(state->EN_RSSI==0) { + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); } - return status ; + return status; } /////////////////////////////////////////////////////////////////////////////// @@ -2456,9 +2278,9 @@ u16 MXL_IFSynthInit(Tuner_struct * Tuner) u32 fracModVal ; Kdbl = 2 ; - if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) + if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL) Kdbl = 2 ; - if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL) + if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) Kdbl = 1 ; // @@ -2467,43 +2289,43 @@ u16 MXL_IFSynthInit(Tuner_struct * Tuner) if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF mode { if (Tuner->IF_LO == 41000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 328000000UL ; } if (Tuner->IF_LO == 47000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 376000000UL ; } if (Tuner->IF_LO == 54000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 324000000UL ; } if (Tuner->IF_LO == 60000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 39250000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 314000000UL ; } if (Tuner->IF_LO == 39650000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 317200000UL ; } if (Tuner->IF_LO == 40150000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 321200000UL ; } if (Tuner->IF_LO == 40650000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 325200000UL ; } } @@ -2511,153 +2333,153 @@ u16 MXL_IFSynthInit(Tuner_struct * Tuner) if (Tuner->Mode || (Tuner->Mode == 0 && Tuner->IF_Mode == 0)) { if (Tuner->IF_LO == 57000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 342000000UL ; } if (Tuner->IF_LO == 44000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352000000UL ; } if (Tuner->IF_LO == 43750000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 350000000UL ; } if (Tuner->IF_LO == 36650000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 366500000UL ; } if (Tuner->IF_LO == 36150000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 361500000UL ; } if (Tuner->IF_LO == 36000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 35250000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352500000UL ; } if (Tuner->IF_LO == 34750000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 347500000UL ; } if (Tuner->IF_LO == 6280000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 376800000UL ; } if (Tuner->IF_LO == 5000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 4500000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 4570000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 365600000UL ; } if (Tuner->IF_LO == 4000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 57400000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 344400000UL ; } if (Tuner->IF_LO == 44400000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 355200000UL ; } if (Tuner->IF_LO == 44150000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 353200000UL ; } if (Tuner->IF_LO == 37050000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 370500000UL ; } if (Tuner->IF_LO == 36550000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 365500000UL ; } if (Tuner->IF_LO == 36125000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 361250000UL ; } if (Tuner->IF_LO == 6000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 5400000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 324000000UL ; } if (Tuner->IF_LO == 5380000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 322800000UL ; } if (Tuner->IF_LO == 5200000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 374400000UL ; } if (Tuner->IF_LO == 4900000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352800000UL ; } if (Tuner->IF_LO == 4400000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352000000UL ; } if (Tuner->IF_LO == 4063000UL) //add for 2.6.8 { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 365670000UL ; } } // CHCAL_INT_MOD_IF // CHCAL_FRAC_MOD_IF - intModVal = Fref / (Tuner->Fxtal * Kdbl/2) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_IF, intModVal ) ; + intModVal = Fref / (state->Fxtal * Kdbl/2) ; + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal ) ; - fracModVal = (2<<15)*(Fref/1000 - (Tuner->Fxtal/1000 * Kdbl/2) * intModVal); - fracModVal = fracModVal / ((Tuner->Fxtal * Kdbl/2)/1000) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_IF, fracModVal) ; + fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) * intModVal); + fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000) ; + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal) ; return status ; } @@ -2706,7 +2528,7 @@ u32 MXL_GetXtalInt(u32 Xtal_Freq) // Functions used: // // MXL_SynthRFTGLO_Calc // // MXL5005_ControlWrite // -// MXL_GetXtalInt // +// MXL_GetXtalInt // // // // Inputs: // // Tuner : Tuner structure defined at higher level // @@ -2718,32 +2540,33 @@ u32 MXL_GetXtalInt(u32 Xtal_Freq) // 0 : Successful // // 1 : Unsuccessful // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) +u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) { + struct mxl5005s_state *state = fe->demodulator_priv; // Declare Local Variables - u16 status = 0 ; - u32 divider_val, E3, E4, E5, E5A ; - u32 Fmax, Fmin, FmaxBin, FminBin ; + u16 status = 0; + u32 divider_val, E3, E4, E5, E5A; + u32 Fmax, Fmin, FmaxBin, FminBin; u32 Kdbl_RF = 2; - u32 tg_divval ; - u32 tg_lo ; - u32 Xtal_Int ; + u32 tg_divval; + u32 tg_lo; + u32 Xtal_Int; u32 Fref_TG; u32 Fvco; // u32 temp; - Xtal_Int = MXL_GetXtalInt(Tuner->Fxtal ) ; + Xtal_Int = MXL_GetXtalInt(state->Fxtal); - Tuner->RF_IN = RF_Freq ; + state->RF_IN = RF_Freq; - MXL_SynthRFTGLO_Calc( Tuner ) ; + MXL_SynthRFTGLO_Calc(fe); - if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL) - Kdbl_RF = 2 ; - if (Tuner->Fxtal > 22000000 && Tuner->Fxtal <= 32000000) - Kdbl_RF = 1 ; + if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL) + Kdbl_RF = 2; + if (state->Fxtal > 22000000 && state->Fxtal <= 32000000) + Kdbl_RF = 1; // // Downconverter Controls @@ -2755,133 +2578,133 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // DN_EN_VHFUHFBAR // DN_GAIN_ADJUST // Change the boundary reference from RF_IN to RF_LO - if (Tuner->RF_LO < 40000000UL) { + if (state->RF_LO < 40000000UL) { return -1; } - if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) { + if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 2) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 423) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ; + status += MXL_ControlWrite(fe, DN_POLY, 2); + status += MXL_ControlWrite(fe, DN_RFGAIN, 3); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); } - if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) { + if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 222) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 3); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); } - if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) { + if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 147) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 3); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); } - if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) { + if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 9) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 3); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); } - if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) { + if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3) ; + status += MXL_ControlWrite(fe, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; } - if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 650000000UL) { + if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 1) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3) ; + status += MXL_ControlWrite(fe, DN_RFGAIN, 1) ; + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ; + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; } - if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 900000000UL) { + if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 2) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3) ; + status += MXL_ControlWrite(fe, DN_RFGAIN, 2) ; + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ; + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; } - if (Tuner->RF_LO > 900000000UL) { + if (state->RF_LO > 900000000UL) { return -1; } // DN_IQTNBUF_AMP // DN_IQTNGNBFBIAS_BST - if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 400000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 400000000UL && Tuner->RF_LO <= 450000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 450000000UL && Tuner->RF_LO <= 500000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 500000000UL && Tuner->RF_LO <= 550000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 550000000UL && Tuner->RF_LO <= 600000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 600000000UL && Tuner->RF_LO <= 650000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 700000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 700000000UL && Tuner->RF_LO <= 750000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 750000000UL && Tuner->RF_LO <= 800000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 800000000UL && Tuner->RF_LO <= 850000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ; + if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1); } - if (Tuner->RF_LO > 850000000UL && Tuner->RF_LO <= 900000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ; + if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1); } // @@ -2898,143 +2721,143 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // Set divider_val, Fmax, Fmix to use in Equations FminBin = 28000000UL ; FmaxBin = 42500000UL ; - if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); divider_val = 64 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 42500000UL ; FmaxBin = 56000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); divider_val = 64 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 56000000UL ; FmaxBin = 85000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ; divider_val = 32 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 85000000UL ; FmaxBin = 112000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ; divider_val = 32 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 112000000UL ; FmaxBin = 170000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ; divider_val = 16 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 170000000UL ; FmaxBin = 225000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ; divider_val = 16 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 225000000UL ; FmaxBin = 300000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 4) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4) ; divider_val = 8 ; Fmax = 340000000UL ; Fmin = FminBin ; } FminBin = 300000000UL ; FmaxBin = 340000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; divider_val = 8 ; Fmax = FmaxBin ; Fmin = 225000000UL ; } FminBin = 340000000UL ; FmaxBin = 450000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 2) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; divider_val = 8 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 450000000UL ; FmaxBin = 680000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 680000000UL ; FmaxBin = 900000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -3047,32 +2870,32 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // Equation E3 // RFSYN_VCO_BIAS - E3 = (((Fmax-Tuner->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, E3) ; + E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3) ; // Equation E4 // CHCAL_INT_MOD_RF - E4 = (Tuner->RF_LO*divider_val/1000)/(2*Tuner->Fxtal*Kdbl_RF/1000) ; - MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, E4) ; + E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000) ; + MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4) ; // Equation E5 // CHCAL_FRAC_MOD_RF // CHCAL_EN_INT_RF - E5 = ((2<<17)*(Tuner->RF_LO/10000*divider_val - (E4*(2*Tuner->Fxtal*Kdbl_RF)/10000)))/(2*Tuner->Fxtal*Kdbl_RF/10000) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ; + E5 = ((2<<17)*(state->RF_LO/10000*divider_val - (E4*(2*state->Fxtal*Kdbl_RF)/10000)))/(2*state->Fxtal*Kdbl_RF/10000) ; + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ; // Equation E5A // RFSYN_LPF_R - E5A = (((Fmax - Tuner->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; - status += MXL_ControlWrite(Tuner, RFSYN_LPF_R, E5A) ; + E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; + status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A) ; // Euqation E5B // CHCAL_EN_INIT_RF - status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0)); + status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0)); //if (E5 == 0) - // status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, 1); + // status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1); //else - // status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ; + // status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ; // // Set TG Synth @@ -3082,98 +2905,98 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // TG_LO_SELVAL // // Set divider_val, Fmax, Fmix to use in Equations - if (Tuner->TG_LO < 33000000UL) { + if (state->TG_LO < 33000000UL) { return -1; } FminBin = 33000000UL ; FmaxBin = 50000000UL ; - if (Tuner->TG_LO >= FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x6) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ; + if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ; divider_val = 36 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 50000000UL ; FmaxBin = 67000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x1) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ; divider_val = 24 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 67000000UL ; FmaxBin = 100000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0xC) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; divider_val = 18 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 100000000UL ; FmaxBin = 150000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; divider_val = 12 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 150000000UL ; FmaxBin = 200000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; divider_val = 8 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 200000000UL ; FmaxBin = 300000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ; divider_val = 6 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 300000000UL ; FmaxBin = 400000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ; divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 400000000UL ; FmaxBin = 600000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ; divider_val = 3 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 600000000UL ; FmaxBin = 900000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ; divider_val = 2 ; Fmax = FmaxBin ; Fmin = FminBin ; } // TG_DIV_VAL - tg_divval = (Tuner->TG_LO*divider_val/100000) - *(MXL_Ceiling(Tuner->Fxtal,1000000) * 100) / (Tuner->Fxtal/1000) ; - status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval) ; + tg_divval = (state->TG_LO*divider_val/100000) + *(MXL_Ceiling(state->Fxtal,1000000) * 100) / (state->Fxtal/1000) ; + status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval) ; - if (Tuner->TG_LO > 600000000UL) - status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval + 1 ) ; + if (state->TG_LO > 600000000UL) + status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1 ) ; Fmax = 1800000000UL ; Fmin = 1200000000UL ; @@ -3181,28 +3004,28 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4 - Fref_TG = (Tuner->Fxtal/1000)/ MXL_Ceiling(Tuner->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000 + Fref_TG = (state->Fxtal/1000)/ MXL_Ceiling(state->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000 - Fvco = (Tuner->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10 + Fvco = (state->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10 tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8; //below equation is same as above but much harder to debug. - //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((Tuner->TG_LO/10000)*divider_val*(Tuner->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ; + //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((state->TG_LO/10000)*divider_val*(state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ; - status += MXL_ControlWrite(Tuner, TG_VCO_BIAS , tg_lo) ; + status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo) ; //add for 2.6.5 //Special setting for QAM - if(Tuner ->Mod_Type == MXL_QAM) + if(state->Mod_Type == MXL_QAM) { - if(Tuner->RF_IN < 680000000) - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; + if(state->RF_IN < 680000000) + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ; else - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 2) ; + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2) ; } @@ -3213,673 +3036,675 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // if (Tuner->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // turn off Bank 1 - status += MXL_SetGPIO(Tuner, 1, 1) ; // turn off Bank 2 - status += MXL_SetGPIO(Tuner, 4, 1) ; // turn off Bank 3 + status += MXL_SetGPIO(fe, 3, 1) ; // turn off Bank 1 + status += MXL_SetGPIO(fe, 1, 1) ; // turn off Bank 2 + status += MXL_SetGPIO(fe, 4, 1) ; // turn off Bank 3 } if (Tuner->TF_Type == MXL_TF_C) // Tracking Filter type C { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; - status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; + status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000) + if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000) + if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000) + if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000) + if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 29) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(fe, DAC_DIN_B, 29) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000) + if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000) + if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 16) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(fe, DAC_DIN_B, 16) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000) + if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 7) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(fe, DAC_DIN_B, 7) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only { - status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000) + if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000) + if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000) + if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000) + if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000) + if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000) + if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000) + if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_D) // Tracking Filter type D { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000) + if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000) + if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000) + if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 { - status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; // if UHF and terrestrial => Turn off Tracking Filter - if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) + if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0) { // Turn off all the banks - status += MXL_SetGPIO(Tuner, 3, 1) ; - status += MXL_SetGPIO(Tuner, 1, 1) ; - status += MXL_SetGPIO(Tuner, 4, 1) ; - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; + status += MXL_SetGPIO(fe, 1, 1) ; + status += MXL_SetGPIO(fe, 4, 1) ; + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; - status += MXL_ControlWrite(Tuner, AGC_IF, 10) ; + status += MXL_ControlWrite(fe, AGC_IF, 10) ; } else // if VHF or cable => Turn on Tracking Filter { - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 140000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 140000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off } - if (Tuner->RF_IN >= 140000000 && Tuner->RF_IN < 240000000) + if (state->RF_IN >= 140000000 && state->RF_IN < 240000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off } - if (Tuner->RF_IN >= 240000000 && Tuner->RF_IN < 340000000) + if (state->RF_IN >= 240000000 && state->RF_IN < 340000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off } - if (Tuner->RF_IN >= 340000000 && Tuner->RF_IN < 430000000) + if (state->RF_IN >= 340000000 && state->RF_IN < 430000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On } - if (Tuner->RF_IN >= 430000000 && Tuner->RF_IN < 470000000) + if (state->RF_IN >= 430000000 && state->RF_IN < 470000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On } - if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 570000000) + if (state->RF_IN >= 470000000 && state->RF_IN < 570000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On } - if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 620000000) + if (state->RF_IN >= 570000000 && state->RF_IN < 620000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Offq + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Offq } - if (Tuner->RF_IN >= 620000000 && Tuner->RF_IN < 760000000) + if (state->RF_IN >= 620000000 && state->RF_IN < 760000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } } if (Tuner->TF_Type == MXL_TF_E) // Tracking Filter type E { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000) + if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000) + if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000) + if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_F) // Tracking Filter type F { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 160000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 160000000 && Tuner->RF_IN < 210000000) + if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 210000000 && Tuner->RF_IN < 300000000) + if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 300000000 && Tuner->RF_IN < 390000000) + if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 390000000 && Tuner->RF_IN < 515000000) + if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 515000000 && Tuner->RF_IN < 650000000) + if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 650000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000) + if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000) + if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000) + if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 50000000 && Tuner->RF_IN < 190000000) + if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 190000000 && Tuner->RF_IN < 280000000) + if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 350000000) + if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 470000000) //modified for 2.6.11 + if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) //modified for 2.6.11 { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN < 820000000) + if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 820000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; // if UHF and terrestrial=> Turn off Tracking Filter - if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) + if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0) { // Turn off all the banks - status += MXL_SetGPIO(Tuner, 3, 1) ; - status += MXL_SetGPIO(Tuner, 1, 1) ; - status += MXL_SetGPIO(Tuner, 4, 1) ; - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; + status += MXL_SetGPIO(fe, 1, 1) ; + status += MXL_SetGPIO(fe, 4, 1) ; + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; //2.6.12 //Turn on RSSI - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1) ; // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5) ; + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3) ; + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2) ; - //status += MXL_ControlWrite(Tuner, AGC_IF, 10) ; //doesn't matter since RSSI is turn on + //status += MXL_ControlWrite(fe, AGC_IF, 10) ; //doesn't matter since RSSI is turn on //following parameter is from analog OTA mode, can be change to seek better performance - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ; } else //if VHF or Cable => Turn on Tracking Filter { //2.6.12 //Turn off RSSI - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0) ; //change back from above condition - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ; + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000) + if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000) + if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000) + if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } } return status ; } -u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val) +// DONE +u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { - u16 status = 0 ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; if (GPIO_Num == 1) - status += MXL_ControlWrite(Tuner, GPIO_1B, GPIO_Val ? 0 : 1) ; - // GPIO2 is not available - if (GPIO_Num == 3) - { + status += MXL_ControlWrite(fe, GPIO_1B, GPIO_Val ? 0 : 1); + + /* GPIO2 is not available */ + + if (GPIO_Num == 3) { if (GPIO_Val == 1) { - status += MXL_ControlWrite(Tuner, GPIO_3, 0) ; - status += MXL_ControlWrite(Tuner, GPIO_3B, 0) ; + status += MXL_ControlWrite(fe, GPIO_3, 0); + status += MXL_ControlWrite(fe, GPIO_3B, 0); } if (GPIO_Val == 0) { - status += MXL_ControlWrite(Tuner, GPIO_3, 1) ; - status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ; + status += MXL_ControlWrite(fe, GPIO_3, 1); + status += MXL_ControlWrite(fe, GPIO_3B, 1); } - if (GPIO_Val == 3) { // tri-state - status += MXL_ControlWrite(Tuner, GPIO_3, 0) ; - status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ; + if (GPIO_Val == 3) { /* tri-state */ + status += MXL_ControlWrite(fe, GPIO_3, 0); + status += MXL_ControlWrite(fe, GPIO_3B, 1); } } - if (GPIO_Num == 4) - { + if (GPIO_Num == 4) { if (GPIO_Val == 1) { - status += MXL_ControlWrite(Tuner, GPIO_4, 0) ; - status += MXL_ControlWrite(Tuner, GPIO_4B, 0) ; + status += MXL_ControlWrite(fe, GPIO_4, 0); + status += MXL_ControlWrite(fe, GPIO_4B, 0); } if (GPIO_Val == 0) { - status += MXL_ControlWrite(Tuner, GPIO_4, 1) ; - status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ; + status += MXL_ControlWrite(fe, GPIO_4, 1); + status += MXL_ControlWrite(fe, GPIO_4B, 1); } - if (GPIO_Val == 3) { // tri-state - status += MXL_ControlWrite(Tuner, GPIO_4, 0) ; - status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ; + if (GPIO_Val == 3) { /* tri-state */ + status += MXL_ControlWrite(fe, GPIO_4, 0); + status += MXL_ControlWrite(fe, GPIO_4B, 1); } } - return status ; + return status; } /////////////////////////////////////////////////////////////////////////////// @@ -3907,17 +3732,19 @@ u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val) // >0 : Value exceed maximum allowed for control number // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value) +// DONE +u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { - u16 status = 0 ; - // Will write ALL Matching Control Name - status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 1 ) ; // Write Matching INIT Control - status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 2 ) ; // Write Matching CH Control + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; + + /* Will write ALL Matching Control Name */ + status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control * + status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control * #ifdef _MXL_INTERNAL - status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 3 ) ; // Write Matching MXL Control + status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control * #endif - - return status ; + return status; } /////////////////////////////////////////////////////////////////////////////// @@ -3947,105 +3774,86 @@ u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value) // 2 : Control name not found // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 controlNum, u32 value, u16 controlGroup) +// DONE +u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) { - u16 i, j, k ; - u32 highLimit ; - u32 ctrlVal ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 i, j, k; + u32 highLimit; + u32 ctrlVal; - if( controlGroup == 1) // Initial Control - { - for (i=0; iInit_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) - { // find the control Name - highLimit = 1 << Tuner->Init_Ctrl[i].size ; - if ( value < highLimit) - { - for( j=0; jInit_Ctrl[i].size; j++) - { - Tuner->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; - // change the register map accordingly - MXL_RegWriteBit( Tuner, (u8)(Tuner->Init_Ctrl[i].addr[j]), - (u8)(Tuner->Init_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ) ; - } - ctrlVal = 0 ; - for(k=0; kInit_Ctrl[i].size; k++) - { - ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ; + if (controlGroup == 1) /* Initial Control */ { + + for (i = 0; i < state->Init_Ctrl_Num; i++) { + + if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { + + highLimit = 1 << state->Init_Ctrl[i].size; + if (value < highLimit) { + for (j = 0; j < state->Init_Ctrl[i].size; j++) { + state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); + MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]), + (u8)(state->Init_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ); } + ctrlVal = 0; + for (k = 0; k < state->Init_Ctrl[i].size; k++) + ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); } else - { - return -1 ; - } + return -1; } } } - if ( controlGroup == 2) // Chan change Control - { - for (i=0; iCH_Ctrl_Num; i++) - { - if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) - { // find the control Name - highLimit = 1 << Tuner->CH_Ctrl[i].size ; - if ( value < highLimit) - { - for( j=0; jCH_Ctrl[i].size; j++) - { - Tuner->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; - // change the register map accordingly - MXL_RegWriteBit( Tuner, (u8)(Tuner->CH_Ctrl[i].addr[j]), - (u8)(Tuner->CH_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ) ; - } - ctrlVal = 0 ; - for(k=0; kCH_Ctrl[i].size; k++) - { - ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ; + if (controlGroup == 2) /* Chan change Control */ { + + for (i = 0; i < state->CH_Ctrl_Num; i++) { + + if (controlNum == state->CH_Ctrl[i].Ctrl_Num ) { + + highLimit = 1 << state->CH_Ctrl[i].size; + if (value < highLimit) { + for (j = 0; j < state->CH_Ctrl[i].size; j++) { + state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); + MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]), + (u8)(state->CH_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ); } + ctrlVal = 0; + for (k = 0; k < state->CH_Ctrl[i].size; k++) + ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); } else - { - return -1 ; - } + return -1; } } } #ifdef _MXL_INTERNAL - if ( controlGroup == 3) // Maxlinear Control - { - for (i=0; iMXL_Ctrl_Num; i++) - { - if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) - { // find the control Name - highLimit = (1 << Tuner->MXL_Ctrl[i].size) ; - if ( value < highLimit) - { - for( j=0; jMXL_Ctrl[i].size; j++) - { - Tuner->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; - // change the register map accordingly - MXL_RegWriteBit( Tuner, (u8)(Tuner->MXL_Ctrl[i].addr[j]), - (u8)(Tuner->MXL_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ) ; - } - ctrlVal = 0 ; - for(k=0; kMXL_Ctrl[i].size; k++) - { - ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1 << k) ; + if (controlGroup == 3) /* Maxlinear Control */ { + + for (i = 0; i < state->MXL_Ctrl_Num; i++) { + + if (controlNum == state->MXL_Ctrl[i].Ctrl_Num ) { + + highLimit = (1 << state->MXL_Ctrl[i].size) ; + if (value < highLimit) { + for (j = 0; j < state->MXL_Ctrl[i].size; j++) { + state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); + MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]), + (u8)(state->MXL_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ); } + ctrlVal = 0; + for(k = 0; k < state->MXL_Ctrl[i].size; k++) + ctrlVal += state->MXL_Ctrl[i].val[k] * (1 << k); } else - { - return -1 ; - } + return -1; } } } #endif - return 0 ; // successful return + return 0 ; /* successful return */ } /////////////////////////////////////////////////////////////////////////////// @@ -4073,20 +3881,20 @@ u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 controlNum, u32 value, u16 c // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal) +// DONE +u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { + struct mxl5005s_state *state = fe->demodulator_priv; int i ; - for (i=0; i<104; i++) - { - if (RegNum == Tuner->TunerRegs[i].Reg_Num ) - { - Tuner->TunerRegs[i].Reg_Val = RegVal ; - return 0 ; + for (i = 0; i < 104; i++) { + if (RegNum == state->TunerRegs[i].Reg_Num) { + state->TunerRegs[i].Reg_Val = RegVal; + return 0; } } - return 1 ; + return 1; } /////////////////////////////////////////////////////////////////////////////// @@ -4113,20 +3921,20 @@ u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal) // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal) +// DONE +u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { + struct mxl5005s_state *state = fe->demodulator_priv; int i ; - for (i=0; i<104; i++) - { - if (RegNum == Tuner->TunerRegs[i].Reg_Num ) - { - *RegVal = (u8)(Tuner->TunerRegs[i].Reg_Val) ; - return 0 ; + for (i = 0; i < 104; i++) { + if (RegNum == state->TunerRegs[i].Reg_Num ) { + *RegVal = (u8)(state->TunerRegs[i].Reg_Val); + return 0; } } - return 1 ; + return 1; } /////////////////////////////////////////////////////////////////////////////// @@ -4150,48 +3958,53 @@ u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_ControlRead(Tuner_struct *Tuner, u16 controlNum, u32 * value) +// DONE +u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 * value) { + struct mxl5005s_state *state = fe->demodulator_priv; u32 ctrlVal ; u16 i, k ; - for (i=0; iInit_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) - { - ctrlVal = 0 ; - for(k=0; kInit_Ctrl[i].size; k++) - ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ; - *value = ctrlVal ; - return 0 ; + for (i = 0; i < state->Init_Ctrl_Num ; i++) { + + if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { + + ctrlVal = 0; + for (k = 0; k < state->Init_Ctrl[i].size; k++) + ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); + *value = ctrlVal; + return 0; } } - for (i=0; iCH_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) - { - ctrlVal = 0 ; - for(k=0; kCH_Ctrl[i].size; k++) - ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ; - *value = ctrlVal ; - return 0 ; + + for (i = 0; i < state->CH_Ctrl_Num ; i++) { + + if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { + + ctrlVal = 0; + for (k = 0; k < state->CH_Ctrl[i].size; k++) + ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); + *value = ctrlVal; + return 0; + } } #ifdef _MXL_INTERNAL - for (i=0; iMXL_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) - { - ctrlVal = 0 ; - for(k=0; kMXL_Ctrl[i].size; k++) - ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1<MXL_Ctrl_Num ; i++) { + + if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { + + ctrlVal = 0; + for (k = 0; k < state->MXL_Ctrl[i].size; k++) + ctrlVal += state->MXL_Ctrl[i].val[k] * (1<demodulator_priv; u16 i, j, k ; u16 Count ; - for (i=0; iInit_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) - { - Count = 1 ; - RegNum[0] = (u8)(Tuner->Init_Ctrl[i].addr[0]) ; + for (i = 0; i < state->Init_Ctrl_Num ; i++) { + + if ( controlNum == state->Init_Ctrl[i].Ctrl_Num ) { + + Count = 1; + RegNum[0] = (u8)(state->Init_Ctrl[i].addr[0]); + + for (k = 1; k < state->Init_Ctrl[i].size; k++) { + + for (j = 0; j < Count; j++) { + + if (state->Init_Ctrl[i].addr[k] != RegNum[j]) { + + Count ++; + RegNum[Count-1] = (u8)(state->Init_Ctrl[i].addr[k]); - for(k=1; kInit_Ctrl[i].size; k++) - { - for (j= 0; jInit_Ctrl[i].addr[k] != RegNum[j]) - { - Count ++ ; - RegNum[Count-1] = (u8)(Tuner->Init_Ctrl[i].addr[k]) ; } } } - *count = Count ; - return 0 ; + *count = Count; + return 0; } } - for (i=0; iCH_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) - { - Count = 1 ; - RegNum[0] = (u8)(Tuner->CH_Ctrl[i].addr[0]) ; + for (i = 0; i < state->CH_Ctrl_Num ; i++) { + + if ( controlNum == state->CH_Ctrl[i].Ctrl_Num ) { + + Count = 1; + RegNum[0] = (u8)(state->CH_Ctrl[i].addr[0]); + + for (k = 1; k < state->CH_Ctrl[i].size; k++) { + + for (j= 0; jCH_Ctrl[i].addr[k] != RegNum[j]) { + + Count ++; + RegNum[Count-1] = (u8)(state->CH_Ctrl[i].addr[k]); - for(k=1; kCH_Ctrl[i].size; k++) - { - for (j= 0; jCH_Ctrl[i].addr[k] != RegNum[j]) - { - Count ++ ; - RegNum[Count-1] = (u8)(Tuner->CH_Ctrl[i].addr[k]) ; } } } - *count = Count ; - return 0 ; + *count = Count; + return 0; } } #ifdef _MXL_INTERNAL - for (i=0; iMXL_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) - { - Count = 1 ; - RegNum[0] = (u8)(Tuner->MXL_Ctrl[i].addr[0]) ; + for (i = 0; i < state->MXL_Ctrl_Num ; i++) { + + if ( controlNum == state->MXL_Ctrl[i].Ctrl_Num ) { + + Count = 1; + RegNum[0] = (u8)(state->MXL_Ctrl[i].addr[0]); + + for (k = 1; k < state->MXL_Ctrl[i].size; k++) { + + for (j = 0; jMXL_Ctrl[i].addr[k] != RegNum[j]) { + + Count ++; + RegNum[Count-1] = (u8)state->MXL_Ctrl[i].addr[k]; - for(k=1; kMXL_Ctrl[i].size; k++) - { - for (j= 0; jMXL_Ctrl[i].addr[k] != RegNum[j]) - { - Count ++ ; - RegNum[Count-1] = (u8)Tuner->MXL_Ctrl[i].addr[k] ; } } } - *count = Count ; - return 0 ; + *count = Count; + return 0; } } #endif - *count = 0 ; - return 1 ; + *count = 0; + return 1; } /////////////////////////////////////////////////////////////////////////////// @@ -4308,7 +4126,7 @@ u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 controlNum, u8 *RegNum, int * co // Inputs: // // Tuner_struct : structure defined at higher level // // address : register address // -// bit : register bit number // +// bit : register bit number // // bitVal : register bit value // // // // Outputs: // @@ -4318,12 +4136,12 @@ u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 controlNum, u8 *RegNum, int * co // NONE // // // /////////////////////////////////////////////////////////////////////////////// - -void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal) +// DONE +void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { + struct mxl5005s_state *state = fe->demodulator_priv; int i ; - // Declare Local Constants const u8 AND_MAP[8] = { 0xFE, 0xFD, 0xFB, 0xF7, 0xEF, 0xDF, 0xBF, 0x7F } ; @@ -4332,17 +4150,16 @@ void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal) 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 } ; - for(i=0; iTunerRegs_Num; i++) { - if ( Tuner->TunerRegs[i].Reg_Num == address ) { + for (i = 0; i < state->TunerRegs_Num; i++) { + if (state->TunerRegs[i].Reg_Num == address) { if (bitVal) - Tuner->TunerRegs[i].Reg_Val |= OR_MAP[bit] ; + state->TunerRegs[i].Reg_Val |= OR_MAP[bit]; else - Tuner->TunerRegs[i].Reg_Val &= AND_MAP[bit] ; + state->TunerRegs[i].Reg_Val &= AND_MAP[bit]; break ; } } -} ; - +} /////////////////////////////////////////////////////////////////////////////// // // @@ -4367,37 +4184,43 @@ void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal) // Computed value // // // /////////////////////////////////////////////////////////////////////////////// -u32 MXL_Ceiling( u32 value, u32 resolution ) +// DONE +u32 MXL_Ceiling(u32 value, u32 resolution) { - return (value/resolution + (value%resolution > 0 ? 1 : 0)) ; -}; + return (value/resolution + (value % resolution > 0 ? 1 : 0)); +} // // Retrieve the Initialzation Registers // -u16 MXL_GetInitRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) +// DONE +u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { + struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i ; - u8 RegAddr[] = {11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, - 76, 77, 91, 134, 135, 137, 147, - 156, 166, 167, 168, 25 } ; - *count = sizeof(RegAddr) / sizeof(u8) ; + u8 RegAddr[] = { + 11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, + 76, 77, 91, 134, 135, 137, 147, + 156, 166, 167, 168, 25 }; - status += MXL_BlockInit(Tuner) ; + *count = sizeof(RegAddr) / sizeof(u8); - for (i=0 ; i< *count; i++) - { - RegNum[i] = RegAddr[i] ; - status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + status += MXL_BlockInit(fe); + + for (i = 0 ; i < *count; i++) { + RegNum[i] = RegAddr[i]; + status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); } - return status ; + return status; } -u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) +// DONE +u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { + struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i ; @@ -4413,203 +4236,207 @@ u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) // RegAddr[i] = i; #endif - *count = sizeof(RegAddr) / sizeof(u8) ; + *count = sizeof(RegAddr) / sizeof(u8); - for (i=0 ; i< *count; i++) - { - RegNum[i] = RegAddr[i] ; - status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + for (i = 0 ; i < *count; i++) { + RegNum[i] = RegAddr[i]; + status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); } - return status ; - + return status; } -u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) +// DONE +u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - u16 status = 0 ; - int i ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; + int i; - u8 RegAddr[] = {43, 136} ; + u8 RegAddr[] = {43, 136}; - *count = sizeof(RegAddr) / sizeof(u8) ; + *count = sizeof(RegAddr) / sizeof(u8); - for (i=0; i<*count; i++) - { - RegNum[i] = RegAddr[i] ; - status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + for (i = 0; i < *count; i++) { + RegNum[i] = RegAddr[i]; + status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); } - return status ; + return status; } -u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) +// DONE +u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - u16 status = 0 ; - int i ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; + int i; - u8 RegAddr[] = {138} ; + u8 RegAddr[] = { 138 }; - *count = sizeof(RegAddr) / sizeof(u8) ; + *count = sizeof(RegAddr) / sizeof(u8); - for (i=0; i<*count; i++) - { - RegNum[i] = RegAddr[i] ; - status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + for (i = 0; i < *count; i++) { + RegNum[i] = RegAddr[i]; + status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); } - return status ; + return status; } +// DONE u16 MXL_GetMasterControl(u8 *MasterReg, int state) { - if (state == 1) // Load_Start - *MasterReg = 0xF3 ; - if (state == 2) // Power_Down - *MasterReg = 0x41 ; - if (state == 3) // Synth_Reset - *MasterReg = 0xB1 ; - if (state == 4) // Seq_Off - *MasterReg = 0xF1 ; - - return 0 ; + if (state == 1) /* Load_Start */ + *MasterReg = 0xF3; + if (state == 2) /* Power_Down */ + *MasterReg = 0x41; + if (state == 3) /* Synth_Reset */ + *MasterReg = 0xB1; + if (state == 4) /* Seq_Off */ + *MasterReg = 0xF1; + + return 0; } #ifdef _MXL_PRODUCTION -u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) +u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) { + struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0 ; if (VCO_Range == 1) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 180224); - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 222822 ) ; - } - if (Tuner->Mode == 1) // Digital Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 229376 ) ; + status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 180224); + } + if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 222822); + } + if (state->Mode == 1) /* Digital Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 229376); } } if (VCO_Range == 2) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41); - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); - } - if (Tuner->Mode == 1) // Digital Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 16384); + status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + } + if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + } + if (state->Mode == 1) /* Digital Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 16384); } } if (VCO_Range == 3) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670); - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670); - } - if (Tuner->Mode == 1) // Digital Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 245760); + status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); + } + if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); + } + if (state->Mode == 1) /* Digital Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 245760); } } if (VCO_Range == 4) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); - } - if (Tuner->Mode == 1) // Digital Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 212992); + status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + } + if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + } + if (state->Mode == 1) /* Digital Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 212992); } } return status; } -u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) +// DONE +u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { + struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; if (Hystersis == 1) - status += MXL_ControlWrite(Tuner, DN_BYPASS_AGC_I2C, 1); + status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1); return status; } -- cgit v1.2.3 From 85d220d03b70180b9958b29d43e99c7135f00654 Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 05:48:14 -0300 Subject: V4L/DVB (7867): mxl5005s: Cleanup #4 Cleanup #4 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 926 +++++++++++++++++++++------------ 1 file changed, 603 insertions(+), 323 deletions(-) (limited to 'drivers/media/common/tuners/mxl5005s.c') diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index d8885484cfbd..7e687171301b 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -24,6 +24,270 @@ #include "mxl5005s.h" +static int debug; + +#define dprintk(level, arg...) do { \ + if (debug >= level) \ + printk(arg); \ + } while (0) + +#define TUNER_REGS_NUM 104 +#define INITCTRL_NUM 40 + +#ifdef _MXL_PRODUCTION +#define CHCTRL_NUM 39 +#else +#define CHCTRL_NUM 36 +#endif + +#define MXLCTRL_NUM 189 +#define MASTER_CONTROL_ADDR 9 + +/* Enumeration of AGC Mode */ +typedef enum +{ + MXL_DUAL_AGC = 0, + MXL_SINGLE_AGC +} AGC_Mode; + +/* Enumeration of Master Control Register State */ +typedef enum +{ + MC_LOAD_START = 1, + MC_POWER_DOWN, + MC_SYNTH_RESET, + MC_SEQ_OFF +} Master_Control_State; + +/* Enumeration of MXL5005 Tuner Mode */ +typedef enum +{ + MXL_ANALOG_MODE = 0, + MXL_DIGITAL_MODE +} Tuner_Mode; + +/* Enumeration of MXL5005 Tuner IF Mode */ +typedef enum +{ + MXL_ZERO_IF = 0, + MXL_LOW_IF +} Tuner_IF_Mode; + +/* Enumeration of MXL5005 Tuner Clock Out Mode */ +typedef enum +{ + MXL_CLOCK_OUT_DISABLE = 0, + MXL_CLOCK_OUT_ENABLE +} Tuner_Clock_Out; + +/* Enumeration of MXL5005 Tuner Div Out Mode */ +typedef enum +{ + MXL_DIV_OUT_1 = 0, + MXL_DIV_OUT_4 + +} Tuner_Div_Out; + +/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */ +typedef enum +{ + MXL_CAP_SEL_DISABLE = 0, + MXL_CAP_SEL_ENABLE + +} Tuner_Cap_Select; + +/* Enumeration of MXL5005 Tuner RSSI Mode */ +typedef enum +{ + MXL_RSSI_DISABLE = 0, + MXL_RSSI_ENABLE + +} Tuner_RSSI; + +/* Enumeration of MXL5005 Tuner Modulation Type */ +typedef enum +{ + MXL_DEFAULT_MODULATION = 0, + MXL_DVBT, + MXL_ATSC, + MXL_QAM, + MXL_ANALOG_CABLE, + MXL_ANALOG_OTA +} Tuner_Modu_Type; + +/* Enumeration of MXL5005 Tuner Tracking Filter Type */ +typedef enum +{ + MXL_TF_DEFAULT = 0, + MXL_TF_OFF, + MXL_TF_C, + MXL_TF_C_H, + MXL_TF_D, + MXL_TF_D_L, + MXL_TF_E, + MXL_TF_F, + MXL_TF_E_2, + MXL_TF_E_NA, + MXL_TF_G +} Tuner_TF_Type; + +/* MXL5005 Tuner Register Struct */ +typedef struct _TunerReg_struct +{ + u16 Reg_Num; /* Tuner Register Address */ + u16 Reg_Val; /* Current sofware programmed value waiting to be writen */ +} TunerReg_struct; + +typedef enum +{ + /* Initialization Control Names */ + DN_IQTN_AMP_CUT = 1, /* 1 */ + BB_MODE, /* 2 */ + BB_BUF, /* 3 */ + BB_BUF_OA, /* 4 */ + BB_ALPF_BANDSELECT, /* 5 */ + BB_IQSWAP, /* 6 */ + BB_DLPF_BANDSEL, /* 7 */ + RFSYN_CHP_GAIN, /* 8 */ + RFSYN_EN_CHP_HIGAIN, /* 9 */ + AGC_IF, /* 10 */ + AGC_RF, /* 11 */ + IF_DIVVAL, /* 12 */ + IF_VCO_BIAS, /* 13 */ + CHCAL_INT_MOD_IF, /* 14 */ + CHCAL_FRAC_MOD_IF, /* 15 */ + DRV_RES_SEL, /* 16 */ + I_DRIVER, /* 17 */ + EN_AAF, /* 18 */ + EN_3P, /* 19 */ + EN_AUX_3P, /* 20 */ + SEL_AAF_BAND, /* 21 */ + SEQ_ENCLK16_CLK_OUT, /* 22 */ + SEQ_SEL4_16B, /* 23 */ + XTAL_CAPSELECT, /* 24 */ + IF_SEL_DBL, /* 25 */ + RFSYN_R_DIV, /* 26 */ + SEQ_EXTSYNTHCALIF, /* 27 */ + SEQ_EXTDCCAL, /* 28 */ + AGC_EN_RSSI, /* 29 */ + RFA_ENCLKRFAGC, /* 30 */ + RFA_RSSI_REFH, /* 31 */ + RFA_RSSI_REF, /* 32 */ + RFA_RSSI_REFL, /* 33 */ + RFA_FLR, /* 34 */ + RFA_CEIL, /* 35 */ + SEQ_EXTIQFSMPULSE, /* 36 */ + OVERRIDE_1, /* 37 */ + BB_INITSTATE_DLPF_TUNE, /* 38 */ + TG_R_DIV, /* 39 */ + EN_CHP_LIN_B, /* 40 */ + + /* Channel Change Control Names */ + DN_POLY = 51, /* 51 */ + DN_RFGAIN, /* 52 */ + DN_CAP_RFLPF, /* 53 */ + DN_EN_VHFUHFBAR, /* 54 */ + DN_GAIN_ADJUST, /* 55 */ + DN_IQTNBUF_AMP, /* 56 */ + DN_IQTNGNBFBIAS_BST, /* 57 */ + RFSYN_EN_OUTMUX, /* 58 */ + RFSYN_SEL_VCO_OUT, /* 59 */ + RFSYN_SEL_VCO_HI, /* 60 */ + RFSYN_SEL_DIVM, /* 61 */ + RFSYN_RF_DIV_BIAS, /* 62 */ + DN_SEL_FREQ, /* 63 */ + RFSYN_VCO_BIAS, /* 64 */ + CHCAL_INT_MOD_RF, /* 65 */ + CHCAL_FRAC_MOD_RF, /* 66 */ + RFSYN_LPF_R, /* 67 */ + CHCAL_EN_INT_RF, /* 68 */ + TG_LO_DIVVAL, /* 69 */ + TG_LO_SELVAL, /* 70 */ + TG_DIV_VAL, /* 71 */ + TG_VCO_BIAS, /* 72 */ + SEQ_EXTPOWERUP, /* 73 */ + OVERRIDE_2, /* 74 */ + OVERRIDE_3, /* 75 */ + OVERRIDE_4, /* 76 */ + SEQ_FSM_PULSE, /* 77 */ + GPIO_4B, /* 78 */ + GPIO_3B, /* 79 */ + GPIO_4, /* 80 */ + GPIO_3, /* 81 */ + GPIO_1B, /* 82 */ + DAC_A_ENABLE, /* 83 */ + DAC_B_ENABLE, /* 84 */ + DAC_DIN_A, /* 85 */ + DAC_DIN_B, /* 86 */ +#ifdef _MXL_PRODUCTION + RFSYN_EN_DIV, /* 87 */ + RFSYN_DIVM, /* 88 */ + DN_BYPASS_AGC_I2C /* 89 */ +#endif +} MXL5005_ControlName; + +/* + * The following context is source code provided by MaxLinear. + * MaxLinear source code - Common_MXL.h (?) + */ + +/* Constants */ +#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104 +#define MXL5005S_LATCH_BYTE 0xfe + +/* Register address, MSB, and LSB */ +#define MXL5005S_BB_IQSWAP_ADDR 59 +#define MXL5005S_BB_IQSWAP_MSB 0 +#define MXL5005S_BB_IQSWAP_LSB 0 + +#define MXL5005S_BB_DLPF_BANDSEL_ADDR 53 +#define MXL5005S_BB_DLPF_BANDSEL_MSB 4 +#define MXL5005S_BB_DLPF_BANDSEL_LSB 3 + +/* Standard modes */ +enum +{ + MXL5005S_STANDARD_DVBT, + MXL5005S_STANDARD_ATSC, +}; +#define MXL5005S_STANDARD_MODE_NUM 2 + +/* Bandwidth modes */ +enum +{ + MXL5005S_BANDWIDTH_6MHZ = 6000000, + MXL5005S_BANDWIDTH_7MHZ = 7000000, + MXL5005S_BANDWIDTH_8MHZ = 8000000, +}; +#define MXL5005S_BANDWIDTH_MODE_NUM 3 + +/* Top modes */ +enum +{ + MXL5005S_TOP_5P5 = 55, + MXL5005S_TOP_7P2 = 72, + MXL5005S_TOP_9P2 = 92, + MXL5005S_TOP_11P0 = 110, + MXL5005S_TOP_12P9 = 129, + MXL5005S_TOP_14P7 = 147, + MXL5005S_TOP_16P8 = 168, + MXL5005S_TOP_19P4 = 194, + MXL5005S_TOP_21P2 = 212, + MXL5005S_TOP_23P2 = 232, + MXL5005S_TOP_25P2 = 252, + MXL5005S_TOP_27P1 = 271, + MXL5005S_TOP_29P2 = 292, + MXL5005S_TOP_31P7 = 317, + MXL5005S_TOP_34P9 = 349, +}; + +/* IF output load */ +enum +{ + MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, + MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, +}; + /* MXL5005 Tuner Control Struct */ typedef struct _TunerControl_struct { u16 Ctrl_Num; /* Control Number */ @@ -77,241 +341,138 @@ struct mxl5005s_state TunerReg_struct TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ -}; - - -int mxl5005s_Initialize( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner - ) -{ - MXL5005S_EXTRA_MODULE *pExtra; - - unsigned char AgcMasterByte; - unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; - unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; - int TableLen; - - // Get tuner extra module. - pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - - // Get AGC master byte - AgcMasterByte = pExtra->AgcMasterByte; + /* Linux driver framework specific */ + const struct mxl5005s_config *config; - // Initialize MxL5005S tuner according to MxL5005S tuner example code. - - // Tuner initialization stage 0 - MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); - AddrTable[0] = MASTER_CONTROL_ADDR; - ByteTable[0] |= AgcMasterByte; - - if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - - // Tuner initialization stage 1 - MXL_GetInitRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen); - - if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - - return FUNCTION_SUCCESS; - -error_status_set_tuner_registers: - return FUNCTION_ERROR; -} + struct dvb_frontend *frontend; + struct i2c_adapter *i2c; +}; -int mxl5005s_SetRfFreqHz( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned long RfFreqHz - ) +// funcs +u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); +u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); +u16 MXL_GetMasterControl(u8 *MasterReg, int state); +void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal); +u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); +u32 MXL_Ceiling(u32 value, u32 resolution); +u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); +u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal); +u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup); +u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); +u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count); +u32 MXL_GetXtalInt(u32 Xtal_Freq); +u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); +void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); +void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); +u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); +int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen); +u16 MXL_IFSynthInit(struct dvb_frontend *fe); + +int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { - MXL5005S_EXTRA_MODULE *pExtra; - BASE_INTERFACE_MODULE *pBaseInterface; - - unsigned char AgcMasterByte; + struct mxl5005s_state *state = fe->tuner_priv; + u8 AgcMasterByte = state->config->AgcMasterByte; unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - unsigned long IfDivval; + u32 IfDivval; unsigned char MasterControlByte; - // Get tuner extra module and base interface module. - pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - pBaseInterface = pTuner->pBaseInterface; - - - // Get AGC master byte - AgcMasterByte = pExtra->AgcMasterByte; - + dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz); // Set MxL5005S tuner RF frequency according to MxL5005S tuner example code. // Tuner RF frequency setting stage 0 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ; AddrTable[0] = MASTER_CONTROL_ADDR; - ByteTable[0] |= AgcMasterByte; - - if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; + ByteTable[0] |= state->config->AgcMasterByte; + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); // Tuner RF frequency setting stage 1 - MXL_TuneRF(&pExtra->MxlDefinedTunerStructure, RfFreqHz); - - MXL_ControlRead(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, &IfDivval); + MXL_TuneRF(fe, RfFreqHz); - MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 0); - MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_EXTPOWERUP, 1); - MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, 8); + MXL_ControlRead(fe, IF_DIVVAL, &IfDivval); - MXL_GetCHRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ; + MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0); + MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1); + MXL_ControlWrite(fe, IF_DIVVAL, 8); + MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen) ; MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; ByteTable[TableLen] = MasterControlByte | AgcMasterByte; TableLen += 1; - if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); // Wait 30 ms. - pBaseInterface->WaitMs(pBaseInterface, 30); - + msleep(30); // Tuner RF frequency setting stage 2 - MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 1) ; - MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, IfDivval) ; - MXL_GetCHRegister_ZeroIF(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ; + MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ; + MXL_ControlWrite(fe, IF_DIVVAL, IfDivval) ; + MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen) ; MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; ByteTable[TableLen] = MasterControlByte | AgcMasterByte ; TableLen += 1; - if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - - - // Set tuner RF frequency parameter. - pTuner->RfFreqHz = RfFreqHz; - pTuner->IsRfFreqHzSet = YES; - - - return FUNCTION_SUCCESS; - + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); -error_status_set_tuner_registers: - return FUNCTION_ERROR; + return 0; } -// DONE -int mxl5005s_GetRfFreqHz(struct dvb_frontend *fe, unsigned long *pRfFreqHz) +/* Write a single byte to a single reg */ +static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val) { - struct mxl5005s_state *state = fe->demodulator_priv; - int ret = -1; - - /* Get tuner RF frequency in Hz from tuner module. */ - if(state->IsRfFreqHzSet == YES) { - *pRfFreqHz = state->RfFreqHz; - ret = 0; + struct mxl5005s_state *state = fe->tuner_priv; + u8 buf[2] = { reg, val }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 2 }; + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write failed\n"); + return -EREMOTEIO; } - - return -1; + return 0; } -int mxl5005s_SetRegsWithTable( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned char *pAddrTable, - unsigned char *pByteTable, - int TableLen - ) +/* Write a word to a single reg */ +static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val) { - BASE_INTERFACE_MODULE *pBaseInterface; - I2C_BRIDGE_MODULE *pI2cBridge; - unsigned char WritingByteNumMax; - - int i; - unsigned char WritingBuffer[I2C_BUFFER_LEN]; - unsigned char WritingIndex; - - - - // Get base interface, I2C bridge, and maximum writing byte number. - pBaseInterface = pTuner->pBaseInterface; - pI2cBridge = pTuner->pI2cBridge; - WritingByteNumMax = pBaseInterface->I2cWritingByteNumMax; - - - // Set registers with table. - // Note: 1. The I2C format of MxL5005S is described as follows: - // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * n + stop_bit - // ... - // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * m + latch_byte + stop_bit - // 2. The latch_byte is 0xfe. - // 3. The following writing byte separating scheme takes latch_byte as two byte data. - for(i = 0, WritingIndex = 0; i < TableLen; i++) - { - // Put register address and register byte value into writing buffer. - WritingBuffer[WritingIndex] = pAddrTable[i]; - WritingBuffer[WritingIndex + 1] = pByteTable[i]; - WritingIndex += 2; - - // If writing buffer is full, send the I2C writing command with writing buffer. - if(WritingIndex > (WritingByteNumMax - 2)) - { - if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - - WritingIndex = 0; - } + struct mxl5005s_state *state = fe->tuner_priv; + u8 buf[3] = { reg, val >> 8 , val & 0xff }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 3 }; + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write16 failed\n"); + return -EREMOTEIO; } - - - // Send the last I2C writing command with writing buffer and latch byte. - WritingBuffer[WritingIndex] = MXL5005S_LATCH_BYTE; - WritingIndex += 1; - - if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - - - return FUNCTION_SUCCESS; - - -error_status_set_tuner_registers: - return FUNCTION_ERROR; + return 0; } -int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, - unsigned char *pAddrTable, - unsigned char *pByteTable, - int TableLen - ) +int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen) { - struct mxl5005s_state *state = fe->demodulator_priv; - int i; + int i, ret; u8 end_two_bytes_buf[]={ 0 , 0 }; - u8 tuner_addr=0x00; - - pTuner->GetDeviceAddr(pTuner , &tuner_addr); for( i = 0 ; i < TableLen - 1 ; i++) { - if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , &pByteTable[i] , 1 ) ) - return FUNCTION_ERROR; + ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i]); + if (!ret) + return ret; } end_two_bytes_buf[0] = pByteTable[i]; end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE; - if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , end_two_bytes_buf , 2 ) ) - return FUNCTION_ERROR; + ret = mxl5005s_writereg16(fe, pAddrTable[i], (end_two_bytes_buf[0] << 8) | end_two_bytes_buf[1]); - return FUNCTION_SUCCESS; + return ret; } int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, @@ -321,7 +482,6 @@ int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, const unsigned char WritingValue ) { - struct mxl5005s_state *state = fe->demodulator_priv; int i; unsigned char Mask; @@ -335,82 +495,18 @@ int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, Shift = Lsb; - /* Get tuner register byte according to register adddress. */ - MXL_RegRead(&pExtra->MxlDefinedTunerStructure, RegAddr, &RegByte); + MXL_RegRead(fe, RegAddr, &RegByte); /* Reserve register byte unmask bit with mask and inlay writing value into it. */ RegByte &= ~Mask; RegByte |= (WritingValue << Shift) & Mask; /* Update tuner register byte table. */ - MXL_RegWrite(&pExtra->MxlDefinedTunerStructure, RegAddr, RegByte); + MXL_RegWrite(fe, RegAddr, RegByte); /* Write tuner register byte with writing byte. */ - if(pExtra->SetRegsWithTable( dib, pTuner, &RegAddr, &RegByte, LEN_1_BYTE) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - - - return FUNCTION_SUCCESS; - - -error_status_set_tuner_registers: - return FUNCTION_ERROR; -} - -// DONE -int mxl5005s_SetSpectrumMode(struct dvb_frontend *fe, int SpectrumMode) -{ - struct mxl5005s_state *state = fe->demodulator_priv; - static const unsigned char BbIqswapTable[SPECTRUM_MODE_NUM] = - { - /* BB_IQSWAP */ - 0, /* Normal spectrum */ - 1, /* Inverse spectrum */ - }; - - /* Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode. */ - mxl5005s_SetRegMaskBits(fe, - MXL5005S_BB_IQSWAP_ADDR, - MXL5005S_BB_IQSWAP_MSB, - MXL5005S_BB_IQSWAP_LSB, - BbIqswapTable[SpectrumMode]); - - return FUNCTION_SUCCESS; -} - -// DONE -int mxl5005s_SetBandwidthHz(struct dvb_frontend *fe, unsigned long BandwidthHz) -{ - struct mxl5005s_state *state = fe->demodulator_priv; - - unsigned char BbDlpfBandsel; - - /* Set BB_DLPF_BANDSEL according to bandwidth. */ - switch(BandwidthHz) - { - default: - case MXL5005S_BANDWIDTH_6MHZ: - BbDlpfBandsel = 3; - break; - case MXL5005S_BANDWIDTH_7MHZ: - BbDlpfBandsel = 2; - break; - case MXL5005S_BANDWIDTH_8MHZ: - BbDlpfBandsel = 0; - break; - } - - if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_DLPF_BANDSEL_ADDR, MXL5005S_BB_DLPF_BANDSEL_MSB, - MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != 0) - goto error_status_set_tuner_registers; - - - return 0; - - -error_status_set_tuner_registers: - return -1; + return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1); } // The following context is source code provided by MaxLinear. @@ -418,7 +514,7 @@ error_status_set_tuner_registers: // DONE u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; state->TunerRegs_Num = TUNER_REGS_NUM ; // state->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; @@ -740,7 +836,7 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) // DONE u16 MXL5005_ControlInit(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; state->Init_Ctrl_Num = INITCTRL_NUM; state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; @@ -1684,7 +1780,6 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) // DONE void InitTunerControls(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; MXL5005_RegisterInit(fe); MXL5005_ControlInit(fe); #ifdef _MXL_INTERNAL @@ -1745,7 +1840,7 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ ) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; state->Mode = Mode; @@ -1798,8 +1893,8 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, // DONE void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; - if (Tuner->Mode == 1) /* Digital Mode */ + struct mxl5005s_state *state = fe->tuner_priv; + if (state->Mode == 1) /* Digital Mode */ state->IF_LO = state->IF_OUT; else /* Analog Mode */ { @@ -1837,7 +1932,7 @@ void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) // DONE void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; if (state->Mode == 1) /* Digital Mode */ { //remove 20.48MHz setting for 2.6.10 @@ -1876,7 +1971,6 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) // DONE u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; status += MXL_ControlWrite(fe, OVERRIDE_1, 1); @@ -1915,7 +2009,7 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) // DONE u16 MXL_BlockInit(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; status += MXL_OverwriteICDefault(fe); @@ -2096,7 +2190,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0); /* Misc Controls */ - if (state->Mode == 0 && Tuner->IF_Mode == 1) /* Analog LowIF mode */ + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */ status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0); else status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1); @@ -2155,7 +2249,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ { - Tuner->AGC_Mode = 1; /* Single AGC Mode */ + state->AGC_Mode = 1; /* Single AGC Mode */ /* Enable RSSI */ status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); @@ -2203,7 +2297,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } if (state->Mod_Type == MXL_ANALOG_CABLE) { /* Analog Cable Mode */ - /* Tuner->Mode = MXL_DIGITAL_MODE; */ + /* state->Mode = MXL_DIGITAL_MODE; */ state->AGC_Mode = 1; /* Single AGC Mode */ @@ -2269,8 +2363,9 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_IFSynthInit(Tuner_struct * Tuner) +u16 MXL_IFSynthInit(struct dvb_frontend *fe) { + struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0 ; // Declare Local Variables u32 Fref = 0 ; @@ -2286,186 +2381,186 @@ u16 MXL_IFSynthInit(Tuner_struct * Tuner) // // IF Synthesizer Control // - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF mode + if (state->Mode == 0 && state->IF_Mode == 1) // Analog Low IF mode { - if (Tuner->IF_LO == 41000000UL) { + if (state->IF_LO == 41000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 328000000UL ; } - if (Tuner->IF_LO == 47000000UL) { + if (state->IF_LO == 47000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 376000000UL ; } - if (Tuner->IF_LO == 54000000UL) { + if (state->IF_LO == 54000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 324000000UL ; } - if (Tuner->IF_LO == 60000000UL) { + if (state->IF_LO == 60000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 39250000UL) { + if (state->IF_LO == 39250000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 314000000UL ; } - if (Tuner->IF_LO == 39650000UL) { + if (state->IF_LO == 39650000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 317200000UL ; } - if (Tuner->IF_LO == 40150000UL) { + if (state->IF_LO == 40150000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 321200000UL ; } - if (Tuner->IF_LO == 40650000UL) { + if (state->IF_LO == 40650000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 325200000UL ; } } - if (Tuner->Mode || (Tuner->Mode == 0 && Tuner->IF_Mode == 0)) + if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) { - if (Tuner->IF_LO == 57000000UL) { + if (state->IF_LO == 57000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 342000000UL ; } - if (Tuner->IF_LO == 44000000UL) { + if (state->IF_LO == 44000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352000000UL ; } - if (Tuner->IF_LO == 43750000UL) { + if (state->IF_LO == 43750000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 350000000UL ; } - if (Tuner->IF_LO == 36650000UL) { + if (state->IF_LO == 36650000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 366500000UL ; } - if (Tuner->IF_LO == 36150000UL) { + if (state->IF_LO == 36150000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 361500000UL ; } - if (Tuner->IF_LO == 36000000UL) { + if (state->IF_LO == 36000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 35250000UL) { + if (state->IF_LO == 35250000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352500000UL ; } - if (Tuner->IF_LO == 34750000UL) { + if (state->IF_LO == 34750000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 347500000UL ; } - if (Tuner->IF_LO == 6280000UL) { + if (state->IF_LO == 6280000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 376800000UL ; } - if (Tuner->IF_LO == 5000000UL) { + if (state->IF_LO == 5000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 4500000UL) { + if (state->IF_LO == 4500000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 4570000UL) { + if (state->IF_LO == 4570000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 365600000UL ; } - if (Tuner->IF_LO == 4000000UL) { + if (state->IF_LO == 4000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 57400000UL) + if (state->IF_LO == 57400000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 344400000UL ; } - if (Tuner->IF_LO == 44400000UL) + if (state->IF_LO == 44400000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 355200000UL ; } - if (Tuner->IF_LO == 44150000UL) + if (state->IF_LO == 44150000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 353200000UL ; } - if (Tuner->IF_LO == 37050000UL) + if (state->IF_LO == 37050000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 370500000UL ; } - if (Tuner->IF_LO == 36550000UL) + if (state->IF_LO == 36550000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 365500000UL ; } - if (Tuner->IF_LO == 36125000UL) { + if (state->IF_LO == 36125000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 361250000UL ; } - if (Tuner->IF_LO == 6000000UL) { + if (state->IF_LO == 6000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 5400000UL) + if (state->IF_LO == 5400000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 324000000UL ; } - if (Tuner->IF_LO == 5380000UL) { + if (state->IF_LO == 5380000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 322800000UL ; } - if (Tuner->IF_LO == 5200000UL) { + if (state->IF_LO == 5200000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 374400000UL ; } - if (Tuner->IF_LO == 4900000UL) + if (state->IF_LO == 4900000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352800000UL ; } - if (Tuner->IF_LO == 4400000UL) + if (state->IF_LO == 4400000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352000000UL ; } - if (Tuner->IF_LO == 4063000UL) //add for 2.6.8 + if (state->IF_LO == 4063000UL) //add for 2.6.8 { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; @@ -2542,7 +2637,7 @@ u32 MXL_GetXtalInt(u32 Xtal_Freq) /////////////////////////////////////////////////////////////////////////////// u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; // Declare Local Variables u16 status = 0; u32 divider_val, E3, E4, E5, E5A; @@ -3034,7 +3129,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) // // Off Chip Tracking Filter Control // - if (Tuner->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks + if (state->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks { status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; @@ -3044,7 +3139,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_SetGPIO(fe, 4, 1) ; // turn off Bank 3 } - if (Tuner->TF_Type == MXL_TF_C) // Tracking Filter type C + if (state->TF_Type == MXL_TF_C) // Tracking Filter type C { status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; @@ -3124,7 +3219,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only + if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only { status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; @@ -3194,7 +3289,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_D) // Tracking Filter type D + if (state->TF_Type == MXL_TF_D) // Tracking Filter type D { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3251,7 +3346,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } - if (Tuner->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 + if (state->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 { status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; @@ -3336,7 +3431,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_E) // Tracking Filter type E + if (state->TF_Type == MXL_TF_E) // Tracking Filter type E { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3392,7 +3487,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_F) // Tracking Filter type F + if (state->TF_Type == MXL_TF_F) // Tracking Filter type F { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3448,7 +3543,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 + if (state->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3504,7 +3599,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 + if (state->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3567,7 +3662,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 + if (state->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3667,7 +3762,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) // DONE u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; if (GPIO_Num == 1) @@ -3735,14 +3829,13 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) // DONE u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; /* Will write ALL Matching Control Name */ - status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control * - status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control * + status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control */ + status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control */ #ifdef _MXL_INTERNAL - status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control * + status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control */ #endif return status; } @@ -3777,7 +3870,7 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) // DONE u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 i, j, k; u32 highLimit; u32 ctrlVal; @@ -3884,7 +3977,7 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u // DONE u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; int i ; for (i = 0; i < 104; i++) { @@ -3924,7 +4017,7 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) // DONE u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; int i ; for (i = 0; i < 104; i++) { @@ -3959,9 +4052,9 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) // // /////////////////////////////////////////////////////////////////////////////// // DONE -u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 * value) +u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u32 ctrlVal ; u16 i, k ; @@ -4033,7 +4126,7 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 * value) // DONE u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 i, j, k ; u16 Count ; @@ -4139,7 +4232,7 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int // DONE void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; int i ; const u8 AND_MAP[8] = { @@ -4196,7 +4289,6 @@ u32 MXL_Ceiling(u32 value, u32 resolution) // DONE u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i ; @@ -4220,7 +4312,6 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c // DONE u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i ; @@ -4249,7 +4340,6 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou // DONE u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i; @@ -4268,7 +4358,6 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i // DONE u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i; @@ -4302,7 +4391,7 @@ u16 MXL_GetMasterControl(u8 *MasterReg, int state) #ifdef _MXL_PRODUCTION u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0 ; if (VCO_Range == 1) { @@ -4432,7 +4521,7 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) // DONE u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; if (Hystersis == 1) @@ -4443,3 +4532,194 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) #endif +/* Linux driver related functions */ + + +int mxl5005s_init2(struct dvb_frontend *fe) +{ + int MxlModMode; + int MxlIfMode; + unsigned long MxlBandwitdh; + unsigned long MxlIfFreqHz; + unsigned long MxlCrystalFreqHz; + int MxlAgcMode; + unsigned short MxlTop; + unsigned short MxlIfOutputLoad; + int MxlClockOut; + int MxlDivOut; + int MxlCapSel; + int MxlRssiOnOff; + unsigned char MxlStandard; + unsigned char MxlTfType; + + /* Set MxL5005S parameters. */ + MxlModMode = MXL_DIGITAL_MODE; + MxlIfMode = MXL_ZERO_IF; +// steve + //MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; + //MxlIfFreqHz = IF_FREQ_4570000HZ; + MxlBandwitdh = MXL5005S_BANDWIDTH_6MHZ; // config + MxlIfFreqHz = IF_FREQ_5380000HZ; // config + MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; // config + MxlAgcMode = MXL_SINGLE_AGC; + MxlTop = MXL5005S_TOP_25P2; + MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; + MxlClockOut = MXL_CLOCK_OUT_DISABLE; + MxlDivOut = MXL_DIV_OUT_4; + MxlCapSel = MXL_CAP_SEL_ENABLE; + MxlRssiOnOff = MXL_RSSI_ENABLE; // config + MxlTfType = MXL_TF_C_H; // config + + MxlStandard = MXL_ATSC; // config + + // TODO: this is bad, it trashes other configs + // Set MxL5005S extra module. + //pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; + + MXL5005_TunerConfig( + fe, + (unsigned char)MxlModMode, + (unsigned char)MxlIfMode, + MxlBandwitdh, + MxlIfFreqHz, + MxlCrystalFreqHz, + (unsigned char)MxlAgcMode, + MxlTop, + MxlIfOutputLoad, + (unsigned char)MxlClockOut, + (unsigned char)MxlDivOut, + (unsigned char)MxlCapSel, + (unsigned char)MxlRssiOnOff, + MxlStandard, MxlTfType); + + return 0; +} + +static int mxl5005s_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + u32 freq; + u32 bw; + + if (fe->ops.info.type == FE_OFDM) + bw = params->u.ofdm.bandwidth; + else + bw = MXL5005S_BANDWIDTH_6MHZ; + + freq = params->frequency; /* Hz */ + dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw); + + return mxl5005s_SetRfFreqHz(fe, freq); +} + +static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct mxl5005s_state *state = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); + + *frequency = state->RF_IN; + + return 0; +} + +static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +{ + struct mxl5005s_state *state = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); + + *bandwidth = state->Chan_Bandwidth; + + return 0; +} + +static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status) +{ + dprintk(1, "%s()\n", __func__); + + *status = 0; + // *status = TUNER_STATUS_LOCKED; + + return 0; +} + +static int mxl5005s_init(struct dvb_frontend *fe) +{ + struct mxl5005s_state *state = fe->tuner_priv; + u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + int TableLen; + + dprintk(1, "%s()\n", __func__); + + /* Initialize MxL5005S tuner according to MxL5005S tuner example code. */ + + /* Tuner initialization stage 0 */ + MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); + AddrTable[0] = MASTER_CONTROL_ADDR; + ByteTable[0] |= state->config->AgcMasterByte; + + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + + /* Tuner initialization stage 1 */ + MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); + + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + + return mxl5005s_init2(fe); +} + +static int mxl5005s_release(struct dvb_frontend *fe) +{ + dprintk(1, "%s()\n", __func__); + kfree(fe->tuner_priv); + fe->tuner_priv = NULL; + return 0; +} + +static const struct dvb_tuner_ops mxl5005s_tuner_ops = { + .info = { + .name = "MaxLinear MXL5005S", + .frequency_min = 48000000, + .frequency_max = 860000000, + .frequency_step = 50000, + }, + + .release = mxl5005s_release, + .init = mxl5005s_init, + + .set_params = mxl5005s_set_params, + .get_frequency = mxl5005s_get_frequency, + .get_bandwidth = mxl5005s_get_bandwidth, + .get_status = mxl5005s_get_status +}; + +struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct mxl5005s_config *config) +{ + struct mxl5005s_state *state = NULL; + dprintk(1, "%s()\n", __func__); + + state = kzalloc(sizeof(struct mxl5005s_state), GFP_KERNEL); + if (state == NULL) + return NULL; + + state->frontend = fe; + state->config = config; + state->i2c = i2c; + + printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address); + + memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops, sizeof(struct dvb_tuner_ops)); + + fe->tuner_priv = state; + return fe; +} +EXPORT_SYMBOL(mxl5005s_attach); + +MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver"); +MODULE_AUTHOR("Jan Hoogenraad"); +MODULE_AUTHOR("Barnaby Shearer"); +MODULE_AUTHOR("Andy Hasper"); +MODULE_AUTHOR("Steven Toth"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 8c66a19d45fb5b88abf10678db353f35179a2cde Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 06:35:48 -0300 Subject: V4L/DVB (7868): mxl5005s: Cleanup #5 Cleanup #5 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 304 +++++++++++---------------------- 1 file changed, 103 insertions(+), 201 deletions(-) (limited to 'drivers/media/common/tuners/mxl5005s.c') diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 7e687171301b..aad88d5c0dc2 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -24,10 +24,10 @@ #include "mxl5005s.h" -static int debug; +static int debug = 2; #define dprintk(level, arg...) do { \ - if (debug >= level) \ + if (level <= debug) \ printk(arg); \ } while (0) @@ -43,13 +43,6 @@ static int debug; #define MXLCTRL_NUM 189 #define MASTER_CONTROL_ADDR 9 -/* Enumeration of AGC Mode */ -typedef enum -{ - MXL_DUAL_AGC = 0, - MXL_SINGLE_AGC -} AGC_Mode; - /* Enumeration of Master Control Register State */ typedef enum { @@ -59,51 +52,6 @@ typedef enum MC_SEQ_OFF } Master_Control_State; -/* Enumeration of MXL5005 Tuner Mode */ -typedef enum -{ - MXL_ANALOG_MODE = 0, - MXL_DIGITAL_MODE -} Tuner_Mode; - -/* Enumeration of MXL5005 Tuner IF Mode */ -typedef enum -{ - MXL_ZERO_IF = 0, - MXL_LOW_IF -} Tuner_IF_Mode; - -/* Enumeration of MXL5005 Tuner Clock Out Mode */ -typedef enum -{ - MXL_CLOCK_OUT_DISABLE = 0, - MXL_CLOCK_OUT_ENABLE -} Tuner_Clock_Out; - -/* Enumeration of MXL5005 Tuner Div Out Mode */ -typedef enum -{ - MXL_DIV_OUT_1 = 0, - MXL_DIV_OUT_4 - -} Tuner_Div_Out; - -/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */ -typedef enum -{ - MXL_CAP_SEL_DISABLE = 0, - MXL_CAP_SEL_ENABLE - -} Tuner_Cap_Select; - -/* Enumeration of MXL5005 Tuner RSSI Mode */ -typedef enum -{ - MXL_RSSI_DISABLE = 0, - MXL_RSSI_ENABLE - -} Tuner_RSSI; - /* Enumeration of MXL5005 Tuner Modulation Type */ typedef enum { @@ -115,22 +63,6 @@ typedef enum MXL_ANALOG_OTA } Tuner_Modu_Type; -/* Enumeration of MXL5005 Tuner Tracking Filter Type */ -typedef enum -{ - MXL_TF_DEFAULT = 0, - MXL_TF_OFF, - MXL_TF_C, - MXL_TF_C_H, - MXL_TF_D, - MXL_TF_D_L, - MXL_TF_E, - MXL_TF_F, - MXL_TF_E_2, - MXL_TF_E_NA, - MXL_TF_G -} Tuner_TF_Type; - /* MXL5005 Tuner Register Struct */ typedef struct _TunerReg_struct { @@ -261,33 +193,6 @@ enum }; #define MXL5005S_BANDWIDTH_MODE_NUM 3 -/* Top modes */ -enum -{ - MXL5005S_TOP_5P5 = 55, - MXL5005S_TOP_7P2 = 72, - MXL5005S_TOP_9P2 = 92, - MXL5005S_TOP_11P0 = 110, - MXL5005S_TOP_12P9 = 129, - MXL5005S_TOP_14P7 = 147, - MXL5005S_TOP_16P8 = 168, - MXL5005S_TOP_19P4 = 194, - MXL5005S_TOP_21P2 = 212, - MXL5005S_TOP_23P2 = 232, - MXL5005S_TOP_25P2 = 252, - MXL5005S_TOP_27P1 = 271, - MXL5005S_TOP_29P2 = 292, - MXL5005S_TOP_31P7 = 317, - MXL5005S_TOP_34P9 = 349, -}; - -/* IF output load */ -enum -{ - MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, - MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, -}; - /* MXL5005 Tuner Control Struct */ typedef struct _TunerControl_struct { u16 Ctrl_Num; /* Control Number */ @@ -342,8 +247,7 @@ struct mxl5005s_state TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ /* Linux driver framework specific */ - const struct mxl5005s_config *config; - + struct mxl5005s_config *config; struct dvb_frontend *frontend; struct i2c_adapter *i2c; }; @@ -367,11 +271,11 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen); u16 MXL_IFSynthInit(struct dvb_frontend *fe); +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe); int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { struct mxl5005s_state *state = fe->tuner_priv; - u8 AgcMasterByte = state->config->AgcMasterByte; unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; @@ -402,13 +306,13 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | AgcMasterByte; + ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte; TableLen += 1; mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); // Wait 30 ms. - msleep(30); + msleep(150); // Tuner RF frequency setting stage 2 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ; @@ -417,39 +321,56 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | AgcMasterByte ; + ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ; TableLen += 1; mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + msleep(100); + return 0; } -/* Write a single byte to a single reg */ -static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val) +static int mxl5005s_reset(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[2] = { reg, val }; + int ret = 0; + + u8 buf[2] = { 0xff, 0x00 }; struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, .buf = buf, .len = 2 }; + dprintk(2, "%s()\n", __func__); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write failed\n"); - return -EREMOTEIO; + printk(KERN_WARNING "mxl5005s I2C reset failed\n"); + ret = -EREMOTEIO; } - return 0; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return ret; } -/* Write a word to a single reg */ -static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val) +/* Write a single byte to a single reg */ +static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) { struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[3] = { reg, val >> 8 , val & 0xff }; + u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, .buf = buf, .len = 3 }; + if(latch == 0) + msg.len = 2; + + dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); + if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write16 failed\n"); + printk(KERN_WARNING "mxl5005s I2C write failed\n"); return -EREMOTEIO; } return 0; @@ -457,20 +378,22 @@ static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val) int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen) { - int i, ret; - u8 end_two_bytes_buf[]={ 0 , 0 }; + int i, ret = 0; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); for( i = 0 ; i < TableLen - 1 ; i++) { - ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i]); - if (!ret) - return ret; + ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i], 0); + if (ret < 0) + break; } - end_two_bytes_buf[0] = pByteTable[i]; - end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE; + ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i], 1); - ret = mxl5005s_writereg16(fe, pAddrTable[i], (end_two_bytes_buf[0] << 8) | end_two_bytes_buf[1]); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); return ret; } @@ -509,6 +432,7 @@ int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1); } + // The following context is source code provided by MaxLinear. // MaxLinear source code - MXL5005_Initialize.cpp // DONE @@ -2034,6 +1958,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); break; case 6000000: + printk("%s() doing 6MHz digital\n", __func__); status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); break; } @@ -2064,7 +1989,6 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) else /* Single AGC Mode Dig Ana */ status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); - if (state->TOP == 55) /* TOP == 5.5 */ status += MXL_ControlWrite(fe, AGC_IF, 0x0); @@ -2294,6 +2218,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_IQSWAP, 0); else /* High IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 1); + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2); + } if (state->Mod_Type == MXL_ANALOG_CABLE) { /* Analog Cable Mode */ @@ -2330,7 +2256,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } /* RSSI disable */ - if(state->EN_RSSI==0) { + if(state->EN_RSSI == 0) { status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); @@ -2539,6 +2465,7 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe) Fref = 324000000UL ; } if (state->IF_LO == 5380000UL) { + printk("%s() doing 5.38\n", __func__); status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 322800000UL ; @@ -3221,6 +3148,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only { + printk("%s() CH filter\n", __func__); status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) @@ -4534,63 +4462,59 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) /* Linux driver related functions */ +int mxl5005s_init(struct dvb_frontend *fe) +{ + struct mxl5005s_state *state = fe->tuner_priv; + + u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + int TableLen; + + dprintk(1, "%s()\n", __func__); + + mxl5005s_reset(fe); + + /* Tuner initialization stage 0 */ + MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); + AddrTable[0] = MASTER_CONTROL_ADDR; + ByteTable[0] |= state->config->AgcMasterByte; -int mxl5005s_init2(struct dvb_frontend *fe) + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + + mxl5005s_AssignTunerMode(fe); // tunre_config + + /* Tuner initialization stage 1 */ + MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); + + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + + return 0; +} + +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe) { - int MxlModMode; - int MxlIfMode; - unsigned long MxlBandwitdh; - unsigned long MxlIfFreqHz; - unsigned long MxlCrystalFreqHz; - int MxlAgcMode; - unsigned short MxlTop; - unsigned short MxlIfOutputLoad; - int MxlClockOut; - int MxlDivOut; - int MxlCapSel; - int MxlRssiOnOff; - unsigned char MxlStandard; - unsigned char MxlTfType; + struct mxl5005s_state *state = fe->tuner_priv; + struct mxl5005s_config *c = state->config; - /* Set MxL5005S parameters. */ - MxlModMode = MXL_DIGITAL_MODE; - MxlIfMode = MXL_ZERO_IF; -// steve - //MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; - //MxlIfFreqHz = IF_FREQ_4570000HZ; - MxlBandwitdh = MXL5005S_BANDWIDTH_6MHZ; // config - MxlIfFreqHz = IF_FREQ_5380000HZ; // config - MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; // config - MxlAgcMode = MXL_SINGLE_AGC; - MxlTop = MXL5005S_TOP_25P2; - MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; - MxlClockOut = MXL_CLOCK_OUT_DISABLE; - MxlDivOut = MXL_DIV_OUT_4; - MxlCapSel = MXL_CAP_SEL_ENABLE; - MxlRssiOnOff = MXL_RSSI_ENABLE; // config - MxlTfType = MXL_TF_C_H; // config - - MxlStandard = MXL_ATSC; // config - - // TODO: this is bad, it trashes other configs - // Set MxL5005S extra module. - //pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; + InitTunerControls(fe); + /* Set MxL5005S parameters. */ MXL5005_TunerConfig( fe, - (unsigned char)MxlModMode, - (unsigned char)MxlIfMode, - MxlBandwitdh, - MxlIfFreqHz, - MxlCrystalFreqHz, - (unsigned char)MxlAgcMode, - MxlTop, - MxlIfOutputLoad, - (unsigned char)MxlClockOut, - (unsigned char)MxlDivOut, - (unsigned char)MxlCapSel, - (unsigned char)MxlRssiOnOff, - MxlStandard, MxlTfType); + c->mod_mode, + c->if_mode, + MXL5005S_BANDWIDTH_6MHZ, + c->if_freq, + c->xtal_freq, + c->agc_mode, + c->top, + c->output_load, + c->clock_out, + c->div_out, + c->cap_select, + c->rssi_enable, + MXL_QAM, + c->tracking_filter); return 0; } @@ -4609,7 +4533,11 @@ static int mxl5005s_set_params(struct dvb_frontend *fe, freq = params->frequency; /* Hz */ dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw); - return mxl5005s_SetRfFreqHz(fe, freq); + mxl5005s_SetRfFreqHz(fe, freq); + + msleep(350); + + return 0; } static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) @@ -4642,32 +4570,6 @@ static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status) return 0; } -static int mxl5005s_init(struct dvb_frontend *fe) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; - u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; - int TableLen; - - dprintk(1, "%s()\n", __func__); - - /* Initialize MxL5005S tuner according to MxL5005S tuner example code. */ - - /* Tuner initialization stage 0 */ - MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); - AddrTable[0] = MASTER_CONTROL_ADDR; - ByteTable[0] |= state->config->AgcMasterByte; - - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); - - /* Tuner initialization stage 1 */ - MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); - - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); - - return mxl5005s_init2(fe); -} - static int mxl5005s_release(struct dvb_frontend *fe) { dprintk(1, "%s()\n", __func__); -- cgit v1.2.3 From 7f5c3affef2883f49e820db62413e1dff1d4cebb Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 06:51:36 -0300 Subject: V4L/DVB(7869): mxl5005s: Cleanup #6 Cleanup #6 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 414 ++++++++++++++++++--------------- 1 file changed, 225 insertions(+), 189 deletions(-) (limited to 'drivers/media/common/tuners/mxl5005s.c') diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index aad88d5c0dc2..f7ed9a72db4a 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -1,26 +1,62 @@ /* - * For the Realtek RTL chip RTL2831U - * Realtek Release Date: 2008-03-14, ver 080314 - * Realtek version RTL2831 Linux driver version 080314 - * ver 080314 - * - * for linux kernel version 2.6.21.4 - 2.6.22-14 - * support MXL5005s and MT2060 tuners (support tuner auto-detecting) - * support two IR types -- RC5 and NEC - * - * Known boards with Realtek RTL chip RTL2821U - * Freecom USB stick 14aa:0160 (version 4) - * Conceptronic CTVDIGRCU - * - * Copyright (c) 2008 Realtek - * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper - * This code is placed under the terms of the GNU General Public License - * - * Released by Realtek under GPLv2. - * Thanks to Realtek for a lot of support we received ! - * - * Revision: 080314 - original version - */ + MaxLinear MXL5005S VSB/QAM/DVBT tuner driver + + Copyright (C) 2008 MaxLinear + Copyright (C) 2006 Steven Toth + Functions: + mxl5005s_reset() + mxl5005s_writereg() + mxl5005s_writeregs() + mxl5005s_init() + mxl5005s_reconfigure() + mxl5005s_AssignTunerMode() + mxl5005s_set_params() + mxl5005s_get_frequency() + mxl5005s_get_bandwidth() + mxl5005s_release() + mxl5005s_attach() + + Copyright (c) 2008 Realtek + Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + Functions: + mxl5005s_SetRfFreqHz() + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + +*/ + +/* + History of this driver (Steven Toth): + I was given a public release of a linux driver that included + support for the MaxLinear MXL5005S silicon tuner. Analysis of + the tuner driver showed clearly three things. + + 1. The tuner driver didn't support the LinuxTV tuner API + so the code Realtek added had to be removed. + + 2. A significant amount of the driver is reference driver code + from MaxLinear, I felt it was important to identify and + preserve this. + + 3. New code has to be added to interface correctly with the + LinuxTV API, as a regular kernel module. + + Other than the reference driver enum's, I've clearly marked + sections of the code and retained the copyright of the + respective owners. +*/ #include "mxl5005s.h" @@ -250,9 +286,12 @@ struct mxl5005s_state struct mxl5005s_config *config; struct dvb_frontend *frontend; struct i2c_adapter *i2c; + + /* Cache values */ + u32 current_mode; + }; -// funcs u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); u16 MXL_GetMasterControl(u8 *MasterReg, int state); @@ -269,9 +308,22 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen); +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len); u16 MXL_IFSynthInit(struct dvb_frontend *fe); -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe); +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); +int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); + +/* ---------------------------------------------------------------- + * Begin: Custom code salvaged from the Realtek driver. + * Copyright (c) 2008 Realtek + * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * This code is placed under the terms of the GNU General Public License + * + * Released by Realtek under GPLv2. + * Thanks to Realtek for a lot of support we received ! + * + * Revision: 080314 - original version + */ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { @@ -292,7 +344,7 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); // Tuner RF frequency setting stage 1 MXL_TuneRF(fe, RfFreqHz); @@ -309,7 +361,7 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte; TableLen += 1; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); // Wait 30 ms. msleep(150); @@ -324,118 +376,18 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ; TableLen += 1; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); msleep(100); return 0; } +/* End: Custom code taken from the Realtek driver */ -static int mxl5005s_reset(struct dvb_frontend *fe) -{ - struct mxl5005s_state *state = fe->tuner_priv; - int ret = 0; - - u8 buf[2] = { 0xff, 0x00 }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 2 }; - - dprintk(2, "%s()\n", __func__); - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C reset failed\n"); - ret = -EREMOTEIO; - } - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - - return ret; -} - -/* Write a single byte to a single reg */ -static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 3 }; - - if(latch == 0) - msg.len = 2; - - dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); - - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write failed\n"); - return -EREMOTEIO; - } - return 0; -} - -int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen) -{ - int i, ret = 0; - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - - for( i = 0 ; i < TableLen - 1 ; i++) - { - ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i], 0); - if (ret < 0) - break; - } - - ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i], 1); - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - - return ret; -} - -int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, - unsigned char RegAddr, - unsigned char Msb, - unsigned char Lsb, - const unsigned char WritingValue - ) -{ - int i; - - unsigned char Mask; - unsigned char Shift; - unsigned char RegByte; - - /* Generate mask and shift according to MSB and LSB. */ - Mask = 0; - for(i = Lsb; i < (unsigned char)(Msb + 1); i++) - Mask |= 0x1 << i; - - Shift = Lsb; - - /* Get tuner register byte according to register adddress. */ - MXL_RegRead(fe, RegAddr, &RegByte); - - /* Reserve register byte unmask bit with mask and inlay writing value into it. */ - RegByte &= ~Mask; - RegByte |= (WritingValue << Shift) & Mask; - - /* Update tuner register byte table. */ - MXL_RegWrite(fe, RegAddr, RegByte); - - /* Write tuner register byte with writing byte. */ - return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1); -} - - -// The following context is source code provided by MaxLinear. -// MaxLinear source code - MXL5005_Initialize.cpp -// DONE +/* ---------------------------------------------------------------- + * Begin: Reference driver code found in the Realtek driver. + * Copyright (c) 2008 MaxLinear + */ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -757,7 +709,6 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) return 0 ; } -// DONE u16 MXL5005_ControlInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1701,7 +1652,6 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) // MaxLinear source code - MXL5005_c.cpp // MXL5005.cpp : Defines the initialization routines for the DLL. // 2.6.12 -// DONE void InitTunerControls(struct dvb_frontend *fe) { MXL5005_RegisterInit(fe); @@ -1744,7 +1694,6 @@ void InitTunerControls(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL5005_TunerConfig(struct dvb_frontend *fe, u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ @@ -1814,7 +1763,6 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1853,7 +1801,6 @@ void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1892,7 +1839,6 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { u16 status = 0; @@ -1930,7 +1876,6 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_BlockInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3687,7 +3632,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) return status ; } -// DONE u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { u16 status = 0; @@ -3754,7 +3698,6 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) // >0 : Value exceed maximum allowed for control number // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { u16 status = 0; @@ -3795,7 +3738,6 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) // 2 : Control name not found // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3902,7 +3844,6 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3942,7 +3883,6 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3979,7 +3919,6 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4051,7 +3990,6 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4157,7 +4095,6 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int // NONE // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4205,7 +4142,6 @@ void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) // Computed value // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u32 MXL_Ceiling(u32 value, u32 resolution) { return (value/resolution + (value % resolution > 0 ? 1 : 0)); @@ -4214,7 +4150,6 @@ u32 MXL_Ceiling(u32 value, u32 resolution) // // Retrieve the Initialzation Registers // -// DONE u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4237,7 +4172,6 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c return status; } -// DONE u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4265,7 +4199,6 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou return status; } -// DONE u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4283,7 +4216,6 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i return status; } -// DONE u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4301,7 +4233,6 @@ u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, in return status; } -// DONE u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) /* Load_Start */ @@ -4446,7 +4377,6 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) return status; } -// DONE u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4457,12 +4387,91 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) return status; } - #endif +/* End: Reference driver code found in the Realtek driver that + * is copyright MaxLinear */ + +/* ---------------------------------------------------------------- + * Begin: Everything after here is new code to adapt the + * proprietary Realtek driver into a Linux API tuner. + * Copyright (C) 2008 Steven Toth + */ +static int mxl5005s_reset(struct dvb_frontend *fe) +{ + struct mxl5005s_state *state = fe->tuner_priv; + int ret = 0; + + u8 buf[2] = { 0xff, 0x00 }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 2 }; + + dprintk(2, "%s()\n", __func__); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C reset failed\n"); + ret = -EREMOTEIO; + } + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return ret; +} + +/* Write a single byte to a single reg, latch the value if required by + * following the transaction with the latch byte. + */ +static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) +{ + struct mxl5005s_state *state = fe->tuner_priv; + u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 3 }; + + if (latch == 0) + msg.len = 2; + + dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write failed\n"); + return -EREMOTEIO; + } + return 0; +} + +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len) +{ + int ret = 0, i; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + for (i = 0 ; i < len-1; i++) { + ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0); + if (ret < 0) + break; + } + + ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return ret; +} -/* Linux driver related functions */ int mxl5005s_init(struct dvb_frontend *fe) +{ + dprintk(1, "%s()\n", __func__); + return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ); +} + +int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4470,7 +4479,7 @@ int mxl5005s_init(struct dvb_frontend *fe) u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - dprintk(1, "%s()\n", __func__); + dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth); mxl5005s_reset(fe); @@ -4479,19 +4488,19 @@ int mxl5005s_init(struct dvb_frontend *fe) AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); - mxl5005s_AssignTunerMode(fe); // tunre_config + mxl5005s_AssignTunerMode(fe, mod_type, bandwidth); /* Tuner initialization stage 1 */ MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); return 0; } -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe) +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; struct mxl5005s_config *c = state->config; @@ -4503,7 +4512,7 @@ int mxl5005s_AssignTunerMode(struct dvb_frontend *fe) fe, c->mod_mode, c->if_mode, - MXL5005S_BANDWIDTH_6MHZ, + bandwidth, c->if_freq, c->xtal_freq, c->agc_mode, @@ -4513,7 +4522,7 @@ int mxl5005s_AssignTunerMode(struct dvb_frontend *fe) c->div_out, c->cap_select, c->rssi_enable, - MXL_QAM, + mod_type, c->tracking_filter); return 0; @@ -4522,22 +4531,62 @@ int mxl5005s_AssignTunerMode(struct dvb_frontend *fe) static int mxl5005s_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) { - u32 freq; - u32 bw; + struct mxl5005s_state *state = fe->tuner_priv; + u32 req_mode, req_bw = 0; + int ret; - if (fe->ops.info.type == FE_OFDM) - bw = params->u.ofdm.bandwidth; - else - bw = MXL5005S_BANDWIDTH_6MHZ; + dprintk(1, "%s()\n", __func__); + + if (fe->ops.info.type == FE_ATSC) { + switch (params->u.vsb.modulation) { + case VSB_8: + req_mode = MXL_ATSC; break; + default: + case QAM_64: + case QAM_256: + case QAM_AUTO: + req_mode = MXL_QAM; break; + } + } + else req_mode = MXL_DVBT; + + /* Change tuner for new modulation type if reqd */ + if (req_mode != state->current_mode) { + switch (req_mode) { + case VSB_8: + case QAM_64: + case QAM_256: + case QAM_AUTO: + req_bw = MXL5005S_BANDWIDTH_6MHZ; + break; + default: + /* Assume DVB-T */ + switch (params->u.ofdm.bandwidth) { + case BANDWIDTH_6_MHZ: + req_bw = MXL5005S_BANDWIDTH_6MHZ; + break; + case BANDWIDTH_7_MHZ: + req_bw = MXL5005S_BANDWIDTH_7MHZ; + break; + case BANDWIDTH_AUTO: + case BANDWIDTH_8_MHZ: + req_bw = MXL5005S_BANDWIDTH_8MHZ; + break; + } + } - freq = params->frequency; /* Hz */ - dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw); + state->current_mode = req_mode; + ret = mxl5005s_reconfigure(fe, req_mode, req_bw); - mxl5005s_SetRfFreqHz(fe, freq); + } else + ret = 0; - msleep(350); + if (ret == 0) { + dprintk(1, "%s() freq=%d\n", __func__, params->frequency); + ret = mxl5005s_SetRfFreqHz(fe, params->frequency); + } - return 0; + return ret; } static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) @@ -4560,16 +4609,6 @@ static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) return 0; } -static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status) -{ - dprintk(1, "%s()\n", __func__); - - *status = 0; - // *status = TUNER_STATUS_LOCKED; - - return 0; -} - static int mxl5005s_release(struct dvb_frontend *fe) { dprintk(1, "%s()\n", __func__); @@ -4592,7 +4631,6 @@ static const struct dvb_tuner_ops mxl5005s_tuner_ops = { .set_params = mxl5005s_set_params, .get_frequency = mxl5005s_get_frequency, .get_bandwidth = mxl5005s_get_bandwidth, - .get_status = mxl5005s_get_status }; struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, @@ -4609,6 +4647,7 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, state->frontend = fe; state->config = config; state->i2c = i2c; + state->current_mode = MXL_QAM; printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address); @@ -4620,8 +4659,5 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, EXPORT_SYMBOL(mxl5005s_attach); MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver"); -MODULE_AUTHOR("Jan Hoogenraad"); -MODULE_AUTHOR("Barnaby Shearer"); -MODULE_AUTHOR("Andy Hasper"); MODULE_AUTHOR("Steven Toth"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 5c1b20514f592af19974166f130b85346c1fbf3a Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 07:04:09 -0300 Subject: V4L/DVB (7870): mxl5005s: Basic digital support. ATSC and QAM should be working but basic testing is required. Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 616 ++++++++++++++++++--------------- 1 file changed, 343 insertions(+), 273 deletions(-) (limited to 'drivers/media/common/tuners/mxl5005s.c') diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index f7ed9a72db4a..64aa864c5dbf 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -1,69 +1,40 @@ /* - MaxLinear MXL5005S VSB/QAM/DVBT tuner driver - - Copyright (C) 2008 MaxLinear - Copyright (C) 2006 Steven Toth - Functions: - mxl5005s_reset() - mxl5005s_writereg() - mxl5005s_writeregs() - mxl5005s_init() - mxl5005s_reconfigure() - mxl5005s_AssignTunerMode() - mxl5005s_set_params() - mxl5005s_get_frequency() - mxl5005s_get_bandwidth() - mxl5005s_release() - mxl5005s_attach() - - Copyright (c) 2008 Realtek - Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper - Functions: - mxl5005s_SetRfFreqHz() - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - -*/ - -/* - History of this driver (Steven Toth): - I was given a public release of a linux driver that included - support for the MaxLinear MXL5005S silicon tuner. Analysis of - the tuner driver showed clearly three things. - - 1. The tuner driver didn't support the LinuxTV tuner API - so the code Realtek added had to be removed. - - 2. A significant amount of the driver is reference driver code - from MaxLinear, I felt it was important to identify and - preserve this. - - 3. New code has to be added to interface correctly with the - LinuxTV API, as a regular kernel module. - - Other than the reference driver enum's, I've clearly marked - sections of the code and retained the copyright of the - respective owners. -*/ + * For the Realtek RTL chip RTL2831U + * Realtek Release Date: 2008-03-14, ver 080314 + * Realtek version RTL2831 Linux driver version 080314 + * ver 080314 + * + * for linux kernel version 2.6.21.4 - 2.6.22-14 + * support MXL5005s and MT2060 tuners (support tuner auto-detecting) + * support two IR types -- RC5 and NEC + * + * Known boards with Realtek RTL chip RTL2821U + * Freecom USB stick 14aa:0160 (version 4) + * Conceptronic CTVDIGRCU + * + * Copyright (c) 2008 Realtek + * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * This code is placed under the terms of the GNU General Public License + * + * Released by Realtek under GPLv2. + * Thanks to Realtek for a lot of support we received ! + * + * Revision: 080314 - original version + */ +#include +#include +#include +#include +#include +#include +#include "dvb_frontend.h" #include "mxl5005s.h" -static int debug = 2; +static int debug; #define dprintk(level, arg...) do { \ - if (level <= debug) \ + if (debug >= level) \ printk(arg); \ } while (0) @@ -79,6 +50,13 @@ static int debug = 2; #define MXLCTRL_NUM 189 #define MASTER_CONTROL_ADDR 9 +/* Enumeration of AGC Mode */ +typedef enum +{ + MXL_DUAL_AGC = 0, + MXL_SINGLE_AGC +} AGC_Mode; + /* Enumeration of Master Control Register State */ typedef enum { @@ -88,6 +66,51 @@ typedef enum MC_SEQ_OFF } Master_Control_State; +/* Enumeration of MXL5005 Tuner Mode */ +typedef enum +{ + MXL_ANALOG_MODE = 0, + MXL_DIGITAL_MODE +} Tuner_Mode; + +/* Enumeration of MXL5005 Tuner IF Mode */ +typedef enum +{ + MXL_ZERO_IF = 0, + MXL_LOW_IF +} Tuner_IF_Mode; + +/* Enumeration of MXL5005 Tuner Clock Out Mode */ +typedef enum +{ + MXL_CLOCK_OUT_DISABLE = 0, + MXL_CLOCK_OUT_ENABLE +} Tuner_Clock_Out; + +/* Enumeration of MXL5005 Tuner Div Out Mode */ +typedef enum +{ + MXL_DIV_OUT_1 = 0, + MXL_DIV_OUT_4 + +} Tuner_Div_Out; + +/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */ +typedef enum +{ + MXL_CAP_SEL_DISABLE = 0, + MXL_CAP_SEL_ENABLE + +} Tuner_Cap_Select; + +/* Enumeration of MXL5005 Tuner RSSI Mode */ +typedef enum +{ + MXL_RSSI_DISABLE = 0, + MXL_RSSI_ENABLE + +} Tuner_RSSI; + /* Enumeration of MXL5005 Tuner Modulation Type */ typedef enum { @@ -99,6 +122,22 @@ typedef enum MXL_ANALOG_OTA } Tuner_Modu_Type; +/* Enumeration of MXL5005 Tuner Tracking Filter Type */ +typedef enum +{ + MXL_TF_DEFAULT = 0, + MXL_TF_OFF, + MXL_TF_C, + MXL_TF_C_H, + MXL_TF_D, + MXL_TF_D_L, + MXL_TF_E, + MXL_TF_F, + MXL_TF_E_2, + MXL_TF_E_NA, + MXL_TF_G +} Tuner_TF_Type; + /* MXL5005 Tuner Register Struct */ typedef struct _TunerReg_struct { @@ -229,6 +268,33 @@ enum }; #define MXL5005S_BANDWIDTH_MODE_NUM 3 +/* Top modes */ +enum +{ + MXL5005S_TOP_5P5 = 55, + MXL5005S_TOP_7P2 = 72, + MXL5005S_TOP_9P2 = 92, + MXL5005S_TOP_11P0 = 110, + MXL5005S_TOP_12P9 = 129, + MXL5005S_TOP_14P7 = 147, + MXL5005S_TOP_16P8 = 168, + MXL5005S_TOP_19P4 = 194, + MXL5005S_TOP_21P2 = 212, + MXL5005S_TOP_23P2 = 232, + MXL5005S_TOP_25P2 = 252, + MXL5005S_TOP_27P1 = 271, + MXL5005S_TOP_29P2 = 292, + MXL5005S_TOP_31P7 = 317, + MXL5005S_TOP_34P9 = 349, +}; + +/* IF output load */ +enum +{ + MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, + MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, +}; + /* MXL5005 Tuner Control Struct */ typedef struct _TunerControl_struct { u16 Ctrl_Num; /* Control Number */ @@ -283,15 +349,13 @@ struct mxl5005s_state TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ /* Linux driver framework specific */ - struct mxl5005s_config *config; + const struct mxl5005s_config *config; + struct dvb_frontend *frontend; struct i2c_adapter *i2c; - - /* Cache values */ - u32 current_mode; - }; +// funcs u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); u16 MXL_GetMasterControl(u8 *MasterReg, int state); @@ -308,26 +372,14 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len); +int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen); u16 MXL_IFSynthInit(struct dvb_frontend *fe); -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); -int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); - -/* ---------------------------------------------------------------- - * Begin: Custom code salvaged from the Realtek driver. - * Copyright (c) 2008 Realtek - * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper - * This code is placed under the terms of the GNU General Public License - * - * Released by Realtek under GPLv2. - * Thanks to Realtek for a lot of support we received ! - * - * Revision: 080314 - original version - */ +static int mxl5005s_init2(struct dvb_frontend *fe); int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { struct mxl5005s_state *state = fe->tuner_priv; + u8 AgcMasterByte = state->config->AgcMasterByte; unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; @@ -344,7 +396,7 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); // Tuner RF frequency setting stage 1 MXL_TuneRF(fe, RfFreqHz); @@ -358,13 +410,13 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte; + ByteTable[TableLen] = MasterControlByte | AgcMasterByte; TableLen += 1; - mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); // Wait 30 ms. - msleep(150); + msleep(30); // Tuner RF frequency setting stage 2 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ; @@ -373,21 +425,101 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ; + ByteTable[TableLen] = MasterControlByte | AgcMasterByte ; TableLen += 1; - mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); - msleep(100); + return 0; +} +/* Write a single byte to a single reg */ +static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val) +{ + struct mxl5005s_state *state = fe->tuner_priv; + u8 buf[2] = { reg, val }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 2 }; + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write failed\n"); + return -EREMOTEIO; + } return 0; } -/* End: Custom code taken from the Realtek driver */ -/* ---------------------------------------------------------------- - * Begin: Reference driver code found in the Realtek driver. - * Copyright (c) 2008 MaxLinear - */ +/* Write a word to a single reg */ +static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val) +{ + struct mxl5005s_state *state = fe->tuner_priv; + u8 buf[3] = { reg, val >> 8 , val & 0xff }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 3 }; + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write16 failed\n"); + return -EREMOTEIO; + } + return 0; +} + +int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen) +{ + int i, ret; + u8 end_two_bytes_buf[]={ 0 , 0 }; + + for( i = 0 ; i < TableLen - 1 ; i++) + { + ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i]); + if (!ret) + return ret; + } + + end_two_bytes_buf[0] = pByteTable[i]; + end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE; + + ret = mxl5005s_writereg16(fe, pAddrTable[i], (end_two_bytes_buf[0] << 8) | end_two_bytes_buf[1]); + + return ret; +} + +int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, + unsigned char RegAddr, + unsigned char Msb, + unsigned char Lsb, + const unsigned char WritingValue + ) +{ + int i; + + unsigned char Mask; + unsigned char Shift; + unsigned char RegByte; + + /* Generate mask and shift according to MSB and LSB. */ + Mask = 0; + for(i = Lsb; i < (unsigned char)(Msb + 1); i++) + Mask |= 0x1 << i; + + Shift = Lsb; + + /* Get tuner register byte according to register adddress. */ + MXL_RegRead(fe, RegAddr, &RegByte); + + /* Reserve register byte unmask bit with mask and inlay writing value into it. */ + RegByte &= ~Mask; + RegByte |= (WritingValue << Shift) & Mask; + + /* Update tuner register byte table. */ + MXL_RegWrite(fe, RegAddr, RegByte); + + /* Write tuner register byte with writing byte. */ + return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1); +} + +// The following context is source code provided by MaxLinear. +// MaxLinear source code - MXL5005_Initialize.cpp +// DONE u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -709,6 +841,7 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) return 0 ; } +// DONE u16 MXL5005_ControlInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1652,6 +1785,7 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) // MaxLinear source code - MXL5005_c.cpp // MXL5005.cpp : Defines the initialization routines for the DLL. // 2.6.12 +// DONE void InitTunerControls(struct dvb_frontend *fe) { MXL5005_RegisterInit(fe); @@ -1694,6 +1828,7 @@ void InitTunerControls(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL5005_TunerConfig(struct dvb_frontend *fe, u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ @@ -1763,6 +1898,7 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// +// DONE void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1801,6 +1937,7 @@ void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// +// DONE void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1839,6 +1976,7 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { u16 status = 0; @@ -1876,6 +2014,7 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_BlockInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1903,7 +2042,6 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); break; case 6000000: - printk("%s() doing 6MHz digital\n", __func__); status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); break; } @@ -1934,6 +2072,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) else /* Single AGC Mode Dig Ana */ status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); + if (state->TOP == 55) /* TOP == 5.5 */ status += MXL_ControlWrite(fe, AGC_IF, 0x0); @@ -2163,8 +2302,6 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_IQSWAP, 0); else /* High IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 1); - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2); - } if (state->Mod_Type == MXL_ANALOG_CABLE) { /* Analog Cable Mode */ @@ -2201,7 +2338,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } /* RSSI disable */ - if(state->EN_RSSI == 0) { + if(state->EN_RSSI==0) { status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); @@ -2410,7 +2547,6 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe) Fref = 324000000UL ; } if (state->IF_LO == 5380000UL) { - printk("%s() doing 5.38\n", __func__); status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 322800000UL ; @@ -3093,7 +3229,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only { - printk("%s() CH filter\n", __func__); status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) @@ -3632,6 +3767,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) return status ; } +// DONE u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { u16 status = 0; @@ -3698,6 +3834,7 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) // >0 : Value exceed maximum allowed for control number // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { u16 status = 0; @@ -3738,6 +3875,7 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) // 2 : Control name not found // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3844,6 +3982,7 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3883,6 +4022,7 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3919,6 +4059,7 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3990,6 +4131,7 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4095,6 +4237,7 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int // NONE // // // /////////////////////////////////////////////////////////////////////////////// +// DONE void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4142,6 +4285,7 @@ void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) // Computed value // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u32 MXL_Ceiling(u32 value, u32 resolution) { return (value/resolution + (value % resolution > 0 ? 1 : 0)); @@ -4150,6 +4294,7 @@ u32 MXL_Ceiling(u32 value, u32 resolution) // // Retrieve the Initialzation Registers // +// DONE u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4172,6 +4317,7 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c return status; } +// DONE u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4199,6 +4345,7 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou return status; } +// DONE u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4216,6 +4363,7 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i return status; } +// DONE u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4233,6 +4381,7 @@ u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, in return status; } +// DONE u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) /* Load_Start */ @@ -4377,6 +4526,7 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) return status; } +// DONE u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4387,224 +4537,141 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) return status; } + #endif -/* End: Reference driver code found in the Realtek driver that - * is copyright MaxLinear */ -/* ---------------------------------------------------------------- - * Begin: Everything after here is new code to adapt the - * proprietary Realtek driver into a Linux API tuner. - * Copyright (C) 2008 Steven Toth - */ -static int mxl5005s_reset(struct dvb_frontend *fe) +/* Linux driver related functions */ + + +int mxl5005s_init(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->tuner_priv; - int ret = 0; + int MxlModMode; + int MxlIfMode; + unsigned long MxlBandwitdh; + unsigned long MxlIfFreqHz; + unsigned long MxlCrystalFreqHz; + int MxlAgcMode; + unsigned short MxlTop; + unsigned short MxlIfOutputLoad; + int MxlClockOut; + int MxlDivOut; + int MxlCapSel; + int MxlRssiOnOff; + unsigned char MxlStandard; + unsigned char MxlTfType; - u8 buf[2] = { 0xff, 0x00 }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 2 }; + /* Set MxL5005S parameters. */ + MxlModMode = MXL_DIGITAL_MODE; + MxlIfMode = MXL_ZERO_IF; +// steve + //MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; + //MxlIfFreqHz = IF_FREQ_4570000HZ; + MxlBandwitdh = MXL5005S_BANDWIDTH_6MHZ; // config + MxlIfFreqHz = IF_FREQ_5380000HZ; // config + MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; // config + MxlAgcMode = MXL_SINGLE_AGC; + MxlTop = MXL5005S_TOP_25P2; + MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; + MxlClockOut = MXL_CLOCK_OUT_DISABLE; + MxlDivOut = MXL_DIV_OUT_4; + MxlCapSel = MXL_CAP_SEL_ENABLE; + MxlRssiOnOff = MXL_RSSI_ENABLE; // config + MxlTfType = MXL_TF_C_H; // config + + MxlStandard = MXL_ATSC; // config + + // TODO: this is bad, it trashes other configs + // Set MxL5005S extra module. + //pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; - dprintk(2, "%s()\n", __func__); + MXL5005_TunerConfig( + fe, + (unsigned char)MxlModMode, + (unsigned char)MxlIfMode, + MxlBandwitdh, + MxlIfFreqHz, + MxlCrystalFreqHz, + (unsigned char)MxlAgcMode, + MxlTop, + MxlIfOutputLoad, + (unsigned char)MxlClockOut, + (unsigned char)MxlDivOut, + (unsigned char)MxlCapSel, + (unsigned char)MxlRssiOnOff, + MxlStandard, MxlTfType); + + return mxl5005s_init2(fe); +} - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); +static int mxl5005s_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + u32 freq; + u32 bw; - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C reset failed\n"); - ret = -EREMOTEIO; - } + if (fe->ops.info.type == FE_OFDM) + bw = params->u.ofdm.bandwidth; + else + bw = MXL5005S_BANDWIDTH_6MHZ; - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + freq = params->frequency; /* Hz */ + dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw); - return ret; + return mxl5005s_SetRfFreqHz(fe, freq); } -/* Write a single byte to a single reg, latch the value if required by - * following the transaction with the latch byte. - */ -static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) +static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) { struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 3 }; - - if (latch == 0) - msg.len = 2; + dprintk(1, "%s()\n", __func__); - dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); + *frequency = state->RF_IN; - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write failed\n"); - return -EREMOTEIO; - } return 0; } -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len) +static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) { - int ret = 0, i; - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - - for (i = 0 ; i < len-1; i++) { - ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0); - if (ret < 0) - break; - } - - ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1); + struct mxl5005s_state *state = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + *bandwidth = state->Chan_Bandwidth; - return ret; + return 0; } - -int mxl5005s_init(struct dvb_frontend *fe) +static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status) { dprintk(1, "%s()\n", __func__); - return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ); + + *status = 0; + // *status = TUNER_STATUS_LOCKED; + + return 0; } -int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) +static int mxl5005s_init2(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; - u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth); + dprintk(1, "%s()\n", __func__); - mxl5005s_reset(fe); + /* Initialize MxL5005S tuner according to MxL5005S tuner example code. */ /* Tuner initialization stage 0 */ MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); - - mxl5005s_AssignTunerMode(fe, mod_type, bandwidth); + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); /* Tuner initialization stage 1 */ MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); - mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); - - return 0; -} - -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) -{ - struct mxl5005s_state *state = fe->tuner_priv; - struct mxl5005s_config *c = state->config; - - InitTunerControls(fe); - - /* Set MxL5005S parameters. */ - MXL5005_TunerConfig( - fe, - c->mod_mode, - c->if_mode, - bandwidth, - c->if_freq, - c->xtal_freq, - c->agc_mode, - c->top, - c->output_load, - c->clock_out, - c->div_out, - c->cap_select, - c->rssi_enable, - mod_type, - c->tracking_filter); - - return 0; -} - -static int mxl5005s_set_params(struct dvb_frontend *fe, - struct dvb_frontend_parameters *params) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u32 req_mode, req_bw = 0; - int ret; - - dprintk(1, "%s()\n", __func__); - - if (fe->ops.info.type == FE_ATSC) { - switch (params->u.vsb.modulation) { - case VSB_8: - req_mode = MXL_ATSC; break; - default: - case QAM_64: - case QAM_256: - case QAM_AUTO: - req_mode = MXL_QAM; break; - } - } - else req_mode = MXL_DVBT; - - /* Change tuner for new modulation type if reqd */ - if (req_mode != state->current_mode) { - switch (req_mode) { - case VSB_8: - case QAM_64: - case QAM_256: - case QAM_AUTO: - req_bw = MXL5005S_BANDWIDTH_6MHZ; - break; - default: - /* Assume DVB-T */ - switch (params->u.ofdm.bandwidth) { - case BANDWIDTH_6_MHZ: - req_bw = MXL5005S_BANDWIDTH_6MHZ; - break; - case BANDWIDTH_7_MHZ: - req_bw = MXL5005S_BANDWIDTH_7MHZ; - break; - case BANDWIDTH_AUTO: - case BANDWIDTH_8_MHZ: - req_bw = MXL5005S_BANDWIDTH_8MHZ; - break; - } - } - - state->current_mode = req_mode; - ret = mxl5005s_reconfigure(fe, req_mode, req_bw); - - } else - ret = 0; - - if (ret == 0) { - dprintk(1, "%s() freq=%d\n", __func__, params->frequency); - ret = mxl5005s_SetRfFreqHz(fe, params->frequency); - } - - return ret; -} - -static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) -{ - struct mxl5005s_state *state = fe->tuner_priv; - dprintk(1, "%s()\n", __func__); - - *frequency = state->RF_IN; - - return 0; -} - -static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) -{ - struct mxl5005s_state *state = fe->tuner_priv; - dprintk(1, "%s()\n", __func__); - - *bandwidth = state->Chan_Bandwidth; + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); return 0; } @@ -4631,6 +4698,7 @@ static const struct dvb_tuner_ops mxl5005s_tuner_ops = { .set_params = mxl5005s_set_params, .get_frequency = mxl5005s_get_frequency, .get_bandwidth = mxl5005s_get_bandwidth, + .get_status = mxl5005s_get_status }; struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, @@ -4647,7 +4715,6 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, state->frontend = fe; state->config = config; state->i2c = i2c; - state->current_mode = MXL_QAM; printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address); @@ -4659,5 +4726,8 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, EXPORT_SYMBOL(mxl5005s_attach); MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver"); +MODULE_AUTHOR("Jan Hoogenraad"); +MODULE_AUTHOR("Barnaby Shearer"); +MODULE_AUTHOR("Andy Hasper"); MODULE_AUTHOR("Steven Toth"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 48937295a63b4e81db907605afcbd81e0464b00f Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 07:15:38 -0300 Subject: V4L/DVB(7871): mxl5005s: Re-org code and update copyrights Re-org code and update copyrights Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 608 +++++++++++++++------------------ 1 file changed, 272 insertions(+), 336 deletions(-) (limited to 'drivers/media/common/tuners/mxl5005s.c') diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 64aa864c5dbf..45ac6a9e71a3 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -1,27 +1,62 @@ /* - * For the Realtek RTL chip RTL2831U - * Realtek Release Date: 2008-03-14, ver 080314 - * Realtek version RTL2831 Linux driver version 080314 - * ver 080314 - * - * for linux kernel version 2.6.21.4 - 2.6.22-14 - * support MXL5005s and MT2060 tuners (support tuner auto-detecting) - * support two IR types -- RC5 and NEC - * - * Known boards with Realtek RTL chip RTL2821U - * Freecom USB stick 14aa:0160 (version 4) - * Conceptronic CTVDIGRCU - * - * Copyright (c) 2008 Realtek - * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper - * This code is placed under the terms of the GNU General Public License - * - * Released by Realtek under GPLv2. - * Thanks to Realtek for a lot of support we received ! - * - * Revision: 080314 - original version - */ + MaxLinear MXL5005S VSB/QAM/DVBT tuner driver + + Copyright (C) 2008 MaxLinear + Copyright (C) 2006 Steven Toth + Functions: + mxl5005s_reset() + mxl5005s_writereg() + mxl5005s_writeregs() + mxl5005s_init() + mxl5005s_reconfigure() + mxl5005s_AssignTunerMode() + mxl5005s_set_params() + mxl5005s_get_frequency() + mxl5005s_get_bandwidth() + mxl5005s_release() + mxl5005s_attach() + + Copyright (c) 2008 Realtek + Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + Functions: + mxl5005s_SetRfFreqHz() + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + +*/ + +/* + History of this driver (Steven Toth): + I was given a public release of a linux driver that included + support for the MaxLinear MXL5005S silicon tuner. Analysis of + the tuner driver showed clearly three things. + 1. The tuner driver didn't support the LinuxTV tuner API + so the code Realtek added had to be removed. + + 2. A significant amount of the driver is reference driver code + from MaxLinear, I felt it was important to identify and + preserve this. + + 3. New code has to be added to interface correctly with the + LinuxTV API, as a regular kernel module. + + Other than the reference driver enum's, I've clearly marked + sections of the code and retained the copyright of the + respective owners. +*/ #include #include #include @@ -31,10 +66,10 @@ #include "dvb_frontend.h" #include "mxl5005s.h" -static int debug; +static int debug = 2; #define dprintk(level, arg...) do { \ - if (debug >= level) \ + if (level <= debug) \ printk(arg); \ } while (0) @@ -50,13 +85,6 @@ static int debug; #define MXLCTRL_NUM 189 #define MASTER_CONTROL_ADDR 9 -/* Enumeration of AGC Mode */ -typedef enum -{ - MXL_DUAL_AGC = 0, - MXL_SINGLE_AGC -} AGC_Mode; - /* Enumeration of Master Control Register State */ typedef enum { @@ -66,51 +94,6 @@ typedef enum MC_SEQ_OFF } Master_Control_State; -/* Enumeration of MXL5005 Tuner Mode */ -typedef enum -{ - MXL_ANALOG_MODE = 0, - MXL_DIGITAL_MODE -} Tuner_Mode; - -/* Enumeration of MXL5005 Tuner IF Mode */ -typedef enum -{ - MXL_ZERO_IF = 0, - MXL_LOW_IF -} Tuner_IF_Mode; - -/* Enumeration of MXL5005 Tuner Clock Out Mode */ -typedef enum -{ - MXL_CLOCK_OUT_DISABLE = 0, - MXL_CLOCK_OUT_ENABLE -} Tuner_Clock_Out; - -/* Enumeration of MXL5005 Tuner Div Out Mode */ -typedef enum -{ - MXL_DIV_OUT_1 = 0, - MXL_DIV_OUT_4 - -} Tuner_Div_Out; - -/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */ -typedef enum -{ - MXL_CAP_SEL_DISABLE = 0, - MXL_CAP_SEL_ENABLE - -} Tuner_Cap_Select; - -/* Enumeration of MXL5005 Tuner RSSI Mode */ -typedef enum -{ - MXL_RSSI_DISABLE = 0, - MXL_RSSI_ENABLE - -} Tuner_RSSI; - /* Enumeration of MXL5005 Tuner Modulation Type */ typedef enum { @@ -122,22 +105,6 @@ typedef enum MXL_ANALOG_OTA } Tuner_Modu_Type; -/* Enumeration of MXL5005 Tuner Tracking Filter Type */ -typedef enum -{ - MXL_TF_DEFAULT = 0, - MXL_TF_OFF, - MXL_TF_C, - MXL_TF_C_H, - MXL_TF_D, - MXL_TF_D_L, - MXL_TF_E, - MXL_TF_F, - MXL_TF_E_2, - MXL_TF_E_NA, - MXL_TF_G -} Tuner_TF_Type; - /* MXL5005 Tuner Register Struct */ typedef struct _TunerReg_struct { @@ -268,33 +235,6 @@ enum }; #define MXL5005S_BANDWIDTH_MODE_NUM 3 -/* Top modes */ -enum -{ - MXL5005S_TOP_5P5 = 55, - MXL5005S_TOP_7P2 = 72, - MXL5005S_TOP_9P2 = 92, - MXL5005S_TOP_11P0 = 110, - MXL5005S_TOP_12P9 = 129, - MXL5005S_TOP_14P7 = 147, - MXL5005S_TOP_16P8 = 168, - MXL5005S_TOP_19P4 = 194, - MXL5005S_TOP_21P2 = 212, - MXL5005S_TOP_23P2 = 232, - MXL5005S_TOP_25P2 = 252, - MXL5005S_TOP_27P1 = 271, - MXL5005S_TOP_29P2 = 292, - MXL5005S_TOP_31P7 = 317, - MXL5005S_TOP_34P9 = 349, -}; - -/* IF output load */ -enum -{ - MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, - MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, -}; - /* MXL5005 Tuner Control Struct */ typedef struct _TunerControl_struct { u16 Ctrl_Num; /* Control Number */ @@ -349,13 +289,15 @@ struct mxl5005s_state TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ /* Linux driver framework specific */ - const struct mxl5005s_config *config; - + struct mxl5005s_config *config; struct dvb_frontend *frontend; struct i2c_adapter *i2c; + + /* Cache values */ + u32 current_mode; + }; -// funcs u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); u16 MXL_GetMasterControl(u8 *MasterReg, int state); @@ -372,14 +314,26 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen); +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len); u16 MXL_IFSynthInit(struct dvb_frontend *fe); -static int mxl5005s_init2(struct dvb_frontend *fe); +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); +int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); + +/* ---------------------------------------------------------------- + * Begin: Custom code salvaged from the Realtek driver. + * Copyright (c) 2008 Realtek + * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * This code is placed under the terms of the GNU General Public License + * + * Released by Realtek under GPLv2. + * Thanks to Realtek for a lot of support we received ! + * + * Revision: 080314 - original version + */ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { struct mxl5005s_state *state = fe->tuner_priv; - u8 AgcMasterByte = state->config->AgcMasterByte; unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; @@ -396,7 +350,7 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); // Tuner RF frequency setting stage 1 MXL_TuneRF(fe, RfFreqHz); @@ -410,13 +364,13 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | AgcMasterByte; + ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte; TableLen += 1; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); // Wait 30 ms. - msleep(30); + msleep(150); // Tuner RF frequency setting stage 2 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ; @@ -425,101 +379,21 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | AgcMasterByte ; + ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ; TableLen += 1; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); - return 0; -} + msleep(100); -/* Write a single byte to a single reg */ -static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[2] = { reg, val }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 2 }; - - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write failed\n"); - return -EREMOTEIO; - } return 0; } +/* End: Custom code taken from the Realtek driver */ -/* Write a word to a single reg */ -static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[3] = { reg, val >> 8 , val & 0xff }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 3 }; - - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write16 failed\n"); - return -EREMOTEIO; - } - return 0; -} - -int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen) -{ - int i, ret; - u8 end_two_bytes_buf[]={ 0 , 0 }; - - for( i = 0 ; i < TableLen - 1 ; i++) - { - ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i]); - if (!ret) - return ret; - } - - end_two_bytes_buf[0] = pByteTable[i]; - end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE; - - ret = mxl5005s_writereg16(fe, pAddrTable[i], (end_two_bytes_buf[0] << 8) | end_two_bytes_buf[1]); - - return ret; -} - -int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, - unsigned char RegAddr, - unsigned char Msb, - unsigned char Lsb, - const unsigned char WritingValue - ) -{ - int i; - - unsigned char Mask; - unsigned char Shift; - unsigned char RegByte; - - /* Generate mask and shift according to MSB and LSB. */ - Mask = 0; - for(i = Lsb; i < (unsigned char)(Msb + 1); i++) - Mask |= 0x1 << i; - - Shift = Lsb; - - /* Get tuner register byte according to register adddress. */ - MXL_RegRead(fe, RegAddr, &RegByte); - - /* Reserve register byte unmask bit with mask and inlay writing value into it. */ - RegByte &= ~Mask; - RegByte |= (WritingValue << Shift) & Mask; - - /* Update tuner register byte table. */ - MXL_RegWrite(fe, RegAddr, RegByte); - - /* Write tuner register byte with writing byte. */ - return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1); -} - -// The following context is source code provided by MaxLinear. -// MaxLinear source code - MXL5005_Initialize.cpp -// DONE +/* ---------------------------------------------------------------- + * Begin: Reference driver code found in the Realtek driver. + * Copyright (c) 2008 MaxLinear + */ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -841,7 +715,6 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) return 0 ; } -// DONE u16 MXL5005_ControlInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1785,7 +1658,6 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) // MaxLinear source code - MXL5005_c.cpp // MXL5005.cpp : Defines the initialization routines for the DLL. // 2.6.12 -// DONE void InitTunerControls(struct dvb_frontend *fe) { MXL5005_RegisterInit(fe); @@ -1828,7 +1700,6 @@ void InitTunerControls(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL5005_TunerConfig(struct dvb_frontend *fe, u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ @@ -1898,7 +1769,6 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1937,7 +1807,6 @@ void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1976,7 +1845,6 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { u16 status = 0; @@ -2014,7 +1882,6 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_BlockInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -2042,6 +1909,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); break; case 6000000: + printk("%s() doing 6MHz digital\n", __func__); status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); break; } @@ -2072,7 +1940,6 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) else /* Single AGC Mode Dig Ana */ status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); - if (state->TOP == 55) /* TOP == 5.5 */ status += MXL_ControlWrite(fe, AGC_IF, 0x0); @@ -2302,6 +2169,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_IQSWAP, 0); else /* High IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 1); + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2); + } if (state->Mod_Type == MXL_ANALOG_CABLE) { /* Analog Cable Mode */ @@ -2338,7 +2207,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } /* RSSI disable */ - if(state->EN_RSSI==0) { + if(state->EN_RSSI == 0) { status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); @@ -2547,6 +2416,7 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe) Fref = 324000000UL ; } if (state->IF_LO == 5380000UL) { + printk("%s() doing 5.38\n", __func__); status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 322800000UL ; @@ -3229,6 +3099,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only { + printk("%s() CH filter\n", __func__); status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) @@ -3767,7 +3638,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) return status ; } -// DONE u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { u16 status = 0; @@ -3834,7 +3704,6 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) // >0 : Value exceed maximum allowed for control number // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { u16 status = 0; @@ -3875,7 +3744,6 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) // 2 : Control name not found // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3982,7 +3850,6 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4022,7 +3889,6 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4059,7 +3925,6 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4131,7 +3996,6 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4237,7 +4101,6 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int // NONE // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4285,7 +4148,6 @@ void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) // Computed value // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u32 MXL_Ceiling(u32 value, u32 resolution) { return (value/resolution + (value % resolution > 0 ? 1 : 0)); @@ -4294,7 +4156,6 @@ u32 MXL_Ceiling(u32 value, u32 resolution) // // Retrieve the Initialzation Registers // -// DONE u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4317,7 +4178,6 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c return status; } -// DONE u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4345,7 +4205,6 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou return status; } -// DONE u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4363,7 +4222,6 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i return status; } -// DONE u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4381,7 +4239,6 @@ u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, in return status; } -// DONE u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) /* Load_Start */ @@ -4526,7 +4383,6 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) return status; } -// DONE u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4537,141 +4393,224 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) return status; } - #endif +/* End: Reference driver code found in the Realtek driver that + * is copyright MaxLinear */ -/* Linux driver related functions */ - - -int mxl5005s_init(struct dvb_frontend *fe) +/* ---------------------------------------------------------------- + * Begin: Everything after here is new code to adapt the + * proprietary Realtek driver into a Linux API tuner. + * Copyright (C) 2008 Steven Toth + */ +static int mxl5005s_reset(struct dvb_frontend *fe) { - int MxlModMode; - int MxlIfMode; - unsigned long MxlBandwitdh; - unsigned long MxlIfFreqHz; - unsigned long MxlCrystalFreqHz; - int MxlAgcMode; - unsigned short MxlTop; - unsigned short MxlIfOutputLoad; - int MxlClockOut; - int MxlDivOut; - int MxlCapSel; - int MxlRssiOnOff; - unsigned char MxlStandard; - unsigned char MxlTfType; + struct mxl5005s_state *state = fe->tuner_priv; + int ret = 0; - /* Set MxL5005S parameters. */ - MxlModMode = MXL_DIGITAL_MODE; - MxlIfMode = MXL_ZERO_IF; -// steve - //MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; - //MxlIfFreqHz = IF_FREQ_4570000HZ; - MxlBandwitdh = MXL5005S_BANDWIDTH_6MHZ; // config - MxlIfFreqHz = IF_FREQ_5380000HZ; // config - MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; // config - MxlAgcMode = MXL_SINGLE_AGC; - MxlTop = MXL5005S_TOP_25P2; - MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; - MxlClockOut = MXL_CLOCK_OUT_DISABLE; - MxlDivOut = MXL_DIV_OUT_4; - MxlCapSel = MXL_CAP_SEL_ENABLE; - MxlRssiOnOff = MXL_RSSI_ENABLE; // config - MxlTfType = MXL_TF_C_H; // config - - MxlStandard = MXL_ATSC; // config - - // TODO: this is bad, it trashes other configs - // Set MxL5005S extra module. - //pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; + u8 buf[2] = { 0xff, 0x00 }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 2 }; - MXL5005_TunerConfig( - fe, - (unsigned char)MxlModMode, - (unsigned char)MxlIfMode, - MxlBandwitdh, - MxlIfFreqHz, - MxlCrystalFreqHz, - (unsigned char)MxlAgcMode, - MxlTop, - MxlIfOutputLoad, - (unsigned char)MxlClockOut, - (unsigned char)MxlDivOut, - (unsigned char)MxlCapSel, - (unsigned char)MxlRssiOnOff, - MxlStandard, MxlTfType); - - return mxl5005s_init2(fe); -} + dprintk(2, "%s()\n", __func__); -static int mxl5005s_set_params(struct dvb_frontend *fe, - struct dvb_frontend_parameters *params) -{ - u32 freq; - u32 bw; + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); - if (fe->ops.info.type == FE_OFDM) - bw = params->u.ofdm.bandwidth; - else - bw = MXL5005S_BANDWIDTH_6MHZ; + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C reset failed\n"); + ret = -EREMOTEIO; + } - freq = params->frequency; /* Hz */ - dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); - return mxl5005s_SetRfFreqHz(fe, freq); + return ret; } -static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) +/* Write a single byte to a single reg, latch the value if required by + * following the transaction with the latch byte. + */ +static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) { struct mxl5005s_state *state = fe->tuner_priv; - dprintk(1, "%s()\n", __func__); + u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 3 }; - *frequency = state->RF_IN; + if (latch == 0) + msg.len = 2; + dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write failed\n"); + return -EREMOTEIO; + } return 0; } -static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len) { - struct mxl5005s_state *state = fe->tuner_priv; - dprintk(1, "%s()\n", __func__); + int ret = 0, i; - *bandwidth = state->Chan_Bandwidth; + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); - return 0; + for (i = 0 ; i < len-1; i++) { + ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0); + if (ret < 0) + break; + } + + ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return ret; } -static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status) + +int mxl5005s_init(struct dvb_frontend *fe) { dprintk(1, "%s()\n", __func__); - - *status = 0; - // *status = TUNER_STATUS_LOCKED; - - return 0; + return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ); } -static int mxl5005s_init2(struct dvb_frontend *fe) +int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; + u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - dprintk(1, "%s()\n", __func__); + dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth); - /* Initialize MxL5005S tuner according to MxL5005S tuner example code. */ + mxl5005s_reset(fe); /* Tuner initialization stage 0 */ MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); + + mxl5005s_AssignTunerMode(fe, mod_type, bandwidth); /* Tuner initialization stage 1 */ MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); + + return 0; +} + +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) +{ + struct mxl5005s_state *state = fe->tuner_priv; + struct mxl5005s_config *c = state->config; + + InitTunerControls(fe); + + /* Set MxL5005S parameters. */ + MXL5005_TunerConfig( + fe, + c->mod_mode, + c->if_mode, + bandwidth, + c->if_freq, + c->xtal_freq, + c->agc_mode, + c->top, + c->output_load, + c->clock_out, + c->div_out, + c->cap_select, + c->rssi_enable, + mod_type, + c->tracking_filter); + + return 0; +} + +static int mxl5005s_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + struct mxl5005s_state *state = fe->tuner_priv; + u32 req_mode, req_bw = 0; + int ret; + + dprintk(1, "%s()\n", __func__); + + if (fe->ops.info.type == FE_ATSC) { + switch (params->u.vsb.modulation) { + case VSB_8: + req_mode = MXL_ATSC; break; + default: + case QAM_64: + case QAM_256: + case QAM_AUTO: + req_mode = MXL_QAM; break; + } + } + else req_mode = MXL_DVBT; + + /* Change tuner for new modulation type if reqd */ + if (req_mode != state->current_mode) { + switch (req_mode) { + case VSB_8: + case QAM_64: + case QAM_256: + case QAM_AUTO: + req_bw = MXL5005S_BANDWIDTH_6MHZ; + break; + default: + /* Assume DVB-T */ + switch (params->u.ofdm.bandwidth) { + case BANDWIDTH_6_MHZ: + req_bw = MXL5005S_BANDWIDTH_6MHZ; + break; + case BANDWIDTH_7_MHZ: + req_bw = MXL5005S_BANDWIDTH_7MHZ; + break; + case BANDWIDTH_AUTO: + case BANDWIDTH_8_MHZ: + req_bw = MXL5005S_BANDWIDTH_8MHZ; + break; + } + } + + state->current_mode = req_mode; + ret = mxl5005s_reconfigure(fe, req_mode, req_bw); + + } else + ret = 0; + + if (ret == 0) { + dprintk(1, "%s() freq=%d\n", __func__, params->frequency); + ret = mxl5005s_SetRfFreqHz(fe, params->frequency); + } + + return ret; +} + +static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct mxl5005s_state *state = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); + + *frequency = state->RF_IN; + + return 0; +} + +static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +{ + struct mxl5005s_state *state = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); + + *bandwidth = state->Chan_Bandwidth; return 0; } @@ -4698,7 +4637,6 @@ static const struct dvb_tuner_ops mxl5005s_tuner_ops = { .set_params = mxl5005s_set_params, .get_frequency = mxl5005s_get_frequency, .get_bandwidth = mxl5005s_get_bandwidth, - .get_status = mxl5005s_get_status }; struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, @@ -4715,6 +4653,7 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, state->frontend = fe; state->config = config; state->i2c = i2c; + state->current_mode = MXL_QAM; printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address); @@ -4726,8 +4665,5 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, EXPORT_SYMBOL(mxl5005s_attach); MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver"); -MODULE_AUTHOR("Jan Hoogenraad"); -MODULE_AUTHOR("Barnaby Shearer"); -MODULE_AUTHOR("Andy Hasper"); MODULE_AUTHOR("Steven Toth"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From d211017b954436bfc516e93d839e8746ec2bbbfe Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 19:35:54 -0300 Subject: V4L/DVB(7872): mxl5005s: checkpatch.pl compliance 4 exceptions where the code would read very ugly otherwise. Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 2496 +++++++++++++------------------- 1 file changed, 1027 insertions(+), 1469 deletions(-) (limited to 'drivers/media/common/tuners/mxl5005s.c') diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 45ac6a9e71a3..21dca5bdca77 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -86,34 +86,30 @@ static int debug = 2; #define MASTER_CONTROL_ADDR 9 /* Enumeration of Master Control Register State */ -typedef enum -{ +enum master_control_state { MC_LOAD_START = 1, MC_POWER_DOWN, MC_SYNTH_RESET, MC_SEQ_OFF -} Master_Control_State; +}; /* Enumeration of MXL5005 Tuner Modulation Type */ -typedef enum -{ +enum { MXL_DEFAULT_MODULATION = 0, MXL_DVBT, MXL_ATSC, MXL_QAM, MXL_ANALOG_CABLE, MXL_ANALOG_OTA -} Tuner_Modu_Type; +} tuner_modu_type; /* MXL5005 Tuner Register Struct */ -typedef struct _TunerReg_struct -{ +struct TunerReg { u16 Reg_Num; /* Tuner Register Address */ - u16 Reg_Val; /* Current sofware programmed value waiting to be writen */ -} TunerReg_struct; + u16 Reg_Val; /* Current sw programmed value waiting to be writen */ +}; -typedef enum -{ +enum { /* Initialization Control Names */ DN_IQTN_AMP_CUT = 1, /* 1 */ BB_MODE, /* 2 */ @@ -219,16 +215,14 @@ typedef enum #define MXL5005S_BB_DLPF_BANDSEL_LSB 3 /* Standard modes */ -enum -{ +enum { MXL5005S_STANDARD_DVBT, MXL5005S_STANDARD_ATSC, }; #define MXL5005S_STANDARD_MODE_NUM 2 /* Bandwidth modes */ -enum -{ +enum { MXL5005S_BANDWIDTH_6MHZ = 6000000, MXL5005S_BANDWIDTH_7MHZ = 7000000, MXL5005S_BANDWIDTH_8MHZ = 8000000, @@ -236,17 +230,16 @@ enum #define MXL5005S_BANDWIDTH_MODE_NUM 3 /* MXL5005 Tuner Control Struct */ -typedef struct _TunerControl_struct { +struct TunerControl { u16 Ctrl_Num; /* Control Number */ u16 size; /* Number of bits to represent Value */ - u16 addr[25]; /* Array of Tuner Register Address for each bit position */ - u16 bit[25]; /* Array of bit position in Register Address for each bit position */ + u16 addr[25]; /* Array of Tuner Register Address for each bit pos */ + u16 bit[25]; /* Array of bit pos in Reg Addr for each bit pos */ u16 val[25]; /* Binary representation of Value */ -} TunerControl_struct; +}; /* MXL5005 Tuner Struct */ -struct mxl5005s_state -{ +struct mxl5005s_state { u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */ u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */ @@ -256,14 +249,18 @@ struct mxl5005s_state u32 Fxtal; /* XTAL Frequency */ u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */ u16 TOP; /* Value: take over point */ - u8 CLOCK_OUT; /* 0: turn off clock out; 1: turn on clock out */ + u8 CLOCK_OUT; /* 0: turn off clk out; 1: turn on clock out */ u8 DIV_OUT; /* 4MHz or 16MHz */ u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */ u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */ - u8 Mod_Type; /* Modulation Type; */ - /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ - u8 TF_Type; /* Tracking Filter Type */ - /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ + + /* Modulation Type; */ + /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ + u8 Mod_Type; + + /* Tracking Filter Type */ + /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ + u8 TF_Type; /* Calculated Settings */ u32 RF_LO; /* Synth RF LO Frequency */ @@ -271,22 +268,22 @@ struct mxl5005s_state u32 TG_LO; /* Synth TG_LO Frequency */ /* Pointers to ControlName Arrays */ - u16 Init_Ctrl_Num; /* Number of INIT Control Names */ - TunerControl_struct - Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ + u16 Init_Ctrl_Num; /* Number of INIT Control Names */ + struct TunerControl + Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ - u16 CH_Ctrl_Num; /* Number of CH Control Names */ - TunerControl_struct - CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ + u16 CH_Ctrl_Num; /* Number of CH Control Names */ + struct TunerControl + CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ - u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ - TunerControl_struct - MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ + u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ + struct TunerControl + MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ /* Pointer to Tuner Register Array */ - u16 TunerRegs_Num; /* Number of Tuner Registers */ - TunerReg_struct - TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ + u16 TunerRegs_Num; /* Number of Tuner Registers */ + struct TunerReg + TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ /* Linux driver framework specific */ struct mxl5005s_config *config; @@ -302,21 +299,27 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); u16 MXL_GetMasterControl(u8 *MasterReg, int state); void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal); -u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); +u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count); u32 MXL_Ceiling(u32 value, u32 resolution); u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal); -u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup); +u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, + u32 value, u16 controlGroup); u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); -u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count); +u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count); u32 MXL_GetXtalInt(u32 Xtal_Freq); u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); -u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len); +u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count); +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, + u8 *datatable, u8 len); u16 MXL_IFSynthInit(struct dvb_frontend *fe); -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, + u32 bandwidth); int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); /* ---------------------------------------------------------------- @@ -343,16 +346,16 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz); - // Set MxL5005S tuner RF frequency according to MxL5005S tuner example code. + /* Set MxL5005S tuner RF frequency according to example code. */ - // Tuner RF frequency setting stage 0 - MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ; + /* Tuner RF frequency setting stage 0 */ + MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); - // Tuner RF frequency setting stage 1 + /* Tuner RF frequency setting stage 1 */ MXL_TuneRF(fe, RfFreqHz); MXL_ControlRead(fe, IF_DIVVAL, &IfDivval); @@ -360,26 +363,28 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0); MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1); MXL_ControlWrite(fe, IF_DIVVAL, 8); - MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen) ; + MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen); - MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; + MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START); AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte; + ByteTable[TableLen] = MasterControlByte | + state->config->AgcMasterByte; TableLen += 1; mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); - // Wait 30 ms. + /* Wait 30 ms. */ msleep(150); - // Tuner RF frequency setting stage 2 - MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ; - MXL_ControlWrite(fe, IF_DIVVAL, IfDivval) ; - MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen) ; + /* Tuner RF frequency setting stage 2 */ + MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1); + MXL_ControlWrite(fe, IF_DIVVAL, IfDivval); + MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen); - MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; + MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START); AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ; + ByteTable[TableLen] = MasterControlByte | + state->config->AgcMasterByte ; TableLen += 1; mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); @@ -398,7 +403,6 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; state->TunerRegs_Num = TUNER_REGS_NUM ; -// state->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; state->TunerRegs[0].Reg_Num = 9 ; state->TunerRegs[0].Reg_Val = 0x40 ; @@ -1655,9 +1659,6 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) return 0 ; } -// MaxLinear source code - MXL5005_c.cpp -// MXL5005.cpp : Defines the initialization routines for the DLL. -// 2.6.12 void InitTunerControls(struct dvb_frontend *fe) { MXL5005_RegisterInit(fe); @@ -1667,57 +1668,28 @@ void InitTunerControls(struct dvb_frontend *fe) #endif } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_ConfigTuner // -// // -// Description: Configure MXL5005Tuner structure for desired // -// Channel Bandwidth/Channel Frequency // -// // -// // -// Functions used: // -// MXL_SynthIFLO_Calc // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// Mode: Tuner Mode (Analog/Digital) // -// IF_Mode: IF Mode ( Zero/Low ) // -// Bandwidth: Filter Channel Bandwidth (in Hz) // -// IF_out: Desired IF out Frequency (in Hz) // -// Fxtal: Crystal Frerquency (in Hz) // -// TOP: 0: Dual AGC; Value: take over point // -// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // -// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // -// DIV_OUT: 0: Div-1; 1: Div-4 // -// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // -// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL5005_TunerConfig(struct dvb_frontend *fe, - u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ - u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ - u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ - u32 IF_out, /* Desired IF Out Frequency */ - u32 Fxtal, /* XTAL Frequency */ - u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ - u16 TOP, /* 0: Dual AGC; Value: take over point */ - u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ - u8 CLOCK_OUT, /* 0: turn off clock out; 1: turn on clock out */ - u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */ - u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ - u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ - u8 Mod_Type, /* Modulation Type; */ - /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ - u8 TF_Type /* Tracking Filter */ - /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ - ) + u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ + u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ + u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ + u32 IF_out, /* Desired IF Out Frequency */ + u32 Fxtal, /* XTAL Frequency */ + u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ + u16 TOP, /* 0: Dual AGC; Value: take over point */ + u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ + u8 CLOCK_OUT, /* 0: turn off clk out; 1: turn on clock out */ + u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */ + u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ + u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ + + /* Modulation Type; */ + /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ + u8 Mod_Type, + + /* Tracking Filter */ + /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ + u8 TF_Type + ) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; @@ -1746,105 +1718,40 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, return status; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_SynthIFLO_Calc // -// // -// Description: Calculate Internal IF-LO Frequency // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; if (state->Mode == 1) /* Digital Mode */ state->IF_LO = state->IF_OUT; - else /* Analog Mode */ - { - if(state->IF_Mode == 0) /* Analog Zero IF mode */ + else /* Analog Mode */ { + if (state->IF_Mode == 0) /* Analog Zero IF mode */ state->IF_LO = state->IF_OUT + 400000; else /* Analog Low IF mode */ state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2; } } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_SynthRFTGLO_Calc // -// // -// Description: Calculate Internal RF-LO frequency and // -// internal Tone-Gen(TG)-LO frequency // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; if (state->Mode == 1) /* Digital Mode */ { - //remove 20.48MHz setting for 2.6.10 + /* remove 20.48MHz setting for 2.6.10 */ state->RF_LO = state->RF_IN; - state->TG_LO = state->RF_IN - 750000; //change for 2.6.6 + /* change for 2.6.6 */ + state->TG_LO = state->RF_IN - 750000; } else /* Analog Mode */ { - if(state->IF_Mode == 0) /* Analog Zero IF mode */ { + if (state->IF_Mode == 0) /* Analog Zero IF mode */ { state->RF_LO = state->RF_IN - 400000; state->TG_LO = state->RF_IN - 1750000; } else /* Analog Low IF mode */ { state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2; - state->TG_LO = state->RF_IN - state->Chan_Bandwidth + 500000; + state->TG_LO = state->RF_IN - + state->Chan_Bandwidth + 500000; } } } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_OverwriteICDefault // -// // -// Description: Overwrite the Default Register Setting // -// // -// // -// Functions used: // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { u16 status = 0; @@ -1857,31 +1764,6 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) return status; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_BlockInit // -// // -// Description: Tuner Initialization as a function of 'User Settings' // -// * User settings in Tuner strcuture must be assigned // -// first // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// Tuner_struct: structure defined at higher level // -// // -// Inputs: // -// Tuner : Tuner structure defined at higher level // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_BlockInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1902,42 +1784,45 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) /* Initialize Low-Pass Filter */ if (state->Mode) { /* Digital Mode */ switch (state->Chan_Bandwidth) { - case 8000000: - status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0); - break; - case 7000000: - status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); - break; - case 6000000: - printk("%s() doing 6MHz digital\n", __func__); - status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); - break; + case 8000000: + status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0); + break; + case 7000000: + status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); + break; + case 6000000: + status += MXL_ControlWrite(fe, + BB_DLPF_BANDSEL, 3); + break; } } else { /* Analog Mode */ switch (state->Chan_Bandwidth) { - case 8000000: /* Low Zero */ - status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 0 : 3)); - break; - case 7000000: - status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 1 : 4)); - break; - case 6000000: - status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 2 : 5)); - break; + case 8000000: /* Low Zero */ + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, + (state->IF_Mode ? 0 : 3)); + break; + case 7000000: + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, + (state->IF_Mode ? 1 : 4)); + break; + case 6000000: + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, + (state->IF_Mode ? 2 : 5)); + break; } } /* Charge Pump Control Dig Ana */ - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8); - status += MXL_ControlWrite(fe, RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1); + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8); + status += MXL_ControlWrite(fe, + RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1); status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0); /* AGC TOP Control */ if (state->AGC_Mode == 0) /* Dual AGC */ { status += MXL_ControlWrite(fe, AGC_IF, 15); status += MXL_ControlWrite(fe, AGC_RF, 15); - } - else /* Single AGC Mode Dig Ana */ + } else /* Single AGC Mode Dig Ana */ status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); if (state->TOP == 55) /* TOP == 5.5 */ @@ -2008,7 +1893,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, EN_AUX_3P, 1); status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); } - if ((state->IF_OUT == 36125000UL) || (state->IF_OUT == 36150000UL)) { + if ((state->IF_OUT == 36125000UL) || + (state->IF_OUT == 36150000UL)) { status += MXL_ControlWrite(fe, EN_AAF, 1); status += MXL_ControlWrite(fe, EN_3P, 1); status += MXL_ControlWrite(fe, EN_AUX_3P, 1); @@ -2021,15 +1907,13 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1); } } else { /* Analog Mode */ - if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) - { + if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) { status += MXL_ControlWrite(fe, EN_AAF, 1); status += MXL_ControlWrite(fe, EN_3P, 1); status += MXL_ControlWrite(fe, EN_AUX_3P, 1); status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); } - if (state->IF_OUT > 5000000UL) - { + if (state->IF_OUT > 5000000UL) { status += MXL_ControlWrite(fe, EN_AAF, 0); status += MXL_ControlWrite(fe, EN_3P, 0); status += MXL_ControlWrite(fe, EN_AUX_3P, 0); @@ -2073,13 +1957,13 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */ /* Set TG_R_DIV */ - status += MXL_ControlWrite(fe, TG_R_DIV, MXL_Ceiling(state->Fxtal, 1000000)); + status += MXL_ControlWrite(fe, TG_R_DIV, + MXL_Ceiling(state->Fxtal, 1000000)); /* Apply Default value to BB_INITSTATE_DLPF_TUNE */ /* RSSI Control */ - if (state->EN_RSSI) - { + if (state->EN_RSSI) { status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); @@ -2098,8 +1982,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) /* Modulation type bit settings * Override the control values preset */ - if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ - { + if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ { state->AGC_Mode = 1; /* Single AGC Mode */ /* Enable RSSI */ @@ -2122,8 +2005,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ - { + if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ { state->AGC_Mode = 1; /* Single AGC Mode */ /* Enable RSSI */ @@ -2141,14 +2023,15 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, RFA_FLR, 2); status += MXL_ControlWrite(fe, RFA_CEIL, 13); status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1); - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); /* Low Zero */ + /* Low Zero */ + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); + if (state->IF_OUT <= 6280000UL) /* Low IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 0); else /* High IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (state->Mod_Type == MXL_QAM) /* QAM Mode */ - { + if (state->Mod_Type == MXL_QAM) /* QAM Mode */ { state->Mode = MXL_DIGITAL_MODE; /* state->AGC_Mode = 1; */ /* Single AGC Mode */ @@ -2163,7 +2046,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); /* change here for v2.6.5 */ + /* change here for v2.6.5 */ + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); if (state->IF_OUT <= 6280000UL) /* Low IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 0); @@ -2183,7 +2067,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); - status += MXL_ControlWrite(fe, AGC_IF, 1); /* change for 2.6.3 */ + /* change for 2.6.3 */ + status += MXL_ControlWrite(fe, AGC_IF, 1); status += MXL_ControlWrite(fe, AGC_RF, 15); status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } @@ -2207,7 +2092,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } /* RSSI disable */ - if(state->EN_RSSI == 0) { + if (state->EN_RSSI == 0) { status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); @@ -2217,34 +2102,10 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) return status; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_IFSynthInit // -// // -// Description: Tuner IF Synthesizer related register initialization // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// Tuner_struct: structure defined at higher level // -// // -// Inputs: // -// Tuner : Tuner structure defined at higher level // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_IFSynthInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0 ; - // Declare Local Variables u32 Fref = 0 ; u32 Kdbl, intModVal ; u32 fracModVal ; @@ -2255,268 +2116,207 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe) if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) Kdbl = 1 ; - // - // IF Synthesizer Control - // - if (state->Mode == 0 && state->IF_Mode == 1) // Analog Low IF mode - { + /* IF Synthesizer Control */ + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ { if (state->IF_LO == 41000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 328000000UL ; } if (state->IF_LO == 47000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 376000000UL ; } if (state->IF_LO == 54000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 324000000UL ; } if (state->IF_LO == 60000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } if (state->IF_LO == 39250000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 314000000UL ; } if (state->IF_LO == 39650000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 317200000UL ; } if (state->IF_LO == 40150000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 321200000UL ; } if (state->IF_LO == 40650000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 325200000UL ; } } - if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) - { + if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) { if (state->IF_LO == 57000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 342000000UL ; } if (state->IF_LO == 44000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 352000000UL ; } if (state->IF_LO == 43750000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 350000000UL ; } if (state->IF_LO == 36650000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 366500000UL ; } if (state->IF_LO == 36150000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 361500000UL ; } if (state->IF_LO == 36000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } if (state->IF_LO == 35250000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 352500000UL ; } if (state->IF_LO == 34750000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 347500000UL ; } if (state->IF_LO == 6280000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 376800000UL ; } if (state->IF_LO == 5000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } if (state->IF_LO == 4500000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } if (state->IF_LO == 4570000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 365600000UL ; } if (state->IF_LO == 4000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } - if (state->IF_LO == 57400000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 57400000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 344400000UL ; } - if (state->IF_LO == 44400000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 44400000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 355200000UL ; } - if (state->IF_LO == 44150000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 44150000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 353200000UL ; } - if (state->IF_LO == 37050000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 37050000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 370500000UL ; } - if (state->IF_LO == 36550000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 36550000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 365500000UL ; } if (state->IF_LO == 36125000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 361250000UL ; } if (state->IF_LO == 6000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } - if (state->IF_LO == 5400000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + if (state->IF_LO == 5400000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 324000000UL ; } if (state->IF_LO == 5380000UL) { - printk("%s() doing 5.38\n", __func__); - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 322800000UL ; } if (state->IF_LO == 5200000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 374400000UL ; } - if (state->IF_LO == 4900000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 4900000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 352800000UL ; } - if (state->IF_LO == 4400000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 4400000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 352000000UL ; } - if (state->IF_LO == 4063000UL) //add for 2.6.8 - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 4063000UL) /* add for 2.6.8 */ { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 365670000UL ; } } - // CHCAL_INT_MOD_IF - // CHCAL_FRAC_MOD_IF - intModVal = Fref / (state->Fxtal * Kdbl/2) ; - status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal ) ; + /* CHCAL_INT_MOD_IF */ + /* CHCAL_FRAC_MOD_IF */ + intModVal = Fref / (state->Fxtal * Kdbl/2); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal); + + fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) * + intModVal); - fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) * intModVal); - fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000) ; - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal) ; + fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal); return status ; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_GetXtalInt // -// // -// Description: return the Crystal Integration Value for // -// TG_VCO_BIAS calculation // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// Crystal Frequency Value in Hz // -// // -// Outputs: // -// Calculated Crystal Frequency Integration Value // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// u32 MXL_GetXtalInt(u32 Xtal_Freq) { if ((Xtal_Freq % 1000000) == 0) - return (Xtal_Freq / 10000) ; + return (Xtal_Freq / 10000); else - return (((Xtal_Freq / 1000000) + 1)*100) ; + return (((Xtal_Freq / 1000000) + 1)*100); } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL5005_TuneRF // -// // -// Description: Set control names to tune to requested RF_IN frequency // -// // -// Globals: // -// None // -// // -// Functions used: // -// MXL_SynthRFTGLO_Calc // -// MXL5005_ControlWrite // -// MXL_GetXtalInt // -// // -// Inputs: // -// Tuner : Tuner structure defined at higher level // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// 1 : Unsuccessful // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) { struct mxl5005s_state *state = fe->tuner_priv; - // Declare Local Variables u16 status = 0; u32 divider_val, E3, E4, E5, E5A; u32 Fmax, Fmin, FmaxBin, FminBin; @@ -2527,8 +2327,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) u32 Fref_TG; u32 Fvco; -// u32 temp; - Xtal_Int = MXL_GetXtalInt(state->Fxtal); @@ -2541,21 +2339,19 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) if (state->Fxtal > 22000000 && state->Fxtal <= 32000000) Kdbl_RF = 1; - // - // Downconverter Controls - // - // Look-Up Table Implementation for: - // DN_POLY - // DN_RFGAIN - // DN_CAP_RFLPF - // DN_EN_VHFUHFBAR - // DN_GAIN_ADJUST - // Change the boundary reference from RF_IN to RF_LO - if (state->RF_LO < 40000000UL) { + /* Downconverter Controls + * Look-Up Table Implementation for: + * DN_POLY + * DN_RFGAIN + * DN_CAP_RFLPF + * DN_EN_VHFUHFBAR + * DN_GAIN_ADJUST + * Change the boundary reference from RF_IN to RF_LO + */ + if (state->RF_LO < 40000000UL) return -1; - } + if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { - // Look-Up Table implementation status += MXL_ControlWrite(fe, DN_POLY, 2); status += MXL_ControlWrite(fe, DN_RFGAIN, 3); status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423); @@ -2563,7 +2359,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); } if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { - // Look-Up Table implementation status += MXL_ControlWrite(fe, DN_POLY, 3); status += MXL_ControlWrite(fe, DN_RFGAIN, 3); status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222); @@ -2571,7 +2366,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); } if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { - // Look-Up Table implementation status += MXL_ControlWrite(fe, DN_POLY, 3); status += MXL_ControlWrite(fe, DN_RFGAIN, 3); status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147); @@ -2579,7 +2373,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); } if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { - // Look-Up Table implementation status += MXL_ControlWrite(fe, DN_POLY, 3); status += MXL_ControlWrite(fe, DN_RFGAIN, 3); status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9); @@ -2587,34 +2380,31 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); } if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { - // Look-Up Table implementation - status += MXL_ControlWrite(fe, DN_POLY, 3) ; - status += MXL_ControlWrite(fe, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 3); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3); } if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) { - // Look-Up Table implementation - status += MXL_ControlWrite(fe, DN_POLY, 3) ; - status += MXL_ControlWrite(fe, DN_RFGAIN, 1) ; - status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ; - status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 1); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3); } if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) { - // Look-Up Table implementation - status += MXL_ControlWrite(fe, DN_POLY, 3) ; - status += MXL_ControlWrite(fe, DN_RFGAIN, 2) ; - status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ; - status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 2); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3); } - if (state->RF_LO > 900000000UL) { + if (state->RF_LO > 900000000UL) return -1; - } - // DN_IQTNBUF_AMP - // DN_IQTNGNBFBIAS_BST + + /* DN_IQTNBUF_AMP */ + /* DN_IQTNGNBFBIAS_BST */ if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); @@ -2680,18 +2470,19 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1); } - // - // Set RF Synth and LO Path Control - // - // Look-Up table implementation for: - // RFSYN_EN_OUTMUX - // RFSYN_SEL_VCO_OUT - // RFSYN_SEL_VCO_HI - // RFSYN_SEL_DIVM - // RFSYN_RF_DIV_BIAS - // DN_SEL_FREQ - // - // Set divider_val, Fmax, Fmix to use in Equations + /* + * Set RF Synth and LO Path Control + * + * Look-Up table implementation for: + * RFSYN_EN_OUTMUX + * RFSYN_SEL_VCO_OUT + * RFSYN_SEL_VCO_HI + * RFSYN_SEL_DIVM + * RFSYN_RF_DIV_BIAS + * DN_SEL_FREQ + * + * Set divider_val, Fmax, Fmix to use in Equations + */ FminBin = 28000000UL ; FmaxBin = 42500000UL ; if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) { @@ -2721,12 +2512,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 56000000UL ; FmaxBin = 85000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); divider_val = 32 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2734,12 +2525,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 85000000UL ; FmaxBin = 112000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); divider_val = 32 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2747,12 +2538,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 112000000UL ; FmaxBin = 170000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2); divider_val = 16 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2760,12 +2551,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 170000000UL ; FmaxBin = 225000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2); divider_val = 16 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2773,12 +2564,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 225000000UL ; FmaxBin = 300000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4); divider_val = 8 ; Fmax = 340000000UL ; Fmin = FminBin ; @@ -2786,12 +2577,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 300000000UL ; FmaxBin = 340000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); divider_val = 8 ; Fmax = FmaxBin ; Fmin = 225000000UL ; @@ -2799,12 +2590,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 340000000UL ; FmaxBin = 450000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); divider_val = 8 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2812,12 +2603,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 450000000UL ; FmaxBin = 680000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2825,67 +2616,66 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 680000000UL ; FmaxBin = 900000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; } - // CHCAL_INT_MOD_RF - // CHCAL_FRAC_MOD_RF - // RFSYN_LPF_R - // CHCAL_EN_INT_RF - - // Equation E3 - // RFSYN_VCO_BIAS + /* CHCAL_INT_MOD_RF + * CHCAL_FRAC_MOD_RF + * RFSYN_LPF_R + * CHCAL_EN_INT_RF + */ + /* Equation E3 RFSYN_VCO_BIAS */ E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; - status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3) ; + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3); - // Equation E4 - // CHCAL_INT_MOD_RF - E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000) ; - MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4) ; + /* Equation E4 CHCAL_INT_MOD_RF */ + E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000); + MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4); - // Equation E5 - // CHCAL_FRAC_MOD_RF - // CHCAL_EN_INT_RF - E5 = ((2<<17)*(state->RF_LO/10000*divider_val - (E4*(2*state->Fxtal*Kdbl_RF)/10000)))/(2*state->Fxtal*Kdbl_RF/10000) ; - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ; + /* Equation E5 CHCAL_FRAC_MOD_RF CHCAL_EN_INT_RF */ + E5 = ((2<<17)*(state->RF_LO/10000*divider_val - + (E4*(2*state->Fxtal*Kdbl_RF)/10000))) / + (2*state->Fxtal*Kdbl_RF/10000); - // Equation E5A - // RFSYN_LPF_R + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5); + + /* Equation E5A RFSYN_LPF_R */ E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; - status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A) ; + status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A); - // Euqation E5B - // CHCAL_EN_INIT_RF + /* Euqation E5B CHCAL_EN_INIT_RF */ status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0)); - //if (E5 == 0) - // status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1); - //else - // status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ; - - // - // Set TG Synth - // - // Look-Up table implementation for: - // TG_LO_DIVVAL - // TG_LO_SELVAL - // - // Set divider_val, Fmax, Fmix to use in Equations - if (state->TG_LO < 33000000UL) { + /*if (E5 == 0) + * status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1); + *else + * status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5); + */ + + /* + * Set TG Synth + * + * Look-Up table implementation for: + * TG_LO_DIVVAL + * TG_LO_SELVAL + * + * Set divider_val, Fmax, Fmix to use in Equations + */ + if (state->TG_LO < 33000000UL) return -1; - } + FminBin = 33000000UL ; FmaxBin = 50000000UL ; if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0); divider_val = 36 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2893,8 +2683,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 50000000UL ; FmaxBin = 67000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0); divider_val = 24 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2902,8 +2692,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 67000000UL ; FmaxBin = 100000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2); divider_val = 18 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2911,8 +2701,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 100000000UL ; FmaxBin = 150000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2); divider_val = 12 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2920,8 +2710,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 150000000UL ; FmaxBin = 200000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2); divider_val = 8 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2929,8 +2719,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 200000000UL ; FmaxBin = 300000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3); divider_val = 6 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2938,8 +2728,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 300000000UL ; FmaxBin = 400000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3); divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2947,8 +2737,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 400000000UL ; FmaxBin = 600000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7); divider_val = 3 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2956,682 +2746,608 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 600000000UL ; FmaxBin = 900000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7); divider_val = 2 ; Fmax = FmaxBin ; Fmin = FminBin ; } - // TG_DIV_VAL - tg_divval = (state->TG_LO*divider_val/100000) - *(MXL_Ceiling(state->Fxtal,1000000) * 100) / (state->Fxtal/1000) ; - status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval) ; + /* TG_DIV_VAL */ + tg_divval = (state->TG_LO*divider_val/100000) * + (MXL_Ceiling(state->Fxtal, 1000000) * 100) / + (state->Fxtal/1000); + + status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval); if (state->TG_LO > 600000000UL) - status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1 ) ; + status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1); Fmax = 1800000000UL ; Fmin = 1200000000UL ; + /* prevent overflow of 32 bit unsigned integer, use + * following equation. Edit for v2.6.4 + */ + /* Fref_TF = Fref_TG * 1000 */ + Fref_TG = (state->Fxtal/1000) / MXL_Ceiling(state->Fxtal, 1000000); - - // to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4 - Fref_TG = (state->Fxtal/1000)/ MXL_Ceiling(state->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000 - - Fvco = (state->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10 + /* Fvco = Fvco/10 */ + Fvco = (state->TG_LO/10000) * divider_val * Fref_TG; tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8; - //below equation is same as above but much harder to debug. - //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((state->TG_LO/10000)*divider_val*(state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ; - - - status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo) ; - + /* below equation is same as above but much harder to debug. + * tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - + * ((state->TG_LO/10000)*divider_val * + * (state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * + * Xtal_Int/100) + 8; + */ + status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo); - //add for 2.6.5 - //Special setting for QAM - if(state->Mod_Type == MXL_QAM) - { - if(state->RF_IN < 680000000) - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ; - else - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2) ; + /* add for 2.6.5 Special setting for QAM */ + if (state->Mod_Type == MXL_QAM) { + if (state->RF_IN < 680000000) + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); + else + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2); } - - //remove 20.48MHz setting for 2.6.10 - - // - // Off Chip Tracking Filter Control - // - if (state->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; - - status += MXL_SetGPIO(fe, 3, 1) ; // turn off Bank 1 - status += MXL_SetGPIO(fe, 1, 1) ; // turn off Bank 2 - status += MXL_SetGPIO(fe, 4, 1) ; // turn off Bank 3 + /* Off Chip Tracking Filter Control */ + if (state->TF_Type == MXL_TF_OFF) { + /* Tracking Filter Off State; turn off all the banks */ + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 3, 1); /* Bank1 Off */ + status += MXL_SetGPIO(fe, 1, 1); /* Bank2 Off */ + status += MXL_SetGPIO(fe, 4, 1); /* Bank3 Off */ } - if (state->TF_Type == MXL_TF_C) // Tracking Filter type C - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; - status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) - { - - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off - } - if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off - } - if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On - } - if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On - } - if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(fe, DAC_DIN_B, 29) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On - } - if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On - } - if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(fe, DAC_DIN_B, 16) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off - } - if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(fe, DAC_DIN_B, 7) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off - } - if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_C) /* Tracking Filter type C */ { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_A, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); + } + if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 4, 1); + } + if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 4, 0); + } + if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 0); + } + if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_B, 29); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 0); + } + if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 0); + } + if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_B, 16); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); + } + if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_B, 7); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); + } + if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); } } - if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only - { - printk("%s() CH filter\n", __func__); - status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) - { - - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off - } - if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off - } - if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On - } - if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On - } - if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On - } - if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On - } - if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off - } - if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off - } - if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_C_H) { + + /* Tracking Filter type C-H for Hauppauge only */ + status += MXL_ControlWrite(fe, DAC_DIN_A, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + } + if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 0); + status += MXL_SetGPIO(fe, 1, 1); + } + if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 0); + status += MXL_SetGPIO(fe, 1, 0); + } + if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 0); + } + if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 0); + } + if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 0); + } + if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + } + if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + } + if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); } } - if (state->TF_Type == MXL_TF_D) // Tracking Filter type D - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_D) { /* Tracking Filter type D */ + + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } - - if (state->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 - { - status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; - - // if UHF and terrestrial => Turn off Tracking Filter - if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0) - { - // Turn off all the banks - status += MXL_SetGPIO(fe, 3, 1) ; - status += MXL_SetGPIO(fe, 1, 1) ; - status += MXL_SetGPIO(fe, 4, 1) ; - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; - - status += MXL_ControlWrite(fe, AGC_IF, 10) ; - } - - else // if VHF or cable => Turn on Tracking Filter - { - if (state->RF_IN >= 43000000 && state->RF_IN < 140000000) - { - - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off + if (state->TF_Type == MXL_TF_D_L) { + + /* Tracking Filter type D-L for Lumanate ONLY change 2.6.3 */ + status += MXL_ControlWrite(fe, DAC_DIN_A, 0); + + /* if UHF and terrestrial => Turn off Tracking Filter */ + if (state->RF_IN >= 471000000 && + (state->RF_IN - 471000000)%6000000 != 0) { + /* Turn off all the banks */ + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, AGC_IF, 10); + } else { + /* if VHF or cable => Turn on Tracking Filter */ + if (state->RF_IN >= 43000000 && + state->RF_IN < 140000000) { + + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); } - if (state->RF_IN >= 140000000 && state->RF_IN < 240000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off + if (state->RF_IN >= 140000000 && + state->RF_IN < 240000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); } - if (state->RF_IN >= 240000000 && state->RF_IN < 340000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off + if (state->RF_IN >= 240000000 && + state->RF_IN < 340000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); } - if (state->RF_IN >= 340000000 && state->RF_IN < 430000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On + if (state->RF_IN >= 340000000 && + state->RF_IN < 430000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); } - if (state->RF_IN >= 430000000 && state->RF_IN < 470000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On + if (state->RF_IN >= 430000000 && + state->RF_IN < 470000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); } - if (state->RF_IN >= 470000000 && state->RF_IN < 570000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On + if (state->RF_IN >= 470000000 && + state->RF_IN < 570000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); } - if (state->RF_IN >= 570000000 && state->RF_IN < 620000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Offq + if (state->RF_IN >= 570000000 && + state->RF_IN < 620000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } - if (state->RF_IN >= 620000000 && state->RF_IN < 760000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->RF_IN >= 620000000 && + state->RF_IN < 760000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } - if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->RF_IN >= 760000000 && + state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } } - if (state->TF_Type == MXL_TF_E) // Tracking Filter type E - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_E) /* Tracking Filter type E */ { + + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } - if (state->TF_Type == MXL_TF_F) // Tracking Filter type F - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_F) { + + /* Tracking Filter type F */ + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } - if (state->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_E_2) { + + /* Tracking Filter type E_2 */ + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } - if (state->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) //modified for 2.6.11 - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_G) { + + /* Tracking Filter type G add for v2.6.8 */ + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) { + + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } - if (state->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - // if UHF and terrestrial=> Turn off Tracking Filter - if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0) - { - // Turn off all the banks - status += MXL_SetGPIO(fe, 3, 1) ; - status += MXL_SetGPIO(fe, 1, 1) ; - status += MXL_SetGPIO(fe, 4, 1) ; - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; - - //2.6.12 - //Turn on RSSI - status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1) ; - - // RSSI reference point - status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5) ; - status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3) ; - status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2) ; - - - //status += MXL_ControlWrite(fe, AGC_IF, 10) ; //doesn't matter since RSSI is turn on - - //following parameter is from analog OTA mode, can be change to seek better performance - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ; - } - - else //if VHF or Cable => Turn on Tracking Filter - { - //2.6.12 - //Turn off RSSI - status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0) ; - - //change back from above condition - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5) ; - - - if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_E_NA) { + + /* Tracking Filter type E-NA for Empia ONLY change for 2.6.8 */ + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + /* if UHF and terrestrial=> Turn off Tracking Filter */ + if (state->RF_IN >= 471000000 && + (state->RF_IN - 471000000)%6000000 != 0) { + + /* Turn off all the banks */ + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + + /* 2.6.12 Turn on RSSI */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); + + /* following parameter is from analog OTA mode, + * can be change to seek better performance */ + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); + } else { + /* if VHF or Cable => Turn on Tracking Filter */ + + /* 2.6.12 Turn off RSSI */ + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); + + /* change back from above condition */ + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); + + + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { + + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } } @@ -3679,72 +3395,24 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) return status; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_ControlWrite // -// // -// Description: Update control name value // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// MXL_ControlWrite( Tuner, controlName, value, Group ) // -// // -// Inputs: // -// Tuner : Tuner structure // -// ControlName : Control name to be updated // -// value : Value to be written // -// // -// Outputs: // -// Tuner : Tuner structure defined at higher level // -// // -// Return: // -// 0 : Successful write // -// >0 : Value exceed maximum allowed for control number // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { u16 status = 0; /* Will write ALL Matching Control Name */ - status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control */ - status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control */ + /* Write Matching INIT Control */ + status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); + /* Write Matching CH Control */ + status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); #ifdef _MXL_INTERNAL - status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control */ + /* Write Matching MXL Control */ + status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); #endif return status; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_ControlWrite // -// // -// Description: Update control name value // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// strcmp // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// ControlName : Control Name // -// value : Value Assigned to Control Name // -// controlGroup : Control Register Group // -// // -// Outputs: // -// NONE // -// // -// Return: // -// 0 : Successful write // -// 1 : Value exceed maximum allowed for control name // -// 2 : Control name not found // -// // -/////////////////////////////////////////////////////////////////////////////// -u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) +u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, + u16 controlGroup) { struct mxl5005s_state *state = fe->tuner_priv; u16 i, j, k; @@ -3763,13 +3431,12 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]), (u8)(state->Init_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ); + (u8)((value>>j) & 0x01)); } ctrlVal = 0; for (k = 0; k < state->Init_Ctrl[i].size; k++) ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); - } - else + } else return -1; } } @@ -3778,7 +3445,7 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u for (i = 0; i < state->CH_Ctrl_Num; i++) { - if (controlNum == state->CH_Ctrl[i].Ctrl_Num ) { + if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { highLimit = 1 << state->CH_Ctrl[i].size; if (value < highLimit) { @@ -3786,13 +3453,12 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]), (u8)(state->CH_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ); + (u8)((value>>j) & 0x01)); } ctrlVal = 0; for (k = 0; k < state->CH_Ctrl[i].size; k++) ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); - } - else + } else return -1; } } @@ -3802,21 +3468,20 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u for (i = 0; i < state->MXL_Ctrl_Num; i++) { - if (controlNum == state->MXL_Ctrl[i].Ctrl_Num ) { + if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { - highLimit = (1 << state->MXL_Ctrl[i].size) ; + highLimit = (1 << state->MXL_Ctrl[i].size); if (value < highLimit) { for (j = 0; j < state->MXL_Ctrl[i].size; j++) { state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]), (u8)(state->MXL_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ); + (u8)((value>>j) & 0x01)); } ctrlVal = 0; - for(k = 0; k < state->MXL_Ctrl[i].size; k++) + for (k = 0; k < state->MXL_Ctrl[i].size; k++) ctrlVal += state->MXL_Ctrl[i].val[k] * (1 << k); - } - else + } else return -1; } } @@ -3825,31 +3490,6 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u return 0 ; /* successful return */ } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_RegWrite // -// // -// Description: Update tuner register value // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// RegNum : Register address to be assigned a value // -// RegVal : Register value to write // -// // -// Outputs: // -// NONE // -// // -// Return: // -// 0 : Successful write // -// -1 : Invalid Register Address // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3865,37 +3505,13 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) return 1; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_RegRead // -// // -// Description: Retrieve tuner register value // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// RegNum : Register address to be assigned a value // -// // -// Outputs: // -// RegVal : Retrieved register value // -// // -// Return: // -// 0 : Successful read // -// -1 : Invalid Register Address // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; int i ; for (i = 0; i < 104; i++) { - if (RegNum == state->TunerRegs[i].Reg_Num ) { + if (RegNum == state->TunerRegs[i].Reg_Num) { *RegVal = (u8)(state->TunerRegs[i].Reg_Val); return 0; } @@ -3904,27 +3520,6 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) return 1; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_ControlRead // -// // -// Description: Retrieve the control value based on the control name // -// // -// Globals: // -// NONE // -// // -// Inputs: // -// Tuner_struct : structure defined at higher level // -// ControlName : Control Name // -// // -// Outputs: // -// value : returned control value // -// // -// Return: // -// 0 : Successful read // -// -1 : Invalid control name // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3937,7 +3532,7 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) ctrlVal = 0; for (k = 0; k < state->Init_Ctrl[i].size; k++) - ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); + ctrlVal += state->Init_Ctrl[i].val[k] * (1<tuner_priv; u16 i, j, k ; @@ -4004,7 +3577,7 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int for (i = 0; i < state->Init_Ctrl_Num ; i++) { - if ( controlNum == state->Init_Ctrl[i].Ctrl_Num ) { + if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { Count = 1; RegNum[0] = (u8)(state->Init_Ctrl[i].addr[0]); @@ -4013,9 +3586,10 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int for (j = 0; j < Count; j++) { - if (state->Init_Ctrl[i].addr[k] != RegNum[j]) { + if (state->Init_Ctrl[i].addr[k] != + RegNum[j]) { - Count ++; + Count++; RegNum[Count-1] = (u8)(state->Init_Ctrl[i].addr[k]); } @@ -4028,18 +3602,19 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int } for (i = 0; i < state->CH_Ctrl_Num ; i++) { - if ( controlNum == state->CH_Ctrl[i].Ctrl_Num ) { + if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { Count = 1; RegNum[0] = (u8)(state->CH_Ctrl[i].addr[0]); for (k = 1; k < state->CH_Ctrl[i].size; k++) { - for (j= 0; jCH_Ctrl[i].addr[k] != RegNum[j]) { + if (state->CH_Ctrl[i].addr[k] != + RegNum[j]) { - Count ++; + Count++; RegNum[Count-1] = (u8)(state->CH_Ctrl[i].addr[k]); } @@ -4052,18 +3627,19 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int #ifdef _MXL_INTERNAL for (i = 0; i < state->MXL_Ctrl_Num ; i++) { - if ( controlNum == state->MXL_Ctrl[i].Ctrl_Num ) { + if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { Count = 1; RegNum[0] = (u8)(state->MXL_Ctrl[i].addr[0]); for (k = 1; k < state->MXL_Ctrl[i].size; k++) { - for (j = 0; jMXL_Ctrl[i].addr[k] != RegNum[j]) { + if (state->MXL_Ctrl[i].addr[k] != + RegNum[j]) { - Count ++; + Count++; RegNum[Count-1] = (u8)state->MXL_Ctrl[i].addr[k]; } @@ -4078,29 +3654,6 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int return 1; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_RegWriteBit // -// // -// Description: Write a register for specified register address, // -// register bit and register bit value // -// // -// Globals: // -// NONE // -// // -// Inputs: // -// Tuner_struct : structure defined at higher level // -// address : register address // -// bit : register bit number // -// bitVal : register bit value // -// // -// Outputs: // -// NONE // -// // -// Return: // -// NONE // -// // -/////////////////////////////////////////////////////////////////////////////// void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4125,38 +3678,14 @@ void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) } } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_Ceiling // -// // -// Description: Complete to closest increment of resolution // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// value : Input number to compute // -// resolution : Increment step // -// // -// Outputs: // -// NONE // -// // -// Return: // -// Computed value // -// // -/////////////////////////////////////////////////////////////////////////////// u32 MXL_Ceiling(u32 value, u32 resolution) { return (value/resolution + (value % resolution > 0 ? 1 : 0)); } -// -// Retrieve the Initialzation Registers -// -u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) +/* Retrieve the Initialzation Registers */ +u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count) { u16 status = 0; int i ; @@ -4178,21 +3707,24 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c return status; } -u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) +u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, + int *count) { u16 status = 0; int i ; -//add 77, 166, 167, 168 register for 2.6.12 +/* add 77, 166, 167, 168 register for 2.6.12 */ #ifdef _MXL_PRODUCTION u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; #else u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; - //u8 RegAddr[171]; - //for (i=0; i<=170; i++) - // RegAddr[i] = i; + /* + u8 RegAddr[171]; + for (i = 0; i <= 170; i++) + RegAddr[i] = i; + */ #endif *count = sizeof(RegAddr) / sizeof(u8); @@ -4205,7 +3737,8 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou return status; } -u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) +u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, + int *count) { u16 status = 0; int i; @@ -4222,7 +3755,8 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i return status; } -u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) +u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, + int *count) { u16 status = 0; int i; @@ -4267,23 +3801,28 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); - if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 1) { + /* Analog Low IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 180224); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 180224); } - if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 0) { + /* Analog Zero IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 222822); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 222822); } if (state->Mode == 1) /* Digital Mode */ { status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 229376); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 229376); } } @@ -4298,23 +3837,28 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); - if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 1) { + /* Analog Low IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 206438); } - if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 0) { + /* Analog Zero IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 206438); } if (state->Mode == 1) /* Digital Mode */ { status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 16384); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 16384); } } @@ -4329,23 +3873,28 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); - if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 1) { + /* Analog Low IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 173670); } - if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 0) { + /* Analog Zero IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 173670); } if (state->Mode == 1) /* Digital Mode */ { status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 245760); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 245760); } } @@ -4360,23 +3909,28 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); - if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 1) { + /* Analog Low IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 206438); } - if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 0) { + /* Analog Zero IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 206438); } if (state->Mode == 1) /* Digital Mode */ { status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 212992); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 212992); } } @@ -4440,7 +3994,7 @@ static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) if (latch == 0) msg.len = 2; - dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); + dprintk(2, "%s(0x%x, 0x%x, 0x%x)\n", __func__, reg, val, msg.addr); if (i2c_transfer(state->i2c, &msg, 1) != 1) { printk(KERN_WARNING "mxl5005s I2C write failed\n"); @@ -4449,7 +4003,8 @@ static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) return 0; } -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len) +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, + u8 len) { int ret = 0, i; @@ -4506,7 +4061,8 @@ int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) return 0; } -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, + u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; struct mxl5005s_config *c = state->config; @@ -4553,8 +4109,8 @@ static int mxl5005s_set_params(struct dvb_frontend *fe, case QAM_AUTO: req_mode = MXL_QAM; break; } - } - else req_mode = MXL_DVBT; + } else + req_mode = MXL_DVBT; /* Change tuner for new modulation type if reqd */ if (req_mode != state->current_mode) { @@ -4655,9 +4211,11 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, state->i2c = i2c; state->current_mode = MXL_QAM; - printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address); + printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", + config->i2c_address); - memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops, sizeof(struct dvb_tuner_ops)); + memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops, + sizeof(struct dvb_tuner_ops)); fe->tuner_priv = state; return fe; -- cgit v1.2.3 From c6c34b1ffd40e00191e05bf0ef543a35ccd7d75d Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Sat, 3 May 2008 14:14:54 -0300 Subject: V4L/DVB(7874): mxl5005s: Fix function statics Fix function statics Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 121 +++++++++++++++++---------------- 1 file changed, 62 insertions(+), 59 deletions(-) (limited to 'drivers/media/common/tuners/mxl5005s.c') diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 21dca5bdca77..96391648871a 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -295,32 +295,34 @@ struct mxl5005s_state { }; -u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); -u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); -u16 MXL_GetMasterControl(u8 *MasterReg, int state); -void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal); -u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, +static u16 MXL_GetMasterControl(u8 *MasterReg, int state); +static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); +static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); +static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, + u8 bitVal); +static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -u32 MXL_Ceiling(u32 value, u32 resolution); -u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); -u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal); -u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, +static u32 MXL_Ceiling(u32 value, u32 resolution); +static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); +static u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal); +static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup); -u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); -u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, +static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); +static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -u32 MXL_GetXtalInt(u32 Xtal_Freq); -u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); -void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); -void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); -u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, +static u32 MXL_GetXtalInt(u32 Xtal_Freq); +static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); +static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); +static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); +static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, +static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len); -u16 MXL_IFSynthInit(struct dvb_frontend *fe); -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, +static u16 MXL_IFSynthInit(struct dvb_frontend *fe); +static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, + u32 bandwidth); +static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); -int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); /* ---------------------------------------------------------------- * Begin: Custom code salvaged from the Realtek driver. @@ -334,14 +336,14 @@ int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); * Revision: 080314 - original version */ -int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) +static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { struct mxl5005s_state *state = fe->tuner_priv; unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - u32 IfDivval; + u32 IfDivval = 0; unsigned char MasterControlByte; dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz); @@ -399,7 +401,7 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) * Begin: Reference driver code found in the Realtek driver. * Copyright (c) 2008 MaxLinear */ -u16 MXL5005_RegisterInit(struct dvb_frontend *fe) +static u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; state->TunerRegs_Num = TUNER_REGS_NUM ; @@ -719,7 +721,7 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) return 0 ; } -u16 MXL5005_ControlInit(struct dvb_frontend *fe) +static u16 MXL5005_ControlInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; state->Init_Ctrl_Num = INITCTRL_NUM; @@ -1659,7 +1661,7 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) return 0 ; } -void InitTunerControls(struct dvb_frontend *fe) +static void InitTunerControls(struct dvb_frontend *fe) { MXL5005_RegisterInit(fe); MXL5005_ControlInit(fe); @@ -1668,7 +1670,7 @@ void InitTunerControls(struct dvb_frontend *fe) #endif } -u16 MXL5005_TunerConfig(struct dvb_frontend *fe, +static u16 MXL5005_TunerConfig(struct dvb_frontend *fe, u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ @@ -1718,7 +1720,7 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, return status; } -void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) +static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; if (state->Mode == 1) /* Digital Mode */ @@ -1731,7 +1733,7 @@ void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) } } -void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) +static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1752,7 +1754,7 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) } } -u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) +static u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { u16 status = 0; @@ -1764,7 +1766,7 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) return status; } -u16 MXL_BlockInit(struct dvb_frontend *fe) +static u16 MXL_BlockInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; @@ -2102,7 +2104,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) return status; } -u16 MXL_IFSynthInit(struct dvb_frontend *fe) +static u16 MXL_IFSynthInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0 ; @@ -2306,7 +2308,7 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe) return status ; } -u32 MXL_GetXtalInt(u32 Xtal_Freq) +static u32 MXL_GetXtalInt(u32 Xtal_Freq) { if ((Xtal_Freq % 1000000) == 0) return (Xtal_Freq / 10000); @@ -2314,7 +2316,7 @@ u32 MXL_GetXtalInt(u32 Xtal_Freq) return (((Xtal_Freq / 1000000) + 1)*100); } -u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) +static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; @@ -3354,7 +3356,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) return status ; } -u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) +static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { u16 status = 0; @@ -3395,7 +3397,7 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) return status; } -u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) +static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { u16 status = 0; @@ -3411,8 +3413,8 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) return status; } -u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, - u16 controlGroup) +static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, + u32 value, u16 controlGroup) { struct mxl5005s_state *state = fe->tuner_priv; u16 i, j, k; @@ -3490,7 +3492,7 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, return 0 ; /* successful return */ } -u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) +static u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { struct mxl5005s_state *state = fe->tuner_priv; int i ; @@ -3505,7 +3507,7 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) return 1; } -u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) +static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; int i ; @@ -3520,7 +3522,7 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) return 1; } -u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) +static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { struct mxl5005s_state *state = fe->tuner_priv; u32 ctrlVal ; @@ -3568,8 +3570,8 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) return 1; } -u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, - int *count) +static u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, + u8 *RegNum, int *count) { struct mxl5005s_state *state = fe->tuner_priv; u16 i, j, k ; @@ -3654,7 +3656,8 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, return 1; } -void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) +static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, + u8 bitVal) { struct mxl5005s_state *state = fe->tuner_priv; int i ; @@ -3678,13 +3681,13 @@ void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) } } -u32 MXL_Ceiling(u32 value, u32 resolution) +static u32 MXL_Ceiling(u32 value, u32 resolution) { return (value/resolution + (value % resolution > 0 ? 1 : 0)); } /* Retrieve the Initialzation Registers */ -u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, +static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -3707,7 +3710,7 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, return status; } -u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, +static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -3737,8 +3740,8 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, return status; } -u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, - int *count) +static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count) { u16 status = 0; int i; @@ -3755,8 +3758,8 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, return status; } -u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, - int *count) +static u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count) { u16 status = 0; int i; @@ -3773,7 +3776,7 @@ u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, return status; } -u16 MXL_GetMasterControl(u8 *MasterReg, int state) +static u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) /* Load_Start */ *MasterReg = 0xF3; @@ -3788,7 +3791,7 @@ u16 MXL_GetMasterControl(u8 *MasterReg, int state) } #ifdef _MXL_PRODUCTION -u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) +static u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0 ; @@ -3937,7 +3940,7 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) return status; } -u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) +static u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; @@ -4003,8 +4006,8 @@ static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) return 0; } -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, - u8 len) +static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, + u8 *datatable, u8 len) { int ret = 0, i; @@ -4025,14 +4028,14 @@ int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, return ret; } - -int mxl5005s_init(struct dvb_frontend *fe) +static int mxl5005s_init(struct dvb_frontend *fe) { dprintk(1, "%s()\n", __func__); return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ); } -int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) +static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, + u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4061,7 +4064,7 @@ int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) return 0; } -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, +static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; -- cgit v1.2.3 From 90257e787faaf5ebfaa1839917e4dc6c5c104c14 Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Sat, 3 May 2008 14:21:58 -0300 Subject: V4L/DVB(7875): mxl5005s: Remove redundant functions Remove redundant functions Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 120 --------------------------------- 1 file changed, 120 deletions(-) (limited to 'drivers/media/common/tuners/mxl5005s.c') diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 96391648871a..786f8daa6de9 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -304,7 +304,6 @@ static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); static u32 MXL_Ceiling(u32 value, u32 resolution); static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); -static u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal); static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup); static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); @@ -3492,21 +3491,6 @@ static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, return 0 ; /* successful return */ } -static u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) -{ - struct mxl5005s_state *state = fe->tuner_priv; - int i ; - - for (i = 0; i < 104; i++) { - if (RegNum == state->TunerRegs[i].Reg_Num) { - state->TunerRegs[i].Reg_Val = RegVal; - return 0; - } - } - - return 1; -} - static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3570,92 +3554,6 @@ static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) return 1; } -static u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, - u8 *RegNum, int *count) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u16 i, j, k ; - u16 Count ; - - for (i = 0; i < state->Init_Ctrl_Num ; i++) { - - if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { - - Count = 1; - RegNum[0] = (u8)(state->Init_Ctrl[i].addr[0]); - - for (k = 1; k < state->Init_Ctrl[i].size; k++) { - - for (j = 0; j < Count; j++) { - - if (state->Init_Ctrl[i].addr[k] != - RegNum[j]) { - - Count++; - RegNum[Count-1] = (u8)(state->Init_Ctrl[i].addr[k]); - - } - } - - } - *count = Count; - return 0; - } - } - for (i = 0; i < state->CH_Ctrl_Num ; i++) { - - if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { - - Count = 1; - RegNum[0] = (u8)(state->CH_Ctrl[i].addr[0]); - - for (k = 1; k < state->CH_Ctrl[i].size; k++) { - - for (j = 0; j < Count; j++) { - - if (state->CH_Ctrl[i].addr[k] != - RegNum[j]) { - - Count++; - RegNum[Count-1] = (u8)(state->CH_Ctrl[i].addr[k]); - - } - } - } - *count = Count; - return 0; - } - } -#ifdef _MXL_INTERNAL - for (i = 0; i < state->MXL_Ctrl_Num ; i++) { - - if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { - - Count = 1; - RegNum[0] = (u8)(state->MXL_Ctrl[i].addr[0]); - - for (k = 1; k < state->MXL_Ctrl[i].size; k++) { - - for (j = 0; j < Count; j++) { - - if (state->MXL_Ctrl[i].addr[k] != - RegNum[j]) { - - Count++; - RegNum[Count-1] = (u8)state->MXL_Ctrl[i].addr[k]; - - } - } - } - *count = Count; - return 0; - } - } -#endif - *count = 0; - return 1; -} - static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { @@ -3758,24 +3656,6 @@ static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, return status; } -static u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum, - u8 *RegVal, int *count) -{ - u16 status = 0; - int i; - - u8 RegAddr[] = { 138 }; - - *count = sizeof(RegAddr) / sizeof(u8); - - for (i = 0; i < *count; i++) { - RegNum[i] = RegAddr[i]; - status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); - } - - return status; -} - static u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) /* Load_Start */ -- cgit v1.2.3 From 7fa2a1462fe0a258fb629f8447f31c1b3a6d6c68 Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Sat, 3 May 2008 14:25:55 -0300 Subject: V4L/DVB(7876): mxl5005s: Remove incorrect copyright holders I was informed by Jan Hoogenraad that two people needed to be removed from the original copyright comments. Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/media/common/tuners/mxl5005s.c') diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 786f8daa6de9..a32c35766a4d 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -16,8 +16,8 @@ mxl5005s_release() mxl5005s_attach() - Copyright (c) 2008 Realtek - Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + Copyright (C) 2008 Realtek + Copyright (C) 2008 Jan Hoogenraad Functions: mxl5005s_SetRfFreqHz() @@ -325,8 +325,8 @@ static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, /* ---------------------------------------------------------------- * Begin: Custom code salvaged from the Realtek driver. - * Copyright (c) 2008 Realtek - * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * Copyright (C) 2008 Realtek + * Copyright (C) 2008 Jan Hoogenraad * This code is placed under the terms of the GNU General Public License * * Released by Realtek under GPLv2. @@ -398,7 +398,7 @@ static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) /* ---------------------------------------------------------------- * Begin: Reference driver code found in the Realtek driver. - * Copyright (c) 2008 MaxLinear + * Copyright (C) 2008 MaxLinear */ static u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { -- cgit v1.2.3 From 77ad55ec2159735b1b88a006a90f8dd2ffe291ca Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Sat, 3 May 2008 14:28:43 -0300 Subject: V4L/DVB(7877): mxl5005s: Ensure debug is off Ensure debug is off Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/media/common/tuners/mxl5005s.c') diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index a32c35766a4d..5d05b5390f66 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -66,7 +66,7 @@ #include "dvb_frontend.h" #include "mxl5005s.h" -static int debug = 2; +static int debug; #define dprintk(level, arg...) do { \ if (level <= debug) \ -- cgit v1.2.3 From 38db143e6feaa2dc649ed8bf69d1a12f7b9c0246 Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Fri, 16 May 2008 00:15:53 -0300 Subject: V4L/DVB (7906): tuners/mxl5005s.c: don't define variables for enums It doesn't seem to be intended that "tuner_modu_type" and "MXL5005_ControlName" were global variables. Signed-off-by: Adrian Bunk Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/media/common/tuners/mxl5005s.c') diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 5d05b5390f66..0dc2bef9f6a3 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -101,7 +101,7 @@ enum { MXL_QAM, MXL_ANALOG_CABLE, MXL_ANALOG_OTA -} tuner_modu_type; +}; /* MXL5005 Tuner Register Struct */ struct TunerReg { @@ -194,7 +194,7 @@ enum { RFSYN_DIVM, /* 88 */ DN_BYPASS_AGC_I2C /* 89 */ #endif -} MXL5005_ControlName; +}; /* * The following context is source code provided by MaxLinear. -- cgit v1.2.3