From 33feef46b497893696039f54160a447be4a1e66c Mon Sep 17 00:00:00 2001 From: Han Xu Date: Fri, 10 Nov 2017 17:37:22 -0600 Subject: MLK-16800: dma: mxs-dma: correctly handle mxs-dma clock enable mxs-dma clock before HW reset and disable clock after it. BuildInfo: - SCFW 15d20cde, IMX-MKIMAGE ff9860c5, ATF - U-Boot 2017.03-00003-gd09f5db Signed-off-by: Han Xu (cherry picked from commit e3176f6d8e71085ebe4bd36ae99380f1acc957dc) --- drivers/dma/mxs-dma.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers') diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c index f585b2737c9a..1b829d59d2a1 100644 --- a/drivers/dma/mxs-dma.c +++ b/drivers/dma/mxs-dma.c @@ -1,5 +1,6 @@ /* * Copyright 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP * * Refer to drivers/dma/imx-sdma.c * @@ -728,12 +729,19 @@ static int mxs_dma_init_rpm(struct mxs_dma_engine *mxs_dma) static int mxs_dma_init(struct mxs_dma_engine *mxs_dma) { + struct device *dev = &mxs_dma->pdev->dev; int ret; ret = mxs_dma_init_rpm(mxs_dma); if (ret) return ret; + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable clock\n"); + return ret; + } + ret = stmp_reset_block(mxs_dma->base); if (ret) goto err_clk; @@ -750,6 +758,9 @@ static int mxs_dma_init(struct mxs_dma_engine *mxs_dma) writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS, mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + err_clk: return ret; } -- cgit v1.2.3