From 33efbe6a9e3aae7bcad3592b927606bf6db18b6c Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Sat, 13 May 2017 16:03:19 +0800 Subject: MLK-17491-35 clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and denominator value in register are start from 0. This can be used to support frac dividers like below: Divider output clock = Divider input clock x [(frac +1) / (div +1)] where frac/div in register is: 000b - Divide by 1. 001b - Divide by 2. 010b - Divide by 3. Cc: Anson Huang Reviewed-by: Bai Ping Signed-off-by: Dong Aisheng --- include/linux/clk-provider.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include/linux/clk-provider.h') diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 4db531ba3597..83030fcc554b 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -565,6 +565,12 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw); * @lock: register lock * * Clock with adjustable fractional divider affecting its output frequency. + * + * Flags: + * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator + * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED + * is set then the numerator and denominator are both the value read + * plus one. */ struct clk_fractional_divider { struct clk_hw hw; @@ -584,6 +590,8 @@ struct clk_fractional_divider { #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) +#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) + extern const struct clk_ops clk_fractional_divider_ops; struct clk *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, -- cgit v1.2.3