From babaf479582f7697fbfd4c001945fbfb766d914d Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Mon, 9 Sep 2019 15:04:37 +0300 Subject: apalis/colibri t30: fix record/playback for sgtl5000 codec Backported commit f997df18c0e4c988de49e984329cefdf6e13ed86 According to the manual [1], SYS_MCLK should base on SYS_FS, not on sample rate. Calculating SYS_MCLK using sample rate only prevents playing/recording samples with rate < 16 kHz: --------------------------------------------------------------- root@apalis-t30:~# aplay test-8k-sample.wav Playing WAVE 'test-8k-sample.wav' : Signed 16 bit [...] tegra-snd-apalis-tk1-sgtl5000 tegra-snd-apalis-tk1-sgtl5000.0: ASoC: machine hw_params failed: -22 Little Endian, Rate 8000 Hz, Stereo aplay: set_params:1403: Unable to install hw params: ... --------------------------------------------------------------- Using the helper from sgtl5000.h fixes this issue. To keep determination of sys_fs solid, use a helper in device driver. [1] https://www.nxp.com/docs/en/data-sheet/SGTL5000.pdf Signed-off-by: Oleksandr Suvorov --- sound/soc/codecs/sgtl5000.c | 22 ++++------------------ 1 file changed, 4 insertions(+), 18 deletions(-) (limited to 'sound/soc/codecs/sgtl5000.c') diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c index b2228e0f5472..22f76d4895dc 100644 --- a/sound/soc/codecs/sgtl5000.c +++ b/sound/soc/codecs/sgtl5000.c @@ -732,27 +732,13 @@ static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate) int clk_ctl = 0; int sys_fs; /* sample freq */ - /* - * sample freq should be divided by frame clock, - * if frame clock lower than 44.1khz, sample feq should set to - * 32khz or 44.1khz. - */ - switch (frame_rate) { - case 8000: - case 16000: - sys_fs = 32000; - break; - case 11025: - case 22050: - sys_fs = 44100; - break; - default: - sys_fs = frame_rate; - break; - } + sys_fs = sgtl5000_srate_to_sys_fs(frame_rate); /* set divided factor of frame clock */ switch (sys_fs / frame_rate) { + case 6: + clk_ctl |= SGTL5000_RATE_MODE_DIV_6 << SGTL5000_RATE_MODE_SHIFT; + break; case 4: clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; break; -- cgit v1.2.3