/* * Copyright 2013 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * */ #include "imx6q-pinfunc.h" #include "imx6qdl.dtsi" / { aliases { ipu1 = &ipu2; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; operating-points = < /* kHz uV */ 1200000 1275000 996000 1250000 852000 1250000 792000 1150000 396000 975000 >; fsl,soc-operating-points = < /* ARM kHz SOC-PU uV */ 1200000 1275000 996000 1250000 852000 1250000 792000 1175000 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks 104>, <&clks 6>, <&clks 16>, <&clks 17>, <&clks 170>; clock-names = "arm", "pll2_pfd2_396m", "step", "pll1_sw", "pll1_sys"; arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; }; cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; }; cpu@2 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <2>; next-level-cache = <&L2>; }; cpu@3 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <3>; next-level-cache = <&L2>; }; }; soc { busfreq { /* BUSFREQ */ compatible = "fsl,imx6_busfreq"; clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>, <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>; clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc"; interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>; interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; fsl,max_ddr_freq = <528000000>; }; gpu: gpu@00130000 { compatible = "fsl,imx6q-gpu"; reg = <0x00130000 0x4000>, <0x00134000 0x4000>, <0x02204000 0x4000>, <0x0 0x0>; reg-names = "iobase_3d", "iobase_2d", "iobase_vg", "phys_baseaddr"; interrupts = <0 9 0x04>, <0 10 0x04>,<0 11 0x04>; interrupt-names = "irq_3d", "irq_2d", "irq_vg"; clocks = <&clks 26>, <&clks 143>, <&clks 27>, <&clks 121>, <&clks 122>, <&clks 74>; clock-names = "gpu2d_axi_clk", "openvg_axi_clk", "gpu3d_axi_clk", "gpu2d_clk", "gpu3d_clk", "gpu3d_shader_clk"; resets = <&src 0>, <&src 3>, <&src 3>; reset-names = "gpu3d", "gpu2d", "gpuvg"; pu-supply = <®_pu>; }; ocram: sram@00900000 { compatible = "mmio-sram"; reg = <0x00904000 0x3C000>; clocks = <&clks 142>; }; hdmi_core: hdmi_core@00120000 { compatible = "fsl,imx6q-hdmi-core"; reg = <0x00120000 0x9000>; clocks = <&clks 124>, <&clks 123>; clock-names = "hdmi_isfr", "hdmi_iahb"; status = "disabled"; }; hdmi_video: hdmi_video@020e0000 { compatible = "fsl,imx6q-hdmi-video"; reg = <0x020e0000 0x1000>; reg-names = "hdmi_gpr"; interrupts = <0 115 0x04>; clocks = <&clks 124>, <&clks 123>; clock-names = "hdmi_isfr", "hdmi_iahb"; status = "disabled"; }; hdmi_audio: hdmi_audio@00120000 { compatible = "fsl,imx6q-hdmi-audio"; clocks = <&clks 124>, <&clks 123>; clock-names = "hdmi_isfr", "hdmi_iahb"; dmas = <&sdma 2 22 0>; dma-names = "tx"; status = "disabled"; }; hdmi_cec: hdmi_cec@00120000 { compatible = "fsl,imx6q-hdmi-cec"; interrupts = <0 115 0x04>; status = "disabled"; }; aips-bus@02000000 { /* AIPS1 */ spba-bus@02000000 { ecspi5: ecspi@02018000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02018000 0x4000>; interrupts = <0 35 0x04>; clocks = <&clks 116>, <&clks 116>; clock-names = "ipg", "per"; status = "disabled"; }; }; vpu@02040000 { status = "okay"; }; iomuxc: iomuxc@020e0000 { compatible = "fsl,imx6q-iomuxc"; }; }; aips-bus@02100000 { /* AIPS2 */ mipi_dsi: mipi@021e0000 { compatible = "fsl,imx6q-mipi-dsi"; reg = <0x021e0000 0x4000>; interrupts = <0 102 0x04>; gpr = <&gpr>; clocks = <&clks 138>, <&clks 204>; clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; status = "disabled"; }; }; sata: sata@02200000 { compatible = "fsl,imx6q-ahci"; reg = <0x02200000 0x4000>; interrupts = <0 39 0x04>; clocks = <&clks 154>, <&clks 187>, <&clks 105>; clock-names = "sata", "sata_ref", "ahb"; status = "disabled"; }; ipu2: ipu@02800000 { compatible = "fsl,imx6q-ipu"; reg = <0x02800000 0x400000>; interrupts = <0 8 0x4 0 7 0x4>; clocks = <&clks 133>, <&clks 134>, <&clks 137>, <&clks 41>, <&clks 42>, <&clks 135>, <&clks 136>; clock-names = "bus", "di0", "di1", "di0_sel", "di1_sel", "ldb_di0", "ldb_di1"; resets = <&src 4>; bypass_reset = <0>; }; }; }; &iomuxc { ipu2 { pinctrl_ipu2_1: ipu2grp-1 { fsl,pins = < MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10 MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10 MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10 MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10 MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10 MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10 MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10 MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10 MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10 MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10 >; }; }; };