/* * Copyright (c) 2015, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ /dts-v1/; #include "skeleton.dtsi" #include #include #include / { model = "Qualcomm Technologies, Inc. IPQ4019"; compatible = "qcom,ipq4019"; interrupt-parent = <&intc>; aliases { spi0 = &spi_0; i2c0 = &i2c_0; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; enable-method = "qcom,kpss-acc-v1"; qcom,acc = <&acc0>; qcom,saw = <&saw0>; reg = <0x0>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; operating-points = < /* kHz uV (fixed) */ 48000 1100000 200000 1100000 500000 1100000 666000 1100000 >; clock-latency = <256000>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; enable-method = "qcom,kpss-acc-v1"; qcom,acc = <&acc1>; qcom,saw = <&saw1>; reg = <0x1>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a7"; enable-method = "qcom,kpss-acc-v1"; qcom,acc = <&acc2>; qcom,saw = <&saw2>; reg = <0x2>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a7"; enable-method = "qcom,kpss-acc-v1"; qcom,acc = <&acc3>; qcom,saw = <&saw3>; reg = <0x3>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; }; }; pmu { compatible = "arm,cortex-a7-pmu"; interrupts = ; }; clocks { sleep_clk: sleep_clk { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; }; xo: xo { compatible = "fixed-clock"; clock-frequency = <48000000>; #clock-cells = <0>; }; }; timer { compatible = "arm,armv7-timer"; interrupts = <1 2 0xf08>, <1 3 0xf08>, <1 4 0xf08>, <1 1 0xf08>; clock-frequency = <48000000>; }; soc { #address-cells = <1>; #size-cells = <1>; ranges; compatible = "simple-bus"; intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; #interrupt-cells = <3>; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; }; gcc: clock-controller@1800000 { compatible = "qcom,gcc-ipq4019"; #clock-cells = <1>; #reset-cells = <1>; reg = <0x1800000 0x60000>; }; rng@22000 { compatible = "qcom,prng"; reg = <0x22000 0x140>; clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "core"; status = "disabled"; }; tlmm: pinctrl@1000000 { compatible = "qcom,ipq4019-pinctrl"; reg = <0x01000000 0x300000>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <0 208 0>; }; blsp_dma: dma@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07884000 0x23000>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; qcom,ee = <0>; status = "disabled"; }; spi_0: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x78b5000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c_0: i2c@78b7000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x78b7000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; clock-names = "iface", "core"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; cryptobam: dma@8e04000 { compatible = "qcom,bam-v1.7.0"; reg = <0x08e04000 0x20000>; interrupts = ; clocks = <&gcc GCC_CRYPTO_AHB_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; qcom,ee = <1>; qcom,controlled-remotely; status = "disabled"; }; crypto@8e3a000 { compatible = "qcom,crypto-v5.1"; reg = <0x08e3a000 0x6000>; clocks = <&gcc GCC_CRYPTO_AHB_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_CLK>; clock-names = "iface", "bus", "core"; dmas = <&cryptobam 2>, <&cryptobam 3>; dma-names = "rx", "tx"; status = "disabled"; }; acc0: clock-controller@b088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; }; acc1: clock-controller@b098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; }; acc2: clock-controller@b0a8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; }; acc3: clock-controller@b0b8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; }; saw0: regulator@b089000 { compatible = "qcom,saw2"; reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; regulator; }; saw1: regulator@b099000 { compatible = "qcom,saw2"; reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; regulator; }; saw2: regulator@b0a9000 { compatible = "qcom,saw2"; reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; regulator; }; saw3: regulator@b0b9000 { compatible = "qcom,saw2"; reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; regulator; }; serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78af000 0x200>; interrupts = <0 107 0>; status = "disabled"; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; dmas = <&blsp_dma 1>, <&blsp_dma 0>; dma-names = "rx", "tx"; }; serial@78b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78b0000 0x200>; interrupts = <0 108 0>; status = "disabled"; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; dmas = <&blsp_dma 3>, <&blsp_dma 2>; dma-names = "rx", "tx"; }; watchdog@b017000 { compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; reg = <0xb017000 0x40>; clocks = <&sleep_clk>; timeout-sec = <10>; status = "disabled"; }; restart@4ab000 { compatible = "qcom,pshold"; reg = <0x4ab000 0x4>; }; wifi0: wifi@a000000 { compatible = "qcom,ipq4019-wifi"; reg = <0xa000000 0x200000>; resets = <&gcc WIFI0_CPU_INIT_RESET>, <&gcc WIFI0_RADIO_SRIF_RESET>, <&gcc WIFI0_RADIO_WARM_RESET>, <&gcc WIFI0_RADIO_COLD_RESET>, <&gcc WIFI0_CORE_WARM_RESET>, <&gcc WIFI0_CORE_COLD_RESET>; reset-names = "wifi_cpu_init", "wifi_radio_srif", "wifi_radio_warm", "wifi_radio_cold", "wifi_core_warm", "wifi_core_cold"; clocks = <&gcc GCC_WCSS2G_CLK>, <&gcc GCC_WCSS2G_REF_CLK>, <&gcc GCC_WCSS2G_RTC_CLK>; clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", "wifi_wcss_rtc"; interrupts = , , , , , , , , , , , , , , , , ; interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "msi8", "msi9", "msi10", "msi11", "msi12", "msi13", "msi14", "msi15", "legacy"; status = "disabled"; }; wifi1: wifi@a800000 { compatible = "qcom,ipq4019-wifi"; reg = <0xa800000 0x200000>; resets = <&gcc WIFI1_CPU_INIT_RESET>, <&gcc WIFI1_RADIO_SRIF_RESET>, <&gcc WIFI1_RADIO_WARM_RESET>, <&gcc WIFI1_RADIO_COLD_RESET>, <&gcc WIFI1_CORE_WARM_RESET>, <&gcc WIFI1_CORE_COLD_RESET>; reset-names = "wifi_cpu_init", "wifi_radio_srif", "wifi_radio_warm", "wifi_radio_cold", "wifi_core_warm", "wifi_core_cold"; clocks = <&gcc GCC_WCSS5G_CLK>, <&gcc GCC_WCSS5G_REF_CLK>, <&gcc GCC_WCSS5G_RTC_CLK>; clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", "wifi_wcss_rtc"; interrupts = , , , , , , , , , , , , , , , , ; interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "msi8", "msi9", "msi10", "msi11", "msi12", "msi13", "msi14", "msi15", "legacy"; status = "disabled"; }; }; };