/* * Copyright 2014 Chen-Yu Tsai * * Chen-Yu Tsai * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include "sun8i-a23-a33.dtsi" #include / { cpu0_opp_table: opp_table0 { compatible = "operating-points-v2"; opp-shared; opp-120000000 { opp-hz = /bits/ 64 <120000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp-240000000 { opp-hz = /bits/ 64 <240000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp-312000000 { opp-hz = /bits/ 64 <312000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp-408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp-504000000 { opp-hz = /bits/ 64 <504000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp-648000000 { opp-hz = /bits/ 64 <648000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp-720000000 { opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1100000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp-816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <1100000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp-912000000 { opp-hz = /bits/ 64 <912000000>; opp-microvolt = <1200000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1200000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; }; cpus { cpu@0 { clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; }; cpu@1 { operating-points-v2 = <&cpu0_opp_table>; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; operating-points-v2 = <&cpu0_opp_table>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; operating-points-v2 = <&cpu0_opp_table>; }; }; de: display-engine { compatible = "allwinner,sun8i-a33-display-engine"; allwinner,pipelines = <&fe0>; status = "disabled"; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&ths>; }; mali_opp_table: gpu-opp-table { compatible = "operating-points-v2"; opp-144000000 { opp-hz = /bits/ 64 <144000000>; }; opp-240000000 { opp-hz = /bits/ 64 <240000000>; }; opp-384000000 { opp-hz = /bits/ 64 <384000000>; }; }; memory { reg = <0x40000000 0x80000000>; }; sound: sound { compatible = "simple-audio-card"; simple-audio-card,name = "sun8i-a33-audio"; simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&link_codec>; simple-audio-card,bitclock-master = <&link_codec>; simple-audio-card,mclk-fs = <512>; simple-audio-card,aux-devs = <&codec_analog>; simple-audio-card,routing = "Left DAC", "AIF1 Slot 0 Left", "Right DAC", "AIF1 Slot 0 Right"; status = "disabled"; simple-audio-card,cpu { sound-dai = <&dai>; }; link_codec: simple-audio-card,codec { sound-dai = <&codec>; }; }; soc@01c00000 { tcon0: lcd-controller@01c0c000 { compatible = "allwinner,sun8i-a33-tcon"; reg = <0x01c0c000 0x1000>; interrupts = ; clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_LCD_CH0>; clock-names = "ahb", "tcon-ch0"; clock-output-names = "tcon-pixel-clock"; resets = <&ccu RST_BUS_LCD>; reset-names = "lcd"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; tcon0_in: port@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; tcon0_in_drc0: endpoint@0 { reg = <0>; remote-endpoint = <&drc0_out_tcon0>; }; }; tcon0_out: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; }; }; }; crypto: crypto-engine@01c15000 { compatible = "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = ; clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; clock-names = "ahb", "mod"; resets = <&ccu RST_BUS_SS>; reset-names = "ahb"; }; dai: dai@01c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun6i-a31-i2s"; reg = <0x01c22c00 0x200>; interrupts = ; clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; clock-names = "apb", "mod"; resets = <&ccu RST_BUS_CODEC>; dmas = <&dma 15>, <&dma 15>; dma-names = "rx", "tx"; status = "disabled"; }; codec: codec@01c22e00 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-a33-codec"; reg = <0x01c22e00 0x400>; interrupts = ; clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; clock-names = "bus", "mod"; status = "disabled"; }; ths: ths@01c25000 { compatible = "allwinner,sun8i-a33-ths"; reg = <0x01c25000 0x100>; #thermal-sensor-cells = <0>; #io-channel-cells = <0>; }; fe0: display-frontend@01e00000 { compatible = "allwinner,sun8i-a33-display-frontend"; reg = <0x01e00000 0x20000>; interrupts = ; clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>, <&ccu CLK_DRAM_DE_FE>; clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_BUS_DE_FE>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; fe0_out: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; fe0_out_be0: endpoint@0 { reg = <0>; remote-endpoint = <&be0_in_fe0>; }; }; }; }; be0: display-backend@01e60000 { compatible = "allwinner,sun8i-a33-display-backend"; reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; reg-names = "be", "sat"; interrupts = ; clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>; clock-names = "ahb", "mod", "ram", "sat"; resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; reset-names = "be", "sat"; assigned-clocks = <&ccu CLK_DE_BE>; assigned-clock-rates = <300000000>; ports { #address-cells = <1>; #size-cells = <0>; be0_in: port@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; be0_in_fe0: endpoint@0 { reg = <0>; remote-endpoint = <&fe0_out_be0>; }; }; be0_out: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; be0_out_drc0: endpoint@0 { reg = <0>; remote-endpoint = <&drc0_in_be0>; }; }; }; }; drc0: drc@01e70000 { compatible = "allwinner,sun8i-a33-drc"; reg = <0x01e70000 0x10000>; interrupts = ; clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>, <&ccu CLK_DRAM_DRC>; clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_BUS_DRC>; assigned-clocks = <&ccu CLK_DRC>; assigned-clock-rates = <300000000>; ports { #address-cells = <1>; #size-cells = <0>; drc0_in: port@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; drc0_in_be0: endpoint@0 { reg = <0>; remote-endpoint = <&be0_out_drc0>; }; }; drc0_out: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; drc0_out_tcon0: endpoint@0 { reg = <0>; remote-endpoint = <&tcon0_in_drc0>; }; }; }; }; }; thermal-zones { cpu_thermal { /* milliseconds */ polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&ths>; cooling-maps { map0 { trip = <&cpu_alert0>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu_alert1>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map2 { trip = <&gpu_alert0>; cooling-device = <&mali 1 THERMAL_NO_LIMIT>; }; map3 { trip = <&gpu_alert1>; cooling-device = <&mali 2 THERMAL_NO_LIMIT>; }; }; trips { cpu_alert0: cpu_alert0 { /* milliCelsius */ temperature = <75000>; hysteresis = <2000>; type = "passive"; }; gpu_alert0: gpu_alert0 { /* milliCelsius */ temperature = <85000>; hysteresis = <2000>; type = "passive"; }; cpu_alert1: cpu_alert1 { /* milliCelsius */ temperature = <90000>; hysteresis = <2000>; type = "hot"; }; gpu_alert1: gpu_alert1 { /* milliCelsius */ temperature = <95000>; hysteresis = <2000>; type = "hot"; }; cpu_crit: cpu_crit { /* milliCelsius */ temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; }; }; &ccu { compatible = "allwinner,sun8i-a33-ccu"; }; &mali { operating-points-v2 = <&mali_opp_table>; }; &pio { compatible = "allwinner,sun8i-a33-pinctrl"; interrupts = , ; uart0_pins_b: uart0@1 { pins = "PB0", "PB1"; function = "uart0"; }; }; &usb_otg { compatible = "allwinner,sun8i-a33-musb"; }; &usbphy { compatible = "allwinner,sun8i-a33-usb-phy"; reg = <0x01c19400 0x14>, <0x01c1a800 0x4>; reg-names = "phy_ctrl", "pmu1"; };