// SPDX-License-Identifier: GPL-2.0 /dts-v1/; /include/ "skeleton.dtsi" / { model = "ARM Versatile AB"; compatible = "arm,versatile-ab"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&vic>; aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; i2c0 = &i2c0; }; chosen { stdout-path = &uart0; }; memory { reg = <0x0 0x08000000>; }; xtal24mhz: xtal24mhz@24M { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; }; core-module@10000000 { compatible = "arm,core-module-versatile", "syscon", "simple-mfd"; reg = <0x10000000 0x200>; led@08.0 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x01>; label = "versatile:0"; linux,default-trigger = "heartbeat"; default-state = "on"; }; led@08.1 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x02>; label = "versatile:1"; linux,default-trigger = "mmc0"; default-state = "off"; }; led@08.2 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x04>; label = "versatile:2"; linux,default-trigger = "cpu0"; default-state = "off"; }; led@08.3 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x08>; label = "versatile:3"; default-state = "off"; }; led@08.4 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x10>; label = "versatile:4"; default-state = "off"; }; led@08.5 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x20>; label = "versatile:5"; default-state = "off"; }; led@08.6 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x40>; label = "versatile:6"; default-state = "off"; }; led@08.7 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x80>; label = "versatile:7"; default-state = "off"; }; /* OSC1 on AB, OSC4 on PB */ osc1: cm_aux_osc@24M { #clock-cells = <0>; compatible = "arm,versatile-cm-auxosc"; clocks = <&xtal24mhz>; }; /* The timer clock is the 24 MHz oscillator divided to 1MHz */ timclk: timclk@1M { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <24>; clock-mult = <1>; clocks = <&xtal24mhz>; }; pclk: pclk@24M { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <1>; clock-mult = <1>; clocks = <&xtal24mhz>; }; }; flash@34000000 { /* 64 MiB NOR flash in non-interleaved chips */ compatible = "arm,versatile-flash", "cfi-flash"; reg = <0x34000000 0x04000000>; bank-width = <4>; }; i2c0: i2c@10002000 { #address-cells = <1>; #size-cells = <0>; compatible = "arm,versatile-i2c"; reg = <0x10002000 0x1000>; rtc@68 { compatible = "dallas,ds1338"; reg = <0x68>; }; }; net@10010000 { compatible = "smsc,lan91c111"; reg = <0x10010000 0x10000>; interrupts = <25>; }; lcd@10008000 { compatible = "arm,versatile-lcd"; reg = <0x10008000 0x1000>; }; amba { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; vic: intc@10140000 { compatible = "arm,versatile-vic"; interrupt-controller; #interrupt-cells = <1>; reg = <0x10140000 0x1000>; clear-mask = <0xffffffff>; valid-mask = <0xffffffff>; }; sic: intc@10003000 { compatible = "arm,versatile-sic"; interrupt-controller; #interrupt-cells = <1>; reg = <0x10003000 0x1000>; interrupt-parent = <&vic>; interrupts = <31>; /* Cascaded to vic */ clear-mask = <0xffffffff>; /* * Valid interrupt lines mask according to * table 4-36 page 4-50 of ARM DUI 0225D */ valid-mask = <0x0760031b>; }; dma@10130000 { compatible = "arm,pl081", "arm,primecell"; reg = <0x10130000 0x1000>; interrupts = <17>; clocks = <&pclk>; clock-names = "apb_pclk"; }; uart0: uart@101f1000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101f1000 0x1000>; interrupts = <12>; clocks = <&xtal24mhz>, <&pclk>; clock-names = "uartclk", "apb_pclk"; }; uart1: uart@101f2000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101f2000 0x1000>; interrupts = <13>; clocks = <&xtal24mhz>, <&pclk>; clock-names = "uartclk", "apb_pclk"; }; uart2: uart@101f3000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101f3000 0x1000>; interrupts = <14>; clocks = <&xtal24mhz>, <&pclk>; clock-names = "uartclk", "apb_pclk"; }; smc@10100000 { compatible = "arm,primecell"; reg = <0x10100000 0x1000>; clocks = <&pclk>; clock-names = "apb_pclk"; }; mpmc@10110000 { compatible = "arm,primecell"; reg = <0x10110000 0x1000>; clocks = <&pclk>; clock-names = "apb_pclk"; }; display@10120000 { compatible = "arm,pl110", "arm,primecell"; reg = <0x10120000 0x1000>; interrupts = <16>; clocks = <&osc1>, <&pclk>; clock-names = "clcd", "apb_pclk"; }; sctl@101e0000 { compatible = "arm,primecell"; reg = <0x101e0000 0x1000>; clocks = <&pclk>; clock-names = "apb_pclk"; }; watchdog@101e1000 { compatible = "arm,primecell"; reg = <0x101e1000 0x1000>; interrupts = <0>; clocks = <&pclk>; clock-names = "apb_pclk"; }; timer@101e2000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x101e2000 0x1000>; interrupts = <4>; clocks = <&timclk>, <&timclk>, <&pclk>; clock-names = "timer0", "timer1", "apb_pclk"; }; timer@101e3000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x101e3000 0x1000>; interrupts = <5>; clocks = <&timclk>, <&timclk>, <&pclk>; clock-names = "timer0", "timer1", "apb_pclk"; }; gpio0: gpio@101e4000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x101e4000 0x1000>; gpio-controller; interrupts = <6>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&pclk>; clock-names = "apb_pclk"; }; gpio1: gpio@101e5000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x101e5000 0x1000>; interrupts = <7>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&pclk>; clock-names = "apb_pclk"; }; rtc@101e8000 { compatible = "arm,pl030", "arm,primecell"; reg = <0x101e8000 0x1000>; interrupts = <10>; clocks = <&pclk>; clock-names = "apb_pclk"; }; sci@101f0000 { compatible = "arm,primecell"; reg = <0x101f0000 0x1000>; interrupts = <15>; clocks = <&pclk>; clock-names = "apb_pclk"; }; spi@101f4000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x101f4000 0x1000>; interrupts = <11>; clocks = <&xtal24mhz>, <&pclk>; clock-names = "SSPCLK", "apb_pclk"; }; fpga { compatible = "arm,versatile-fpga", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x10000000 0x10000>; sysreg@0 { compatible = "arm,versatile-sysreg", "syscon"; reg = <0x00000 0x1000>; }; aaci@4000 { compatible = "arm,primecell"; reg = <0x4000 0x1000>; interrupts = <24>; clocks = <&pclk>; clock-names = "apb_pclk"; }; mmc@5000 { compatible = "arm,pl180", "arm,primecell"; reg = <0x5000 0x1000>; interrupts-extended = <&vic 22 &sic 1>; clocks = <&xtal24mhz>, <&pclk>; clock-names = "mclk", "apb_pclk"; }; kmi@6000 { compatible = "arm,pl050", "arm,primecell"; reg = <0x6000 0x1000>; interrupt-parent = <&sic>; interrupts = <3>; clocks = <&xtal24mhz>, <&pclk>; clock-names = "KMIREFCLK", "apb_pclk"; }; kmi@7000 { compatible = "arm,pl050", "arm,primecell"; reg = <0x7000 0x1000>; interrupt-parent = <&sic>; interrupts = <4>; clocks = <&xtal24mhz>, <&pclk>; clock-names = "KMIREFCLK", "apb_pclk"; }; }; }; };