/* * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. */ #include static iomux_v3_cfg_t mx6q_arm2_pads[] = { /* UART4 for debug */ MX6Q_PAD_KEY_COL0__UART4_TXD, MX6Q_PAD_KEY_ROW0__UART4_RXD, /* USB HSIC ports use the same pin with ENET */ #ifdef CONFIG_USB_EHCI_ARC_HSIC /* USB H2 strobe/data pin */ MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE, MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA, /* USB H3 strobe/data pin */ MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE, MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA, /* ENET */ #else MX6Q_PAD_KEY_COL1__ENET_MDIO, MX6Q_PAD_KEY_COL2__ENET_MDC, MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC, MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0, MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1, MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2, MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3, MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL, MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK, MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC, MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0, MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1, MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2, MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3, MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL, #ifdef CONFIG_FEC_1588 MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT, #endif #endif /* MCLK for csi0 */ MX6Q_PAD_GPIO_0__CCM_CLKO, MX6Q_PAD_GPIO_3__CCM_CLKO2, /* SD1 */ MX6Q_PAD_SD1_CLK__USDHC1_CLK, MX6Q_PAD_SD1_CMD__USDHC1_CMD, MX6Q_PAD_SD1_DAT0__USDHC1_DAT0, MX6Q_PAD_SD1_DAT1__USDHC1_DAT1, MX6Q_PAD_SD1_DAT2__USDHC1_DAT2, MX6Q_PAD_SD1_DAT3__USDHC1_DAT3, /* SD2 */ MX6Q_PAD_SD2_CLK__USDHC2_CLK, MX6Q_PAD_SD2_CMD__USDHC2_CMD, MX6Q_PAD_SD2_DAT0__USDHC2_DAT0, MX6Q_PAD_SD2_DAT1__USDHC2_DAT1, MX6Q_PAD_SD2_DAT2__USDHC2_DAT2, MX6Q_PAD_SD2_DAT3__USDHC2_DAT3, /* SD3 */ MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ, MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ, MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ, MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ, MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ, MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ, MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ, MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ, MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ, MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ, MX6Q_PAD_SD3_RST__USDHC3_RST, /* SD3 VSelect */ MX6Q_PAD_GPIO_18__USDHC3_VSELECT, /* SD3_CD and SD3_WP */ MX6Q_PAD_NANDF_CS0__GPIO_6_11, MX6Q_PAD_NANDF_CS1__GPIO_6_14, /* SD4 */ MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ, MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ, MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ, MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ, MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ, MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ, MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ, MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ, MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ, MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ, MX6Q_PAD_NANDF_ALE__USDHC4_RST, /* eCSPI1 */ MX6Q_PAD_EIM_EB2__ECSPI1_SS0, MX6Q_PAD_EIM_D16__ECSPI1_SCLK, MX6Q_PAD_EIM_D17__ECSPI1_MISO, MX6Q_PAD_EIM_D18__ECSPI1_MOSI, MX6Q_PAD_EIM_D19__ECSPI1_SS1, MX6Q_PAD_EIM_EB2__GPIO_2_30, /*SS0*/ MX6Q_PAD_EIM_D19__GPIO_3_19, /*SS1*/ /* ESAI */ MX6Q_PAD_ENET_RXD0__ESAI1_HCKT, MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT, MX6Q_PAD_ENET_RXD1__ESAI1_FST, MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2, MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3, MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1, MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0, MX6Q_PAD_NANDF_CS2__ESAI1_TX0, MX6Q_PAD_NANDF_CS3__ESAI1_TX1, /* I2C1 */ MX6Q_PAD_CSI0_DAT8__I2C1_SDA, MX6Q_PAD_CSI0_DAT9__I2C1_SCL, /* I2C2 */ MX6Q_PAD_KEY_COL3__I2C2_SCL, MX6Q_PAD_KEY_ROW3__I2C2_SDA, /* DISPLAY */ MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, MX6Q_PAD_EIM_D24__GPIO_3_24, /* UART2 */ MX6Q_PAD_EIM_D26__UART2_RXD, MX6Q_PAD_EIM_D27__UART2_TXD, MX6Q_PAD_EIM_D28__UART2_RTS, MX6Q_PAD_EIM_D29__UART2_CTS, /* PWM1 */ MX6Q_PAD_GPIO_9__PWM1_PWMO, /* DISP0 DET */ MX6Q_PAD_EIM_D31__GPIO_3_31, /* DISP0 RESET */ MX6Q_PAD_EIM_WAIT__GPIO_5_0, /* HDMI */ MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE, MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0, MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1, /* USBOTG ID pin */ MX6Q_PAD_GPIO_1__USBOTG_ID, /* MLB150 */ MX6Q_PAD_GPIO_3__MLB_MLBCLK, MX6Q_PAD_GPIO_6__MLB_MLBSIG, MX6Q_PAD_GPIO_2__MLB_MLBDAT, }; static iomux_v3_cfg_t mx6q_arm2_i2c3_pads[] = { MX6Q_PAD_GPIO_5__I2C3_SCL, MX6Q_PAD_GPIO_16__I2C3_SDA, }; static iomux_v3_cfg_t mx6q_arm2_spdif_pads[] = { /* SPDIF */ MX6Q_PAD_GPIO_16__SPDIF_IN1, MX6Q_PAD_GPIO_17__SPDIF_OUT1, }; static iomux_v3_cfg_t mx6q_arm2_can_pads[] = { /* CAN1 */ MX6Q_PAD_GPIO_7__CAN1_TXCAN, MX6Q_PAD_KEY_ROW2__CAN1_RXCAN, MX6Q_PAD_GPIO_17__GPIO_7_12, /* CAN1 STBY */ MX6Q_PAD_GPIO_18__GPIO_7_13, /* CAN1 EN */ /* CAN2 */ MX6Q_PAD_KEY_COL4__CAN2_TXCAN, MX6Q_PAD_KEY_ROW4__CAN2_RXCAN, MX6Q_PAD_CSI0_DAT6__GPIO_5_24, /* CAN2 EN */ }; static iomux_v3_cfg_t mx6q_arm2_esai_record_pads[] = { MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR, MX6Q_PAD_ENET_MDIO__ESAI1_SCKR, MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR, }; static iomux_v3_cfg_t mx6q_arm2_csi0_sensor_pads[] = { MX6Q_PAD_GPIO_0__CCM_CLKO, /* ipu1 csi0 */ MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12, MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13, MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14, MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15, MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16, MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17, MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18, MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19, MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC, MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC, MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK, /* camera reset */ MX6Q_PAD_GPIO_19__GPIO_4_5, /* camera powerdown */ MX6Q_PAD_CSI0_DAT5__GPIO_5_23, }; static iomux_v3_cfg_t mx6q_arm2_csi0_tvin_pads[] = { /* ipu1 csi0 */ MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12, MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13, MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14, MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15, MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16, MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17, MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18, MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19, MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC, MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC, MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK, /* camera reset */ MX6Q_PAD_CSI0_DAT7__GPIO_5_25, /* camera powerdown */ MX6Q_PAD_CSI0_DAT5__GPIO_5_23, }; static iomux_v3_cfg_t mx6q_arm2_mipi_sensor_pads[] = { MX6Q_PAD_CSI0_MCLK__CCM_CLKO, }; static iomux_v3_cfg_t mx6q_arm2_audmux_pads[] = { /* AUDMUX */ MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC, MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD, MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS, MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD, }; #define MX6Q_USDHC_PAD_SETTING(id, speed) \ mx6q_sd##id##_##speed##mhz[] = { \ MX6Q_PAD_SD##id##_CLK__USDHC##id##_CLK_##speed##MHZ, \ MX6Q_PAD_SD##id##_CMD__USDHC##id##_CMD_##speed##MHZ, \ MX6Q_PAD_SD##id##_DAT0__USDHC##id##_DAT0_##speed##MHZ, \ MX6Q_PAD_SD##id##_DAT1__USDHC##id##_DAT1_##speed##MHZ, \ MX6Q_PAD_SD##id##_DAT2__USDHC##id##_DAT2_##speed##MHZ, \ MX6Q_PAD_SD##id##_DAT3__USDHC##id##_DAT3_##speed##MHZ, \ MX6Q_PAD_SD##id##_DAT4__USDHC##id##_DAT4_##speed##MHZ, \ MX6Q_PAD_SD##id##_DAT5__USDHC##id##_DAT5_##speed##MHZ, \ MX6Q_PAD_SD##id##_DAT6__USDHC##id##_DAT6_##speed##MHZ, \ MX6Q_PAD_SD##id##_DAT7__USDHC##id##_DAT7_##speed##MHZ, \ } static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 50); static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 100); static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 200); static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(4, 50); static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(4, 100); static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(4, 200); /* The GPMI is conflicted with SD3, so init this in the driver. */ static iomux_v3_cfg_t mx6q_gpmi_nand[] __initdata = { MX6Q_PAD_NANDF_CLE__RAWNAND_CLE, MX6Q_PAD_NANDF_ALE__RAWNAND_ALE, MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N, MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N, MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N, MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N, MX6Q_PAD_NANDF_RB0__RAWNAND_READY0, MX6Q_PAD_SD4_DAT0__RAWNAND_DQS, MX6Q_PAD_NANDF_D0__RAWNAND_D0, MX6Q_PAD_NANDF_D1__RAWNAND_D1, MX6Q_PAD_NANDF_D2__RAWNAND_D2, MX6Q_PAD_NANDF_D3__RAWNAND_D3, MX6Q_PAD_NANDF_D4__RAWNAND_D4, MX6Q_PAD_NANDF_D5__RAWNAND_D5, MX6Q_PAD_NANDF_D6__RAWNAND_D6, MX6Q_PAD_NANDF_D7__RAWNAND_D7, MX6Q_PAD_SD4_CMD__RAWNAND_RDN, MX6Q_PAD_SD4_CLK__RAWNAND_WRN, MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN, }; static iomux_v3_cfg_t mx6q_arm2_hdmi_ddc_pads[] = { MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL, /* HDMI DDC SCL */ MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, /* HDMI DDC SDA */ }; static iomux_v3_cfg_t mx6q_arm2_i2c2_pads[] = { MX6Q_PAD_KEY_COL3__I2C2_SCL, /* I2C2 SCL */ MX6Q_PAD_KEY_ROW3__I2C2_SDA, /* I2C2 SDA */ };