/* This header is usually included twice. Dependent on the existence of
 * FOR_DL_SOLO it names variable used for DL_SOLO or Quad CPUs.
 * The FIRST_INCLUDE_DONE macro can be used for stuff which is common
 * and does exist only once */

#undef MX6PAD
#undef MX6NAME
#undef MX6

//#define ONE_WIRE

#ifdef FOR_DL_SOLO
#define MX6(a) MX6DL_##a
#define MX6PAD(a) MX6DL_PAD_##a
#define MX6NAME(a) mx6dl_solo_##a
#else
#define MX6(a) MX6Q_##a
#define MX6PAD(a) MX6Q_PAD_##a
#define MX6NAME(a) mx6q_##a
#endif

static iomux_v3_cfg_t MX6NAME(exported_gpio_pads)[] = {
	/* Apalis GPIO */
	MX6PAD(NANDF_D4__GPIO_2_4),	/* 1 */
	MX6PAD(NANDF_D5__GPIO_2_5),	/* 2 */
	MX6PAD(NANDF_D6__GPIO_2_6),	/* 3 */
	MX6PAD(NANDF_D7__GPIO_2_7),	/* 4 */
	MX6PAD(NANDF_RB0__GPIO_6_10),	/* 5 */
	MX6PAD(NANDF_WP_B__GPIO_6_9),	/* 6 */
	MX6PAD(GPIO_2__GPIO_1_2),	/* 7 */
	MX6PAD(GPIO_6__GPIO_1_6),	/* 8 */
};
#ifndef FIRST_INCLUDE_DONE
#define APALIS_GPIO1 IMX_GPIO_NR(2, 4)
#define APALIS_GPIO2 IMX_GPIO_NR(2, 5)
#define APALIS_GPIO3 IMX_GPIO_NR(2, 6)
#define APALIS_GPIO4 IMX_GPIO_NR(2, 7)
#define APALIS_GPIO5 IMX_GPIO_NR(6, 10)
#define APALIS_GPIO6 IMX_GPIO_NR(6, 9)
/* GPIO7 is used by PCIe driver on Evaluation board */
#define APALIS_GPIO7 IMX_GPIO_NR(1, 2)
#define APALIS_GPIO8 IMX_GPIO_NR(1, 6)

static struct gpio apalis_imx6_gpios[] = {
	{APALIS_GPIO1,	GPIOF_IN,	"GPIO1 X1-1"},
	{APALIS_GPIO2,	GPIOF_IN,	"GPIO2 X1-3"},
	{APALIS_GPIO3,	GPIOF_IN,	"GPIO3 X1-5"},
	{APALIS_GPIO4,	GPIOF_IN,	"GPIO4 X1-7"},
	{APALIS_GPIO5,	GPIOF_IN,	"GPIO5 X1-9"},
	{APALIS_GPIO6,	GPIOF_IN,	"GPIO6 X1-11"},
	/* GPIO7 is used by PCIe driver on Evaluation board */
/*	{APALIS_GPIO7,	GPIOF_IN,	"GPIO7 X1-13"}, */
	{APALIS_GPIO8,	GPIOF_IN,	"GPIO8 X1-15, FAN"},
};
#endif

static iomux_v3_cfg_t MX6NAME(common_pads)[] = {

	/* Apalis Digital Audio pins as GPIO */
	MX6PAD(DISP0_DAT16__GPIO_5_10),
	MX6PAD(DISP0_DAT17__GPIO_5_11),
	MX6PAD(DISP0_DAT18__GPIO_5_12),
	MX6PAD(DISP0_DAT19__GPIO_5_13),
	MX6PAD(GPIO_19__GPIO_4_5),		/* I2S sys_mclk */

	/* CCM  */
	MX6PAD(GPIO_5__CCM_CLKO),		/* I2S sys_mclk */
	MX6PAD(NANDF_CS2__CCM_CLKO2),		/* MXM193 CAM1_MCLK */

	/* Apalis SPI1, ECSPI1 */
	MX6PAD(CSI0_DAT6__ECSPI1_MISO),
	MX6PAD(CSI0_DAT5__ECSPI1_MOSI),
	MX6PAD(CSI0_DAT4__ECSPI1_SCLK),
	MX6PAD(CSI0_DAT7__GPIO_5_25),

	/* Apalis SPI2, ECSPI2 */
	MX6PAD(EIM_CS1__ECSPI2_MOSI),
	MX6PAD(EIM_CS0__ECSPI2_SCLK),
	MX6PAD(EIM_OE__ECSPI2_MISO),
	MX6PAD(EIM_RW__GPIO_2_26),

	/* ENET */
	MX6PAD(ENET_MDIO__ENET_MDIO),
	MX6PAD(ENET_MDC__ENET_MDC),
	MX6PAD(RGMII_TXC__ENET_RGMII_TXC),
	MX6PAD(RGMII_TD0__ENET_RGMII_TD0),
	MX6PAD(RGMII_TD1__ENET_RGMII_TD1),
	MX6PAD(RGMII_TD2__ENET_RGMII_TD2),
	MX6PAD(RGMII_TD3__ENET_RGMII_TD3),
	MX6PAD(RGMII_TX_CTL__ENET_RGMII_TX_CTL),
	MX6PAD(ENET_REF_CLK__ENET_TX_CLK),
	MX6PAD(RGMII_RXC__ENET_RGMII_RXC),
	MX6PAD(RGMII_RD0__ENET_RGMII_RD0),
	MX6PAD(RGMII_RD1__ENET_RGMII_RD1),
	MX6PAD(RGMII_RD2__ENET_RGMII_RD2),
	MX6PAD(RGMII_RD3__ENET_RGMII_RD3),
	MX6PAD(RGMII_RX_CTL__ENET_RGMII_RX_CTL),
	MX6PAD(ENET_TXD0__GPIO_1_30),		/* Micrel RGMII Phy Interrupt */
	MX6PAD(ENET_CRS_DV__GPIO_1_25),		/* Micrel RGMII Phy Reset */
#ifdef TODO
	/* GPIO1 */
	MX6PAD(ENET_RX_ER__GPIO_1_24),		/* J9 - Microphone Detect */

	/* GPIO2 */
	MX6PAD(NANDF_D1__GPIO_2_1),	/* J14 - Menu Button */
	MX6PAD(NANDF_D2__GPIO_2_2),	/* J14 - Back Button */
	MX6PAD(NANDF_D3__GPIO_2_3),	/* J14 - Search Button */

	/* GPIO4 */
	MX6PAD(GPIO_19__GPIO_4_5),	/* J14 - Volume Down */
#endif

	/* CSI1/Bootmode pins - J12 */
#ifdef FOR_DL_SOLO
	/* Dualite/Solo doesn't have IPU2 */
	MX6PAD(EIM_EB2__IPU1_CSI1_D_19),	/* GPIO2[30] */
	MX6PAD(EIM_A23__IPU1_CSI1_D_18),	/* GPIO6[6] */
	MX6PAD(EIM_A22__IPU1_CSI1_D_17),	/* GPIO2[16] */
	MX6PAD(EIM_A21__IPU1_CSI1_D_16),	/* GPIO2[17] */
	MX6PAD(EIM_A20__IPU1_CSI1_D_15),	/* GPIO2[18] */
	MX6PAD(EIM_A19__IPU1_CSI1_D_14),	/* GPIO2[19] */
	MX6PAD(EIM_A18__IPU1_CSI1_D_13),	/* GPIO2[20] */
	MX6PAD(EIM_A17__IPU1_CSI1_D_12),	/* GPIO2[21] */
	MX6PAD(EIM_EB0__IPU1_CSI1_D_11),	/* GPIO2[28] */
	MX6PAD(EIM_EB1__IPU1_CSI1_D_10),	/* GPIO2[29] */
	MX6PAD(EIM_DA0__IPU1_CSI1_D_9),		/* GPIO3[0] */
	MX6PAD(EIM_DA1__IPU1_CSI1_D_8),		/* GPIO3[1] */
	MX6PAD(EIM_DA2__IPU1_CSI1_D_7),		/* GPIO3[2] */
	MX6PAD(EIM_DA3__IPU1_CSI1_D_6),		/* GPIO3[3] */
	MX6PAD(EIM_DA4__IPU1_CSI1_D_5),		/* GPIO3[4] */
	MX6PAD(EIM_DA5__IPU1_CSI1_D_4),		/* GPIO3[5] */
	MX6PAD(EIM_DA6__IPU1_CSI1_D_3),		/* GPIO3[6] */
	MX6PAD(EIM_DA7__IPU1_CSI1_D_2),		/* GPIO3[7] */
	MX6PAD(EIM_DA8__IPU1_CSI1_D_1),		/* GPIO3[8] */
	MX6PAD(EIM_DA9__IPU1_CSI1_D_0),		/* GPIO3[9] */
	MX6PAD(EIM_DA10__IPU1_CSI1_DATA_EN),	/* GPIO3[10] */
	MX6PAD(EIM_DA11__IPU1_CSI1_HSYNC),	/* GPIO3[11] */
	MX6PAD(EIM_DA12__IPU1_CSI1_VSYNC),	/* GPIO3[12] */
	MX6PAD(EIM_A16__IPU1_CSI1_PIXCLK),	/* GPIO2[22] */
#else
#ifdef TODO
	MX6PAD(EIM_EB2__IPU2_CSI1_D_19),	/* GPIO2[30] */
	MX6PAD(EIM_A23__IPU2_CSI1_D_18),	/* GPIO6[6] */
	MX6PAD(EIM_A22__IPU2_CSI1_D_17),	/* GPIO2[16] */
	MX6PAD(EIM_A21__IPU2_CSI1_D_16),	/* GPIO2[17] */
	MX6PAD(EIM_A20__IPU2_CSI1_D_15),	/* GPIO2[18] */
	MX6PAD(EIM_A19__IPU2_CSI1_D_14),	/* GPIO2[19] */
	MX6PAD(EIM_A18__IPU2_CSI1_D_13),	/* GPIO2[20] */
	MX6PAD(EIM_A17__IPU2_CSI1_D_12),	/* GPIO2[21] */
	MX6PAD(EIM_EB0__IPU2_CSI1_D_11),	/* GPIO2[28] */
	MX6PAD(EIM_EB1__IPU2_CSI1_D_10),	/* GPIO2[29] */
	MX6PAD(EIM_DA0__IPU2_CSI1_D_9),		/* GPIO3[0] */
	MX6PAD(EIM_DA1__IPU2_CSI1_D_8),		/* GPIO3[1] */
	MX6PAD(EIM_DA2__IPU2_CSI1_D_7),		/* GPIO3[2] */
	MX6PAD(EIM_DA3__IPU2_CSI1_D_6),		/* GPIO3[3] */
	MX6PAD(EIM_DA4__IPU2_CSI1_D_5),		/* GPIO3[4] */
	MX6PAD(EIM_DA5__IPU2_CSI1_D_4),		/* GPIO3[5] */
	MX6PAD(EIM_DA6__IPU2_CSI1_D_3),		/* GPIO3[6] */
	MX6PAD(EIM_DA7__IPU2_CSI1_D_2),		/* GPIO3[7] */
	MX6PAD(EIM_DA8__IPU2_CSI1_D_1),		/* GPIO3[8] */
	MX6PAD(EIM_DA9__IPU2_CSI1_D_0),		/* GPIO3[9] */
	MX6PAD(EIM_DA10__IPU2_CSI1_DATA_EN),	/* GPIO3[10] */
	MX6PAD(EIM_DA11__IPU2_CSI1_HSYNC),	/* GPIO3[11] */
	MX6PAD(EIM_DA12__IPU2_CSI1_VSYNC),	/* GPIO3[12] */
	MX6PAD(EIM_A16__IPU2_CSI1_PIXCLK),	/* GPIO2[22] */
#endif
#endif
	MX6PAD(EIM_DA13__GPIO_3_13),		/* BKL1_ON */
	MX6PAD(EIM_DA14__GPIO_3_14),		/* BKL1_PWM */
	MX6PAD(EIM_A25__GPIO_5_2),		/* BKL1_PWM_EN */
	MX6PAD(EIM_BCLK__GPIO_6_31),		/* VGA_PSAVE# */

	MX6PAD(KEY_ROW2__HDMI_TX_CEC_LINE),	/* HDMI CEC */

	MX6PAD(EIM_WAIT__GPIO_5_0),		/* TS_6 */
#ifdef TODO
	MX6PAD(EIM_A24__GPIO_5_4),		/* Field */
#endif
	MX6PAD(EIM_LBA__GPIO_2_27),		/* DAP1_RESET */
#ifdef TODO
	MX6PAD(EIM_EB3__GPIO_2_31),		/* GPIO2[31] - unused */
#endif
	MX6PAD(EIM_DA15__GPIO_3_15),		/* SATA1_ACT# */

	/* NANDF_CS1/2/3 are unused for sabrelite */
	MX6PAD(NANDF_CS1__GPIO_6_14),		/* SD1_CD# */
	MX6PAD(NANDF_CS3__GPIO_6_16),		/* TS_DIFF6- */

	MX6PAD(GPIO_18__GPIO_7_13),		/* PWR_INT */

	MX6PAD(DI0_PIN4__GPIO_4_20),		/* MMC1_CD# */

	/* Apalis CAN1 */
	MX6PAD(GPIO_7__CAN1_TXCAN),
	MX6PAD(GPIO_8__CAN1_RXCAN),
	/* Apalis CAN2 */
	MX6PAD(KEY_ROW4__CAN2_RXCAN),
	MX6PAD(KEY_COL4__CAN2_TXCAN),
#ifdef TODO
	MX6PAD(GPIO_2__GPIO_1_2),		/* STNDBY */
	MX6PAD(GPIO_7__GPIO_1_7),		/* NERR */
	NEW_PAD_CTRL(MX6PAD(GPIO_7__GPIO_1_7), CAN1_ERR_TEST_PADCFG),
	MX6PAD(GPIO_4__GPIO_1_4),		/* Enable */
#endif

	MX6PAD(GPIO_9__PWM1_PWMO),		/* PWM1 */
	MX6PAD(GPIO_1__PWM2_PWMO),		/* PWM2 */
	MX6PAD(SD4_DAT1__PWM3_PWMO),		/* PWM3 */
	MX6PAD(SD4_DAT2__PWM4_PWMO),		/* PWM4 */
#ifdef TODO
	MX6PAD(NANDF_D0__GPIO_2_0),		/* J6 - LVDS Display contrast */
#endif

#ifdef TODO
	/* PWM1 */
	MX6PAD(SD1_DAT3__PWM1_PWMO),		/* GPIO1[21] */

	/* PWM2 */
	MX6PAD(SD1_DAT2__PWM2_PWMO),		/* GPIO1[19] */

	/* PWM3 */
	MX6PAD(SD1_DAT1__PWM3_PWMO),		/* GPIO1[17] */

	/* PWM4 */
	MX6PAD(SD1_CMD__PWM4_PWMO),		/* GPIO1[18] */
#endif
	/* RTC ISL1208 irq*/
	MX6PAD(NANDF_CLE__GPIO_6_7),		/* TS_DIFF5- */

	/* Apalis UART1 */
	MX6PAD(CSI0_DAT10__UART1_TXD),
	MX6PAD(CSI0_DAT11__UART1_RXD),
	MX6PAD(EIM_D19__UART1_CTS),
	MX6PAD(EIM_D20__UART1_RTS),
	MX6PAD(EIM_D23__UART1_DCD),
	MX6PAD(EIM_D24__UART1_DTR),
	MX6PAD(EIM_D25__UART1_DSR),
	MX6PAD(EIM_EB3__UART1_RI),

	/*Apalis UART2 */
	MX6PAD(SD4_DAT4__UART2_RXD),
	MX6PAD(SD4_DAT5__UART2_RTS),
	MX6PAD(SD4_DAT6__UART2_CTS),
	MX6PAD(SD4_DAT7__UART2_TXD),

	/*Apalis UART3 */
	MX6PAD(KEY_COL0__UART4_TXD),
	MX6PAD(KEY_ROW0__UART4_RXD),

	/*Apalis UART4 */
	MX6PAD(KEY_COL1__UART5_TXD),
	MX6PAD(KEY_ROW1__UART5_RXD),

	/* Apalis, AUDMUX, local I2S */
	MX6PAD(DISP0_DAT20__AUDMUX_AUD4_TXC),
	MX6PAD(DISP0_DAT21__AUDMUX_AUD4_TXD),
	MX6PAD(DISP0_DAT22__AUDMUX_AUD4_TXFS),
	MX6PAD(DISP0_DAT23__AUDMUX_AUD4_RXD),

	/* USBOTG ID pin */
	MX6PAD(ENET_RX_ER__ANATOP_USBOTG_ID),
	/* USBOTG USB_VBUS_DET to internal HUB pin */
	MX6PAD(EIM_D28__GPIO_3_28),
	/* USB OTG OC pin */
	MX6PAD(EIM_D21__USBOH3_USBOTG_OC),
	/* USBOTG Power Enable */
	MX6PAD(EIM_D22__GPIO_3_22),

	/* USBH Power Enable */
	MX6PAD(GPIO_0__GPIO_1_0), /*GPIO_0__USBOH3_USBH1_PWR*/
	/* USB OC pin */
	MX6PAD(GPIO_3__USBOH3_USBH1_OC),

	/* Apalis I2C1, i.MX I2C1*/
	MX6PAD(CSI0_DAT9__I2C1_SCL),
	MX6PAD(CSI0_DAT8__I2C1_SDA),

	/* Apalis power I2C, i.MX I2C2*/
	MX6PAD(KEY_COL3__I2C2_SCL),
	MX6PAD(KEY_ROW3__I2C2_SDA),

	/* Apalis I2C3 (CAM), i.MX I2C3 */
	MX6PAD(EIM_D17__I2C3_SCL),
	MX6PAD(EIM_D18__I2C3_SDA),

	/* Touch Int */
	MX6PAD(KEY_COL2__GPIO_4_10),

	/* Type specific, others */
	MX6PAD(EIM_D29__GPIO_3_29),
	MX6PAD(NANDF_ALE__GPIO_6_8),
	MX6PAD(NANDF_CS0__GPIO_6_11),
	MX6PAD(SD4_CMD__GPIO_7_9),
	MX6PAD(SD4_CLK__GPIO_7_10),
	MX6PAD(SD4_DAT0__GPIO_2_8),
	MX6PAD(SD4_DAT3__GPIO_2_11),

	/* Unconnected Pins, GPIO with pull down */
	MX6PAD(ENET_RXD0__GPIO_1_27 | PAD_CTL_PUS_100K_DOWN),
	MX6PAD(ENET_RXD1__GPIO_1_26 | PAD_CTL_PUS_100K_DOWN),
	MX6PAD(ENET_TXD1__GPIO_1_29 | PAD_CTL_PUS_100K_DOWN),
	MX6PAD(ENET_TX_EN__GPIO_1_28 | PAD_CTL_PUS_100K_DOWN),
	0
};

/* Apalis I2C2 (DDC) */
static iomux_v3_cfg_t MX6NAME(hdmi_hdcp_pads)[] = {
	MX6PAD(EIM_EB2__HDMI_TX_DDC_SCL), /* HDMI DDC SCL */
	MX6PAD(EIM_D16__HDMI_TX_DDC_SDA), /* HDMI DDC SDA */
	0
};
static iomux_v3_cfg_t MX6NAME(hdmi_ddc_pads)[] = {
	MX6PAD(EIM_EB2__GPIO_2_30), 	/* HDMI DDC SCL GPIO bitbang driver */
	MX6PAD(EIM_D16__GPIO_3_16), 	/* HDMI DDC SDA GPIO bitbang driver */
	0
};

/* Apalis MXM LCD1 */
static iomux_v3_cfg_t MX6NAME(lcd_pads_enable)[] = {
	MX6PAD(EIM_A16__IPU1_DI1_DISP_CLK),
	MX6PAD(EIM_DA10__IPU1_DI1_PIN15),		/* DE */
	MX6PAD(EIM_DA11__IPU1_DI1_PIN2),		/* HSync */
	MX6PAD(EIM_DA12__IPU1_DI1_PIN3),		/* VSync */
	MX6PAD(EIM_DA9__IPU1_DISP1_DAT_0),
	MX6PAD(EIM_DA8__IPU1_DISP1_DAT_1),
	MX6PAD(EIM_DA7__IPU1_DISP1_DAT_2),
	MX6PAD(EIM_DA6__IPU1_DISP1_DAT_3),
	MX6PAD(EIM_DA5__IPU1_DISP1_DAT_4),
	MX6PAD(EIM_DA4__IPU1_DISP1_DAT_5),
	MX6PAD(EIM_DA3__IPU1_DISP1_DAT_6),
	MX6PAD(EIM_DA2__IPU1_DISP1_DAT_7),
	MX6PAD(EIM_DA1__IPU1_DISP1_DAT_8),
	MX6PAD(EIM_DA0__IPU1_DISP1_DAT_9),
	MX6PAD(EIM_EB1__IPU1_DISP1_DAT_10),
	MX6PAD(EIM_EB0__IPU1_DISP1_DAT_11),
	MX6PAD(EIM_A17__IPU1_DISP1_DAT_12),
	MX6PAD(EIM_A18__IPU1_DISP1_DAT_13),
	MX6PAD(EIM_A19__IPU1_DISP1_DAT_14),
	MX6PAD(EIM_A20__IPU1_DISP1_DAT_15),
	MX6PAD(EIM_A21__IPU1_DISP1_DAT_16),
	MX6PAD(EIM_A22__IPU1_DISP1_DAT_17),
	MX6PAD(EIM_A23__IPU1_DISP1_DAT_18),
	MX6PAD(EIM_A24__IPU1_DISP1_DAT_19),
	MX6PAD(EIM_D31__IPU1_DISP1_DAT_20),
	MX6PAD(EIM_D30__IPU1_DISP1_DAT_21),
	MX6PAD(EIM_D26__IPU1_DISP1_DAT_22),
	MX6PAD(EIM_D27__IPU1_DISP1_DAT_23),
	0
};

static iomux_v3_cfg_t MX6NAME(lcd_pads_disable)[] = {
	MX6PAD(EIM_A16__GPIO_2_22),
	MX6PAD(EIM_DA10__GPIO_3_10),		/* DE */
	MX6PAD(EIM_DA11__GPIO_3_11),		/* HSync */
	MX6PAD(EIM_DA12__GPIO_3_12),		/* VSync */
	MX6PAD(EIM_DA9__GPIO_3_9),
	MX6PAD(EIM_DA8__GPIO_3_8),
	MX6PAD(EIM_DA7__GPIO_3_7),
	MX6PAD(EIM_DA6__GPIO_3_6),
	MX6PAD(EIM_DA5__GPIO_3_5),
	MX6PAD(EIM_DA4__GPIO_3_4),
	MX6PAD(EIM_DA3__GPIO_3_3),
	MX6PAD(EIM_DA2__GPIO_3_2),
	MX6PAD(EIM_DA1__GPIO_3_1),
	MX6PAD(EIM_DA0__GPIO_3_0),
	MX6PAD(EIM_EB1__GPIO_2_29),
	MX6PAD(EIM_EB0__GPIO_2_28),
	MX6PAD(EIM_A17__GPIO_2_21),
	MX6PAD(EIM_A18__GPIO_2_20),
	MX6PAD(EIM_A19__GPIO_2_19),
	MX6PAD(EIM_A20__GPIO_2_18),
	MX6PAD(EIM_A21__GPIO_2_17),
	MX6PAD(EIM_A22__GPIO_2_16),
	MX6PAD(EIM_A23__GPIO_6_6),
	MX6PAD(EIM_A24__GPIO_5_4),
	MX6PAD(EIM_D31__GPIO_3_31),
	MX6PAD(EIM_D30__GPIO_3_30),
	MX6PAD(EIM_D26__GPIO_3_26),
	MX6PAD(EIM_D27__GPIO_3_27),
	0
};

/* Apalis MXM VGA DAC */
static iomux_v3_cfg_t MX6NAME(vga_dac_enable)[] = {
#ifdef FOR_DL_SOLO /* do not have IPU2 */
	MX6PAD(DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
	MX6PAD(DI0_PIN2__IPU1_DI0_PIN2),		/* HSync */
	MX6PAD(DI0_PIN3__IPU1_DI0_PIN3),		/* VSync */
	MX6PAD(DI0_PIN15__IPU1_DI0_PIN15),		/* DE */
	MX6PAD(DISP0_DAT0__IPU1_DISP0_DAT_0),
	MX6PAD(DISP0_DAT1__IPU1_DISP0_DAT_1),
	MX6PAD(DISP0_DAT2__IPU1_DISP0_DAT_2),
	MX6PAD(DISP0_DAT3__IPU1_DISP0_DAT_3),
	MX6PAD(DISP0_DAT4__IPU1_DISP0_DAT_4),
	MX6PAD(DISP0_DAT5__IPU1_DISP0_DAT_5),
	MX6PAD(DISP0_DAT6__IPU1_DISP0_DAT_6),
	MX6PAD(DISP0_DAT7__IPU1_DISP0_DAT_7),
	MX6PAD(DISP0_DAT8__IPU1_DISP0_DAT_8),
	MX6PAD(DISP0_DAT9__IPU1_DISP0_DAT_9),
	MX6PAD(DISP0_DAT10__IPU1_DISP0_DAT_10),
	MX6PAD(DISP0_DAT11__IPU1_DISP0_DAT_11),
	MX6PAD(DISP0_DAT12__IPU1_DISP0_DAT_12),
	MX6PAD(DISP0_DAT13__IPU1_DISP0_DAT_13),
	MX6PAD(DISP0_DAT14__IPU1_DISP0_DAT_14),
	MX6PAD(DISP0_DAT15__IPU1_DISP0_DAT_15),
	0,
#else
	MX6PAD(DI0_DISP_CLK__IPU2_DI0_DISP_CLK),
	MX6PAD(DI0_PIN2__IPU2_DI0_PIN2),		/* HSync */
	MX6PAD(DI0_PIN3__IPU2_DI0_PIN3),		/* VSync */
	MX6PAD(DI0_PIN15__IPU2_DI0_PIN15),		/* DE */
	MX6PAD(DISP0_DAT0__IPU2_DISP0_DAT_0),
	MX6PAD(DISP0_DAT1__IPU2_DISP0_DAT_1),
	MX6PAD(DISP0_DAT2__IPU2_DISP0_DAT_2),
	MX6PAD(DISP0_DAT3__IPU2_DISP0_DAT_3),
	MX6PAD(DISP0_DAT4__IPU2_DISP0_DAT_4),
	MX6PAD(DISP0_DAT5__IPU2_DISP0_DAT_5),
	MX6PAD(DISP0_DAT6__IPU2_DISP0_DAT_6),
	MX6PAD(DISP0_DAT7__IPU2_DISP0_DAT_7),
	MX6PAD(DISP0_DAT8__IPU2_DISP0_DAT_8),
	MX6PAD(DISP0_DAT9__IPU2_DISP0_DAT_9),
	MX6PAD(DISP0_DAT10__IPU2_DISP0_DAT_10),
	MX6PAD(DISP0_DAT11__IPU2_DISP0_DAT_11),
	MX6PAD(DISP0_DAT12__IPU2_DISP0_DAT_12),
	MX6PAD(DISP0_DAT13__IPU2_DISP0_DAT_13),
	MX6PAD(DISP0_DAT14__IPU2_DISP0_DAT_14),
	MX6PAD(DISP0_DAT15__IPU2_DISP0_DAT_15),
	0
#endif
};

static iomux_v3_cfg_t MX6NAME(vga_dac_disable)[] = {
	MX6PAD(DI0_DISP_CLK__GPIO_4_16),
	MX6PAD(DI0_PIN2__GPIO_4_18),			/* HSync */
	MX6PAD(DI0_PIN3__GPIO_4_19),			/* VSync */
	MX6PAD(DI0_PIN15__GPIO_4_17),		/* DE */
	MX6PAD(DISP0_DAT0__GPIO_4_21),
	MX6PAD(DISP0_DAT1__GPIO_4_22),
	MX6PAD(DISP0_DAT2__GPIO_4_23),
	MX6PAD(DISP0_DAT3__GPIO_4_24),
	MX6PAD(DISP0_DAT4__GPIO_4_25),
	MX6PAD(DISP0_DAT5__GPIO_4_26),
	MX6PAD(DISP0_DAT6__GPIO_4_27),
	MX6PAD(DISP0_DAT7__GPIO_4_28),
	MX6PAD(DISP0_DAT8__GPIO_4_29),
	MX6PAD(DISP0_DAT9__GPIO_4_30),
	MX6PAD(DISP0_DAT10__GPIO_4_31),
	MX6PAD(DISP0_DAT11__GPIO_5_5),
	MX6PAD(DISP0_DAT12__GPIO_5_6),
	MX6PAD(DISP0_DAT13__GPIO_5_7),
	MX6PAD(DISP0_DAT14__GPIO_5_8),
	MX6PAD(DISP0_DAT15__GPIO_5_9),
	0
};

#if defined(CONFIG_MXC_CAMERA_OV5640_MIPI) || defined(CONFIG_MXC_CAMERA_OV5640_MIPI_MODULE)
static iomux_v3_cfg_t MX6NAME(mipi_pads)[] = {
	MX6PAD(NANDF_WP_B__GPIO_6_9),		/* J16 - MIPI Powerdown - Nitrogen6x, SOM is NC */
	MX6PAD(NANDF_D5__GPIO_2_5),		/* J16 - MIPI camera reset - Nitrogen6x/SOM */
	MX6PAD(NANDF_CS0__GPIO_6_11),		/* Camera Reset, SOM jumpered */
	MX6PAD(GPIO_6__GPIO_1_6),		/* Camera GP */
	0
};
#endif

#if defined(CSI0_CAMERA)
static iomux_v3_cfg_t MX6NAME(csi0_sensor_pads)[] = {
	/* IPU1 Camera */
	MX6PAD(CSI0_DATA_EN__IPU1_CSI0_DATA_EN),
	MX6PAD(CSI0_DAT12__IPU1_CSI0_D_12),
	MX6PAD(CSI0_DAT13__IPU1_CSI0_D_13),
	MX6PAD(CSI0_DAT14__IPU1_CSI0_D_14),
	MX6PAD(CSI0_DAT15__IPU1_CSI0_D_15),
	MX6PAD(CSI0_DAT16__IPU1_CSI0_D_16),
	MX6PAD(CSI0_DAT17__IPU1_CSI0_D_17),
	MX6PAD(CSI0_DAT18__IPU1_CSI0_D_18),
	MX6PAD(CSI0_DAT19__IPU1_CSI0_D_19),
	MX6PAD(CSI0_MCLK__IPU1_CSI0_HSYNC),
	MX6PAD(CSI0_PIXCLK__IPU1_CSI0_PIXCLK),
	MX6PAD(CSI0_VSYNC__IPU1_CSI0_VSYNC),
	0
};
#else
static iomux_v3_cfg_t MX6NAME(csi0_gpio_pads)[] = {
	/* IPU1 Camera */
	MX6PAD(CSI0_DATA_EN__GPIO_5_20),
	MX6PAD(CSI0_DAT12__GPIO_5_30),
	MX6PAD(CSI0_DAT13__GPIO_5_31),
	MX6PAD(CSI0_DAT14__GPIO_6_0),
	MX6PAD(CSI0_DAT15__GPIO_6_1),
	MX6PAD(CSI0_DAT16__GPIO_6_2),
	MX6PAD(CSI0_DAT17__GPIO_6_3),
	MX6PAD(CSI0_DAT18__GPIO_6_4),
	MX6PAD(CSI0_DAT19__GPIO_6_5),
	MX6PAD(CSI0_MCLK__GPIO_5_19),
	MX6PAD(CSI0_PIXCLK__GPIO_5_18),
	MX6PAD(CSI0_VSYNC__GPIO_5_21),
	0
};
#endif

#ifdef TODO
static iomux_v3_cfg_t MX6NAME(mc33902_flexcan_pads)[] = {
	NEW_PAD_CTRL(MX6PAD(GPIO_7__GPIO_1_7), CAN1_ERR_PADCFG),
	0
};
#endif

/* MMC / SD Cards */
#define MX6Q_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ	(PAD_CTL_PKE | PAD_CTL_PUE |	\
		PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
		PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define MX6Q_USDHC_PAD_CTRL_50MHZ	MX6Q_USDHC_PAD_CTRL
#define MX6Q_PAD_SD3_CLK__USDHC3_CLK	MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ
#define MX6Q_PAD_SD3_CMD__USDHC3_CMD	MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ
#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
#define MX6Q_PAD_SD4_CLK__USDHC4_CLK	MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ
#define MX6Q_PAD_SD4_CMD__USDHC4_CMD	MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ
#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0	MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ
#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1	MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ
#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2	MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ
#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3	MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ

#define MX6DL_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ	MX6Q_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ
#define MX6DL_USDHC_PAD_CTRL_50MHZ	MX6DL_USDHC_PAD_CTRL
#define MX6DL_PAD_SD3_CLK__USDHC3_CLK	MX6DL_PAD_SD3_CLK__USDHC3_CLK_50MHZ
#define MX6DL_PAD_SD3_CMD__USDHC3_CMD	MX6DL_PAD_SD3_CMD__USDHC3_CMD_50MHZ
#define MX6DL_PAD_SD3_DAT0__USDHC3_DAT0	MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
#define MX6DL_PAD_SD3_DAT1__USDHC3_DAT1	MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
#define MX6DL_PAD_SD3_DAT2__USDHC3_DAT2	MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
#define MX6DL_PAD_SD3_DAT3__USDHC3_DAT3	MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
#define MX6DL_PAD_SD3_DAT4__USDHC3_DAT4	MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
#define MX6DL_PAD_SD3_DAT5__USDHC3_DAT5	MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
#define MX6DL_PAD_SD3_DAT6__USDHC3_DAT6	MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
#define MX6DL_PAD_SD3_DAT7__USDHC3_DAT7	MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
#define MX6DL_PAD_SD4_CLK__USDHC4_CLK	MX6DL_PAD_SD4_CLK__USDHC4_CLK_50MHZ
#define MX6DL_PAD_SD4_CMD__USDHC4_CMD	MX6DL_PAD_SD4_CMD__USDHC4_CMD_50MHZ
#define MX6DL_PAD_SD4_DAT0__USDHC4_DAT0	MX6DL_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ
#define MX6DL_PAD_SD4_DAT1__USDHC4_DAT1	MX6DL_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ
#define MX6DL_PAD_SD4_DAT2__USDHC4_DAT2	MX6DL_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ
#define MX6DL_PAD_SD4_DAT3__USDHC4_DAT3	MX6DL_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ

#define NP(id, pin, pad_ctl) \
	NEW_PAD_CTRL(MX6PAD(SD##id##_##pin##__USDHC##id##_##pin), MX6(pad_ctl))

#define SD_PINS(id, pad_ctl) \
	NP(id, CLK, pad_ctl),	\
	NP(id, CMD, pad_ctl),	\
	NP(id, DAT0, pad_ctl),	\
	NP(id, DAT1, pad_ctl),	\
	NP(id, DAT2, pad_ctl),	\
	NP(id, DAT3, pad_ctl)

/* Apalis MMC1 */
#define SD_PINS1(pad_ctl) \
	SD_PINS(1, pad_ctl), \
	NEW_PAD_CTRL(MX6PAD(NANDF_D0__USDHC1_DAT4), MX6(pad_ctl)), \
	NEW_PAD_CTRL(MX6PAD(NANDF_D1__USDHC1_DAT5), MX6(pad_ctl)), \
	NEW_PAD_CTRL(MX6PAD(NANDF_D2__USDHC1_DAT6), MX6(pad_ctl)), \
	NEW_PAD_CTRL(MX6PAD(NANDF_D3__USDHC1_DAT7), MX6(pad_ctl))

/* Apalis SD1 */
#define SD_PINS2(pad_ctl) \
	SD_PINS(2, pad_ctl)

/* Apalis eMMC */
#define SD_PINS3(pad_ctl) \
	SD_PINS(3, pad_ctl), \
	NEW_PAD_CTRL(MX6PAD(SD3_DAT4__USDHC3_DAT4), MX6(pad_ctl)), \
	NEW_PAD_CTRL(MX6PAD(SD3_DAT5__USDHC3_DAT5), MX6(pad_ctl)), \
	NEW_PAD_CTRL(MX6PAD(SD3_DAT6__USDHC3_DAT6), MX6(pad_ctl)), \
	NEW_PAD_CTRL(MX6PAD(SD3_DAT7__USDHC3_DAT7), MX6(pad_ctl)), \
	MX6PAD(SD3_RST__USDHC3_RST)

/* not in default pinmuxing, pins partly used for UART2 & PWM */
#define SD_PINS4(pad_ctl) \
	SD_PINS(4, pad_ctl)

#define MX6_USDHC_PAD_SETTING(id, speed, pad_ctl)	\
		MX6NAME(sd##id##_##speed##mhz)[] = { SD_PINS##id(pad_ctl), 0 }

static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(1, 50, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(1, 100, USDHC_PAD_CTRL_100MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(1, 200, USDHC_PAD_CTRL_200MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 50, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 100, USDHC_PAD_CTRL_100MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 200, USDHC_PAD_CTRL_200MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(3, 50, USDHC_PAD_CTRL_50MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(3, 100, USDHC_PAD_CTRL_100MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(3, 200, USDHC_PAD_CTRL_200MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(4, 50, USDHC_PAD_CTRL_50MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(4, 100, USDHC_PAD_CTRL_100MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(4, 200, USDHC_PAD_CTRL_200MHZ);

#define _50MHZ 0
#define _100MHZ 1
#define _200MHZ 2
#define SD_SPEED_CNT 3
static iomux_v3_cfg_t * MX6NAME(sd_pads)[] =
{
	MX6NAME(sd1_50mhz),
	MX6NAME(sd1_100mhz),
	MX6NAME(sd1_200mhz),
	MX6NAME(sd2_50mhz),
	MX6NAME(sd2_100mhz),
	MX6NAME(sd2_200mhz),
	MX6NAME(sd3_50mhz),
	MX6NAME(sd3_100mhz),
	MX6NAME(sd3_200mhz),
	MX6NAME(sd4_50mhz),
	MX6NAME(sd4_100mhz),
	MX6NAME(sd4_200mhz),
};

/* Apalis SPDIF */
static iomux_v3_cfg_t MX6NAME(spdif_pads)[] = {
	MX6PAD(GPIO_16__SPDIF_IN1),
	MX6PAD(GPIO_17__SPDIF_OUT1),
};
#define FIRST_INCLUDE_DONE