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 * Copyright (c) 2007-2009 NVIDIA Corporation.
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 * modification, are permitted provided that the following conditions are met:
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 * Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 *
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 * may be used to endorse or promote products derived from this software
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/**
 * @file
 * <b>NVIDIA APX ODM Kit::
 *         The KBC GPIO pin definitions</b>
 *
 * @b Description: Define the KBC GPIO pins in row and column numbers.
 */

#ifndef NVODM_QUERY_KBC_GPIO_DEF_H
#define NVODM_QUERY_KBC_GPIO_DEF_H

typedef enum
{
    NvOdmKbcGpioPin_KBRow0 = 0,
    NvOdmKbcGpioPin_KBRow1,
    NvOdmKbcGpioPin_KBRow2,
    NvOdmKbcGpioPin_KBRow3,
    NvOdmKbcGpioPin_KBRow4,
    NvOdmKbcGpioPin_KBRow5,
    NvOdmKbcGpioPin_KBRow6,
    NvOdmKbcGpioPin_KBRow7,
    NvOdmKbcGpioPin_KBRow8,
    NvOdmKbcGpioPin_KBRow9,
    NvOdmKbcGpioPin_KBRow10,
    NvOdmKbcGpioPin_KBRow11,
    NvOdmKbcGpioPin_KBRow12,
    NvOdmKbcGpioPin_KBRow13,
    NvOdmKbcGpioPin_KBRow14,
    NvOdmKbcGpioPin_KBRow15,
    NvOdmKbcGpioPin_KBCol0,
    NvOdmKbcGpioPin_KBCol1,
    NvOdmKbcGpioPin_KBCol2,
    NvOdmKbcGpioPin_KBCol3,
    NvOdmKbcGpioPin_KBCol4,
    NvOdmKbcGpioPin_KBCol5,
    NvOdmKbcGpioPin_KBCol6,
    NvOdmKbcGpioPin_KBCol7,
    NvOdmKbcGpioPin_Num,
    NvOdmKbcGpioPin_Force32 = 0x7FFFFFFF
}NvOdmKbcGpioPin;

#endif // NVODM_QUERY_KBC_GPIO_DEF_H