// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for NXP LS1012A 2G5RDB Board.
 *
 * Copyright 2017 NXP
 *
 * Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
 */
/dts-v1/;

#include "fsl-ls1012a.dtsi"

/ {
	model = "LS1012A 2G5RDB Board";
	compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";

	aliases {
		ethernet0 = &pfe_mac0;
		ethernet1 = &pfe_mac1;
		mmc0 = &esdhc0;
		mmc1 = &esdhc1;
	};
};

&duart0 {
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&qspi {
	num-cs = <2>;
	bus-num = <0>;
	status = "okay";

	qflash0: s25fs512s@0 {
		compatible = "spansion,m25p80";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <20000000>;
		m25p,fast-read;
		reg = <0>;
	};
};

&sata {
	status = "okay";
};

&pfe {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	pfe_mac0: ethernet@0 {
		compatible = "fsl,pfe-gemac-port";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x0>;	/* GEM_ID */
		fsl,mdio-mux-val = <0x0>;
		phy-mode = "sgmii-2500";
		phy-handle = <&sgmii_phy1>;
	};

	pfe_mac1: ethernet@1 {
		compatible = "fsl,pfe-gemac-port";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x1>;	/* GEM_ID */
		fsl,mdio-mux-val = <0x0>;
		phy-mode = "sgmii-2500";
		phy-handle = <&sgmii_phy2>;
	};

	mdio@0 {
		#address-cells = <1>;
		#size-cells = <0>;

		sgmii_phy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c45";
			reg = <0x1>;
		};

		sgmii_phy2: ethernet-phy@2 {
			compatible = "ethernet-phy-ieee802.3-c45";
			reg = <0x2>;
		};
	};
};