// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Freescale LS1012A RDB Board.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 *
 */
/dts-v1/;

#include "fsl-ls1012a.dtsi"

/ {
	model = "LS1012A RDB Board";
	compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";

	aliases {
		ethernet0 = &pfe_mac0;
		ethernet1 = &pfe_mac1;
	};
};

&pcie {
	status = "okay";
};

&duart0 {
	status = "okay";
};

&esdhc0 {
	sd-uhs-sdr104;
	sd-uhs-sdr50;
	sd-uhs-sdr25;
	sd-uhs-sdr12;
	status = "okay";
};

&esdhc1 {
	mmc-hs200-1_8v;
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&sata {
	status = "okay";
};

&pfe {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	pfe_mac0: ethernet@0 {
		compatible = "fsl,pfe-gemac-port";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x0>;	/* GEM_ID */
		fsl,mdio-mux-val = <0x0>;
		phy-mode = "sgmii";
		phy-handle = <&sgmii_phy>;
	};

	pfe_mac1: ethernet@1 {
		compatible = "fsl,pfe-gemac-port";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x1>;	/* GEM_ID */
		fsl,mdio-mux-val = <0x0>;
		phy-mode = "rgmii-txid";
		phy-handle = <&rgmii_phy>;
	};
	mdio@0 {
		#address-cells = <1>;
		#size-cells = <0>;

		sgmii_phy: ethernet-phy@2 {
			reg = <0x2>;
		};

		rgmii_phy: ethernet-phy@1 {
			reg = <0x1>;
		};
	};
};

&qspi {
	status = "okay";

	s25fs512s0: flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <20000000>;
		m25p,fast-read;
		reg = <0>;
		spi-rx-bus-width = <1>;
		spi-tx-bus-width = <1>;
	};

};