// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for NXP LS1028A RDB Board.
 *
 * Copyright 2018-2019 NXP
 *
 * Harninder Rai <harninder.rai@nxp.com>
 *
 */

/dts-v1/;
#include "fsl-ls1028a.dtsi"

/ {
	model = "LS1028A RDB Board";
	compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";

	aliases {
		crypto = &crypto;
		serial0 = &duart0;
		serial1 = &duart1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x1 0x0000000>;
	};

	sys_mclk: clock-mclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "1P8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	sb_3v3: regulator-sb3v3 {
		compatible = "regulator-fixed";
		regulator-name = "3v3_vbus";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,widgets =
			"Microphone", "Microphone Jack",
			"Headphone", "Headphone Jack",
			"Speaker", "Speaker Ext",
			"Line", "Line In Jack";
		simple-audio-card,routing =
			"MIC_IN", "Microphone Jack",
			"Microphone Jack", "Mic Bias",
			"LINE_IN", "Line In Jack",
			"Headphone Jack", "HP_OUT",
			"Speaker Ext", "LINE_OUT";

		simple-audio-card,cpu {
			sound-dai = <&sai4>;
			frame-master;
			bitclock-master;
		};

		simple-audio-card,codec {
			sound-dai = <&sgtl5000>;
			frame-master;
			bitclock-master;
			system-clock-frequency = <25000000>;
		};
	};
};

&esdhc {
	sd-uhs-sdr104;
	sd-uhs-sdr50;
	sd-uhs-sdr25;
	sd-uhs-sdr12;
	status = "okay";
};

&esdhc1 {
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	bus-width = <8>;
	status = "okay";
};

&usb1 {
	dr_mode = "otg";
};

&i2c0 {
	status = "okay";

	i2c-mux@77 {
		compatible = "nxp,pca9847";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x1>;

			sgtl5000: audio-codec@a {
				#sound-dai-cells = <0>;
				compatible = "fsl,sgtl5000";
				reg = <0xa>;
				VDDA-supply = <&reg_1p8v>;
				VDDIO-supply = <&reg_1p8v>;
				clocks = <&sys_mclk>;
				sclk-strength = <3>;
			};
		};

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x02>;

			current-monitor@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <500>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			temperature-sensor@4c {
				compatible = "nxp,sa56004";
				reg = <0x4c>;
				vcc-supply = <&sb_3v3>;
			};

			rtc@51 {
				compatible = "nxp,pcf2129";
				reg = <0x51>;
			};
		};
	};
};

&can0 {
	status = "okay";

	can-transceiver {
		max-bitrate = <5000000>;
	};
};

&can1 {
	status = "okay";

	can-transceiver {
		max-bitrate = <5000000>;
	};
};

&fspi {
	status = "okay";
	mt35xu02g: flash@0 {
		compatible = "spansion,m25p80";
		#address-cells = <1>;
		#size-cells = <1>;
		m25p,fast-read;
		spi-max-frequency = <20000000>;
		reg = <0>;
		/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
		spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
		spi-tx-bus-width = <1>; /* 1 SPI Tx line */
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&enetc_port0 {
	phy-handle = <&sgmii_phy0>;
	phy-connection-type = "sgmii";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		sgmii_phy0: ethernet-phy@2 {
			reg = <0x2>;
		};
	};
};

&enetc_port1 {
	status = "disabled";
};

&enetc_mdio_pf3 {
	qsgmii_phy1: ethernet-phy@10 {
		reg = <0x10>;
	};

	qsgmii_phy2: ethernet-phy@11 {
		reg = <0x11>;
	};

	qsgmii_phy3: ethernet-phy@12 {
		reg = <0x12>;
	};

	qsgmii_phy4: ethernet-phy@13 {
		reg = <0x13>;
	};
};

/* l2switch ports */
&mscc_felix_ports {
	port@0 {
		status = "okay";
		phy-handle = <&qsgmii_phy1>;
		phy-mode = "qsgmii";
		managed = "in-band-status";
	};

	port@1 {
		status = "okay";
		phy-handle = <&qsgmii_phy2>;
		phy-mode = "qsgmii";
		managed = "in-band-status";
	};

	port@2 {
		status = "okay";
		phy-handle = <&qsgmii_phy3>;
		phy-mode = "qsgmii";
		managed = "in-band-status";
	};

	port@3 {
		status = "okay";
		phy-handle = <&qsgmii_phy4>;
		phy-mode = "qsgmii";
		managed = "in-band-status";
	};
};

&sai4 {
	status = "okay";
};

&sata {
	status = "okay";
};

&hdptx0 {
	lane-mapping = <0x4e>;
	status = "okay";
};